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Micron Technology Inc patents (2017 archive)


Recent patent applications related to Micron Technology Inc. Micron Technology Inc is listed as an Agent/Assignee. Note: Micron Technology Inc may have other listings under different names/spellings. We're not affiliated with Micron Technology Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "M" | Micron Technology Inc-related inventors


Apparatuses and methods for erasure-assisted ecc decoding

One example of erasure-assisted error correction code (ecc) decoding can include reading a codeword with a first trim level, reading the codeword with a second trim level, and reading the codeword with a third trim level. A first result from reading the codeword with the first trim level, a second result from reading the codeword with the second trim level, and a third result from reading the codeword with the third trim level can be accumulated. ... Micron Technology Inc

Error correction code (ecc) operations in memory

Apparatuses and methods for performing an error correction code (ecc) operation are provided. One example method can include generating a codeword based on a number of low density parity check (ldpc) codewords failing a ldpc decoding operation and performing a bch decoding operation on the codeword.. ... Micron Technology Inc

Transistors and methods of forming transistors

Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. ... Micron Technology Inc

Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors

A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain region is at opposite ends of the channel. ... Micron Technology Inc

Integrated structures containing vertically-stacked memory cells

Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. ... Micron Technology Inc

Integrated structures and methods of forming integrated structures

Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. ... Micron Technology Inc

Memory cell pillar including source junction plug

Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.. . ... Micron Technology Inc

Semiconductor device comprising gate structure sidewalls having different angles

The present disclosure provides a semiconductor device including a substrate, a first active region, a second active region, and a gate structure. The first active region and the second active region are disposed in the substrate. ... Micron Technology Inc

Semiconductor device including semiconductor chips mounted over both surfaces of substrate

A semiconductor chip 10 flip-chip mounted on a first surface 32 of a wiring substrate 30, a semiconductor chip 20 flip-chip mounted on a second surface 33 of the wiring substrate 30, a sealing resin 71 covering the semiconductor chip 10, a sealing resin 72 covering the semiconductor chip 20, a plurality of conductive posts provided to penetrate through the sealing resin 72, and a plurality of solder balls mounted on second ends of the plurality of conductive posts exposed from the sealing resin 72 are provided; and the mounting directions of the semiconductor chips 10 and 20 are mutually different by 90°. Both of the planar shapes of the semiconductor chips 10 and 20 are rectangular shapes, the semiconductor chip 10 is mounted so that the long sides thereof are parallel to the long sides of the wiring substrate 30, and the semiconductor chip 20 is mounted so that the long sides thereof are perpendicular to the long sides of the wiring substrate 30.. ... Micron Technology Inc

Vias and conductive routing layers in semiconductor substrates

Through vias and conductive routing layers in semiconductor substrates and associated methods of manufacturing are disclosed herein. In one embodiment, a method for processing a semiconductor substrate includes forming an aperture in a semiconductor substrate and through a dielectric on the semiconductor substrate. ... Micron Technology Inc

Methods of forming one or more covered voids in a semiconductor substrate

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. ... Micron Technology Inc

Methods of forming one or more covered voids in a semiconductor substrate

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. ... Micron Technology Inc

12/28/17 / #20170372913

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. ... Micron Technology Inc

12/28/17 / #20170372861

Fuse element assemblies

Some embodiments include a fuse element assembly having a first portion configured to rupture as materials of the first portion flow to a second portion through electromigration. The assembly has a second portion configured to accumulate the materials that have flowed from the first portion. ... Micron Technology Inc

12/28/17 / #20170372795

Systems and methods for testing a semiconductor memory device having a reference memory array

Semiconductor memory testing devices and methods are disclosed. In one respect, a device is disclosed that includes a first memory cell array having a first bit-line and a plurality of first memory cells coupled to the first bit-line; a second memory cell array having a second bit-line and a plurality of second memory cells coupled to the second bit-line, the number of second memory cells being smaller than that of the first memory cells; a sense amplifier coupled to the first bit-line and a first end of the second bit-line; a word decoder configured to operate the second memory cells responsive to a first test signal; and a transistor coupled to a second end of the second bit-line and operated by a second test signal.. ... Micron Technology Inc

12/28/17 / #20170372784

Connecting memory cells to a data line sequentially while applying a program voltage to the memory cells

Programming methods include applying a voltage to a selected access line commonly connected to a plurality of memory cells, and, while the voltage applied to the selected access line remains at a program voltage without being discharged, electrically connecting a subset of the plurality of memory cells to one data line so that only one memory cell of the subset of the plurality of memory cells is electrically connected to the one data line at a time.. . ... Micron Technology Inc

12/28/17 / #20170372765

Multi-level storage in ferroelectric memory

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. In some examples, multi-level accessing, sensing, and other operations for ferroelectric memory may be based on sensing multiple charges, including a first charge associated with a dielectric of the memory cell and a second charge associated with a polarization of the memory cell. ... Micron Technology Inc

12/28/17 / #20170371811

Systems and devices for accessing a state machine

A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. ... Micron Technology Inc

12/28/17 / #20170371574

Managing host communication with a regulator in a low power mode

A solid-state drive (ssd) includes a connector communicatively coupling the ssd to a host device, a controller coupled to the connector, and a memory device. The ssd also include a regulator configured to receive an instruction to enter a low power mode of the ssd, enter the low power mode upon receipt of the instruction, receive an indication to exit the low power mode, and exit the low power mode upon receipt of the indication.. ... Micron Technology Inc

12/28/17 / #20170371539

Bank to bank data transfer

The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.. ... Micron Technology Inc

12/21/17 / #20170366188

Apparatuses with an embedded combination logic circuit for high speed operations

Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.. ... Micron Technology Inc

12/21/17 / #20170366184

Apparatus and method for standby current control of signal path

Apparatuses and methods for standby current control of a signal path in a semiconductor device are described. An example apparatus includes: first and second logic gates coupled in series; a first circuit coupled between the first logic gate and a power supply line that activates the first logic gate responsive to a first control signal; and a second circuit coupled between the second logic gate and the power supply line that activates the second logic gate responsive to a second control signal that is different from the first control signal.. ... Micron Technology Inc

12/21/17 / #20170365642

Cross-point memory and methods for fabrication of same

The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. ... Micron Technology Inc

12/21/17 / #20170365619

Memory having memory cell string and coupling components

Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described.. ... Micron Technology Inc

12/21/17 / #20170365618

Systems including memory cells on opposing sides of a pillar

Systems including a processor and a memory device in communication with the processor include an array of non-volatile memory cells configured in a nand architecture. The array includes a plurality of series-coupled first non-volatile memory cells, each first non-volatile memory cell curving around a first curved side of a substantially vertical pillar and terminating at an isolation region, and a plurality of series-coupled second non-volatile memory cells, each second non-volatile memory cell curving around a second curved side of the substantially vertical pillar and terminating at the isolation region. ... Micron Technology Inc

12/21/17 / #20170365617

Integrated structures and methods of forming integrated structures

Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. ... Micron Technology Inc

12/21/17 / #20170365615

Floating gate memory cells in vertical memory

Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. ... Micron Technology Inc

12/21/17 / #20170365614

Charge storage apparatus and methods

Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. ... Micron Technology Inc

12/21/17 / #20170365584

Semiconductor device assembly with heat transfer structure formed from semiconductor material

Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. ... Micron Technology Inc

12/21/17 / #20170365580

Semiconductor package and fabrication method thereof

A semiconductor package may include a first logic die and a second logic die located laterally adjacent to the first logic die. A bridge memory die may be coupled to both the first logic die and the second logic die on a first active face of the first logic die and a second active face of the second logic die. ... Micron Technology Inc

12/21/17 / #20170365481

Semiconductor structures

Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate materials, and laterally removing a portion of each of the tier control gate materials to form control gate recesses. A charge blocking material comprising a charge trapping portion is formed on exposed surfaces of the tier dielectric materials and tier control gate materials in the opening. ... Micron Technology Inc

12/21/17 / #20170365360

Plate defect mitigation techniques

Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells. ... Micron Technology Inc

12/21/17 / #20170365358

Methods of operating a memory device

Methods of operating a memory device include comparing an input address to one or more addresses stored in the memory device and indicative of problematic memory cells of the memory device, determining a status value of an indicator corresponding to a matched address if the input address matches a stored address, and storing data corresponding to the input address to a first memory array of the memory device and to a second memory array of the memory device if the indicator has a first status value. Methods may further include storing the data corresponding to the input address to only the first memory array or the second memory array if the indicator has a second status value.. ... Micron Technology Inc

12/21/17 / #20170365356

Shared error detection and correction memory

Apparatuses and methods of sharing error correction memory on an interface chip are described. An example apparatus includes: at least one memory chip having a plurality of first memory cells and an interface chip coupled to the at least one memory chip and having a control circuit and a storage area. ... Micron Technology Inc

12/21/17 / #20170365353

Apparatuses and/or methods for operating a memory cell as an anti-fuse

Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.. . ... Micron Technology Inc

12/21/17 / #20170365345

Fast programming memory device

In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.. . ... Micron Technology Inc

12/21/17 / #20170365344

Methods of operating a memory during a programming operation

Methods of operating a memory include increasing a voltage applied to a first access line from a first voltage to a second voltage higher than the first voltage while applying the first voltage to a second access line, the first access line coupled to a target memory cell of the programming operation and an unselected memory cell not targeted for the programming operation, and the second access line coupled to memory cells not targeted for the programming operation. After increasing the voltage applied to the first access line, increasing the voltage applied to the first access line from the second voltage to a third voltage higher than the second voltage and increasing a voltage applied to the second access line from the first voltage to a fourth voltage higher than the first voltage and lower than the third voltage.. ... Micron Technology Inc

12/21/17 / #20170365343

Boosting channels of memory cells

A method for programming a non-volatile memory device includes concurrently boosting channels of memory cells in a selected memory string and an unselected memory string of the memory device, discharging the boosted channels of the memory cells in the selected memory string, and programming a selected memory cell in the selected memory string after discharging the boosted channels in the selected memory string.. . ... Micron Technology Inc

12/21/17 / #20170365342

Memory as a programmable logic device

Methods for operating a memory, and memory configured to perform similar methods, include programming a first series string of memory cells of a first group of memory cells such that pairs of complementary memory cells have complementary states to provide a first minterm, the first minterm comprising a plurality of first variables wherein each variable is enabled responsive to a state of its respective memory cell, and programming a second series string of memory cells of a second group of memory cells such that pairs of complementary memory cells have complementary states to provide a second minterm, the second minterm comprising the first minterm that is enabled responsive to the state of its respective memory cell, the second minterm further comprising a plurality of second variables that are each enabled responsive to the state of their respective memory cell.. . ... Micron Technology Inc

12/21/17 / #20170365339

Memory programming methods and memory systems

Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. ... Micron Technology Inc

12/21/17 / #20170365323

Memory cell imprint avoidance

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. ... Micron Technology Inc

12/21/17 / #20170365322

Cell-specific reference generation and sensing

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A portion of charge of a memory cell may be captured and, for example, stored using a capacitor or intrinsic capacitance of the memory array that includes the memory cell. ... Micron Technology Inc

12/21/17 / #20170365321

Ferroelectric memory cell sensing

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may maintain a digit line voltage at a ground reference for a duration associated with biasing a ferroelectric capacitor of a memory cell. ... Micron Technology Inc

12/21/17 / #20170365319

Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory

Virtual ground sensing circuits, electrical systems, computing devices, and related methods are disclosed. A virtual ground sensing circuit includes a sense circuit configured to compare a reference voltage potential to a sense node voltage potential, and virtual ground circuitry operably coupled to the sense circuit. ... Micron Technology Inc

12/21/17 / #20170365318

Array data bit inversion

Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. ... Micron Technology Inc

12/21/17 / #20170365310

Comparison operations in memory

The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. ... Micron Technology Inc

12/21/17 / #20170365304

Data gathering in memory

Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of access line. The examples can include storing a second element in memory cells coupled to a second sense line and the plurality of access lines. ... Micron Technology Inc

12/21/17 / #20170365301

Apparatuses and methods for performing compare operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (io) line of a memory array to a voltage. ... Micron Technology Inc

12/21/17 / #20170365299

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. ... Micron Technology Inc

12/21/17 / #20170365298

Interconnections for 3d memory

Apparatuses and methods for interconnections for 3d memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. ... Micron Technology Inc

12/21/17 / #20170364474

Devices for time division multiplexing of state machine engine signals

A device includes a plurality of blocks. Each block of the plurality of blocks includes a plurality of rows. ... Micron Technology Inc

12/21/17 / #20170364444

Cache architecture for comparing data

The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the present disclosure can include an array of memory cells configured to store multiple cache entries per page of memory cells; and sense circuitry configured to determine whether cache data corresponding to a request from a cache controller is located at a location in the array corresponding to the request, and return a response to the cache controller indicating whether cache data is located at the location in the array corresponding to the request.. ... Micron Technology Inc

12/21/17 / #20170364439

Data storage layout

Examples of the present disclosure provide apparatuses and methods for determining a data storage layout. An example apparatus comprising a first address space of a memory array comprising a first number of memory cells coupled to a plurality of sense lines and to a first select line. ... Micron Technology Inc

12/21/17 / #20170364438

Methods of operating a storage device

Methods of operating a storage device include reading first data from a first storage location of a first memory of the storage device, storing the first data to a first storage location of a second memory of the storage device, compressing the first data and storing the compressed first data to a second storage location of the second memory, evaluating the compressed first data to determine if it is deemed compressible, storing the first data from the first storage location of the second memory to a different storage location of the first memory if the compressed first data was determined to not be compressible, and combining the compressed first data with additional compressed data and storing the combined compressed data to a different storage location of the first memory if the compressed first data was determined to be compressible.. . ... Micron Technology Inc

12/21/17 / #20170364337

Method and apparatus for compiling regular expressions

Apparatus, systems, and methods for a compiler are described. One such compiler converts source code into an automaton comprising states and transitions between the states, wherein the states in the automaton include a special purpose state that corresponds to a special purpose hardware element. ... Micron Technology Inc

12/21/17 / #20170364301

Data deduplication

The present disclosure includes devices and methods for data deduplication. One such method includes receiving a write command, transforming data associated with the write command, determining if a transformation value of the data exists in a transformation table, and responsive to a determination that the transformation value does not exist in the transformation table, writing the data associated with the write command to a memory device.. ... Micron Technology Inc

12/21/17 / #20170364268

Memory devices having distributed controller systems

Apparatus including a memory array further include an analog voltage generation circuit, an analog controller, a data cache, a data cache controller, and a master controller. The master controller is configured to generate an indication in response to an interpreted command. ... Micron Technology Inc

12/21/17 / #20170364135

Apparatuses and methods for exiting low power states in memory devices

According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification. ... Micron Technology Inc

12/14/17 / #20170358741

Semiconductor devices with magnetic and attracter materials and methods of fabrication

A magnetic cell includes an attracter material proximate to a magnetic region (e.g., a free region). The attracter material is formulated to have a higher chemical affinity for a diffusible species of a magnetic material, from which the magnetic region is formed, compared to a chemical affinity between the diffusible species and at least another species of the magnetic material. ... Micron Technology Inc

12/14/17 / #20170358737

Magnetic cell structures, and methods of fabrication

A magnetic cell structure comprises a seed material including tantalum, platinum, and ruthenium. The seed material comprises a platinum portion overlying a tantalum portion, and a ruthenium portion overlying the platinum portion. ... Micron Technology Inc

12/14/17 / #20170358629

Phase change memory stack with treated sidewalls

Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. ... Micron Technology Inc

12/14/17 / #20170358628

Cross-point memory and methods for fabrication of same

A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap that includes a buried void. ... Micron Technology Inc

12/14/17 / #20170358627

Select device for memory cell applications

The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first electrode having a particular geometry, a semiconductor material formed on the first electrode and a second electrode having the particular geometry with formed on the semiconductor material, wherein the select device is configured to snap between resistive states in response to signals that are applied to the select device.. ... Micron Technology Inc

12/14/17 / #20170358599

Apparatuses having a ferroelectric field-effect transistor memory array and related method

An apparatus comprises field-effect transistor (fet) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of fet structures, and a ferroelectric material separating the fet structures and the gates. Individual ferroelectric fets (fefets) are formed at intersections of the fet structures, the gates, and the ferroelectric material. ... Micron Technology Inc

12/14/17 / #20170358598

Memory cells comprising a programmable field effect transistor having a reversibly programmable gate insulator

A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different vt's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. ... Micron Technology Inc

12/14/17 / #20170358595

Vertical memory blocks and related devices and methods

Vertical memory blocks for semiconductor devices include a memory cell region including an array of memory cell pillars and at least one via region including a dielectric stack of alternating dielectric materials and at least one conductive via extending through the dielectric stack. Semiconductor devices including a vertical memory block include at least one vertical memory block, which includes slots extending between adjacent memory cells of a three-dimensional array. ... Micron Technology Inc

12/14/17 / #20170358583

Memory device and fabricating method thereof

A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a first active region, a second active region, a gate structure, and a capping layer. ... Micron Technology Inc

12/14/17 / #20170358580

Three-dimensional devices having reduced contact length

Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. ... Micron Technology Inc

12/14/17 / #20170358559

Methods of manufacturing a semiconductor device package including a controller element

Semiconductor device packages include a stack of semiconductor memory devices positioned over an interposer substrate, a controller element, and a redistribution substrate positioned laterally adjacent to the controller element. At least a portion of the controller element is positioned directly between the stack and the interposer substrate. ... Micron Technology Inc

12/14/17 / #20170358556

Semiconductor device assembly with through-mold cooling channel formed in encapsulant

Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. ... Micron Technology Inc

12/14/17 / #20170358547

Semiconductor devices including conductive pillars

A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. ... Micron Technology Inc

12/14/17 / #20170358532

Electronic component of integrated circuitry and a method of forming a conductive via to a region of semiconductor material

An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface. ... Micron Technology Inc

12/14/17 / #20170358370

Ferroelectric memory cell recovery

Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell that is fatigued due to repeated access (read or write) operations. ... Micron Technology Inc

12/14/17 / #20170358366

Inferring threshold voltage distributions associated with memory cells via interpolation

The present disclosure includes apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation. A number of embodiments include determining soft data for a group of memory cells each programmed to one of a number of data states, wherein the soft data comprises a number of different soft data values, determining a quantity of memory cells associated with each of the different soft data values, and inferring at least a portion of a threshold voltage distribution associated with the group of memory cells via an interpolation process using the determined quantities of memory cells associated with each of the different soft data values.. ... Micron Technology Inc

12/14/17 / #20170358359

Methods of programming memory

Methods of programming a memory include applying a programming voltage on an access line selected for a programming operation of a single page of the memory, applying a second voltage on an access line unselected for the programming operation, increasing the programming voltage for a first plurality of steps of the programming operation, and increasing the second voltage for a second plurality of steps of a first portion of the programming operation, then decreasing the second voltage at a particular point of the programming operation after completing the second plurality of steps and before completing the first plurality of steps.. . ... Micron Technology Inc

12/14/17 / #20170358348

Memory device architecture

Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.. . ... Micron Technology Inc

12/14/17 / #20170358347

Apparatuses, devices and methods for sensing a snapback event in a circuit

Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. ... Micron Technology Inc

12/14/17 / #20170358340

Boosting a digit line voltage for a write operation

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. The magnitude of a voltage applied across a ferroelectric capacitor may be dynamically increased during a write operation. ... Micron Technology Inc

12/14/17 / #20170358339

Cell-based reference voltage generation

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first state and a second ferroelectric memory cell may be initialized to a different state. ... Micron Technology Inc

12/14/17 / #20170358338

Half density ferroelectric memory and operation

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. ... Micron Technology Inc

12/14/17 / #20170358336

Stack access control for memory device

Apparatuses and methods including an interface die that interfaces with dice through memory channels are described. An example apparatus includes a first die. ... Micron Technology Inc

12/14/17 / #20170358333

Division operations in memory

Examples of the present disclosure provide apparatuses and methods related to performing division operations in memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a dividend element. ... Micron Technology Inc

12/14/17 / #20170358332

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. ... Micron Technology Inc

12/14/17 / #20170358331

Apparatuses and methods for converting a mask to an index

The present disclosure includes apparatuses and methods related to converting a mask to an index. An example apparatus comprises an array of memory cells and periphery logic configured to: generate an indicator mask by resetting, in response to a first control signal, a second digit of a mask different from a first digit of the mask that is set; and convert, in response to a second control signal, a digit position in the indicator mask of the first digit that is set to an identifier value as an index.. ... Micron Technology Inc

12/14/17 / #20170358328

Apparatus and methods to perform read-while write (rww) operations

Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a plurality of block configurations may be employed. ... Micron Technology Inc

12/14/17 / #20170357870

Descriptor guided fast marching method for analyzing images and systems using the same

Methods and systems for descriptor guided fast marching method based image analysis and associated systems are disclosed. A representative image processing method includes processing an image of a microelectronic device using a fast marching algorithm to obtain arrival time information for the image. ... Micron Technology Inc

12/14/17 / #20170357605

System and method for independent, direct and parallel communication among multiple field programmable gate arrays

Representative embodiments are disclosed for data transfer between field programmable gate arrays (fpgas). A representative system includes: a pcie communication network comprising a pcie switch and a plurality of pcie communication lines; a host computing system coupled to the pcie communication network; a nonblocking crossbar switch; a plurality of memory circuits; and a plurality of field programmable gate arrays, each field programmable gate array configurable for a plurality of data transfers to and from the host computing system and any other field programmable gate array of the plurality of field programmable gate arrays, with each data transfer including a designation of a first memory address, a file size, and a stream number. ... Micron Technology Inc

12/14/17 / #20170357482

Apparatuses and methods for timing domain crossing

Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. ... Micron Technology Inc

12/14/17 / #20170357467

Stripe mapping in memory

Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (raid) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.. ... Micron Technology Inc

12/14/17 / #20170357057

Photonics grating coupler and method of manufacture

A structure for coupling an optical signal between an integrated circuit photonic structure and an external optical fiber is disclosed as in a method of formation. The coupling structure is sloped relative to a horizontal surface of the photonic structure such that light entering or leaving the photonic structure is substantially normal to its upper surface.. ... Micron Technology Inc

12/14/17 / #20170356946

Apparatus and methods for testing devices

The present disclosure includes apparatuses and methods related to test devices, for example testing devices by measuring signals emitted by a device. One example apparatus can include a first portion including a number of sidewalls positioned to at least partially surround a device under test; and a second portion electrically coupled to the first portion, wherein the second portion is configured to move in the x-direction, the y-direction, and z-direction.. ... Micron Technology Inc

12/07/17 / #20170353187

Apparatus and methods for leakage current reduction in integrated circuits

This disclosure relates to leakage current reduction in integrated circuits (ics). In one aspect, an ic can include a digital logic circuit and a polarization circuit. ... Micron Technology Inc

12/07/17 / #20170353183

Semiconductor device including buffer circuit

A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. ... Micron Technology Inc

12/07/17 / #20170352704

Cell pillar structures and integrated flows

Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (sgd), and a memory stack arranged between the source material and the sgd. ... Micron Technology Inc

12/07/17 / #20170352681

Integrated structures comprising charge-storage regions along outer portions of vertically-extending channel material

Some embodiments include an integrated structure having stacked conductive levels. At least some of the conductive levels are wordline levels and include control gate regions of memory cells. ... Micron Technology Inc

12/07/17 / #20170352677

Memory circuitry comprising a vertical string of memory cells and a conductive via and method used in forming a vertical string of memory cells and a conductive via

A method used in forming a vertical string of memory cells and a conductive via comprises forming a first lower opening and a second lower opening into a lower material. A first material is formed within the first and second lower openings. ... Micron Technology Inc

12/07/17 / #20170352645

Thermal pads between stacked semiconductor dies and associated systems and methods

Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. ... Micron Technology Inc

12/07/17 / #20170352644

Apparatuses and methods for scalable memory

Apparatuses and methods are provided for scalable memory. An example apparatus comprises a logic component, a plurality of memory components adjacent to and coupled to one another and the logic component, a plurality of memory component programmable delay lines (pdls), of the plurality of memory component pdls associated with a respective one of the plurality of memory components, and a logic component programmable delay line (lpdl) coupled to the logic component and each of the plurality of memory component pdls.. ... Micron Technology Inc

12/07/17 / #20170352633

Collars for under-bump metal structures and associated systems and methods

The present technology is directed to manufacturing collars for under-bump metal (ubm) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. ... Micron Technology Inc

12/07/17 / #20170352620

Assemblies having shield lines of an upper wiring level electrically coupled with shield lines of a lower wiring level

Some embodiments include an assembly having a first wiring level with a plurality of first shield lines and first signal lines. The first shield lines and first signal lines have first segments extending along a first direction and second segments extending along the first direction and laterally offset from the first segments. ... Micron Technology Inc

12/07/17 / #20170352616

Semiconductor constructions, patterning methods, and methods of forming electrically conductive lines

Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. ... Micron Technology Inc

12/07/17 / #20170352580
12/07/17 / #20170352579
12/07/17 / #20170352578

Methods of forming one or more covered voids in a semiconductor substrate

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. ... Micron Technology Inc

12/07/17 / #20170352577

Methods of forming one or more covered voids in a semiconductor substrate

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. ... Micron Technology Inc

12/07/17 / #20170352563

Systems and methods for wafer alignment

Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. ... Micron Technology Inc

12/07/17 / #20170352431

Memory devices configured to perform leak checks

Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a particular voltage to an unselected access line of a program operation, sensing a current of a selected access line of the program operation while applying the particular voltage to the unselected access line, indicating a fail status of the program operation if an absolute value of the sensed current of the selected access line is greater than a particular current, and proceeding with the program operation if the absolute value of the sensed current of the selected access line is less than a particular current.. . ... Micron Technology Inc

12/07/17 / #20170352429

Memory refresh methods and apparatuses

Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device being powered on, and reprogramming corrected data to the memory device if errors are found in checking the portion of the nonvolatile memory for errors. Other apparatuses and memory refresh methods are disclosed.. ... Micron Technology Inc

12/07/17 / #20170352426

Memory read apparatus and methods

Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. ... Micron Technology Inc

12/07/17 / #20170352421

Memory array with power-efficient read architecture

Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. ... Micron Technology Inc

12/07/17 / #20170352420

Feram-dram hybrid memory

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory cell array, where a first digit line coupled to the first memory cell is coupled to a paging buffer register including a sense amplifier. ... Micron Technology Inc

12/07/17 / #20170352417

Methods and apparatuses having a voltage generator with an adjustable voltage drop for representing a voltage drop of a memory cell and/or a current mirror circuit and replica circuit

Apparatus and methods utilize a replica circuit to generate a voltage for programming of a memory cell, such as a memory cell of a phase-change memory (pcm). Current passing through a circuit including the memory cell to be programmed is mirrored in a scaled or unscaled manner, and provided as an input to the replica circuit. ... Micron Technology Inc

12/07/17 / #20170352416

Apparatuses, memories, and methods for address decoding and selecting an access line

Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. ... Micron Technology Inc

12/07/17 / #20170352414

Phase change memory device

A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. ... Micron Technology Inc

12/07/17 / #20170352411

Apparatuses and methods for bi-directional access of cross-point arrays

The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of accessing memory cells in a cross point memory array. In one aspect, an apparatus comprises a memory array. ... Micron Technology Inc

12/07/17 / #20170352410

Accessing memory cells in parallel in a cross-point array

Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. ... Micron Technology Inc

12/07/17 / #20170352409

Programming memories with stepped programming pulses

Methods of operating a memory device include applying a programming pulse to a plurality of memory cells selected for programming having an initial portion having a first voltage level and a subsequent portion having a second voltage level less than the first voltage level, inhibiting a particular memory cell of the plurality of memory cells from programming during the initial portion of the programming pulse while a different memory cell of the plurality of memory cells is enabled for programming, and inhibiting the different memory cell from programming during the subsequent portion of the programming pulse while the particular memory cell is enabled for programming.. . ... Micron Technology Inc

12/07/17 / #20170352402

Timing control circuit shared by a plurality of banks

Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first memory bank including at least one first sense amplifier that is enabled responsive to a first activation signal; a second memory bank including at least one second sense amplifier that is enabled responsive to a second activation signal; and a control circuit that receives a control signal. ... Micron Technology Inc

12/07/17 / #20170352398

Power reduction for a sensing operation of a memory cell

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may leverage non-volatile memory properties of a ferroelectric capacitor—e.g., that a ferroelectric capacitor may remain polarized at one of two states without a voltage applied across the ferroelectric capacitor—to activate a subset of sensing components corresponding to multiple memory cells with a common word line. ... Micron Technology Inc

12/07/17 / #20170352397

Charge mirror-based sensing for ferroelectric memory

Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a ferroelectric memory cell or cells is described. The scheme employs a charge mirror to extract the full charge difference between the two states of a selected memory cell. ... Micron Technology Inc

12/07/17 / #20170352396

Charge sharing between memory cell plates

Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. ... Micron Technology Inc

12/07/17 / #20170352391

Shifting data

The present disclosure includes apparatuses and methods related to shifting data. A number of embodiments of the present disclosure include an apparatus comprising a shift register comprising an initial stage and a final stage. ... Micron Technology Inc

12/07/17 / #20170352388

Flexible memory system with a controller and a stack of memory

Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. ... Micron Technology Inc

12/07/17 / #20170352387

Interconnection for memory electrodes

Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.. ... Micron Technology Inc

12/07/17 / #20170351780

Inexact search acceleration

A system and method are disclosed for inexact search acceleration using reference data. A representative system includes one or more memory circuits storing a plurality of queries and a fm-index of the reference data; and one or more fpgas configured to select a query; select a substring of the selected query; read a section of the fm-index and calculate a plurality of suffix array intervals for the sub string with a corresponding plurality of prepended characters in a first or next position; read a first or next character in the first or next position of the query and select a suffix array interval for the read first character; determine whether the suffix array interval is valid and whether a beginning of the query has been reached; returning a first search result when the suffix array interval is valid and the beginning of the query has been reached; and returning a second search result that no match of the query with the reference data was found when the suffix array interval is not valid.. ... Micron Technology Inc

12/07/17 / #20170351737

Methods and systems for autonomous memory searching

Methods and systems operate to receive a plurality of search requests for searching a database in a memory system. The search requests can be stored in a fifo queue and searches can be subsequently generated for each search request. ... Micron Technology Inc

12/07/17 / #20170351637

Devices, systems, and methods of reducing chip select

Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (id_a and id_m). ... Micron Technology Inc

12/07/17 / #20170351631

Methods and apparatuses for providing data received by a state machine engine

An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. ... Micron Technology Inc

12/07/17 / #20170351628

Logic component switch

The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses, and methods for controlling logic die circuitries. One example apparatus comprises a logic die including a first serialization/deserialization (serdes) component and a second serdes component coupled to the logic die, and a switch component coupled to the first serdes component and the second serdes component configured to activate one of the number of serdes components.. ... Micron Technology Inc

12/07/17 / #20170351570

Apparatuses and methods for selective determination of data error repair

Apparatuses and methods are described for selective determination of data error repair. An example apparatus includes a memory array and a controller coupled to the memory array. ... Micron Technology Inc

12/07/17 / #20170351458

Multi-partitioning of memories

Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. ... Micron Technology Inc

12/07/17 / #20170351451

Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination

An arbitration system and method is disclosed. The apparatus includes a first and a second memory devices, and a resistor coupled in common to the first and second memory devices, the first memory device includes a first calibration circuit configured to perform a first calibration operation responsive, at least in part, to an external calibration command, the first calibration operation being performed based on the resistor, and the second memory device includes a second calibration circuit configured to perform a second calibration operation responsive, at least in part, to the external calibration command, the second calibration operation being performed based on the resistor after the first calibration operation has finished.. ... Micron Technology Inc

12/07/17 / #20170351433

Memory protocol

The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can perform operations on a number of block buffers of the memory device based on commands received from a host using a block configuration register, wherein the operations can read data from the number of block buffers and write data to the number of block buffers on the memory device.. ... Micron Technology Inc

11/30/17 / #20170346471

Synchronized semiconductor device with phase adjustment circuit

According to one embodiment, a synchronous semiconductor device is disclosed. According to this embodiment, the synchronous semiconductor device includes a pulse width detection circuit to provide detection information responsive to a plurality of delay amounts being different from one another and at least one of a high pulse width and a low pulse width of a first clock signal. ... Micron Technology Inc

11/30/17 / #20170346007

Resistive memory cell

Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. ... Micron Technology Inc

11/30/17 / #20170345996

Semiconductor devices with magnetic regions and stressor structures, and methods of operation

A magnetic cell core includes at least one stressor structure proximate to a magnetic region (e.g., a free region or a fixed region). The magnetic region may be formed of a magnetic material exhibiting magnetostriction. ... Micron Technology Inc

11/30/17 / #20170345972

Light emitting diodes and associated methods of manufacturing

Light emitting diodes and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode (led) includes a substrate, a semiconductor material carried by the substrate, and an active region proximate to the semiconductor material. ... Micron Technology Inc

11/30/17 / #20170345910

Platinum-containing constructions, and methods of forming platinum-containing constructions

Some embodiments include constructions which have platinum-containing structures. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures and across metal oxide. ... Micron Technology Inc

11/30/17 / #20170345831

Ferroelectric devices and methods of forming ferroelectric devices

Some embodiments include a ferroelectric device comprising ferroelectric material adjacent an electrode. The device includes a semiconductor material-containing region along a surface of the ferroelectric material nearest the electrode. ... Micron Technology Inc

11/30/17 / #20170345578

Apparatuses, multi-chip modules and capacitive chips

Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and dielectric layers in a capacitor stack. ... Micron Technology Inc

11/30/17 / #20170345573

Structure and methods of forming the structure (as amended)

Capacitors, apparatus including a capacitor, and methods for forming a capacitor are provided. One such capacitor may include a first conductor a second conductor above the first conductor, and a dielectric between the first conductor and the second conductor. ... Micron Technology Inc

11/30/17 / #20170345511

Pre-compensation of memory threshold voltage

Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state. The program verify operation including: an intermediate verify corresponding to an amount of aggression to apply a voltage to the data node when performing the intermediate verify, based on the at least one bit of the second target state stored in the aggressor data latch; and a program verify corresponding to a condition of no aggression to apply to the voltage to the data node when performing the program verify, based on the at least one bit of the second target state stored in the aggressor data latch. ... Micron Technology Inc

11/30/17 / #20170345506

Methods of operating memory under erase conditions

Methods of operating a memory include applying a first voltage level to a first semiconductor material of a first conductivity type forming a channel region for a memory cell of a string of series-connected memory cells, wherein the first semiconductor material is electrically connected to a second semiconductor material of the first conductivity type through a first conductive material of a second conductivity type different than the first conductivity type, and wherein the second semiconductor material forms a channel region for a different memory cell of the string of series-connected memory cells; and applying a second voltage level, less than the first voltage level, to a control gate of the memory cell and applying a third voltage level, less than the second voltage level, to a control gate of the different memory cell while applying the first voltage level to the first semiconductor material.. . ... Micron Technology Inc

11/30/17 / #20170345501

Methods for backup sequence using three transistor memory cell devices

Methods for a backup sequence includes reading first data from a first data memory to a page buffer, copying the first data from the page buffer to a backup page comprising three transistor memory cell devices, erasing the first data memory, programming the first data from the page buffer to a second data memory, and erasing the backup page.. . ... Micron Technology Inc

11/30/17 / #20170345499

Multi-function resistance change memory cells and apparatuses including the same

Various embodiments comprise apparatuses having a number of memory cells including drive circuitry to provide signal pulses of a selected time duration and/or amplitude, and an array of resistance change memory cells electrically coupled to the drive circuitry. The resistance change memory cells may be programmed for a range of retention time periods and operating speeds based on the received signal pulse. ... Micron Technology Inc

11/30/17 / #20170345498

Apparatuses and methods including memory access in cross point memory

Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. ... Micron Technology Inc

11/30/17 / #20170345495

Methods, articles, and devices for pulse adjustment to program a memory cell

Embodiments disclosed herein may relate to adjusting an aspect of a programming pulse for one or more memory cells, such as based at least in part on one or more detected programmed resistance values for the one or more memory cells.. . ... Micron Technology Inc

11/30/17 / #20170345493

Apparatuses and methods for accessing memory cells

Apparatuses and methods for accessing a memory cell are described. An example apparatus includes a first voltage circuit coupled to a node and is configured to provide a first voltage to the node and includes a second voltage circuit coupled to a node and is configured to provide a second voltage to the node. ... Micron Technology Inc

11/30/17 / #20170345481

Performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells, sensing circuitry coupled to the array of memory cells via a sense line, and a controller coupled to the array of memory cells and the sensing circuitry. ... Micron Technology Inc

11/30/17 / #20170345468

Asynchronous/synchronous interface

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. ... Micron Technology Inc

11/30/17 / #20170345467

Indirect register access method and system

Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. ... Micron Technology Inc

11/30/17 / #20170345463

Power delivery circuitry

Embodiments of the present disclosure are directed to a system that includes a memory device. The memory device includes a memory system and an energy storage device including a capacitor. ... Micron Technology Inc

11/30/17 / #20170344299

Memory device error based adaptive refresh rate and methods

One embodiment describes an automation system including a sensor that determines operational parameters of the automation system; one or more actuators that perform control actions during operation of the automation system; and a control system communicatively coupled to the sensor and the one or more actuators. The control system includes memory that stores the operational parameters; determines occurrence of memory errors in data stored in the memory; determines error parameters that indicate characteristics of the memory errors; determines error-corrected data by correcting the memory errors based at least in part on the error parameters; adaptively adjusts a refresh rate used to refresh stored data in the memory based at least in part on the error parameters; and determines control commands instructing the one or more actuators to perform the control actions by processing the error-corrected data.. ... Micron Technology Inc

11/23/17 / #20170338412

Semiconductor devices, memory devices, and related methods

Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. ... Micron Technology Inc

11/23/17 / #20170338411

Memory cells, memory arrays, and methods of forming memory cells and arrays

Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. ... Micron Technology Inc

11/23/17 / #20170338280

Array of memory cells and methods of forming an array of memory cells

A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. ... Micron Technology Inc

11/23/17 / #20170338266

Color filter array, imagers and systems having same, and methods of fabrication and use thereof

A pixel cell with a photosensitive region formed in association with a substrate, a color filter formed over the photosensitive region, the color filter comprising a first material layer and a second material layer formed in association with the first shaping material layer.. . ... Micron Technology Inc

11/23/17 / #20170338181

Integrated circuit structures comprising conductive vias and methods of forming conductive vias

A method of forming conductive vias comprises forming a first via opening and a second via opening within a substrate. First conductive material of a first conductivity is formed into the first and second via openings. ... Micron Technology Inc

11/23/17 / #20170338121

Method of forming a semiconductor device including a pitch multiplication

Disclosed herein is a manufacturing method of a semiconductor device that includes forming first and second layers over an underlying martial such that the first layer is between the underlying material and the second layer, forming a third layer over the second layer, forming first and second core portions apart from each other over the third layer, forming a gap portion between the first and the second core portions; and removing the second and the third layers by using the first and the second core portions and the gap portion as a mask to expose a part of the first layer.. . ... Micron Technology Inc

11/23/17 / #20170337982

Semiconductor device and control method of the same

A semiconductor device comprises a bit determination circuit to count the number of bits at a first level in an input address signal formed of a plurality of bits and to output a result indicating whether or not a value of the count exceeds a predetermined determination threshold value, as a bit determination result signal, and a selection control circuit to select a non-volatile program element to be cut off, based on the bit determination result signal and the address signal. Additional apparatus and methods are described.. ... Micron Technology Inc

11/23/17 / #20170337974

Random telegraph signal noise reduction scheme for semiconductor memories

Embodiments are provided that include a method including providing a first voltage to a selected memory cell and providing a second voltage to the selected memory cell during an operation. The first voltage is greater in magnitude than the second voltage and the first voltage is applied for a shorter duration than the second voltage. ... Micron Technology Inc

11/23/17 / #20170337954

Apparatuses and methods for shifting data

The present disclosure includes apparatuses and methods related to shifting data. A number of embodiments include an apparatus comprising pre-charge lines and n-channel transistors without complementary p-channel transistors. ... Micron Technology Inc

11/23/17 / #20170337953

Apparatuses and methods for scatter and gather

The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. ... Micron Technology Inc

11/23/17 / #20170337951

Apparatuses and methods for performing intra-module databus inversion operations

Apparatuses, memory modules, and methods for performing intra-module data bus inversion operations are described. An example apparatus include a memory module comprising a data bus inversion (dbi) and buffer circuit and a plurality of memories. ... Micron Technology Inc

11/23/17 / #20170337325

Hardware acceleration of short read mapping for genomic and other types of analyses

A scalable fpga-based solution to the short read mapping problem in dna sequencing is disclosed which greatly accelerates the task of aligning short length reads to a known reference genome. A representative system comprises one or more memory circuits storing a plurality of short reads and a reference genome sequence; and one or more field programmable gate arrays configured to select a short read; to extract a plurality of seeds from the short read, each seed comprising a genetic subsequence of the short read; for each seed, to determine at least one candidate alignment location (cal) in the reference genome sequence to form a plurality of cals; for each cal, to determine a likelihood of the short read matching the reference genome sequence in the vicinity of the cal; and to select one or more cals having the currently greater likelihood of the short read matching the reference genome sequence.. ... Micron Technology Inc

11/23/17 / #20170337128

Swap operations in memory

Examples of the present disclosure provide apparatuses and methods related to performing swap operations in a memory. An example apparatus might include a first group of memory cells coupled to a first sense line and configured to store a first element. ... Micron Technology Inc

11/23/17 / #20170337126

Apparatuses and methods for memory device as a store for program instructions

The present disclosure includes apparatuses and methods related to a memory device as the store to program instructions. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. ... Micron Technology Inc

11/23/17 / #20170336989

Apparatuses and methods for parallel writing to multiple memory device structures

The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. ... Micron Technology Inc

11/23/17 / #20170336820

Apparatuses and related methods for staggering power-up of a stack of semiconductor dies

An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. ... Micron Technology Inc

11/23/17 / #20170336470

Methods of testing semiconductor devices

Apparatus for testing semiconductor devices comprising die stacks, the apparatus comprising a substrate having an array of pockets in a surface thereof arranged to correspond to conductive elements protruding from a semiconductor device to be tested. The pockets include conductive contacts with traces extending to conductive pads, which may be configured as test pads, jumper pads, edge connects or contact pads. ... Micron Technology Inc

11/16/17 / #20170332030

Pixel array with shared pixels in a single column and associated devices, systems, and methods

Pixel array with shared pixels in a single column and associated devices, systems, and methods are disclosed herein. In one embodiment, a pixel array includes a floating diffusion region, a source a source follower transistor having a gate coupled to the floating diffusion region, a plurality of first pixels associated with a first color, and a plurality of second pixels associated with a second color different than the first color and arranged in a single column with the first pixels. ... Micron Technology Inc

11/16/17 / #20170331036

Semiconductor structures including liners and related methods

A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. ... Micron Technology Inc

11/16/17 / #20170331035

Thermally optimized phase change memory cells and methods of fabricating the same

A thermally optimized phase change memory cell includes a phase change material element disposed between first and second electrodes. The second electrode includes a thermally insulating region having a first thermal resistivity over the first electrode and a metallic contact region interposed between the phase change material element and the thermally insulating region, where the metallic contact layer has a second thermal resistivity lower than the first thermal resistivity.. ... Micron Technology Inc

11/16/17 / #20170331032

Magnetic tunnel junctions

A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and comprising magnetic reference material, and a non-magnetic tunnel insulator material between the first and second electrodes. The magnetic reference material of the second electrode comprises a synthetic antiferromagnetic construction comprising two spaced magnetic regions one of which is closer to the tunnel insulator material than is the other. ... Micron Technology Inc

11/16/17 / #20170330882

Semiconductor memory device having coplanar digit line contacts and storage node contacts in memory array and method for fabricating the same

A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. ... Micron Technology Inc

11/16/17 / #20170330881

Array of cross point memory cells and methods of forming an array of cross point memory cells

A method of forming an array of cross point memory cells comprises using two, and only two, masking steps to collectively pattern within the array spaced lower first lines, spaced upper second lines which cross the first lines, and individual programmable devices between the first lines and the second lines where such cross that have an upwardly open generally u-shape vertical cross-section of programmable material laterally between immediately adjacent of the first lines beneath individual of the upper second lines. Arrays of cross point memory cells independent of method of manufacture are disclosed.. ... Micron Technology Inc

11/16/17 / #20170330784

Semiconductor structures comprising polymeric materials

Methods of forming semiconductor structures include providing a polymeric material over a carrier substrate, bonding another substrate to the polymeric material, and lowering a temperature of the polymeric material to below about 15° c. To separate the another substrate from the carrier substrate. ... Micron Technology Inc

11/16/17 / #20170330627

Memory cell programming

Methods of operating a memory include applying a programming pulse having a particular voltage level to a selected access line connected to selected memory cells of a programming operation, assigning the selected memory cells to respective groups of memory cells each having a different range of threshold voltages, determining a respective value of vgvt for each group of memory cells, applying a subsequent programming pulse to the selected access line and having a particular voltage level determined in response to the value of vgvt for a particular group of memory cells, enabling the selected memory cells of the particular group of memory cells for programming while the subsequent programming pulse has the particular voltage level, and repeating for a next group of memory cells.. . ... Micron Technology Inc

11/16/17 / #20170330626

3d nand memory z-decoder

Apparatus and methods are disclosed, including an apparatus having first and second units of vertically arranged strings of memory cells, each unit including multiple tiers of a semiconductor material, each tier including an access line of at least one memory cell and a channel of a decoder transistor, wherein the channel of the decoder transistor of each of the multiple tiers of the first unit of memory cells is coupled to the channel of the decoder transistor of a corresponding tier of the second unit of memory cells. Methods of forming such apparatus are disclosed, as well as methods of operation, and other embodiments.. ... Micron Technology Inc

11/16/17 / #20170329671

Data storage error protection

Apparatuses and methods for data storage error protection are described. One example apparatus for data storage error protection includes an array of memory cells arranged in a first dimension and a second dimension. ... Micron Technology Inc

11/16/17 / #20170329577

Signed division in memory

Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a sense line and to a number of first access lines. ... Micron Technology Inc

11/16/17 / #20170329545

Systems and methods for packing data in a scalable memory system protocol

A memory device includes a memory component that stores data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. ... Micron Technology Inc

11/16/17 / #20170329534

Apparatuses and methods for variable latency memory operations

Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to provide first information during a variable latency period indicating the memory is not available to perform a command, wherein the first information is indicative of a remaining length of the variable latency period, the remaining length is one of a relatively short, normal, or long period of time, the memory configured to provide second information in response to receiving the command after the latency period.. ... Micron Technology Inc

11/16/17 / #20170329363

Serial peripheral interface and methods of operating same

Serial peripheral interfaces and methods of operating the same are provided. An apparatus can have a serial peripheral interface (spi) including a first command state machine (csm), and a second csm.. ... Micron Technology Inc

11/09/17 / #20170324034

Resistive memory having confined filament formation

Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening.. ... Micron Technology Inc

11/09/17 / #20170324032

Method, system, and device for l-shaped memory component

Embodiments disclosed herein may relate to forming reduced size storage components in a cross-point memory array. In an embodiment, a storage cell comprising an l-shaped storage component having an approximately vertical portion extending from a first electrode positioned below the storage material to a second electrode positioned above and/or on the storage component. ... Micron Technology Inc

11/09/17 / #20170324014

Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated systems and methods

Solid-state transducers (“ssts”) and vertical high voltage ssts having buried contacts are disclosed herein. An sst die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. ... Micron Technology Inc

11/09/17 / #20170323979

Integrated structures having gallium-containing regions

Some embodiments include an integrated structure having a gallium-containing material between a charge-storage region and a semiconductor-containing channel region. Some embodiments include an integrated structure having a charge-storage region under a conductive gate, a tunneling region under the charge-storage region, and a semiconductor-containing channel region under the tunneling region. ... Micron Technology Inc

11/09/17 / #20170323927

Magnetic devices with magnetic and getter regions and methods of formation

A magnetic cell includes magnetic, secondary oxide, and getter seed regions. During formation, a diffusive species is transferred from a precursor magnetic material to the getter seed region, due to a chemical affinity elicited by a getter species. ... Micron Technology Inc

11/09/17 / #20170323866

Semiconductor package with multiple coplanar interposers

A semiconductor package includes a first interposer, a second interposer, and a gap between the first interposer and the second interposer. The first interposer and the second interposer are coplanar. ... Micron Technology Inc

11/09/17 / #20170323828

Microfeature workpieces and methods for forming interconnects in microfeature workpieces

Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. The microfeature workpieces may have a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side. ... Micron Technology Inc

11/09/17 / #20170323802

Semiconductor die assemblies with heat sink and associated systems and methods

Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. ... Micron Technology Inc

11/09/17 / #20170323675

Apparatuses and methods for targeted refreshing of memory

Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. ... Micron Technology Inc

11/09/17 / #20170323668

Memories having select devices between access lines and in memory cells formed of a same type of circuit element

Memories may include a first select device connected between a first access line and a second access line, and a plurality of memory cells. Each memory cell of the plurality of memory cells may be connected between the second access line and a respective third access line of a plurality of third access lines. ... Micron Technology Inc

11/09/17 / #20170322784

Dynamic arrays and overlays with bounds policies

Systems and methods are provided for writing code to access data arrays. One aspect provides a method of accessing a memory array. ... Micron Technology Inc

11/09/17 / #20170322749

Memory access techniques in memory devices with multiple partitions

Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (c/a) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. ... Micron Technology Inc

11/09/17 / #20170322726

Non-deterministic memory protocol

The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. ... Micron Technology Inc

11/09/17 / #20170320154

Microfeature workpieces having alloyed conductive structures, and associated methods

Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a bond pad of a microfeature workpiece, with the volume of material including a first metallic constituent and the bond pad including a second constituent. ... Micron Technology Inc

10/26/17 / #20170310325

Circuits, apparatuses, and methods for frequency division

Circuits, apparatuses, and methods are disclosed for frequency division. In one such example circuit, a frequency divider is configured to alternate between providing a common frequency clock signal as an output clock signal through a first circuit responsive to a reference clock signal and providing a reduced frequency clock signal as the output clock signal through a second circuit responsive to the reference clock signal. ... Micron Technology Inc

10/26/17 / #20170309820

Memory cell materials and semiconductor device structures

A method of forming a memory cell material comprises forming a first portion of a dielectric material over a substrate by atomic layer deposition. Discrete conductive particles are formed on the first portion of the dielectric material by atomic layer deposition. ... Micron Technology Inc

10/26/17 / #20170309818

Memory cells including dielectric materials, memory devices including the memory cells, and methods of forming same

A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. ... Micron Technology Inc

10/26/17 / #20170309680

Magnetic memory cells and semiconductor devices comprising the magnetic memory cells

Memory cells are disclosed. Magnetic regions within the memory cells include an alternating structure of magnetic sub-regions and coupler sub-regions. ... Micron Technology Inc

10/26/17 / #20170309641

Semiconductor apparatus with multiple tiers, and methods

Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. ... Micron Technology Inc

10/26/17 / #20170309607

Method for embedding silicon die into a stacked package

Several embodiments of microelectronic configurations with logic components and associated methods of manufacturing are disclosed herein. In one embodiment, the configuration includes a substrate with a recess, a first die carried by the substrate wherein the die substantially covers the recess, and a logic component carried by the die in a location exposed by the recess. ... Micron Technology Inc

10/26/17 / #20170309508

Interfaces and die packages, and appartuses including the same

A memory device includes a memory die package including a plurality of memory dies, an interface device including an interface circuit, and a memory controller configured to control the interface with control data received from at least one of the plurality of memory dies. The interface device of the memory device is configured to divide and multiplex an io channel between the memory die package and the memory controller into more than one channel using the control data receive from the at least one of the plurality of memory dies. ... Micron Technology Inc

10/26/17 / #20170309341

Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line

Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.. ... Micron Technology Inc

10/26/17 / #20170309333

Operational signals generated from capacitive stored charge

Methods, a memory device, and a system. Are disclosed. ... Micron Technology Inc

10/26/17 / #20170309331

Apparatuses and methods of reading memory cells based on response to a test pulse

The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of reading memory cells in a memory array, such as a cross point memory array. In one aspect, the method comprises providing a memory array comprising a memory cell in one of a plurality of states. ... Micron Technology Inc

10/26/17 / #20170309323

Methods and apparatuses including command delay adjustment circuit

Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.. ... Micron Technology Inc

10/26/17 / #20170309322

Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays

Some embodiments include a ferroelectric transistor. The transistor has gate dielectric material configured as a first container, with the first container having a first inner surface. ... Micron Technology Inc

10/26/17 / #20170309320

Methods and apparatuses including command delay adjustment circuit

Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.. ... Micron Technology Inc

10/26/17 / #20170309319

Apparatuses and methods for detecting frequency ranges corresponding to signal delays of conductive vias

Apparatuses for monitoring a signal on a conductive via are described. An example apparatus includes: a controller, a first conductive via, a second conductive via and an evaluation circuit. ... Micron Technology Inc

10/26/17 / #20170309318

Apparatuses and methods for memory operations having variable latencies

Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and perform a memory operation responsive to the memory instruction. ... Micron Technology Inc

10/26/17 / #20170309316

Apparatuses and methods for performing corner turn operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and a sense line. ... Micron Technology Inc

10/26/17 / #20170309315

Simulating access lines

Examples of the present disclosure provide apparatuses and methods for simulating access lines in a memory. An example method can include receiving a first bit-vector and a second bit-vector in a format associated with storing the first bit-vector in memory cells coupled to a first access line and a first number of sense lines and storing the second bit-vector in memory cells coupled to a second access line and the first number of sense lines. ... Micron Technology Inc

10/26/17 / #20170309314

Apparatuses and methods for performing corner turn operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and one of the plurality of sense lines. ... Micron Technology Inc

10/26/17 / #20170308385

Overflow detection and correction in state machine engines

State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. ... Micron Technology Inc

10/26/17 / #20170308382

Apparatuses and methods for memory operations having variable latencies

Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. ... Micron Technology Inc

10/12/17 / #20170295619

Self-identifying solid-state transducer modules and associated systems and methods

Self-identifying solid-state transducer (sst) modules and associated systems and methods are disclosed herein. In several embodiments, for example, an sst system can include a driver and at least one sst module electrically coupled to the driver. ... Micron Technology Inc

10/12/17 / #20170294511

Methods, devices, and systems related to forming semiconductor power devices with a handle substrate

Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a semiconductor device assembly that includes a handle substrate, a semiconductor structure having a first side and a second side opposite the first side, and an intermediary material between the semiconductor structure and the handle substrate. ... Micron Technology Inc

10/12/17 / #20170294447

Three-dimensional structured memory devices

A 3d structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. ... Micron Technology Inc

10/12/17 / #20170294414

Computer modules with small thicknesses and associated methods of manufacturing

Computer modules with small thicknesses and associated methods of manufacturing are disclosed. In one embodiment, the computer modules can include a module substrate having a module material and an aperture extending at least partially into the module material. ... Micron Technology Inc

10/12/17 / #20170294383

Semiconductor device structures including staircase structures, and related methods and electronic systems

A semiconductor device structure comprises stacked tiers each comprising a conductive structure and an insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and an opening laterally adjacent a first side of the at least one staircase structure and extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. Conductive structures of the stacked tiers laterally extend from the steps of the at least one staircase structure completely across a second side of the at least one staircase structure opposing the first side to form continuous conductive paths laterally extending completely across the stacked tiers. ... Micron Technology Inc

10/12/17 / #20170294317

Patterns forming method

A patterns forming method begins with performing a lithography process on a photoresist film with a photomask having first apertures in a first mask region and second apertures in a second mask region to respectively form first main features and dummy features, on which the second mask region is located between the border of the photomask and the first mask region, and a size of each of the first apertures is greater than a size of each of the second apertures. Subsequently, a material is filled into the first main features to respectively form second main features and into the dummy features to seal the dummy features. ... Micron Technology Inc

10/12/17 / #20170294235

Memory programming methods and memory systems

Memory programming methods and memory systems are described. One example memory programming method includes programming a plurality of main cells of a main memory and erasing a plurality of second main cells of the main memory. ... Micron Technology Inc

10/12/17 / #20170294233

Boosted channel programming of memory

Methods of operating a memory include generating a programming pulse for a programming operation having a plurality of steps prior to a program voltage level of the programming pulse, and generating a subsequent programming pulse for the programming operation having the plurality of steps prior to a program voltage level of the subsequent programming pulse, wherein a particular step of the plurality of steps of the programming pulse has a different magnitude than a corresponding step of the plurality of steps of the subsequent programming pulse.. . ... Micron Technology Inc

10/12/17 / #20170294220

Dynamic adjustment of memory cell digit line capacitance

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. ... Micron Technology Inc

10/12/17 / #20170294219

Methods of operating ferroelectric memory cells, and related ferroelectric memory cells and capacitors

Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. ... Micron Technology Inc

10/12/17 / #20170293434

Span mask generation

Examples of the present disclosure provide apparatuses and methods for span mask generation. An example method comprises creating, using sensing circuitry, a number of bit vectors, wherein each of the number of bit vectors includes a repeating pattern based on a size of the number of bit vectors and a particular mask depth.. ... Micron Technology Inc

10/05/17 / #20170288682

Clock signal and supply voltage variation tracking

Embodiments disclosed herein provide an apparatus comprising a clock generation circuit configured to generate a first signal for a first time period and a second signal for a second time period, a charge pump circuit coupled to the clock generation circuit and configured to generate a first voltage and a second voltage based, at least in part, on the first time period and the second time period, and a comparison circuit coupled to the charge pump circuit, the comparison circuit configured to compare a difference between the first voltage and the second voltage with a threshold value and generate an active tracking enablement signal in response to determining that the difference between the first and second voltages exceeds the threshold value.. . ... Micron Technology Inc

10/05/17 / #20170288542

Apparatuses and methods for a load current control circuit for a source follower voltage regulator

According to one embodiment of this disclosure, an apparatus is disclosed. The apparatus includes a voltage regulator configured to produce a regulated voltage, a plurality of current circuits coupled in parallel between an output node and a power node, each of the plurality of current circuits including first and second transistors coupled in series, the first transistor of each of the plurality of current circuits being biased with the regulated voltage, and a control circuit configured to activate the second transistor of selected one or ones of the plurality of current circuits responsive, at least in part, to a voltage at the output node.. ... Micron Technology Inc

10/05/17 / #20170288177

Pre-encapsulated lead frames for microelectronic device packages, and associated methods

Pre-encapsulated lead frames suitable for use in microelectronic device packages are disclosed. Individual lead frames can include a set of multiple lead fingers arranged side by side with neighboring lead fingers spaced apart from each other by a corresponding gap. ... Micron Technology Inc

10/05/17 / #20170288110

High-voltage solid-state transducers and associated systems and methods

High-voltage solid-state transducer (sst) devices and associated systems and methods are disclosed herein. An sst device in accordance with a particular embodiment of the present technology includes a carrier substrate, a first terminal, a second terminal and a plurality of sst dies connected in series between the first and second terminals. ... Micron Technology Inc

10/05/17 / #20170288089

Light emitting diodes with n-polarity and associated methods of manufacturing

Light emitting diodes (“leds”) with n-polarity and associated methods of manufacturing are disclosed herein. In one embodiment, a method for forming a light emitting diode on a substrate having a substrate material includes forming a nitrogen-rich environment at least proximate a surface of the substrate without forming a nitrodizing product of the substrate material on the surface of the substrate. ... Micron Technology Inc

10/05/17 / #20170287980

Thermal insulation for three-dimensional memory arrays

Methods, systems, and devices for a three-dimensional memory array are described. Memory cells may transform when exposed to elevated temperatures, including elevated temperatures associated with a read or write operation of a neighboring cell, corrupting the data stored in them. ... Micron Technology Inc

10/05/17 / #20170287864

Bond pad with micro-protrusions for direct metallic bonding

A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (tsv) extending through the semiconductor substrate, and a copper pad electrically connected to the tsv and having a coupling side. ... Micron Technology Inc

10/05/17 / #20170287857

Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods

The present technology is directed to manufacturing semiconductor dies with under-bump metal (ubm) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (ubm) structures on a semiconductor die comprises constructing a ubm pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. ... Micron Technology Inc

10/05/17 / #20170287719

Methods of forming memory cells with air gaps and other low dielectric constant materials

Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. ... Micron Technology Inc

10/05/17 / #20170287565

Apparatuses and methods using dummy cells programmed to different states

Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string, and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.. ... Micron Technology Inc

10/05/17 / #20170287548

Apparatuses and methods for refresh control

Apparatuses and methods of for refresh control of a semiconductor device are described. An example apparatus includes a command control circuit that provides a plurality of pulses on a first control signal in series responsive to a plurality of refresh commands issued in series; a signal generation circuit that produces a plurality of pulses on a second control signal in sequence; and a refresh control circuit that receives two or more of the plurality of pulses on the first control signal during a period of time between one pulse and a succeeding pulse of the plurality of pulses on the second control signal, disables refresh operations responsive to at least one of the two or more of the plurality of first control signal and executes a refresh operation responsive to remaining one or more pulses of the two or more of the plurality of pulses on the first control signal.. ... Micron Technology Inc

10/05/17 / #20170287547

Semiconductor device

A semiconductor device according to an aspect of the present invention has: a plurality of memory cells mc; a plurality of word lines wl each coupled to a corresponding one of the plurality of memory cells mc; and a control circuit that intermittently monitors accesses to the plurality of word lines wl, stores/erases some captured row-addresses in a first number of registers, and detects, by comparison with stored addresses, in response to a first number of accesses to one of the word lines wl in a first period of time. According to the present invention, access histories can be precisely analyzed by a small-scale circuit configuration, and measures against, for example, the row hammer problem, etc. ... Micron Technology Inc

10/05/17 / #20170287544

Refresh circuitry

The present disclosure includes apparatuses and methods related to refresh circuitry. An example apparatus can include a memory array including a main portion and a redundant portion. ... Micron Technology Inc

10/05/17 / #20170287541

Charge extraction from ferroelectric memory cell

A ferroelectric capacitor of a memory cell may be in electronic communication with a sense capacitor through a digit line. The digit line may be virtually grounded during memory cell sensing, limiting or avoiding voltage drop across the digit line, and allowing all or substantially all of the stored charge of the ferroelectric capacitor to be extracted and transferred to the sense capacitor. ... Micron Technology Inc

10/05/17 / #20170287531

Apparatuses and methods for controlling data timing in a multi-memory system

Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. ... Micron Technology Inc

10/05/17 / #20170287530

Vertical bit vector shift in memory

Examples of the present disclosure provide apparatuses and methods for vertical bit vector shift in a memory. An example method comprises storing a vertical bit vector of data in a memory array, wherein the vertical bit vector is stored in memory cells coupled to a sense line and a plurality of access lines and the vertical bit vector is separated by at least one sense line from a neighboring vertical bit vector; and performing, using sensing circuitry, a vertical bit vector shift of a number of elements of the vertical bit vector.. ... Micron Technology Inc

10/05/17 / #20170287529

Apparatuses and methods for compensating for process, voltage, and temperature variation in a memory

Systems and methods are described for compensating for variations in process, voltage, temperature, or combinations thereof in an apparatus. An example apparatus may be a memory circuit. ... Micron Technology Inc

10/05/17 / #20170286286

Memory devices including dynamic superblocks, and related methods and electronic systems

A memory device includes a memory array having non-volatile memory cells, and a memory controller configured to dynamically construct a superblock during each garbage collection process based, at least in part, on an amount of valid data present in each physical block of the memory array. Another memory device includes physical blocks of memory cells and a memory controller configured to construct a new superblock dynamically each time garbage collection occurs for the physical blocks regardless of whether any physical blocks are determined to be bad. ... Micron Technology Inc

10/05/17 / #20170286217

Error correction code (ecc) operations in memory

The present disclosure includes apparatuses and methods for ecc operation associated with memory. One example apparatus comprises a controller configured to perform an error correction code (ecc) operation on a codeword stored in the memory, wherein the codeword includes a first number of ecc bits and the first number of ecc bits are generated based on an encoding matrix, wherein each row of the encoding matrix has an odd number of bits having a binary value of 1.. ... Micron Technology Inc

10/05/17 / #20170285988

Memory power coordination

The present disclosure includes apparatuses and methods related to bank coordination in a memory device. A number of embodiments include a method comprising concurrently performing a memory operation by a threshold number of memory regions, and executing a command to cause a budget area to perform a power budget operation associated with the memory operation.. ... Micron Technology Inc

10/05/17 / #20170285938

Latching data for output at an edge of a clock signal generated in response to an edge of another clock signal

In an example, a method of operating a memory device to latch data for output from the memory device may include generating a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, generating a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and latching the data in response to the second clock edge of the first clock signal for output from the memory device.. . ... Micron Technology Inc

10/05/17 / #20170283954

Methods of forming interconnects and semiconductor structures

A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. ... Micron Technology Inc

09/28/17 / #20170278848

Semiconductor device having a memory cell and method of forming the same

There is provided an apparatus includes a substrate having a main surface, a wordline buried in the substrate and a bitline buried in a shallower area than the wordline in the substrate.. . ... Micron Technology Inc

09/28/17 / #20170278775

Semiconductor dies with recesses, associated leadframes, and associated systems and methods

Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one embodiment includes a semiconductor die having a first surface and a second surface facing opposite from the first surface, with the first surface having a die recess. ... Micron Technology Inc

09/28/17 / #20170278584

Apparatus and methods for debugging on a host and memory device

The present disclosure includes apparatus and methods for debugging on a host and memory device. An example apparatus comprises a memory device having an array of memory cells. ... Micron Technology Inc

09/28/17 / #20170278572

Devices including memory arrays, row decoder circuitries and column decoder circuitries

Some embodiments include a device having an array of memory cells, a memory control unit at least partially under the array, row decoder circuitry in data communication with the memory control unit, and column decoder circuitry in data communication with the memory control unit. Some embodiments include a device having an array of memory cells, row decoder circuitry and column decoder circuitry. ... Micron Technology Inc

09/28/17 / #20170278568

Cross-point memory compensation

The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. ... Micron Technology Inc

09/28/17 / #20170278559

Apparatuses and methods for data movement

The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. ... Micron Technology Inc

09/28/17 / #20170278002

Adaptive content inspection

Methods and apparatus are provided involving adaptive content inspection. In one embodiment, a content inspection processor may identify information with respect to input data and provide the information to a host controller. ... Micron Technology Inc

09/28/17 / #20170277637

Apparatuses and methods for cache operations

The present disclosure includes apparatuses and methods for cache operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. ... Micron Technology Inc

09/28/17 / #20170277581

Apparatus and methods for debugging on a memory device

The present disclosure includes apparatus and methods for debugging on a memory device. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. ... Micron Technology Inc

09/28/17 / #20170277449

Read cache memory

The present disclosure includes methods and apparatuses for read cache memory. One apparatus includes a read cache memory apparatus comprising a first dram array, a first and a second nand array, and a controller configured to manage movement of data between the dram array and the first nand array, and between the first nand array and the second nand array.. ... Micron Technology Inc

09/28/17 / #20170277440

Apparatuses and methods to determine timing of operations

The present disclosure includes apparatuses and methods to determine timing of operations. An example method includes performing a first operation type that uses a shared resource in a memory device. ... Micron Technology Inc

09/28/17 / #20170277433

Mask patterns generated in memory from seed vectors

The present disclosure includes apparatuses and methods related to mask patterns generated in memory from seed vectors. An example method includes performing operations on a plurality of data units of a seed vector and generating, by performance of the operations, a vector element in a mask pattern.. ... Micron Technology Inc

09/21/17 / #20170271582

Structures incorporating and methods of forming metal lines including carbon

Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. ... Micron Technology Inc

09/21/17 / #20170271411

Semiconductor constructions, electronic systems, and methods of forming cross-point memory arrays

Some embodiments include vertical stacks of memory units, with individual memory units each having a memory element, a wordline, a bitline and at least one diode. The memory units may correspond to cross-point memory, and the diodes may correspond to band-gap engineered diodes containing two or more dielectric layers sandwiched between metal layers. ... Micron Technology Inc

09/21/17 / #20170271228

Carrierless chip package for integrated circuit devices, and methods of making same

Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each of the plurality of wire bonds being conductively coupled to a conductive exposed portion, a portion of the conductive exposed portion being positioned in the plane defined by the backside surface, and an encapsulant material positioned adjacent the integrated circuit chip and the plurality of wire bonds.. ... Micron Technology Inc

09/21/17 / #20170271010

Feram-dram hybrid memory

Methods of operating a memory include determining indications of programming voltages sufficient to program respective groups of memory cells of a plurality of groups of memory cells to a particular range of threshold voltages, applying a stepped programming pulse to a selected access line connected to each memory cell of the plurality of groups of memory cells, and enabling each group of memory cells for programming when a voltage level of the stepped programming pulse corresponds to the respective indication of the programming voltage sufficient to program that group of memory cells to the particular range of threshold voltages.. . Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory cell array, where a first digit line coupled to the first memory cell is coupled to a paging buffer register including a sense amplifier. ... Micron Technology Inc

09/21/17 / #20170271006

Memory cells having a plurality of resistance variable materials

Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. ... Micron Technology Inc

09/21/17 / #20170270992

Ferroelectric memory cell apparatuses and methods of operating ferroelectric memory cells

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. ... Micron Technology Inc

09/21/17 / #20170270991

Ferroelectric memory cell sensing

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may maintain a digit line voltage at a ground reference for a duration associated with biasing a ferroelectric capacitor of a memory cell. ... Micron Technology Inc

09/21/17 / #20170270990

Cell-specific reference generation and sensing

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A portion of charge of a memory cell may be captured and, for example, stored using a capacitor or intrinsic capacitance of the memory array that includes the memory cell. ... Micron Technology Inc

09/21/17 / #20170270989

Apparatuses and methods for setting a signal in variable resistance memory

An example of a method reads a spin torque transfer (stt) memory cell, and writes the stt memory cell using information obtained during the reading of the stt memory cell to set a pulse to write the stt memory cell. An example of an apparatus includes a stt memory cell and read/write circuitry coupled to the stt memory cell to determine a read current (iread) through the stt memory cell and to set a pulse to write the stt memory cell using iread. ... Micron Technology Inc

09/21/17 / #20170270983

Apparatuses and methods for concurrently accessing different memory planes of a memory

Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. ... Micron Technology Inc

09/21/17 / #20170270976

Methods and apparatuses for providing a program voltage responsive to a voltage determination

Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. ... Micron Technology Inc

09/21/17 / #20170269997

Semiconductor device having error correction code (ecc) circuit

An apparatus may comprise an ecc circuit configured to receive read data from a memory cell array to correct, an error bit contained in a data portion of the read data responsive, at least in part, to a parity portion of the read data, to generate a plurality of first error determination signals and a plurality of second error determination signals. Each of the plurality of first error determination signals provided in common to n data terminals and corresponding to an associated one of burst data of m bits. ... Micron Technology Inc

09/21/17 / #20170269903

Signed division in memory

Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a first access line and a number of sense lines. ... Micron Technology Inc

09/21/17 / #20170269865

Apparatuses and methods for operations using compressed and decompressed data

The present disclosure includes apparatuses and methods for operations using compressed and decompressed data. An example method includes receiving compressed data to a processing in memory (pim) device and decompressing the compressed data on the pim device.. ... Micron Technology Inc

09/21/17 / #20170269625

Apparatuses and methods for power regulation based on input power

Apparatuses and methods for power regulation based on input power using circuitry are disclosed herein. An example apparatus may include a reference circuit configured to receive a first voltage and a second voltage and to provide an output reference voltage at an output node having a value equal to the second voltage subtracted from the first voltage. ... Micron Technology Inc

09/21/17 / #20170269299

Apparatuses and methods for photonic communication and photonic addressing

Apparatuses and methods for photonic communication and photonic addressing are disclosed herein. An example apparatus includes a plurality of photonic sources, a plurality of memory die, a logic die, each of the plurality of photonic sources provides a photonic signal of a different wavelength and are provided to a first photonic path. ... Micron Technology Inc

09/14/17 / #20170265319

Folding device stand for portable devices

A device stand for a portable device, comprising a foldable extension leg which supports the portable device at a cable connection instead of directly supporting the portable device itself. In one or more embodiments, the device stand can be connected to a storage device such as a flash drive, or can directly incorporate a storage device into its form.. ... Micron Technology Inc

09/14/17 / #20170264312

Read threshold calibration for ldpc

Apparatuses and methods for soft read threshold location calibration are provided. One example method can include selecting read threshold sets (rtss), and determining log-likelihood-ratios (llrs) based on a number of decisions that correspond to each bin associated with the selected rtss. ... Micron Technology Inc

09/14/17 / #20170264277

Apparatuses and methods for adjusting timing of signals

Apparatuses and methods for adjusting timing of signals are described herein. An example apparatus may include a first signal adjustment cell configured to receive a first clock signal and to adjust skew of rising or falling edges of the first clock signal based on a first control signal. ... Micron Technology Inc

09/14/17 / #20170264273

Apparatuses and methods for voltage buffering

An apparatuses and methods for buffering a voltage from a circuit without current drive ability are described. An example apparatus includes a voltage buffer that includes two identical stages. ... Micron Technology Inc

09/14/17 / #20170263865

Buried low-resistance metal word lines for cross-point variable-resistance material memories

Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. ... Micron Technology Inc

09/14/17 / #20170263862

Conductive hard mask for memory device formation

Methods, systems, and devices for memory arrays that use a conductive hard mask during formation and, in some cases, operation are described. A hard mask may be used to define features or components during the numerous material formation and removal steps used to create memory cells within a memory array. ... Micron Technology Inc

09/14/17 / #20170263685

Constructions comprising stacked memory arrays

Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. ... Micron Technology Inc

09/14/17 / #20170263684

Replacement materials processes for forming cross point memory

Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. ... Micron Technology Inc

09/14/17 / #20170263683

Three dimensional memory array with select device

Three dimensional memory arrays and methods of forming the same are provided. An example three dimensional memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines such that the at least one conductive extension intersects each of the plurality of first conductive lines. ... Micron Technology Inc

09/14/17 / #20170263563

Semiconductor constructions

Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. ... Micron Technology Inc

09/14/17 / #20170263556

Conductive structures, systems and devices including conductive structures and related methods

Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. ... Micron Technology Inc

09/14/17 / #20170263552

Semiconductor device structures

A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. ... Micron Technology Inc

09/14/17 / #20170263469

Semiconductor package with sidewall-protected rdl interposer

A semiconductor package includes a redistribution layer (rdl) interposer having a first side, a second side opposite to the first side, and a vertical sidewall extending between the first side and the second side; at least one semiconductor die mounted on the first side of the rdl interposer; a molding compound disposed on the first side and covering the at least one semiconductor die and the vertical sidewall of the rdl interposer; and a plurality of solder bumps or solder balls mounted on the second side of the rdl interposer.. . ... Micron Technology Inc

09/14/17 / #20170263467

Methods of forming a portion of a memory array having a conductor having a variable concentration of germanium

An embodiment of a method of forming a portion of a memory array includes forming a conductor with a concentration of germanium that decreases with an increasing thickness of the conductor, removing a portion of the conductor at a rate governed by the concentration of germanium to form a tapered first opening through the conductor, removing a sacrificial material below the conductor to form a second opening contiguous with the tapered first opening, and forming a semiconductor in the contiguous first and second openings, wherein a portion of the semiconductor pinches off within the first opening adjacent an upper surface of the conductor before the contiguous first and second openings are completely filled with the semiconductor.. . ... Micron Technology Inc

09/14/17 / #20170263456

Methods of forming nanostructures having low defect density

A method of forming a nanostructure comprises forming self-assembled nucleic acids on at least a portion of a substrate. The method further comprises contacting the self-assembled nucleic acids on the at least a portion of a substrate with a solution comprising at least one repair enzyme to repair defects in the self-assembled nucleic acids. ... Micron Technology Inc

09/14/17 / #20170263306

Apparatuses and methods for logic/memory devices

Apparatuses and methods are provided for logic/memory devices. An example apparatus comprises a plurality of memory components adjacent to and coupled to one another. ... Micron Technology Inc

09/14/17 / #20170263304

Memory cell sensing with storage component isolation

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be selected using a selection component that is in electronic communication with a sense amplifier and a ferroelectric capacitor of a ferroelectric memory cell. ... Micron Technology Inc

09/14/17 / #20170263303

Parallel access techniques within memory sections through section independence

A memory device having a plurality sections of memory cells, such as ferroelectric memory cells (hybrid ram (hram) cells) may provide for concurrent access to memory cells within independent sections of the memory device. A first memory cell may be activated, and it may be determined that a second memory cell is independent of the first memory cell. ... Micron Technology Inc

09/14/17 / #20170263302

Offset compensation for ferroelectric memory cell sensing

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Offsets in the threshold voltage of switching components (e.g., transistors) connected to digit lines may be compensated by using various operating techniques or additional circuit components, or both. ... Micron Technology Inc

09/14/17 / #20170263292

Apparatus for power management

Apparatus include an array of memory cells, a controller to perform access operations on the array of memory cells, a clock signal node, a counter having an input selectively connected to the clock signal node, and a clock generator having an output connected to the input of the counter.. . ... Micron Technology Inc

09/14/17 / #20170262669

Systems and methods to determine kinematical parameters using rfid tags

Systems and methods to determine kinematical parameters of physical objects using radio frequency identification (rfid) tags attached to the objects. In one embodiment, one of a population of rfid tags is selectively instructed by an rfid reader to backscatter the interrogating electromagnetic wave and thus allow the rfid reader to measure the position, speed, acceleration, and/or jerk of the object to which the tag is attached. ... Micron Technology Inc

09/14/17 / #20170262376

Memory having a static cache and a dynamic cache

The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (slc) cache and a second portion configured to operate as a dynamic slc cache when the entire first portion of the memory has data stored therein.. ... Micron Technology Inc

09/14/17 / #20170262369

Apparatuses and methods for cache invalidate

The present disclosure includes apparatuses and methods for cache invalidate. An example apparatus comprises a bit vector capable memory device and a channel controller coupled to the memory device. ... Micron Technology Inc

09/14/17 / #20170262222

Memory system data management

The present disclosure includes apparatuses and methods for memory system data management. A number of embodiments include writing data from a host to a buffer in the memory system, receiving, at the buffer, a notification from a memory device in the memory system that the memory device is ready to receive data, sending at least a portion of the data from the buffer to the memory device, and writing the portion of the data to the memory device.. ... Micron Technology Inc

09/14/17 / #20170261956

Counter operation in a state machine lattice

Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. ... Micron Technology Inc

09/14/17 / #20170261929

Method, apparatus and system providing holographic layer as micro-lens and color filter array in an imager

A method, apparatus, and system that provides a holographic layer as a micro-lens array and/or a color filter array in an imager. The method of writing the holographic layer results in overlapping areas in the hologram for corresponding adjacent pixels in the imager which increases collection of light at the pixels, thereby increasing quantum efficiency.. ... Micron Technology Inc

09/07/17 / #20170256710

Methods for forming narrow vertical pillars and integrated circuit devices having the same

In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. ... Micron Technology Inc

09/07/17 / #20170256551

Semiconductor device structures including staircase structures, and related methods and electronic systems

A semiconductor device structure comprises stacked tiers each comprising at least one conductive structure and at least one insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and at least one opening extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. The at least one conductive structure of each of the stacked tiers extends continuously from at least one of the steps of the at least one staircase structure and around the at least one opening to form at least one continuous conductive path extending completely across each of the stacked tiers. ... Micron Technology Inc

09/07/17 / #20170256529

Apparatuses and methods for semiconductor circuit layout

Apparatuses including circuit layout regions of a semiconductor device and methods of designing the circuit layout regions of a semiconductor device are described. An example apparatus includes a first layout region including a first transistor area including at least one first transistor, at least one contact in proximity to the first transistor area, and a first resistor area comprising at least one first resistor coupled to the at least one first transistor. ... Micron Technology Inc

09/07/17 / #20170256528

Methods of making semiconductor device packages and related semiconductor device packages

Methods of fabricating a semiconductor device package may involve providing a fan out wafer including semiconductor-device-package locations at a base level. Laterally offset semiconductor dice may be stacked at least some semiconductor-device-package locations of the fan out wafer to expose bond pads at a lateral periphery of each of the laterally offset semiconductor dice. ... Micron Technology Inc

09/07/17 / #20170256527

Semiconductor memory device including output buffer

A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module substrate and coupled to the line pattern, and a termination resister on the module substrate and coupled to the line pattern, the termination resistor being located between the first and second semiconductor chips.. . ... Micron Technology Inc

09/07/17 / #20170256501

Methods of forming semiconductor devices including determining misregistration between semiconductor levels and related apparatuses

A method of determining a lateral misregistration between levels of a semiconductor structure comprises imaging at least one first alignment mark in a first level of the structure and at least one second alignment mark in a second level of the structure. A digital image of the first and second alignment marks is formed, each of which are defined by a set of points having an x-value and a y-value. ... Micron Technology Inc

09/07/17 / #20170256490

Low capacitance through substrate via structures

Apparatuses and methods are disclosed herein for the formation of low capacitance through substrate via structures. An example apparatus includes an opening formed in a substrate, wherein the opening has at least one sidewall, a first dielectric at least formed on the sidewall of the opening, a first conductor at least formed on the first dielectric, a second dielectric at least formed on the first conductor, and a second conductor at least formed on a sidewall of the second dielectric.. ... Micron Technology Inc

09/07/17 / #20170256452

Methods of forming through substrate interconnects

A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. ... Micron Technology Inc

09/07/17 / #20170256417

Method of forming patterns

A substrate having a target material layer is provided. A first hard mask layer, a second hard mask layer, and a photoresist layer are formed on the target material layer. ... Micron Technology Inc

09/07/17 / #20170256319

Apparatuses and methods for performing multiple memory operations

The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. ... Micron Technology Inc

09/07/17 / #20170256300

Ground reference scheme for a memory cell

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. ... Micron Technology Inc

09/07/17 / #20170255878

Space efficient random forests implementation utilizing automata processors

An apparatus includes a processing resource configured to receive a feature vector of a data stream. The feature vector includes a set of feature values. ... Micron Technology Inc

09/07/17 / #20170255249

Apparatuses and methods of entering unselected memories into a different power mode during multi-memory operation

Disclosed are examples of apparatuses including memory devices and systems comprising memories sharing a common enable signal, wherein the memories may be put into different power modes. Example methods for setting the different power modes of the memories are disclosed. ... Micron Technology Inc

08/31/17 / #20170250711

Multi channel memory with flexible code-length ecc

Apparatuses and methods for error correction and detection of data from memory on a plurality of channels are described. An example apparatus includes: a first memory cell array including first input/output nodes; a second memory cell array including second input/output nodes and third input/output nodes; a first error correcting code (ecc) control circuit including fourth input/output nodes and fifth input/output nodes; and a second ecc control circuit including sixth input/output nodes coupled respectively to the third input/output nodes of the second memory cell array. ... Micron Technology Inc

08/31/17 / #20170250689

Apparatuses and methods for level shifting

Apparatuses and methods for level shifting in a semiconductor device are described. An example apparatus includes: a splitter circuit that operates on a first voltage potential to produce a first signal having a first polarity and a second signal having a second polarity that is substantially opposite to the first polarity; an one-shot pulse circuit that operates on the first voltage potential to produce a first one-shot pulse signal responsive to the first signal and a second one-shot pulse signal responsive to the second signal; and a logic circuit configured to operate on a second voltage potential to produce a third signal responsive to the first and second one-shot pulse signals, the second voltage potential being different from the first voltage potential.. ... Micron Technology Inc

08/31/17 / #20170250341

Memory arrays and methods of forming memory arrays

Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines over the first series of access/sense lines and which extend along a second direction substantially orthogonal to the first direction, and memory cells vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. ... Micron Technology Inc

08/31/17 / #20170250313

Solid-state radiation transducer devices having at least partially transparent buried-contact elements, and associated systems and methods

Solid-state radiation transducer (ssrt) devices having buried contacts that are at least partially transparent and associated systems and methods are disclosed herein. An ssrt device configured in accordance with a particular embodiment can include a radiation transducer including a first semiconductor material, a second semiconductor material, and an active region between the first semiconductor material and the second semiconductor material. ... Micron Technology Inc

08/31/17 / #20170250190

Memory array having connections going through control gates

Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. ... Micron Technology Inc

08/31/17 / #20170250110

Methods for isolating portions of a loop of pitch-multiplied material and related structures

Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. ... Micron Technology Inc

08/31/17 / #20170249985

Current sense amplifiers, memory devices and methods

A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. ... Micron Technology Inc

08/31/17 / #20170249984

Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes

Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. ... Micron Technology Inc

08/31/17 / #20170249274

High speed, parallel configuration of multiple field programmable gate arrays

Representative embodiments are disclosed for a rapid and highly parallel configuration process for field programmable gate arrays (fpgas). In a representative method embodiment, using a host processor, a first configuration bit image for an application is stored in a host memory; one of more fpgas are configured with a communication functionality such as pcie using a second configuration bit image stored in a nonvolatile memory; a message is transmitted by the host processor to the fpgas, usually via pcie lines, with the message comprising a memory address and also a file size of the first configuration bit image in the host memory; using a dma engine, each fpga obtains the first configuration bit image from the host memory and is then configured using the first configuration bit image. ... Micron Technology Inc

08/31/17 / #20170249253

Microprocessor architecture having alternative memory access paths

The present invention is directed to a system and method which employ two memory access paths: 1) a cache-access path in which block data is fetched from main memory for loading to a cache, and 2) a direct-access path in which individually-addressed data is fetched from main memory. The system may comprise one or more processor cores that utilize the cache-access path for accessing data. ... Micron Technology Inc

08/31/17 / #20170249211

Redundant array of independent nand for a three-dimensional memory array

The present disclosure includes a redundant array of independent nand for a three dimensional memory array. A number of embodiments include a three-dimensional array of memory cells, wherein the array includes a plurality of pages of memory cells, a number of the plurality of pages include a parity portion of a redundant array of independent nand (rain) stripe, and the parity portion of the rain stripe in each respective page comprises only a portion of that respective page.. ... Micron Technology Inc

08/24/17 / #20170243921

Methods of forming vertical field-effect transistor with selfaligned contacts for memory devices with planar periphery/array and intermediate structures formed thereby

Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. ... Micron Technology Inc

08/24/17 / #20170243758

Removing polysilicon

Methods include exposing polysilicon to an aqueous composition comprising nitric acid, poly-carboxylic acid and ammonium fluoride, and removing a portion of the polysilicon selective to an oxide using the aqueous composition.. . ... Micron Technology Inc

08/24/17 / #20170243644

Refresh architecture and algorithm for non-volatile memories

Methods and systems to refresh a nonvolatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.. ... Micron Technology Inc

08/24/17 / #20170243631

Method and apparatus for controlling access to a common bus by multiple components

Apparatuses and methods for controlling access to a common bus including a plurality of memory devices coupled to a common bus, wherein individual ones of the plurality of memory devices are configured to access the common bus responsive to a strobe signal, and a strobe line driver programmed with a first delay associated with a combination of a first command type and a first one of the plurality of memory devices to provide a first strobe signal to the first one of the plurality of memory devices, and further programmed with a second delay associated with a combination of a second command type and a second one of the plurality of memory devices to provide a second strobe signal to the second one of the plurality of memory devices.. . ... Micron Technology Inc

08/24/17 / #20170243623

Modified decode for corner turn

Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an array of memory cell and decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element. ... Micron Technology Inc

08/24/17 / #20170242902

Data transfer with a bit vector operation device

Examples of the present disclosure provide apparatuses and methods for direct data transfer. An example method comprises transferring data between a first device and a second device, wherein the first device is a bit vector operation device, and transforming the data using a data transform engine (dte) by rearranging the data to enable the data to be stored on the first device when transferring the data between the second device and first memory device.. ... Micron Technology Inc

08/24/17 / #20170242747

Error rate reduction

The present disclosure includes apparatuses and methods for error rate reduction. One example method comprises adding an amount of error rate reduction (err) data to an amount of received user data, and writing the amount of user data along with the amount of err data to a memory.. ... Micron Technology Inc

08/24/17 / #20170242623

Apparatuses and methods for multiple address registers for a solid state device

The present disclosure includes apparatuses, systems, and methods related to multiple address registers for a solid state device (ssd). An example apparatus includes a controller including a plurality of base address registers (bars) each including same addresses for data storage in a same memory resource and an ssd that includes the same memory resource.. ... Micron Technology Inc

08/24/17 / #20170242190

Apparatuses and methods for photonic communication and photonic addressing

Apparatuses and methods for photonic communication and photonic addressing are disclosed herein. An example apparatus includes a photonic source layer that provides a plurality of photonic sources, each at a different wavelength, a plurality of second layers, and a third layer. ... Micron Technology Inc

08/17/17 / #20170237435

Apparatuses and methods for voltage level control

Apparatuses for voltage level control in a semiconductor device are described. An example apparatus includes: a plurality of circuits coupled in parallel between first and second nodes, the first node being supplied with a first voltage; and a voltage supply circuit that supplies the second node with one of second and third voltages, the first voltage being greater than the second voltage, and the second voltage being greater than the third voltage. ... Micron Technology Inc

08/17/17 / #20170236976

Solid state lighting devices with improved contacts and associated methods of manufacturing

Solid state lighting (“ssl”) devices with improved contacts and associated methods of manufacturing are disclosed herein. In one embodiment, an ssl device includes an ssl structure having a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. ... Micron Technology Inc

08/17/17 / #20170236828

Memory cells

A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. ... Micron Technology Inc

08/17/17 / #20170236804

Apparatuses and methods for internal heat spreading for packaged semiconductor die

Apparatuses and methods for internal heat spreading for packaged semiconductor die are disclosed herein. An example apparatus may include a plurality of die in a stack, a bottom die supporting the plurality of die, a barrier and a heat spreader. ... Micron Technology Inc

08/17/17 / #20170236744

Array of gated devices and methods of forming an array of gated devices

An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. ... Micron Technology Inc

08/17/17 / #20170236597

Selectors on interface die for memory device

Apparatuses including an interface chip that interfaces with dice through memory channels are described. An example apparatus includes: an interface chip that interfaces with a plurality of dice through a plurality of memory channels, each of the dice comprising a plurality of memory cells, and the interface chip comprising a test circuit. ... Micron Technology Inc

08/17/17 / #20170236589

Memory devices with a connecting region having a band gap lower than a band gap of a body region

Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. ... Micron Technology Inc

08/17/17 / #20170236584

Memory cell architecture for multilevel cell programming

Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary memory elements, which may include phase change material. ... Micron Technology Inc

08/17/17 / #20170236565

Loop structure for operations in memory

Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might also include a controller configured to cause sensing circuitry to iterate through a plurality of first elements and a plurality of second elements via a loop structure to perform an operation using the plurality of first elements and the plurality of second elements, wherein a conditional statement associated with the loop structure is used to determine whether at least one of a plurality of bits stored as an iterator mask has a particular bit-value. ... Micron Technology Inc

08/17/17 / #20170236564

Data gathering in memory

Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of access line. The examples can include storing a second element in memory cells coupled to a second sense line and the plurality of access lines. ... Micron Technology Inc

08/17/17 / #20170236562

Read threshold voltage selection

Apparatuses and methods for read threshold voltage selection are provided. One example method can include setting a first soft read threshold voltage and a second soft read threshold voltage based on a difference between a first number of memory cells that are read as being programmed to a first state when read using a first threshold voltage and a second number of memory that are read as being programmed to the first state when read using another threshold voltage.. ... Micron Technology Inc

08/17/17 / #20170236560

Semiconductor device with single ended main i/o line

Apparatuses included a single-ended main input/output line in a semiconductor device are described. An example apparatus includes: a pair of differential data lines coupled to a sense amplifier; a single-ended data line; a first transistor coupled between the one of the pair of differential data lines and the power line and coupled to the single-ended data line at a control node thereof; a second transistor coupled between the single-ended data line and the power line and coupled to the one of the pair of differential data lines at a control node thereof; and a third transistor coupled between the single-ended data line and the other of the pair of differential data lines.. ... Micron Technology Inc

08/17/17 / #20170235637

High performance memory controller

A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. ... Micron Technology Inc

08/17/17 / #20170235584

Distributed input/output virtualization

The present disclosure includes apparatuses and methods related to distributed input/output (i/o) virtualization. A number of embodiments include an apparatus comprising a host computing device, a distributed virtualization controller (dvc) disposed on the host computing device, and a virtualized input/output (i/o) device in communication with the dvc.. ... Micron Technology Inc

08/17/17 / #20170235515

Apparatuses and methods for data movement

The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. ... Micron Technology Inc

08/10/17 / #20170229758

Systems and methods to selectively connect antennas to receive and backscatter radio frequency signals

Systems and methods to selectively attach and control antennas via diodes. In one embodiment, a system includes: a reader having a plurality of reader antennas of different polarizations to transmit radio frequency signals; and at least one radio frequency device. ... Micron Technology Inc

08/10/17 / #20170229644

Methods, apparatuses, and circuits for programming a memory device

Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.. . ... Micron Technology Inc

08/10/17 / #20170229516

Methods of forming metal on inhomogeneous surfaces and structures incorporating metal on inhomogeneous surfaces

The disclosed technology relates to integrate circuits, including memory devices. A method of forming an integrated circuit comprises providing a surface comprising a first region and a second region, wherein the first region is formed of a different material than the second region. ... Micron Technology Inc

08/10/17 / #20170229470

Integrated structures and methods of forming vertically-stacked memory cells

Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. ... Micron Technology Inc

08/10/17 / #20170229439

Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths

Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. ... Micron Technology Inc

08/10/17 / #20170229183

Fast programming memory device

In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.. . ... Micron Technology Inc

08/10/17 / #20170229180

Memory devices with a transistor that selectively connects a data line to another data line and methods for programming and sensing

In an example, a memory device has a first string of memory cells selectively connected to a first data line, a second string of memory cells selectively connected to a second data line, and a transistor that selectively connects the first data line to the second data line.. . ... Micron Technology Inc

08/10/17 / #20170229175

Memory systems and memory programming methods

Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state.. ... Micron Technology Inc

08/10/17 / #20170229165

Semiconductor device

Disclosed herein is a semiconductor device that includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command: and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle, to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.. ... Micron Technology Inc

08/10/17 / #20170228284

Methods of operating memory including receipt of ecc data

Methods of operating a memory, including receiving first data to be written to an array of memory cells of the memory, receiving error correction code (ecc) data corresponding to the first data, and receiving a flag having a value. Such methods further include storing the first data, the ecc data and the flag to the array of memory cells without performing error correction on the first data using the ecc data if the flag has a first value, and if the flag has a second value different than the first value and the first data does not contain an error. ... Micron Technology Inc

08/10/17 / #20170228268

Command line output redirection

A method including invoking, via an application, a call of a command line utility; providing, via the application, an identifier in the call of the command line utility, where the identifier comprises an operating system controlled memory location; storing output from the command line utility in operating system shared memory at the operating system controlled memory location identified by the identifier; and retrieving, by the application, the command line utility output from the operating system shared memory at the operating system controlled memory location identified by the identifier.. . ... Micron Technology Inc

08/10/17 / #20170228192

Apparatuses and methods for partitioned parallel data movement

The present disclosure includes apparatuses and methods for partitioned parallel data movement. An example apparatus includes a memory device that includes a plurality of partitions, where each partition of the plurality of partitions includes a subset of a plurality of subarrays of memory cells. ... Micron Technology Inc

08/10/17 / #20170228010

Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination

An arbitration system and method is disclosed. The apparatus includes first and second memory devices and a resistor coupled in common to the first and second memory devices, the first memory device including a first calibration circuit configured to perform, when activated, a first calibration operation based on the resistor and a first arbiter configured to activate the first calibration circuit responsive, at least in part, to an assertion of a first command or keep the first calibration circuit inactive irrespective of the assertion of the first command.. ... Micron Technology Inc

08/10/17 / #20170227975

Apparatuses and methods for providing constant current

An apparatus is described comprising a bandgap reference circuit comprising: an amplifier including first and second inputs and an output; and a bandgap transistor coupled to the output of the amplifier at a control electrode thereof, the bandgap transistor being further coupled commonly to the first and second inputs of the amplifier at a first electrode thereof to form a feedback path. The apparatus further comprises a resistor coupled to the first electrode of the bandgap transistor.. ... Micron Technology Inc

08/03/17 / #20170222663

Progressive effort decoder architecture

A memory device may include memory components to store data. The memory device may also include a processor that may decode a codeword associated with the data. ... Micron Technology Inc

08/03/17 / #20170222111

Solid-state radiation transducer devices having flip-chip mounted solid-state radiation transducers and associated systems and methods

Solid-state radiation transducer (ssrt) devices and methods of manufacturing and using ssrt devices are disclosed herein. One embodiment of the ssrt device includes a radiation transducer (e.g., a light-emitting diode) and a transmissive support assembly including a transmissive support member, such as a transmissive support member including a converter material. ... Micron Technology Inc

08/03/17 / #20170221965

Methods of forming phase change memory apparatuses

Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. ... Micron Technology Inc

08/03/17 / #20170221873

Apparatuses and methods for forming die stacks

Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base die onto the temporary adhesive, curing the temporary adhesive, forming a die stack that includes the base die, activating a release layer disposed on the substrate, wherein the release layer is between the substrate and the temporary adhesive, removing the die stack from the substrate, and removing the temporary adhesive from the die stack.. ... Micron Technology Inc

08/03/17 / #20170221588

Semiconductor device including a roll call circuit for outputting addresses of defective memory cells

A semiconductor device that includes a plurality of memory cells assigned with addresses that are different from each other, a redundant memory cell replacing a defective memory cell among the memory cells, a fuse circuit storing an address of the defective memory cell, an access control circuit accessing the redundant memory cell when the address of the defective memory cell stored in the fuse circuit is supplied, and a roll call circuit outputting the address of the defective memory cell to outside the semiconductor device in a serial manner.. . ... Micron Technology Inc

08/03/17 / #20170221565

Erasable block segmentation for memory

Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of the block of memory corresponds to a respective one of a number of segmented sources. ... Micron Technology Inc

08/03/17 / #20170221561

Memories having a shared resistance variable material

Memories having a plurality of resistive storage elements in a shared resistance variable material, a plurality of select devices coupled to the plurality of resistive storage elements in a one-to-one relationship and sense circuitry coupled to the plurality of select devices.. . ... Micron Technology Inc

08/03/17 / #20170221542

Cell-based reference voltage generation

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first state and a second ferroelectric memory cell may be initialized to a different state. ... Micron Technology Inc

08/03/17 / #20170221536

Methods and apparatuses for modulating threshold voltages of memory cells

Methods and apparatuses for increasing the voltage budget window of a memory array are disclosed. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. ... Micron Technology Inc

08/03/17 / #20170221533

Device having multiple channels with calibration circuit shared by multiple channels

An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. ... Micron Technology Inc

08/03/17 / #20170221532

System and method of command based and current limit controlled memory device power up

Devices and systems for powering up a memory device, for example, are disclosed. One such memory device includes power up circuitry configured to receive an external power supply and to provide an internal power supply to the memory device upon receipt of a command. ... Micron Technology Inc

08/03/17 / #20170220516

Memory device for a hierarchical memory architecture

A hierarchical memory device having multiple interfaces with different memory formats includes a phase change memory (pcm). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure with other memories. ... Micron Technology Inc

08/03/17 / #20170220411

Memory device having address and command selectable capabilities

Subject matter disclosed herein relates to memory management, and more particularly to partitioning a memory based on memory attributes.. . ... Micron Technology Inc

08/03/17 / #20170219104

Three-way valve and method for using the same

A three-way valve includes a sample port acting as a dual port, a sensor port and a purge port. The purge port selectively provides the sample port with a purge gas when an etching chamber is idle and the sensor port is not in use.. ... Micron Technology Inc

07/27/17 / #20170214403

Apparatus and method for standby current control of signal path

Apparatuses and methods for standby current control of a signal path in a semiconductor device are described. An example apparatus includes: first and second logic gates coupled in series; a first circuit coupled between the first logic gate and a power supply line that activates the first logic gate responsive to a first control signal; and a second circuit coupled between the second logic gate and the power supply line that activates the second logic gate responsive to a second control signal that is different from the first control signal.. ... Micron Technology Inc

07/27/17 / #20170213885

Semiconductor structure and fabricating method thereof

A semiconductor structure and a method of fabricating thereof are provided. The semiconductor structure includes a substrate and a capacitor structure. ... Micron Technology Inc

07/27/17 / #20170213837

Method of fabricating semiconductor memory device having enlarged cell contact area

A semiconductor substrate is provided. Active areas and trench isolation regions are formed. ... Micron Technology Inc

07/27/17 / #20170213834

Semiconductor memory device having enlarged cell contact area and method of fabricating the same

A memory array includes a semiconductor substrate having thereon a plurality of active areas and trench isolation regions between the active areas. Buried word lines are disposed in the semiconductor substrate. ... Micron Technology Inc

07/27/17 / #20170213801

Method for manufacturing a package-on-package assembly

A method for fabricating a package-on-package assembly is provided. A carrier with a passivation layer on the carrier is provided. ... Micron Technology Inc

07/27/17 / #20170213764

Method for fabricating a semiconductor device

A method of fabricating a semiconductor device. A wafer having a front side and a back side opposite to the front side is prepared. ... Micron Technology Inc

07/27/17 / #20170213761

Semiconductor devices including a diode structure over a conductive strap and methods of forming such semiconductor devices

Semiconductor devices including at least one diode over a conductive strap. The semiconductor device may include at least one conductive strap over an insulator material, at least one diode comprising a single crystalline silicon material over a conductive material, and a memory cell on the at least one diode. ... Micron Technology Inc

07/27/17 / #20170213760

Semiconductor with through-substrate interconnect

Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. ... Micron Technology Inc

07/27/17 / #20170213740

Method for fabricating semiconductor package

A method for fabricating a semiconductor package, the method includes forming at least one conductive via having a first end and a second end opposite the first end in a wafer, in which the wafer has a first surface and a second surface opposite the first surface, and the first end of the conductive via is exposed of the first surface of the wafer; grinding the second surface of the wafer to form an inner portion and a ring portion surrounding the inner portion of the wafer, wherein the inner portion has a thinner thickness than that of the ring portion; and etching the inner portion to expose the second end of the conductive via.. . ... Micron Technology Inc

07/27/17 / #20170213733

Method of forming patterns

A method of forming patterns includes the steps of providing a substrate on which a target layer and a hard mask layer are formed; forming a plurality of first resist patterns on the hard mask layer; performing a tilt-angle ion implant process to form a first doped area and a second doped area in the hard mask layer between adjacent two of the first resist patterns; removing the first resist patterns; coating a directed self-assembly (dsa) material layer onto the hard mask layer; performing a self-assembling process of the dsa material layer to form repeatedly arranged block copolymer patterns in the dsa material layer; removing undesired portions from the dsa material layer to form second resist patterns on the hard mask layer; transferring the second resist patterns to the hard mask layer to form third resist patterns; and etching the target layer through the third resist patterns.. . ... Micron Technology Inc

07/27/17 / #20170213650

Apparatuses, multi-chip modules and capacitive chips

Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and dielectric layers in a capacitor stack. ... Micron Technology Inc

07/27/17 / #20170213589

Apparatuses and methods for accessing memory cells in semiconductor memories

Apparatuses and methods for accessing a memory cell are described. An example apparatus includes a first voltage circuit coupled to a node and is configured to provide a first voltage to the node and includes a second voltage circuit coupled to a node and is configured to provide a second voltage to the node. ... Micron Technology Inc

07/27/17 / #20170212695

Apparatuses and methods for encoding and decoding of signal lines for multi-level communication architectures

Apparatuses and methods for multi-level communication architectures are disclosed herein. An example apparatus may include a driver circuit configured to convert a plurality of bitstreams into a plurality of multilevel signals. ... Micron Technology Inc

07/27/17 / #20170212694

Memory systems and methods including training, data organizing, and/or shadowing

Described embodiments include memory systems that may shadow certain data stored in a first memory device (e.g. Nand flash device) onto a second memory device (e.g. ... Micron Technology Inc

07/20/17 / #20170207366

Ultrathin solid state dies and methods of manufacturing the same

Various embodiments of sst dies and solid state lighting (“ssl”) devices with sst dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a sst die includes a substrate material, a first semiconductor material and a second semiconductor material on the substrate material, an active region between the first semiconductor material and the second semiconductor material, and a support structure defined by the substrate material. ... Micron Technology Inc

07/20/17 / #20170207274

Diode/superionic conductor/polymer memory structure

A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. ... Micron Technology Inc

07/20/17 / #20170207273

Memory cell with independently-sized elements

Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. ... Micron Technology Inc

07/20/17 / #20170207206

Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods

Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. ... Micron Technology Inc

07/20/17 / #20170207195

Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture

Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the same pin assignments as the first die bond pads. ... Micron Technology Inc

07/20/17 / #20170207154

Semiconductor device

A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. ... Micron Technology Inc

07/20/17 / #20170207139

Methods for forming interconnect assemblies with probed bond pads

An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. ... Micron Technology Inc

07/20/17 / #20170206977

Memory devices that apply a programming potential to a memory cell in a string coupled to a source and data line concurrently with biasing the data line to a greater potential than the source

A first string of memory cells, including a selected memory cell, and a second string of memory cells are coupled to a common data line and a common source. The data line is biased to a first potential greater than a second potential to which the source is biased and a select gate coupled between the second string of memory cells and the data line is deactivated during a programming operation performed on the selected memory cell. ... Micron Technology Inc

07/20/17 / #20170206967

Functional data programming in a non-volatile memory

Methods of operating a memory include receiving a plurality of digits of data, determining a value of the plurality of digits of data, and selecting a function to represent the value of the plurality of digits of data. The selected function is a function of a cell number of each memory cell within a grouping of memory cells. ... Micron Technology Inc

07/20/17 / #20170206964

Integrated circuitry and 3d memory

Integrated circuitry comprises an array circuitry region comprising a repeating array of electronic components. An adjacent circuitry region is immediately laterally adjacent to and contacts one elongated major peripheral side of the array circuitry region. ... Micron Technology Inc

07/20/17 / #20170206942

Apparatuses, circuits, and methods for biasing signal lines

Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. ... Micron Technology Inc

07/20/17 / #20170206157

Recovery for non-volatile memory after power loss

Non-volatile memory array can be recovered after a power loss. In one example, pages of a memory array are scanned to find a first free page after the power loss. ... Micron Technology Inc

07/20/17 / #20170206131

Non-volatile memory including selective error correction

Some embodiments include apparatuses and methods using a first memory area and a second memory area included a memory device, and using control circuitry included in the memory device to communicate with a memory controller. The memory controller includes an error correction engine. ... Micron Technology Inc

07/20/17 / #20170206036

Non-volatile memory module architecture to support memory error correction

Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. ... Micron Technology Inc

07/20/17 / #20170205712

Development apparatus and method for developing photoresist layer on wafer using the same

A development apparatus includes a rotatable table for mounting a wafer, and a shower nozzle positioned directly above the rotatable table. The shower nozzle comprises a housing having a liquid inlet and a nozzle plate. ... Micron Technology Inc

07/13/17 / #20170200887

Semiconductor devices with magnetic regions and attracter material and methods of fabrication

A magnetic cell includes an attracter material proximate to a magnetic region (e.g., a free region). The attracter material is formulated to have a higher chemical affinity for a diffusible species of a magnetic material, from which the magnetic region is formed, compared to a chemical affinity between the diffusible species and at least another species of the magnetic material. ... Micron Technology Inc

07/13/17 / #20170200801

Devices and methods including an etch stop protection material

Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. ... Micron Technology Inc

07/13/17 / #20170200737

Integrated structures and methods of forming vertically-stacked memory cells

Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. ... Micron Technology Inc

07/13/17 / #20170200724

Memory device and fabricating method thereof

A memory device and a method for fabricating the same are provided. The memory device includes a substrate and an isolation structure. ... Micron Technology Inc

07/13/17 / #20170200722

Memory device and method for fabricating the same

A memory device with a dielectric layer or an air gap between contacts and a method of making the same are disclosed. The method comprises a series of steps including: forming a plurality of conductive lines having trenches therebetween; forming a contact layer in the trench; and forming a dielectric layer interposed in the contact layer and configured to divide the contact layer into two contacts. ... Micron Technology Inc

07/13/17 / #20170200661

Waters having a die region and a scribe-line region adjacent to the die region

A wafer and a forming method thereof are provided. The wafer has a die region and a scribe-line region adjacent to the die region, and includes a conductive bonding pad in the die region of the wafer and a wafer acceptance test (wat) pad in the scribe-line region of the wafer. ... Micron Technology Inc

07/13/17 / #20170200635

Forming array contacts in semiconductor memories

Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. ... Micron Technology Inc

07/13/17 / #20170200497

Apparatuses and methods for current limitation in threshold switching memories

The present invention relates to apparatuses and methods for limiting current in threshold switching memories. An example apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. ... Micron Technology Inc

07/13/17 / #20170199828

Chained bus method

Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. ... Micron Technology Inc

07/13/17 / #20170199775

Estimation of error correcting performance of low-density parity-check (ldpc) codes

Some embodiments include apparatuses and methods using a low-density parity-check (ldpc) decoding circuit to receive information retrieved from memory cells, the information including codewords, and a calculating circuit to calculate a rate of codeword errors in the codewords. The calculation is based on a rate of erroneous bits in the information and a rate of erroneous bits with a selected reliability level. ... Micron Technology Inc

07/13/17 / #20170199708

Apparatuses and methods for configuring i/os of memory for hybrid memory modules

Apparatuses, hybrid memory modules, memories, and methods for configuring i/os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. ... Micron Technology Inc

07/13/17 / #20170199702

Solid state memory formatting

The present disclosure includes methods and devices for solid state drive formatting. One device embodiment includes control circuitry coupled to a number of memory arrays, wherein each memory array has multiple physical blocks of memory cells. ... Micron Technology Inc

07/13/17 / #20170199666

Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory

Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. ... Micron Technology Inc

07/06/17 / #20170194537

Packaged leds with phosphor films, and associated systems and methods

Packaged leds with phosphor films, and associated systems and methods are disclosed. A system in accordance with a particular embodiment of the disclosure includes a support member having a support member bond site, an led carried by the support member and having an led bond site, and a wire bond electrically connected between the support member bond site and the led bond site. ... Micron Technology Inc

07/06/17 / #20170194494

Transistors

Some embodiments include a construction having a second semiconductor material over a first semiconductor material. A region of the second semiconductor material proximate the first semiconductor material has strain due to different lattice characteristics of the first and second semiconductor materials. ... Micron Technology Inc

07/06/17 / #20170194351

Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures

Methods for fabricating semiconductor-metal-on-insulator (smoi) structures include forming an acceptor wafer including an insulator material on a first semiconductor substrate, forming a donor wafer including a conductive material and an amorphous silicon material on a second semiconductor substrate, and bonding the amorphous silicon material of the donor wafer to the insulator material of the acceptor wafer. Smoi structures formed from such methods are also disclosed, as are semiconductor devices including such smoi structures.. ... Micron Technology Inc

07/06/17 / #20170194348

Semiconductor constructions, methods of forming vertical memory strings, and methods of forming vertically-stacked structures

Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. ... Micron Technology Inc

07/06/17 / #20170194181

Overhead traveling vehicle, transportation system with the same, and method of operating the same

An overhead traveling vehicle configured to transport wafers includes a mobile drive unit configured to move along a predetermined route on one side of a ceiling and a hoist unit configured to move along the predetermined route according to a position of the mobile drive unit. The mobile drive unit and the hoist unit respectively include a first magnet and a second magnet so that the hoist unit may be hung on the ceiling by the magnetic force generated between the magnets.. ... Micron Technology Inc

07/06/17 / #20170193351

Methods and systems for vector length management

An apparatus includes a state machine lattice. The apparatus also includes a memory. ... Micron Technology Inc

07/06/17 / #20170192911

Memory tile access and selection patterns

In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. ... Micron Technology Inc

07/06/17 / #20170192844

Error code calculation on sensing circuitry

Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are coupled to sense lines. ... Micron Technology Inc

06/29/17 / #20170187546

Computerized apparatus with a high speed data bus

A computerized apparatus configured for high-speed data transactions between components thereof. In one embodiment, the computerized apparatus includes a high-speed data bus apparatus; a user interface apparatus in data communication with the high-speed data bus apparatus configured to enable a user to interact with the computerized apparatus; an input/output apparatus in data communication with the high-speed data bus apparatus and configured to interchange data with one or more devices external to the computerized apparatus; a mass storage apparatus in data communication with the high-speed data bus apparatus and configured to store data; a computer program for use by the high-speed data bus apparatus; and a substantially unified data interface in data communication with each of the user interface apparatus, the input/output apparatus, the mass storage apparatus, and the high-speed data bus apparatus.. ... Micron Technology Inc

06/29/17 / #20170186816

Cross-point memory and methods for fabrication of same

The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. ... Micron Technology Inc

06/29/17 / #20170186757

Methods of forming a ferroelectric memory cell

A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. ... Micron Technology Inc

06/29/17 / #20170186729

Stacked semiconductor dies with selective capillary under fill

Stacked semiconductor dies are provided with selective capillary under fill to avoid wafer warpage during curing. In one embodiment, a method of manufacturing a semiconductor device includes forming at least three stacks of semiconductor dies over a substrate, the stacks spaced apart from one another by gaps. ... Micron Technology Inc

06/29/17 / #20170186499

Test mode circuit for memory apparatus

Apparatuses for error detection and correction for a semiconductor device are described. An example apparatus includes: at least one memory cell array including a plurality of memory cells; and a control circuit that receives read data from the plurality of memory cells, compares the read data with reference data, and further provides an error signal. ... Micron Technology Inc

06/29/17 / #20170186487

Apparatuses and methods of reading memory cells

A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (vth) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (vth1) of the memory cell and determining whether the vth1 is within the overlapped vth region. ... Micron Technology Inc

06/29/17 / #20170186479

Semiconductor memory device including output buffer

An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.. . ... Micron Technology Inc

06/29/17 / #20170186475

Memory device command receiving and decoding methods

Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. ... Micron Technology Inc

06/29/17 / #20170186468

Data shift by elements of a vector in memory

Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. ... Micron Technology Inc

06/29/17 / #20170185136

Apparatuses and methods for exiting low power states in memory devices

According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification, the apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.. ... Micron Technology Inc

06/22/17 / #20170179383

Method and apparatus providing multi-planed array memory device

A three-dimensional variable resistance memory array and method of forming the same. The memory array has memory cells in multiple planes in three dimensions. ... Micron Technology Inc

06/22/17 / #20170179143

Memory having a continuous channel

The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.. ... Micron Technology Inc

06/22/17 / #20170179045

Methods of processing wafer-level assemblies to reduce warpage, and related assemblies

Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of the wafer. ... Micron Technology Inc

06/22/17 / #20170179031

Electronic component of integrated circuitry and a method of forming a conductive via to a region of semiconductor material

An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface. ... Micron Technology Inc

06/22/17 / #20170178738

Reducing programming disturbance in memory devices

Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then he applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. ... Micron Technology Inc

06/22/17 / #20170178737

Programming memory cells to be programmed to different levels to an intermediate level from a lowest level

First memory cells are programmed to an intermediate level from a lowest level, corresponding to a lowest data state, where the first memory cells are to be programmed from the intermediate level to levels other than the lowest level. The first memory cells are not read or verified at the intermediate level. ... Micron Technology Inc

06/22/17 / #20170178732

Apparatuses and methods for charging a global access line prior to accessing a memory

Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a memory. ... Micron Technology Inc

06/22/17 / #20170178730

Methods and apparatuses including a string of memory cells having a first select transistor coupled to a second select transistor

Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. ... Micron Technology Inc

06/22/17 / #20170178701

Control lines to sensing components

Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might include an array of memory cells. ... Micron Technology Inc

06/22/17 / #20170178696

Methods and apparatuses for compensating for source voltage

Apparatuses and methods for compensating for source voltage are described. An example apparatus includes a source cooled to a memory cell and a read-write circuit coupled to the memory cell. ... Micron Technology Inc

06/22/17 / #20170177478

Phase change memory in a dual inline memory module

Subject matter disclosed herein relates to management of a memory device.. . ... Micron Technology Inc

06/22/17 / #20170177301

Asymmetric chip-to-chip interconnect

Methods and apparatus to transfer data between a first device and a second device, is disclosed. An apparatus according to various embodiments may comprise a first device and a second device. ... Micron Technology Inc

06/22/17 / #20170177019

Apparatuses and methods for providing reference voltages

A reference voltage generator is disclosed that may provide a plurality of reference voltages. A reference voltage generator may include a voltage divider, a multiplexer coupled to the voltage divider, an operational amplifier that may receive a voltage from the multiplexer, and a plurality of resistors that may receive an output from the operational amplifier. ... Micron Technology Inc

06/15/17 / #20170170158

Apparatuses and methods for forming die stacks

Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base die onto the temporary adhesive, curing the temporary adhesive, forming a die stack that includes the base die, activating a release layer disposed on the substrate, wherein the release layer is between the substrate and the temporary adhesive, removing the die stack from the substrate, and removing the temporary adhesive from the die stack.. ... Micron Technology Inc

06/15/17 / #20170170149

Memory devices with controllers under memory packages and associated systems and methods

Semiconductor devices with controllers under stacks of semiconductor packages and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate, a controller attached to the package substrate, and at least two semiconductor packages disposed over the controller. ... Micron Technology Inc

06/15/17 / #20170169885

Threshold voltage distribution determination

Apparatuses and methods for threshold voltage (vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. ... Micron Technology Inc

06/15/17 / #20170169875

Apparatuses and methods for dynamic voltage and frequency switching for dynamic random access memory

According to one embodiment, an apparatus is disclosed. The apparatus includes a first power supply having a first fixed voltage, a second power supply having a second fixed voltage, a plurality of circuits coupled to the first power supply via a first switch and the second power supply via a second switch, and a power control circuit configured to selectively enable one of the first switch and the second switch responsive to power demand information.. ... Micron Technology Inc

06/15/17 / #20170169863

Apparatus for impedance adjustment and methods of their operation

Apparatus include a data bus and a signal driver circuit having pluralities of first and second termination devices connected in parallel between a voltage node and an output node. Each of the termination devices is configured to be deactivated in response to control signals having a particular set of logic levels, and to be activated in response to control signals having a set of logic levels other than the particular set of logic levels. ... Micron Technology Inc

06/15/17 / #20170168817

Conditional operation in an internal processor of a memory device

The present techniques provide an internal processor of a memory device configured to selectively execute instructions in parallel, for example. One such internal processor includes a plurality of arithmetic logic units (alus), each connected to conditional masking logic, and each configured to process conditional instructions. ... Micron Technology Inc

06/15/17 / #20170168728

Systems and methods for reordering packet transmissions in a scalable memory system protocol

A memory device includes a plurality of memory components that stores data and a processor communicatively coupled to the plurality of memory components. The processor may receive a plurality of packets associated with a plurality of data operations, such that each of the plurality of packets includes a transaction window field indicating a type of memory component associated with a respective data operation of the respective packet. ... Micron Technology Inc

06/08/17 / #20170163287

Error correction methods and apparatuses using first and second decoders

Apparatuses and methods for error correcting data are provided. A first error correction code (ecc) decoder is configured to decode a first codeword to provide a first result and to decode a second codeword to provide a second result. ... Micron Technology Inc

06/08/17 / #20170163251

Phase interpolators and push-pull buffers

Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the clock signals output from the push-pull buffers.. ... Micron Technology Inc

06/08/17 / #20170163147

Methods and apparatus for generation of voltages

Methods of operating voltage generation circuits include applying a clock signal to a first electrode of a first capacitance having a second electrode connected to a first node of a first current path, applying the clock signal to a second capacitance having a second electrode connected to a gate of a second current path connected in parallel with the first current path and with the second electrode further connected to a first end of a resistance having a second end connected to the second node, passing charge across at least one of the first current path and the second current path while the clock signal has a first logic phase, and mitigating current flow across the first current path and the second current path while the clock signal has a second logic phase opposite the first logic phase, as well as apparatus facilitating such methods.. . ... Micron Technology Inc

06/08/17 / #20170162589

Transistors, semiconductor constructions, and methods of forming semiconductor constructions

Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. ... Micron Technology Inc

06/08/17 / #20170162587

Ferroelectric capacitor, ferroelectric field effect transistor, and method used in forming an electronic component comprising conductive material and ferroelectric material

A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. ... Micron Technology Inc

06/08/17 / #20170162440

Low capacitance interconnect structures and associated systems and methods

Semiconductor device interconnect structures having low capacitance and associated systems and methods are disclosed herein. In one embodiment, a method of manufacturing an interconnect structure includes forming an opening in a surface of a semiconductor device and forming an interconnect structure at least within the opening. ... Micron Technology Inc

06/08/17 / #20170162269

Apparatuses and methods for reducing read disturb

Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (sgd) switch and a first select gate source (sgs) switch, a second memory subblock including a second sgd switch and a second sgs switch, and an access line associated with the first and second memory subblocks. ... Micron Technology Inc

06/08/17 / #20170162265

Programming a memory device in response to its program history

A method includes determining, internal to a memory device, a number of program pulses required to program a sample of memory cells of the memory device during a first programming operation, comparing the determined number of program pulses required to program the sample of memory cells of the memory device to a target number of program pulses, and adjusting a program starting voltage level of one or more program pulses applied to one or more memory cells of the sample of memory cells during a second programming operation subsequent to the first programming operation when the determined number of program pulses required to program the sample of memory cells in the first programming operation is different than the target number so that the number of program pulses applied during the second programming operation tends toward the target number.. . ... Micron Technology Inc

06/08/17 / #20170162263

Apparatuses and methods including memory access in cross point memory

Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. ... Micron Technology Inc

06/08/17 / #20170162254

Providing power availability information to memory

The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. ... Micron Technology Inc

06/08/17 / #20170162253

Systems, methods, and apparatuses for performing refresh operations

An apparatus is disclosed. The apparatus includes an address counter configured to provide a refresh address to a refresh circuit, wherein the address counter includes a plurality of counter cells coupled in series from a first counter cell to a last counter cell downstream of the first counter cell, wherein an output of each of the plurality of counter cells each correspond to an address bit of the refresh address, wherein the address bit of the refresh address provided by a later counter cell downstream of an earlier counter cell is a less significant bit of the refresh address than the address bit of the refresh address provided by the earlier counter cell.. ... Micron Technology Inc

06/08/17 / #20170162243

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. ... Micron Technology Inc

06/08/17 / #20170162241

Apparatuses including multiple read modes and methods for same

Apparatuses and methods including multiple read modes for reading data from a memory are described. An example apparatus includes a memory including a first read mode and a second read mode. ... Micron Technology Inc

06/08/17 / #20170162240

Systems, circuits, and methods for charge sharing

Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. ... Micron Technology Inc

06/08/17 / #20170161197

Apparatuses and methods for pre-fetching and write-back for a segmented cache memory

Apparatuses and methods for a cache memory are described. In an example method, a transaction history associated with a cache block is referenced, and requested information is read from memory. ... Micron Technology Inc

06/08/17 / #20170160977

Solid state drive controller

A memory device may comprise circuitry to adjust between latency and throughput in transferring information through a memory port, wherein the circuitry may be capable of configuring individual partitions or individual sectors as high-throughput storage or low-latency storage.. . ... Micron Technology Inc

06/08/17 / #20170160973

Controller to manage nand memories

A single virtualized ecc nand controller executes an ecc algorithm and manages a stack of nand flash memories. The virtualized ecc nand controller allows the host processor to drive the stack of flash memory devices as a single nand chip while the controller redirects the data to the selected nand memory device in the stack.. ... Micron Technology Inc

06/01/17 / #20170154999

Recessed transistors containing ferroelectric material

Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an interior of the first insulative structure, and a ferroelectric structure lines an interior of the first conductive structure. ... Micron Technology Inc

06/01/17 / #20170154952

Capacitor, array of capacitors, and device comprising an electrode

A capacitor includes an elevationally inner capacitor electrode, an elevationally outer capacitor electrode, and capacitor insulator between the elevationally inner and outer capacitor electrodes. The elevationally inner capacitor electrode comprises a hollow longitudinally-elongated conductive cylinder-like portion and a non-hollow longitudinally-elongated conductive cylinder-like portion electrically coupled with the hollow cylinder-like portion. ... Micron Technology Inc

06/01/17 / #20170154676

Apparatuses and methods for providing set and reset voltages at the same time

Apparatuses and methods are described, such as those involving driver circuits that are configured to provide reset and set voltages to different variable state material memory cells in an array at the same time. Additional apparatuses, and methods are described.. ... Micron Technology Inc

06/01/17 / #20170154663

Apparatus having dice to perorm refresh operations

Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first memory cells, and a second memory chip having second memory cells. The first memory cells may be refreshed in response to a first clock signal based on the original clock signal. ... Micron Technology Inc

06/01/17 / #20170153817

Storage devices configured to generate linked lists

Storage devices including a controller, a first memory coupled to the controller, and a second memory coupled to the controller, wherein the controller is configured to generate a linked list in response to a received access command, the linked list comprising one or more first entries corresponding to user data to be received from or outputted to an external device and one or more second entries for metadata to be generated by the storage device, and having a defined order of the first entries and the second entries corresponding to a defined data structure of a page of data of the first memory.. . ... Micron Technology Inc

05/18/17 / #20170141121

Vertical memory blocks and related devices and methods

Vertical memory blocks for semiconductor devices include a memory cell region including an array of memory cell pillars and at least one via region including a dielectric stack of alternating dielectric materials and at least one conductive via extending through the dielectric stack. Semiconductor devices including a vertical memory block include at least one vertical memory block, which includes slots extending between adjacent memory cells of a three-dimensional array. ... Micron Technology Inc

05/18/17 / #20170141119

Integrated structures and methods of forming integrated structures

Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. ... Micron Technology Inc

05/18/17 / #20170141096

Proximity coupling of interconnect packaging systems and methods

Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. ... Micron Technology Inc

05/18/17 / #20170141085

Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices

A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. ... Micron Technology Inc

05/18/17 / #20170140833

Erasing memory segments in a memory block of memory cells using select gate control line voltages

A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile nand architecture memory device during an erase operation. The memory block of memory cells includes a plurality of memory segments and a corresponding plurality of first select gate control lines. ... Micron Technology Inc

05/18/17 / #20170140830

Apparatuses and methods for transistor protection by charge sharing

Apparatuses and methods for protecting transistors through charge sharing are disclosed herein. An example apparatus includes a transistor comprising a gate node and a bulk node, a charge sharing circuit coupled between the gate and bulk nodes, and logic. ... Micron Technology Inc

05/18/17 / #20170140806

Stt-mram cell structures

A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. ... Micron Technology Inc

05/18/17 / #20170140142

Method for controlling user access to an electronic device

A method and system for authenticating a user to access a computer system. The method comprises communicating security information to the computer system, and providing the computer system with an implicit input. ... Micron Technology Inc

05/18/17 / #20170139163

Apparatus providing simplified alignment of optical fiber in photonic integrated circuits

A structure for optically aligning an optical fiber to a photonic device and method of fabrication of same. The structure optically aligns an optical fiber to the photonic device using a lens between the two which is moveable by actuator heads. ... Micron Technology Inc

05/11/17 / #20170134676

Method, apparatus and system providing a storage gate pixel with high dynamic range

A method, apparatus and system are described providing a high dynamic range pixel. An integration period has multiple sub-integration periods during which charges are accumulated in a photosensor and repeatedly transferred to a storage node, where the charges are accumulated for later transfer to another storage node for output.. ... Micron Technology Inc

05/11/17 / #20170133587

Methods of forming resistive memory elements

A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising longitudinally extending, columnar grains of crystalline material, an ion reservoir material over the buffer material, and a second electrode over the ion reservoir material. A memory cell, a memory device, an electronic system, and a method of forming a resistive memory element are also described.. ... Micron Technology Inc

05/11/17 / #20170133478

Transistors, memory cells and semiconductor constructions

Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. ... Micron Technology Inc

05/11/17 / #20170133433

Self-aligned cross-point phase change memory-switch array

Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of fabricating same.. . ... Micron Technology Inc

05/11/17 / #20170133392

Memory including blocking dielectric in etch stop tier

Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. ... Micron Technology Inc

05/11/17 / #20170133385

Wiring with external terminal

Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a connection wiring of a ring-shape having comprising a hole and a conductive layer surrounding the hole, the conductive layer including a first connection point and a second connection point that are located so that a straight line between the first connection point and the second connection point crosses over the hole; an external terminal coupled to the first connection point of the conductive layer of the connection wiring; and an internal circuit coupled to the second connection point of the conductive layer of the connection wiring.. ... Micron Technology Inc

05/11/17 / #20170133383

Enhanced charge storage materials, related semiconductor memory cells and semiconductor devices, and related systems and methods

Volatile memory cells including dielectric materials exhibiting a nonlinear capacitance as a function of voltage. The volatile memory cells comprise a source region and a drain region within a substrate and a capacitor coupled to one of the source region and the drain region. ... Micron Technology Inc

05/11/17 / #20170133359

Semiconductor device with modified current distribution

Semiconductor devices having modified current distribution and methods of forming the same are described herein. As an example, a memory die in contact with a logic die can be configured to draw a sum amount of current from a current source. ... Micron Technology Inc

05/11/17 / #20170133105

Autorecovery after manufacturing/system integration

Methods of managing systems comprising a processor and a memory device external to the processor, including exposing the memory device to temperature levels associated with soldering, starting up the memory device and testing pre-programmed data using control circuitry of the memory device. When results of the testing indicate repair of the pre-programmed data should be performed, issuing a command from the processor to the memory device indicative of a desire for the memory device to repair the pre-programmed data, and in response to the memory device receiving the command, repairing the pre-programmed data using the control circuitry of the memory device.. ... Micron Technology Inc

05/11/17 / #20170133080

Frequency synthesis for memory input-output operations

A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. ... Micron Technology Inc

05/11/17 / #20170133076

Fixed voltage sensing in a memory device

Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. ... Micron Technology Inc

05/11/17 / #20170133075

Unidirectional spin torque transfer magnetic memory cell structure

Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. ... Micron Technology Inc

05/11/17 / #20170133066

Comparison operations in memory

The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. ... Micron Technology Inc

05/11/17 / #20170132162

Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding

Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding are disclosed. An example apparatus may include first and second channels, a receiver coupled to the first and second channels, and first and second transmitters coupled to the first and second channels, respectively. ... Micron Technology Inc

05/11/17 / #20170132076

Setting a default read signal based on error correction

The present disclosure includes apparatuses and methods related to setting a default read signal based on error correction. A number of methods can include reading a page of data from a group of memory cells with a first discrete read signal and error correcting at least one codeword of the page of data as read with the first discrete read signal. ... Micron Technology Inc

05/11/17 / #20170132073

Memory devices having differently configured blocks of memory cells

A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of the plurality of blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, to configure a second block of the plurality of blocks of memory cells in a second configuration comprising a group of user data memory cells and a group of overhead data memory cells, and to configure a third block of the plurality of blocks of memory cells in a third configuration comprising only a group of user data memory cells. The group of overhead data memory cells of the second block of memory cells has a different storage capacity than at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block.. ... Micron Technology Inc

05/11/17 / #20170131915

Interconnect systems and methods using hybrid memory cube links to send packetized data over different endpoints of a data handling device

System on a chip (soc) devices include two packetized memory buses for conveying local memory packets and system interconnect packets. In an in-situ configuration of a data processing system two or more socs are coupled with one or more hybrid memory cubes (hmcs). ... Micron Technology Inc

05/11/17 / #20170131904

Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation

Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. ... Micron Technology Inc

05/04/17 / #20170125484

Three-dimensional memory apparatuses and methods of use

A three dimensional (3d) memory array is disclosed. The 3d memory array may include an electrode plane and a memory material disposed through and coupled to the electrode plane. ... Micron Technology Inc

05/04/17 / #20170125426

Integrated assemblies and methods of forming assemblies

Some embodiments include an integrated assembly having a first semiconductor structure containing heavily-doped silicon, a germanium-containing interface material over the first semiconductor structure, and a second semiconductor structure over the germanium-containing interface material. The second semiconductor structure has a heavily-doped lower region adjacent the germanium-containing interface material and has a lightly-doped upper region above the heavily-doped lower region. ... Micron Technology Inc

05/04/17 / #20170125390

Solid state transducers with state detection, and associated systems and methods

Solid state transducers with state detection, and associated systems and methods are disclosed. A solid state transducer system in accordance with a particular embodiment includes a support substrate and a solid state emitter carried by the support substrate. ... Micron Technology Inc

05/04/17 / #20170125342

Semiconductor constructions

Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. ... Micron Technology Inc

05/04/17 / #20170125106

Semiconductor memory column decoder device and method

Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. ... Micron Technology Inc

05/04/17 / #20170125099

Apparatuses and methods for adjusting write parameters based on a write count

According to one embodiment of the present invention, an apparatus disclosed. The apparatus includes a memory array having a plurality of memory cells. ... Micron Technology Inc

05/04/17 / #20170125097

Apparatuses and methods including memory and operation of same

Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. ... Micron Technology Inc

05/04/17 / #20170125075

Memory bank signal coupling buffer and method

A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. ... Micron Technology Inc

05/04/17 / #20170124453

Methods and systems for power management in a pattern recognition processing system

A device includes a state machine. The state machine includes a plurality of blocks, where each of the blocks includes a plurality of rows. ... Micron Technology Inc

05/04/17 / #20170124332

Self-measuring nonvolatile memory device systems and methods

One embodiment describes a computing system that includes a boot device. The boot device includes nonvolatile memory that stores startup routine instructions and a first pointer, in which the first pointer identifies a first one or more memory addresses in the nonvolatile memory where at least a portion of the startup routine instructions are stored, and a microcontroller that retrieves the startup routine instructions from the nonvolatile memory using the first pointer and determines whether the startup routine instructions are corrupted before executing any portion of the startup routine instructions. ... Micron Technology Inc

05/04/17 / #20170124318

Methods of operating storage systems including encrypting a key salt

A method of operating a storage system includes using a device driver coupled to a storage device to encrypt a key salt and a number of iterations, storing the encrypted key salt and the encrypted number of iterations in a secure storage area of the storage device, using the device driver to combine a password, the key salt, and the number of iterations to generate a primary key, using the device driver to generate a key schedule from the primary key, receiving an encrypted master key at the device driver, and using the device driver to decrypt the encrypted master key with the key schedule.. . ... Micron Technology Inc

05/04/17 / #20170124310

System and method for controlling user access to an electronic device

A method and system for authenticating a user to access a computer system. The method comprises communicating security information to the computer system, and providing the computer system with an implicit input. ... Micron Technology Inc

05/04/17 / #20170123715

Data transfer techniques for multiple devices on a shared bus

Direct data transfer between devices having a shared bus may be implemented with reduced involvement from a controller associated with the devices. A controller, a source memory device, and a target memory device may be coupled with a shared bus. ... Micron Technology Inc

05/04/17 / #20170123707

Memory cells configured in multiple configuration modes

Some embodiments include apparatuses and methods having an interface to communicate with a host, memory cells, and a control unit coupled to the interface to associate a portion of the memory cells with a logical address range based on control information provided to the interface from the host. The control unit is configured to cause the portion of the memory cells to operate in a configuration mode indicated by the control information from the host. ... Micron Technology Inc

04/27/17 / #20170117449

Ohmic contacts for semiconductor structures

A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a tialxny material at least partially contiguous with the semiconductor structure. ... Micron Technology Inc

04/27/17 / #20170117319

Pixel with strained silicon layer for improving carrier mobility and blue response in imagers

An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.. ... Micron Technology Inc

04/27/17 / #20170117295

Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical ferroelectric field effect transistors, vertical strings of ferroelectric field effect transistors, and vertical strings of laterally opposing pairs of vertical ferroelectric field effect transistors

A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. ... Micron Technology Inc

04/27/17 / #20170117292

Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells

A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. ... Micron Technology Inc

04/27/17 / #20170117258

Solid state lighting device with different illumination parameters at different regions of an emitter array

Solid state lighting (ssl) devices and methods of manufacturing such devices. One embodiment of an ssl device comprises a support and an emitter array having a plurality of ssl emitters carried by the support. ... Micron Technology Inc

04/27/17 / #20170117254

Apparatuses and methods for heat transfer from packaged semiconductor die

Apparatuses and methods for heat transfer from packaged semiconductor die are described. For example, an apparatus may include a plurality of die in a stack, and a barrier in close proximity to at least an edge of each of the plurality of die. ... Micron Technology Inc

04/27/17 / #20170117205

Semiconductor device packages with improved thermal management and related methods

Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. ... Micron Technology Inc

04/27/17 / #20170117044

Semiconductor device and error correction method

A device with error correction is provided. The device includes a plurality of memory cells, and reference read write circuit, a plurality of sense amplifiers, and an error-correction code control block. ... Micron Technology Inc

04/27/17 / #20170117020

Apparatuses and methods for storing a data value in multiple columns

An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a control component configured to cause computing of a data value equal to a logical or between the digit of a mask and a data value stored in a memory cell located in a row at a column of the array corresponding to a digit of a vector stored in the array. ... Micron Technology Inc

04/27/17 / #20170116139

Command packets for the direct control of non-volatile memory channels within a solid state drive

Apparatuses and methods for providing and interpreting command packets for the direct control of non-volatile memory channels within a solid state drive are disclosed herein. An example apparatus may include a plurality of flash memories configured into a plurality of channels and a controller coupled to the plurality of flash memories. ... Micron Technology Inc

04/27/17 / #20170116049

Efficient operations of components in a wireless communications device

Various embodiments comprise apparatuses and methods including a communications subsystem having an interface module and a protocol module with the communications subsystem being configured to be coupled to an antenna. An applications subsystem includes a software applications module and an abstraction module. ... Micron Technology Inc

04/27/17 / #20170115893

Interface device accessing a stack of memory dice and a solid state disk

Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. ... Micron Technology Inc

04/20/17 / #20170110402

Conductive structures, systems and devices including conductive structures and related methods

Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures. ... Micron Technology Inc

04/20/17 / #20170110381

External gettering method and device

Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be incorporated as part of an electronic packaging for the structure, is disclosed. ... Micron Technology Inc

04/20/17 / #20170110198

Apparatuses and methods to control body potential in memory operations

Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. ... Micron Technology Inc

04/20/17 / #20170110174

Device having multiple switching buffers for data paths controlled based on io configuration modes

A device includes a first data terminal, a second data terminal, a first switching buffer coupled between a data node and the first data terminal and a second switching buffer coupled between the data node and the second data terminal. The first switching buffer and the second switching buffer are arranged such that a distance between the first switching buffer and the second data terminal is shorter than a distance between the second switching buffer and the second data terminal and that a distance between the first switching buffer and the first data terminal is shorter than a distance between the second switching buffer and the first data terminal.. ... Micron Technology Inc

04/20/17 / #20170110173

Method and apparatus for decoding commands

Method and apparatuses for of decoding commands for a semiconductor device are described. An example method includes receiving a portion of a command at first and second clock cycles; validating the portion of the command received at the first and second clock cycles at a third clock cycle when a chip select signal indicates a first state and continuing to receive the remaining portion of the command at the third clock cycle and a fourth clock cycle so that the command can be completely received by the semiconductor device by the fourth clock cycle; and invalidating the portion of the command received at the first and second clock cycles at the third clock cycle when the chip select signal indicates a second state different from the first state, so that a new command can be input to the semiconductor device at the third clock cycle.. ... Micron Technology Inc

04/20/17 / #20170109275

Persistent content in nonvolatile memory

Applications may request persistent storage in nonvolatile memory. The persistent storage is maintained across power events and application instantiations. ... Micron Technology Inc

04/20/17 / #20170109249

Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination

An arbitration system and method is disclosed. The apparatus includes first and second memory devices, and a resistor coupled in common to the first and second memory devices, the first memory device including a first calibration circuit configured to perform, when activated, a first calibration operation based on the resistor and a first arbiter configured to activate the first calibration circuit responsive, at least in part, to an assertion of a first command or keep the first calibration circuit inactive irrespective of the assertion of the first command.. ... Micron Technology Inc

04/20/17 / #20170109091

Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination

An arbitration system and method is disclosed. The apparatus includes a fiat and a second memory devices, and a resistor coupled in common to the first and second memory devices, the first memory device includes a first calibration circuit configured to perform a first calibration operation responsive, at least in part, to an external calibration command, the first calibration operation being performed based on the resistor, and the second memory device includes a second calibration circuit configured to perform a second calibration operation responsive, at least in part, to the external calibration command, the second calibration operation being performed based on the resistor after the first calibration operation has finished.. ... Micron Technology Inc

04/20/17 / #20170109084

Logical address history management in memory device

Some embodiments include apparatuses and methods including memory cells and a control unit to store information in a portion of the memory cells and to generate an entry associated with the information. The information is associated with a logical address recognized by a host. ... Micron Technology Inc

04/13/17 / #20170104156

Methods of forming memory devices having electrodes comprising nanowires

Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. ... Micron Technology Inc

04/13/17 / #20170104155

Transistors and methods of forming transistors

Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. ... Micron Technology Inc

04/13/17 / #20170104126

Light emitting devices with built-in chromaticity conversion and methods of manufacturing

Various embodiments of light emitting devices with built-in chromaticity conversion and associated methods of manufacturing are described herein. In one embodiment, a method for manufacturing a light emitting device includes forming a first semiconductor material, an active region, and a second semiconductor material on a substrate material in sequence, the active region being configured to produce a first emission. ... Micron Technology Inc

04/13/17 / #20170104059

Memory arrays

The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. ... Micron Technology Inc

04/13/17 / #20170104030

Memory including a selector switch on a variable resistance memory cell

Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.. ... Micron Technology Inc

04/13/17 / #20170103961

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. ... Micron Technology Inc

04/13/17 / #20170103798

Semiconductor device including subword driver circuit

The present invention is provided with; subword drivers swd for driving subword lines swl, a selection circuit for supplying either negative potential vkk1 or vkk2 to the subword drivers swd, and memory cells mc that are selected in the case when the subword line swl is set to an active potential vpp and are not selected in the case when the subword line swl is either a negative potential vkk1 or vkk2.. . ... Micron Technology Inc

04/13/17 / #20170103794

Apparatuses and methods for setting a signal in variable resistance memory

An example of a method reads a spin torque transfer (stt) memory cell, and writes the stt memory cell using information obtained during the reading of the stt memory cell to set a pulse to write the stt memory cell. An example of an apparatus includes a stt memory cell and read/write circuitry coupled to the stt memory cell to determine a read current (iread) through the stt memory cell and to set a pulse to write the stt memory cell using iread. ... Micron Technology Inc

04/13/17 / #20170102759

Sequence power control

The present disclosure includes apparatuses and methods for sequence power control. A number of embodiments include executing a number of sequences associated with a number of commands, wherein a number of logical unit (lun) controllers execute the number of sequences by locating power consumption information and a starting address of the number of sequences stored in a data structure on the number of lun controllers.. ... Micron Technology Inc

04/06/17 / #20170098660

Apparatuses having a ferroelectric field-effect transistor memory array and related method

An apparatus comprises field-effect transistor (fet) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of fet structures, and a ferroelectric material separating the fet structures and the gates. Individual ferroelectric fets (fefets) are formed at intersections of the fet structures, the gates, and the ferroelectric material. ... Micron Technology Inc

04/06/17 / #20170098480

Soft post package repair of memory devices

Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. ... Micron Technology Inc

04/06/17 / #20170098157

Methods and systems for event reporting

An automaton is implemented in a state machine engine. The automaton is configured to observe data from a beginning of an input data stream until a point when an end of data (eod) signal is seen. ... Micron Technology Inc

04/06/17 / #20170098154

Methods and systems for creating networks

The automata processor workbench (ap workbench) is an application for creating and editing designs of ap networks (e.g., one or more portions of the state machine engine, one or more portions of the fsm lattice, or the like) based on, for example, an automata network markup language (anml). For instance, the application may include a tangible, non-transitory computer-readable medium configured to store instructions executable by a processor of an electronic device, wherein the instructions include instructions to represent an automata network as a graph.. ... Micron Technology Inc

04/06/17 / #20170098102

Secure subsystem

An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the secure operations. ... Micron Technology Inc

04/06/17 / #20170097901

Block or page lock features in serial interface memory

Embodiments are provided for protecting boot block space in a memory device. Such a memory device may include a memory array having a protected portion and a serial interface controller. ... Micron Technology Inc

04/06/17 / #20170097859

Estimating an error rate associated with memory

The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.. ... Micron Technology Inc

04/06/17 / #20170097852

Methods and systems for representing processing resources

A markup language is provided. The markup language describes the composition of automata networks. ... Micron Technology Inc

04/06/17 / #20170097781

Solid state storage device with variable logical capacity based on memory lifecycle

Several embodiments of memory devices and systems having a variable logical memory capacity are disclosed herein. In one embodiment, a memory device can include a plurality of memory regions that collectively define a physical memory capacity and a controller operably coupled to the plurality of memory regions. ... Micron Technology Inc

03/30/17 / #20170093386

System and method for duty cycle correction

Apparatuses and methods for correcting a duty cycle of a clock signal are described. An example apparatus includes: a duty cycle corrector (dcc) that receives an input clock signal and a control signal and produces an output clock signal responsive, at least in part, to the input clock signal and the control signal; a circuit that divides a frequency of the input clock signal by a positive even integer and generates an intermediate clock signal; and a phase detector that generates the control signal responsive, at least in part, to a difference in phase between the output clock signal and the intermediate clock signal.. ... Micron Technology Inc

03/30/17 / #20170092855

Methods of forming conductive elements of semiconductor devices and of forming memory cells

Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. ... Micron Technology Inc

03/30/17 / #20170092696

Phase change memory device with voltage control elements

A phase change memory device with reduced programming disturbance and its operation are described. The phase change memory includes an array with word lines and bit lines and voltage controlling elements coupled to bit lines adjacent to an addressed bit line to maintain the voltage of the adjacent bit lines within an allowed range.. ... Micron Technology Inc

03/30/17 / #20170092695

Arrays of memory cells and methods of forming an array of memory cells

An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. ... Micron Technology Inc

03/30/17 / #20170090503

Apparatuses and methods for power regulation based on input power

Apparatuses and methods for power regulation based on input power using circuitry are disclosed herein. An example apparatus may include a reference circuit configured to receive a first voltage and a second voltage and to provide an output reference voltage at an output node having a value equal to the second voltage subtracted from the first voltage. ... Micron Technology Inc

03/30/17 / #20170089766

Systems and methods for reducing temperature sensor reading variation due to device mismatch

A temperature sensor is disclosed. The temperature sensor includes an analog core having at least first and second circuit nodes and configured to provide a temperature dependent output, a multiplexer coupled to the first and second circuit nodes and configured for at least first and second states in each of which the first circuit node couples to a different circuit element and in each of which the second circuit node couples to a different circuit element, and a controller coupled to the analog core and configured to provide a temperature measurement that is an average of at least first and second readings of the temperature dependent output of the analog core, the first reading taken while the multiplexer is in the first state, and the second reading taken while the multiplexer is in the second state.. ... Micron Technology Inc

03/23/17 / #20170084585

Stacked microfeature devices and associated methods

Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. ... Micron Technology Inc

03/23/17 / #20170083452

Memory management for a hierarchical memory system

Disclosed are systems and methods for managing memory. A memory management system may include a table having multiple virtual memory addresses. ... Micron Technology Inc

03/23/17 / #20170083263

Apparatuses and methods for providing data from a buffer

Apparatuses and methods for providing data from a buffer are disclosed herein. An example apparatus may include an array, a buffer, and a memory control unit. ... Micron Technology Inc

03/23/17 / #20170083260

Systems and methods for providing file information in a memory system protocol

A memory device includes a memory component and controller circuitry. The memory component stores data and the controller circuitry receives, from a host electronic device, one or more commands of a memory system protocol. ... Micron Technology Inc

03/16/17 / #20170077955

Multi channel memory with flexible code-length ecc

Apparatuses and methods for error correction and detection of data from memory on a plurality of channels are described. An example apparatus includes: a first memory cell array including first input/output nodes; a second memory cell array including second input/output nodes and third input/output nodes; a first error correcting code (ecc) control circuit including fourth input/output nodes and fifth input/output nodes; and a second ecc control circuit including sixth input/output nodes coupled respectively to the third input/output nodes of the second memory cell array. ... Micron Technology Inc

03/16/17 / #20170077930

Boolean logic in a state machine lattice

Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable boolean logic cell that may be programmed to perform various logic functions on a data stream. ... Micron Technology Inc

03/16/17 / #20170077393

Magnetic tunnel junctions, methods used while forming magnetic tunnel junctions, and methods of forming magnetic tunnel junctions

A method used while forming a magnetic tunnel junction comprises forming non-magnetic tunnel insulator material over magnetic electrode material. The tunnel insulator material comprises mgo and the magnetic electrode material comprises co and fe. ... Micron Technology Inc

03/16/17 / #20170077067

Semiconductor substrates with unitary vias and via terminals, and associated systems and methods

Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative system in accordance with a particular embodiment includes a semiconductor substrate having an opening that includes a generally cylindrical portion with a generally smooth, uniform surface. ... Micron Technology Inc

03/16/17 / #20170077052

Collars for under-bump metal structures and associated systems and methods

The present technology is directed to manufacturing collars for under-bump metal (ubm) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. ... Micron Technology Inc

03/16/17 / #20170076977

Stair step formation using at least two masks

Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. ... Micron Technology Inc

03/16/17 / #20170076808

Methods and apparatuses having strings of memory cells and select gates with double gates

An apparatus, a method, and a system are disclosed. The apparatus includes a string of memory cells coupled to a select gate drain transistor that has a front control gate and a back control gate. ... Micron Technology Inc

03/16/17 / #20170076806

Access line management in a memory device

Memory devices are configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. ... Micron Technology Inc

03/16/17 / #20170076778

Timing control circuit shared by a plurality of banks

Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first memory bank including at least one first sense amplifier that is enabled responsive to a first activation signal; a second memory bank including at least one second sense amplifier that is enabled responsive to a second activation signal; and a control circuit that receives a control signal. ... Micron Technology Inc

03/16/17 / #20170075613

Sense operation flags in a memory device

In a memory device, odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. Even bit lines of the flag memory cell array are disconnected from the dynamic data cache. ... Micron Technology Inc

03/09/17 / #20170070219

Adjustable delay circuit for optimizing timing margin

The present invention relates to timing margin adjustment circuits using adjustable delay circuits. An example adjustable delay circuit may include a signal line, an output circuit, and a plurality of delay circuits. ... Micron Technology Inc

03/09/17 / #20170069732

Methods of forming diodes

Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. ... Micron Technology Inc

03/09/17 / #20170069603

Semiconductor devices and packages and methods of forming semiconductor device packages

Semiconductor device packages include first and second semiconductor dice in a facing relationship. At least one group of solder bumps is substantially along a centerline between the semiconductor dice and operably coupled with integrated circuitry of the first and second semiconductor dice. ... Micron Technology Inc

03/09/17 / #20170069538

Integrated circuitry and methods of forming transistors

Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. ... Micron Technology Inc

03/09/17 / #20170069454

Fuse element assemblies

Some embodiments include a fuse element assembly having a first portion configured to rupture as materials of the first portion flow to a second portion through electromigration. The assembly has a second portion configured to accumulate the materials that have flowed from the first portion. ... Micron Technology Inc

03/09/17 / #20170069392

Apparatuses and methods for charging a global access line prior to accessing a memory

Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a memory. ... Micron Technology Inc

03/09/17 / #20170069381

Systems, methods and devices for programming a multilevel resistive memory cell

Embodiments disclosed herein may relate to programming a multi-level memory cell with programming pulse sequences that comprise forward-biased and reverse-biased programming pulses.. . ... Micron Technology Inc

03/09/17 / #20170069375

Via formation for cross-point memory

Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a lithographic operation also utilized to form electrically conductive lines in a first electrode layer of the cross-point memory array device.. ... Micron Technology Inc

03/09/17 / #20170069363

Quantizing circuits having improved sensing

A system including a processor and a memory device. The memory device includes a memory array having a plurality of memory elements connected to a bit-line and a quantizing circuit. ... Micron Technology Inc

03/09/17 / #20170069362

Apparatuses including multiple read modes and methods for same

Apparatuses and methods including multiple read modes for reading data from a memory are described. An example apparatus includes a memory including a first read mode and a second read mode. ... Micron Technology Inc

03/09/17 / #20170068717

Methods and apparatuses for searching data stored in a memory array using a replicated data pattern

A method includes replicating a data pattern to be searched for, storing the replicated data pattern into a first row of memory cells, and comparing the replicated data pattern to data stored into a second row of memory cells. In response to detecting the data pattern in the data stored into the second row of memory cells, storing into a third row a value indicative of at least one of an occurrence of the data pattern or a position of the searched for data pattern in the data stored into the row of memory cells.. ... Micron Technology Inc

03/09/17 / #20170068707

Methods and apparatuses for reducing power consumption in a pattern recognition processor

Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of programmed state machines to enable selective activation and deactivation of the block during a pattern search. ... Micron Technology Inc

03/09/17 / #20170068617

Line termination methods

Methods for termination of signal lines within a memory system include appointing a particular memory device of a plurality of memory devices to act as a termination device during a memory device operation on a memory device of the plurality of memory devices corresponding to a particular address of the memory system, wherein appointing the particular memory device to act as a termination device comprises storing termination information in the particular memory device corresponding to the particular address.. . ... Micron Technology Inc

03/09/17 / #20170068464

Searching data in parallel using processor-in-memory devices

A method includes comparing, in parallel, a data pattern with data stored into a plurality of columns of memory cells, and in response to detecting the data pattern in the data stored into a particular column of memory cells of the plurality of columns of memory cells, storing in a memory cell of the particular column a value indicative of at least one of an occurrence of the data pattern or a position of the data pattern in the data stored into the particular column.. . ... Micron Technology Inc

03/02/17 / #20170062715

Clamp elements for phase change memory arrays

Clamp elements, memories, apparatuses, and methods for forming the same are disclosed herein. An example memory may include an array of memory cells and a plurality of clamp elements. ... Micron Technology Inc

03/02/17 / #20170062577

Apparatus including gettering agents in memory charge storage structures

Apparatus having a processor and a memory device in communication with the processor, the memory device including an array of memory cells and a control logic to control access of the array of memory cells, wherein the array of memory cells includes a memory cell having a first dielectric adjacent a semiconductor, a control gate, a second dielectric between the control gate and the first dielectric, and a charge storage structure between the first dielectric and the second dielectric, and wherein the charge storage structure includes a charge-storage material and a gettering agent.. . ... Micron Technology Inc

03/02/17 / #20170062365

Semiconductor device assemblies including intermetallic compound interconnect structures

A method of forming a semiconductor device assembly comprises forming on a first substrate, at least one bond pad comprising a first nickel material over the first substrate, a first copper material on the first nickel material, and a solder-wetting material on the first copper material. On a second substrate is formed at least one conductive pillar comprising a second nickel material, a second copper material directly contacting the second nickel material, and a solder material directly contacting the second copper material. ... Micron Technology Inc

03/02/17 / #20170062338

Integrated circuit structures comprising conductive vias and methods of forming conductive vias

A method of forming conductive vias comprises forming a first via opening and a second via opening within a substrate. First conductive material of a first conductivity is formed into the first and second via openings. ... Micron Technology Inc

03/02/17 / #20170062337

Methods of forming semiconductor device structures including stair step structures, and related semiconductor device structures and semiconductor devices

A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. ... Micron Technology Inc

03/02/17 / #20170062324

Semiconductor devices including conductive lines and methods of forming the semiconductor devices

A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. ... Micron Technology Inc

03/02/17 / #20170062053

Storing information and updating management data in non-volatile memory

Some embodiments include apparatuses and methods having memory cells and a control unit. The control unit can retrieve information from a first portion of the memory cells. ... Micron Technology Inc

03/02/17 / #20170062037

Methods of operating ferroelectric memory cells, and related ferroelectric memory cells and capacitors

Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. ... Micron Technology Inc

03/02/17 / #20170060789

Apparatuses and methods for transferring data from memory on a data path

Apparatuses and methods for transferring data from memory on a data path are described. An example apparatus includes: one or more data terminals; a plurality of memory banks, one of the plurality of memory banks being selected responsive, at least in part, to a bank address; and a data path including a plurality of data path routes and a plurality of switching buffers on the plurality of data path routes. ... Micron Technology Inc

03/02/17 / #20170060649

Programmable device, heirarchical parallel machines, and methods for providing state information

Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable elements are provided. ... Micron Technology Inc

02/23/17 / #20170054580

Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding

Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding are disclosed. An example apparatus may include first and second channels, a receiver coupled to die first and second channels, and first and second transmitters coupled to the first and second channels, respectively. ... Micron Technology Inc

02/23/17 / #20170054036

Integrated structures

Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. ... Micron Technology Inc

02/23/17 / #20170053986

Integrated structures containing vertically-stacked memory cells

Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. ... Micron Technology Inc

02/23/17 / #20170053881

Bonding pads with thermal pathways

Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. ... Micron Technology Inc

02/23/17 / #20170053714

Read voltage offset

Apparatuses, methods, and data structures that can be utilized to provide a read voltage offset are described. One or more apparatuses can include a memory device and a controller coupled to the memory device and configured to: access a data structure comprising write temperature data corresponding to a number of data segments stored in the memory device; read a particular data segment using a read voltage offset determined based on: the write temperature data from the data structure and corresponding to the particular data segment; and read temperature data corresponding to the particular data segment.. ... Micron Technology Inc

02/23/17 / #20170053711

Multi-channel testing

Apparatus and methods can include an interface chip that can include a test channel to couple to a memory tester, a memory channel controller to couple with a plurality of memory arrays via a plurality of memory channels, and a test circuit coupled between the test channel and the channel controller, the test circuit to provide first and second test clock information to the memory channel controller. In certain examples, the test circuit can operate to receive multiple commands and to propagate the multiple commands to groups of memory channels substantially simultaneously in order to test cross-channel interference using the multi-channel memory. ... Micron Technology Inc

02/23/17 / #20170053709

Apparatuses and/or methods for operating a memory cell as an anti-fuse

Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.. . ... Micron Technology Inc

02/23/17 / #20170053701

Program and read trim setting

A trim set register for a memory device has a plurality of individual trim settings. Each trim setting has a program trim value, a step-up trim value, and a program pulse width. ... Micron Technology Inc

02/23/17 / #20170053693

Comparison operations in memory

One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.. ... Micron Technology Inc

02/23/17 / #20170052906

Encryption of executables in computational memory

The present disclosure is related to encryption of executables in computational memory. Computational memory can traverse an operating system page table in the computational memory for a page marked as executable. ... Micron Technology Inc

02/16/17 / #20170047474

Light-emitting metal-oxide-semiconductor devices and associated systems, devices, and methods

Various embodiments of solid state transducer (“sst”) devices are disclosed. In several embodiments, a light emitter device includes a metal-oxide-semiconductor (mos) capacitor, an active region operably coupled to the mos capacitor, and a bulk semiconductor material operably coupled to the active region. ... Micron Technology Inc

02/16/17 / #20170047231

Method for packaging circuits

A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. ... Micron Technology Inc

02/16/17 / #20170047187

Fuses, and methods of forming and using fuses

Some embodiments include a fuse having a tungsten-containing structure directly contacting an electrically conductive structure. The electrically conductive structure may be a titanium-containing structure. ... Micron Technology Inc

02/16/17 / #20170047120

Memory devices having source lines directly coupled to body regions and methods

Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. ... Micron Technology Inc

02/16/17 / #20170047117

Memory device with reduced neighbor memory cell disturbance

In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping element, and control circuit. ... Micron Technology Inc

02/09/17 / #20170040986

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a clock generator circuit configured to provide first and second clock signals responsive to an input dock signal. ... Micron Technology Inc

02/09/17 / #20170040563

Solid state optoelectronic device with plated support substrate

A vertical solid state lighting (ssl) device is disclosed. In one embodiment, the ssl device includes a light emitting structure formed on a growth substrate. ... Micron Technology Inc

02/09/17 / #20170040534

Memory cells and methods of forming memory cells

Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. ... Micron Technology Inc

02/09/17 / #20170040533

Memory cells including a metal chalcogenide material and related methods

A method of forming a metal chalcogenide material. The method comprises introducing a metal precursor and a chalcogenide precursor into a chamber, and reacting the metal precursor and the chalcogenide precursor to form a metal chalcogenide material on a substrate. ... Micron Technology Inc

02/09/17 / #20170040375

Semiconductor devices including back-side integrated circuitry

Semiconductor devices may include a semiconductor substrate comprising at least one of transistors and capacitors may be located at an active surface of the semiconductor substrate. An imperforate dielectric material may be located on the active surface, the imperforate dielectric material covering the at least one of transistors and the capacitors. ... Micron Technology Inc

02/09/17 / #20170040327

Method of forming conductive material of a buried transistor gate line and method of forming a buried transistor gate line

A method of forming conductive material of a buried transistor gate line includes adhering a precursor comprising tungsten and chlorine to material within a substrate trench. The precursor is reduced with hydrogen to form elemental-form tungsten material over the material within the substrate trench from the precursor.. ... Micron Technology Inc

02/09/17 / #20170040303

Semiconductor device assembly with through-package interconnect and associated systems, devices, and methods

Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. ... Micron Technology Inc

02/09/17 / #20170040049

Output buffer circuit with low sub-threshold leakage current

A device includes a cutting circuit that is coupled between power supply lines in series with first and second output circuits which drive an output terminal in a push-pull manner. Each of the first and second output circuits includes a plurality of output transistors. ... Micron Technology Inc

02/09/17 / #20170040045

Sense circuits, memory devices, and related methods for resistance variable memory

Sense circuits, memory devices, and related methods are disclosed. A sense circuit includes sample and hold circuitry configured to sample and hold a second response voltage potential, a first response voltage potential, and a third response voltage potential responsive to an evaluation signal applied to a resistance variable memory cell. ... Micron Technology Inc

02/02/17 / #20170033683

Generation of voltages

Voltage generation circuits are useful in the generation of internal voltages for use in integrated circuits. Voltage generation circuits may include a stage capacitance and a voltage isolation device connected to the stage capacitance. ... Micron Technology Inc

02/02/17 / #20170033155

Semiconductor devices comprising magnetic memory cells and methods of fabrication

A magnetic cell core includes a seed region with a plurality of magnetic regions and a plurality of nonmagnetic regions thereover. The seed region provides a template that enables formation of an overlying nonmagnetic region with a microstructure that enables formation of an overlying free region with a desired crystal structure. ... Micron Technology Inc

02/02/17 / #20170033115

Memory cell and an array of memory cells

A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. ... Micron Technology Inc

02/02/17 / #20170033042

Connections for memory electrode lines

Subject matter disclosed herein may relate to word line electrodes and/or digit line electrodes in a cross-point array memory device. One or more word line electrodes may be configured to form a socket area to provide connection points to drivers and/or other circuitry that may be located within a footprint of an array of memory cells.. ... Micron Technology Inc

02/02/17 / #20170032157

Systems and methods to determine motion parameters using rfid tags

Systems and methods to determine motion parameters of physical objects using radio frequency identification (rfid) tags attached to the objects. In one embodiment, a method implemented in a radio frequency identification (rfid) system includes determining a motion parameter of the rfid tag based on detecting a doppler frequency shift in a radio frequency signal received from the rfid tag.. ... Micron Technology Inc

02/02/17 / #20170031851

Interrupted write memory operation in a serial interface memory with a portion of a memory

Subject matter disclosed herein relates to read and write processes of a memory device.. . ... Micron Technology Inc

01/26/17 / #20170026183

Solid state storage device with command and control access

Several embodiments of memory devices and systems with command and control access are described herein. In one embodiment, a memory device includes a controller having a processor and a memory component operably coupled to the processor. ... Micron Technology Inc

01/26/17 / #20170025606

Semiconductor constructions and memory arrays

Some embodiments include semiconductor constructions having an electrically conductive interconnect with an upper surface, and having an electrically conductive structure over the interconnect. The structure includes a horizontal first portion along the upper surface and a non-horizontal second portion joined to the first portion at a corner. ... Micron Technology Inc

01/26/17 / #20170025604

Array of cross point memory cells and methods of forming an array of cross point memory cells

A method of forming an array of cross point memory cells comprises forming spaced conductive lower electrode pillars for individual of the memory cells being formed along and elevationally over spaced lower first lines. Walls cross elevationally over the first lines and between the electrode pillars that are along the first lines. ... Micron Technology Inc

01/26/17 / #20170025517

Thyristor random access memory device and method

Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. ... Micron Technology Inc

01/26/17 / #20170025477

Memory arrays and methods of forming memory arrays

Some embodiments include a memory array having a first memory cell adjacent to a second memory cell along a lateral direction. The second memory cell is vertically offset relative to the first memory cell. ... Micron Technology Inc

01/26/17 / #20170025474

Array of cross point memory cells

An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two immediately adjacent of the second lines and a same single one of the first lines.. ... Micron Technology Inc

01/26/17 / #20170025348

Apparatuses including stair-step structures and methods of forming the same

Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. ... Micron Technology Inc

01/26/17 / #20170025181

Concurrently reading first and second pages of memory cells having different page addresses

In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. ... Micron Technology Inc

01/26/17 / #20170025170

Two-part programming methods

A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be programmed to a second level less than the first level is inhibited while programing the first memory cell to the first level. ... Micron Technology Inc

01/26/17 / #20170025161

Interfaces and die packages, and appartuses including the same

A memory device includes a memory die package including a plurality of memory dies, an interface device including an interface circuit, and a memory controller configured to control the interface with control data received from at least one of the plurality of memory dies. The interface device of the memory device is configured to divide and multiplex an io channel between the memory die package and the memory controller into more than one channel using the control data receive from the at least one of the plurality of memory dies. ... Micron Technology Inc

01/26/17 / #20170025160

Apparatuses and methods for performing compare operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (io) line of a memory array to a voltage. ... Micron Technology Inc

01/26/17 / #20170024337

Memory having internal processors and data communication methods in memory

Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. ... Micron Technology Inc

01/26/17 / #20170024277

Method and apparatus for a volume management system in a non-volatile memory device

Embodiments for partitioning a non-volatile memory device is described. In one embodiment a memory system includes a first addressable range of memory blocks for storing different types of data. ... Micron Technology Inc

01/19/17 / #20170019380

Secure shared key sharing systems and methods

Systems and methods used to securely communicate a shared key to devices. One embodiment describes a method to securely communicate a shared key to a first device and a second device that includes receiving, using the first device, a shared key and unique identifier pairing associated with the first device from a key generator; receiving, using a trusted third party, the shared key and unique identifier pairing from the key generator; generating, using the first device, a signature using the unique identifier and the shared key; transmitting, using the first device, the signature and the unique identifier to the trusted third party; verifying, using the trusted third party, the unique identifier based on the signature; determining, using the trusted third party, the shared key when the unique identifier is verified; and transmitting, using the trusted third party, the shared key to the second device to enable the first device and the second device to communicate securely by encoding and decoding communicated data using the shared key.. ... Micron Technology Inc

01/19/17 / #20170018708

Memory cells, memory arrays, and methods of forming memory cells and arrays

Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. ... Micron Technology Inc

01/19/17 / #20170018705

Magnetic tunnel junctions

Some embodiments include a magnetic tunnel junction comprising magnetic reference material having an iridium-containing region between a multi-layer stack and a polarizer region. Some embodiments include a magnetic tunnel junction having a conductive first magnetic electrode which contains magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and which contains magnetic reference material, and a non-magnetic insulator material between the first and second electrodes. ... Micron Technology Inc

01/19/17 / #20170018598

Memory devices and memory device forming methods

Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.. ... Micron Technology Inc

01/19/17 / #20170018489

Solder bond site including an opening with discontinous profile

Apparatuses and methods for formation of a bond site including an opening with a discontinuous profile are disclosed herein. An example apparatus may at least include a substrate, a contact on the substrate, and a mask layer formed on the substrate and at least a portion of the contact. ... Micron Technology Inc

01/19/17 / #20170018309

Apparatuses and methods for segmented sgs lines

Apparatuses and methods for segmented sgs lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.. ... Micron Technology Inc

01/19/17 / #20170017252

Apparatuses and methods for providing reference voltages

A reference voltage generator is disclosed that may provide a plurality of reference voltages. A reference voltage generator may include a voltage divider, a multiplexer coupled to the voltage divider, an operational amplifier that may receive a voltage from the multiplexer, and a plurality of resistors that may receive an output from the operational amplifier. ... Micron Technology Inc

01/12/17 / #20170012523

Apparatuses and methods for charge pump regulation

Certain embodiments of the present invention include an apparatus comprising a charge pump, configured to provide an output voltage at an output node of the charge pump, and a charge pump regulator circuit coupled to the charge pump. One such charge pump regulator circuit is configured to control the charge pump to increase the output voltage during a first period of time. ... Micron Technology Inc

01/12/17 / #20170012053

Integrated structures and methods of forming vertically-stacked memory cells

Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. ... Micron Technology Inc

01/12/17 / #20170012031

Methods of making semiconductor device packages and related semiconductor device packages

Methods of making semiconductor device packages may involve providing a fan out wafer including semiconductor-device-package locations. Each semiconductor-device-package location may include at least two mutually spaced semiconductor dice and a dielectric material laterally surrounding each of the dice and extending between adjacent semiconductor-device-package locations. ... Micron Technology Inc

01/12/17 / #20170011948

Semiconductor structures including carrier wafers and methods of using such semiconductor structures

A semiconductor structure comprising a carrier wafer and a device wafer. The carrier wafer comprises trenches sized and configured to receive conductive pillars of the device wafer. ... Micron Technology Inc

01/12/17 / #20170011782

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. ... Micron Technology Inc

01/12/17 / #20170011094

Devices, systems, and methods to synchronize simultaneous dma parallel processing of a single data stream by multiple devices

Disclosed are methods and devices, among which is a system that includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster, for example. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream.. ... Micron Technology Inc

01/12/17 / #20170008129

Systems and methods for forming apertures in microfeature workpieces

Systems and methods for forming apertures in microfeature workpieces are disclosed herein. In one embodiment, a method includes directing a laser beam toward a microfeature workpiece to form an aperture and sensing the laser beam pass through the microfeature workpiece in real time. ... Micron Technology Inc

01/05/17 / #20170005233

Solid state transducer dies having reflective features over contacts and associated systems and methods

Systems and methods for improved light emitting efficiency of a solid state transducer (sst), for example light emitting diodes (led), are disclosed. One embodiment of an sst die in accordance with the technology includes a reflective material disposed over electrical connectors on a front side of the die. ... Micron Technology Inc

01/05/17 / #20170004878

Determining soft data

The present disclosure includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. ... Micron Technology Inc

01/05/17 / #20170004872

System and method for decoding commands based on command signals and operating state

A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. ... Micron Technology Inc








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