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Micron Technology Inc patents (2018 archive)


Recent patent applications related to Micron Technology Inc. Micron Technology Inc is listed as an Agent/Assignee. Note: Micron Technology Inc may have other listings under different names/spellings. We're not affiliated with Micron Technology Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "M" | Micron Technology Inc-related inventors


Methods and apparatuses for signal translation in a buffered memory

According to one embodiment, a data buffer is described. The data buffer comprises a first input/output circuit configured to receive and provide a first signal encoded according to a first communications protocol, a second input/output circuit configured to receive and provide a second signal encoded according to a second communications protocol, and a conversion circuit coupled to the first and second input/output circuits and configured to convert the first signal to the second signal and to convert the second signal to the first signal.. ... Micron Technology Inc

Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures

Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures are disclosed herein. An example method may include comparing a current channel state of a channel of a multi-level communication bus with a next channel state of the channel. ... Micron Technology Inc

Semiconductor devices with magnetic and attracter materials and methods of fabrication

A magnetic cell includes an attracter material proximate to a magnetic region (e.g., a free region). The attracter material is formulated to have a higher chemical affinity for a diffusible species of a magnetic material, from which the magnetic region is formed, compared to a chemical affinity between the diffusible species and at least another species of the magnetic material. ... Micron Technology Inc

Memory arrays and methods of forming an array of memory cells

A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. ... Micron Technology Inc

Memory including a selector switch on a variable resistance memory cell

Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.. ... Micron Technology Inc

Semiconductor device structures including two-dimensional material structures, and related semiconductor devices and electronic systems

A method of forming a semiconductor device structure comprises forming at least one 2d material over a substrate. The at least one 2d material is treated with at least one laser beam having a frequency of electromagnetic radiation corresponding to a resonant frequency of crystalline defects within the at least one 2d material to selectively energize and remove the crystalline defects from the at least one 2d material. ... Micron Technology Inc

Methods of verifying data path integrity

Methods for verifying data path integrity are provided. One such method includes reading a partially programmed first set of data from an array of memory cells of the memory device into a page register of the memory device, loading the partially programmed first set of data into a cache register of the memory device, writing a partial set of test data to a portion of the cache register not containing the partially programmed first set of data during a read of a second set of data from the array of memory cells to the page register, reading the partial set of test data from the cache register during the read of the second set of data from the array of memory cells to the page register, and comparing the partial set of test data read from the cache register to the original partial set of test data.. ... Micron Technology Inc

Methods of operating a memory with redistribution of received data

Methods of operating a memory include receiving data for programming to a plurality of memory cells of the memory, redistributing the received data in a reversible manner, programming the redistributed data to the plurality of memory cells, and programming respective second data to each memory cell of the plurality of memory cells containing the redistributed data, wherein the respective second data for any memory cell of the plurality of memory cells has a same data value as the respective second data for each remaining memory cell of the plurality of memory cells.. . ... Micron Technology Inc

Timing control for input receiver

Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes a signal receiver that receives information signal; a control circuit that provides a plurality of control signals; and a signal receiver replica circuit that receives a first reference signal. ... Micron Technology Inc

Multiple plate line architecture for multideck memory array

Methods, systems, and devices for multiple plate line architecture for multideck memory arrays are described. A memory device may include two or more three-dimensional arrays of ferroelectric memory cells overlying a substrate layer that includes various components of support circuitry, such as decoders and sense amplifiers. ... Micron Technology Inc

Semiconductor layered device with data bus

Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch circuit that receives a plurality of data signals, and further provides the plurality of data signals to a plurality of corresponding first ports among a plurality of first data ports and a first data redundancy port; and a second die including a second switch circuit that receives the plurality of data signals from the first die at a plurality of corresponding second ports among a plurality of second data ports and a second data redundancy port and further provides the plurality of data signals to a memory array.. ... Micron Technology Inc

Apparatuses and methods for operating neural networks

The present disclosure includes apparatuses and methods for operating neural networks. An example apparatus includes a plurality of neural networks, wherein the plurality of neural networks are configured to receive a particular portion of data and wherein each of the plurality of neural networks are configured to operate on the particular portion of data during a particular time period to make a determination regarding a characteristic of the particular portion of data.. ... Micron Technology Inc

Enabling a secure boot from non-volatile memory

A system may include a host that may include a processor coupled to a non-volatile memory over a secure communication protocol, as a result, prior to release for manufacturing, a binding code may k established between the host and the non-volatile memory, in some embodiments, this binding code may be stored on the non-volatile memory and not on the host. Then during a boot up of the system, the boot up process may be initiated by the host using code associated with the host, followed by secure booting using the secure protocol using code stored on the non-volatile memory.. ... Micron Technology Inc

Apparatus and methods for in data path compute operations

The present disclosure includes apparatuses and methods for in data path compute operations. An example apparatus includes an array of memory cells. ... Micron Technology Inc

09/27/18 / #20180275964

Apparatuses and methods for random number generation

The present disclosure includes apparatuses and methods for random number generation. An example method includes operating a sense amplifier of a memory device to perform sensing a first voltage on a first sense line coupled to the sense amplifier and sensing a second voltage on a complementary second sense line coupled to the sense amplifier. ... Micron Technology Inc

09/27/18 / #20180275883

Apparatuses and methods for in-memory data switching networks

The present disclosure includes apparatuses and methods for in-memory data switching networks. An example apparatus includes an array of memory cells. ... Micron Technology Inc

09/27/18 / #20180275239

Memory arrays

Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. ... Micron Technology Inc

09/20/18 / #20180269904

Error correction code (ecc) operations in memory for providing redundant error correction

Apparatuses and methods for performing an error correction code (ecc) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.. ... Micron Technology Inc

09/20/18 / #20180269875

Apparatuses and methods for partial bit de-emphasis

Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. ... Micron Technology Inc

09/20/18 / #20180269365

Solid state lighting devices having improved color uniformity and associated methods

Solid state lighting (ssl) devices and methods of manufacturing ssl devices are disclosed herein. In one embodiment, an ssl device comprises a support having a surface and a solid state emitter (sse) at the surface of the support. ... Micron Technology Inc

09/20/18 / #20180269356

Epitaxial formation support structures and associated methods

Epitaxial formation support structures and associated methods of manufacturing epitaxial formation support structures and solid state lighting devices are disclosed herein. In several embodiments, a method of manufacturing an epitaxial formation support substrate can include forming an uncured support substrate that has a first side, a second side opposite the first side, and coefficient of thermal expansion substantially similar to n-type gallium nitride. ... Micron Technology Inc

09/20/18 / #20180269350

Light-emitting metal-oxide-semiconductor devices and associated systems, devices, and methods

Various embodiments of solid state transducer (“sst”) devices are disclosed. In several embodiments, a light emitter device includes a metal-oxide-semiconductor (mos) capacitor, an active region operably coupled to the mos capacitor, and a bulk semiconductor material operably coupled to the active region. ... Micron Technology Inc

09/20/18 / #20180269283

Integrated memory, integrated assemblies, and methods of forming memory arrays

Some embodiments include an integrated memory having an array of capacitors. The array has edges. ... Micron Technology Inc

09/20/18 / #20180269254

Memory devices, systems, and methods of fabrication

Memory devices include an array of memory cells including magnetic tunnel junction regions. The array of memory cells includes access lines extending in a first direction and data lines extending in a second direction transverse to the first direction. ... Micron Technology Inc

09/20/18 / #20180269227

Memory cells and integrated structures

A memory cell comprises, in the following order, channel material, a charge-passage structure, charge-storage material, a charge-blocking region, and a control gate. The charge-passage structure comprises a first material closest to the channel material, a third material furthest from the channel material, and a second material between the first material and the third material. ... Micron Technology Inc

09/20/18 / #20180268909

Memory devices having source lines directly coupled to body regions and methods

Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. ... Micron Technology Inc

09/20/18 / #20180268899

Enhancing nucleation in phase-change memory cells

Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (pcm) cells of a memory array into a temperature regime where nucleation probability of the pcm cells is enhanced prior to applying a subsequent set programming signal. In one embodiment, the method includes applying a nucleation signal to the pcm cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. ... Micron Technology Inc

09/20/18 / #20180268896

Memory cell state in a valley between adjacent data states

The present disclosure includes apparatuses and methods related to memory cell state in a valley between adjacent data states. A number of methods can include determining whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. ... Micron Technology Inc

09/20/18 / #20180268883

Devices, methods, and systems supporting on unit termination

The present disclosure includes devices, methods, and systems supporting on unit termination. A number of embodiments include a number of memory units, wherein a memory unit includes termination circuitry, and a memory unit does not include termination circuitry.. ... Micron Technology Inc

09/20/18 / #20180268876

Apparatuses and methods for sharing transmission vias for memory devices

Apparatuses and methods for transmitting die state information between a plurality of dies are described. An example apparatus includes: a plurality of dies, wherein each die of the plurality of dies includes a first through electrode and a second through electrode; a first path including the first electrodes of the plurality of dies in series; and a second path including the first electrodes of the plurality of dies in series. ... Micron Technology Inc

09/20/18 / #20180267851

Tiered error correction code (ecc) operations in memory

Apparatuses and methods for performing an error correction code (ecc) operation are provided. One example method can include performing a first error code correction (ecc) operation on a portion of data, performing a second ecc operation on the portion of data in response to the first ecc operation failing, and performing a third ecc operation on the portion of data in response to the second ecc operation failing.. ... Micron Technology Inc

09/20/18 / #20180267738

Apparatuses and methods for data movement

The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. ... Micron Technology Inc

09/06/18 / #20180255552

Wireless devices and systems including examples of configuration modes for baseband units and remote radio heads

Examples described herein include systems and methods which include wireless devices and systems with examples of configuration modes for baseband units (bbu) and remote radio heads (rrh). For example, a computing system including a bbu and a rrh may receive a configuration mode selection including information indicative of a configuration mode for respective processing units of the bbu and the rrh. ... Micron Technology Inc

09/06/18 / #20180255546

Wireless devices and systems including examples of configuration modes for baseband units and remote radio heads

Examples described herein include systems and methods which include wireless devices and systems with examples of configuration modes for baseband units (bbu) and remote radio heads (rrh). For example, a computing system including a bbu and a rrh may receive a configuration mode selection including information indicative of a configuration mode for respective processing units of the bbu and the rrh. ... Micron Technology Inc

09/06/18 / #20180255001

Methods and apparatuses for processing multiple communications signals with a single integrated circuit chip

An apparatus is disclosed. The apparatus comprises a plurality of antennas and an integrated circuit chip coupled to the plurality of antennas, and is configured to process cellular signals received from the plurality of antennas in accordance with a cellular communication protocol and to process radio frequency identification (rfid) signals received from the plurality of antennas in accordance with an rfd protocol.. ... Micron Technology Inc

09/06/18 / #20180254930

Wireless devices and systems including examples of full duplex transmission

Examples described herein include systems and methods which include wireless devices and systems with examples of full duplex compensation with a self-interference noise calculator. The self-interference noise calculator may be coupled to antennas of a wireless device and configured to generate adjusted signals that compensate self-interference. ... Micron Technology Inc

09/06/18 / #20180254413

Methods of forming and using materials containing silicon and nitrogen

Some embodiments include methods utilizing atomic layer deposition to form material containing silicon and nitrogen (e.g., silicon nitride). The atomic layer deposition uses sii4 as one precursor and uses a nitrogen-containing material as another precursor. ... Micron Technology Inc

09/06/18 / #20180254334

Methods of forming nand cell units and nand cell units

Some embodiments include methods of forming charge storage transistor gates and standard fet gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. Fet and charge storage transistor gate stacks may be formed. ... Micron Technology Inc

09/06/18 / #20180254283

Integrated structures, capacitors and methods of forming capacitors

Some embodiments include an integrated structure having a semiconductor base and an insulative frame over the semiconductor base. The insulative frame has vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets. ... Micron Technology Inc

09/06/18 / #20180254282

Memory device including pass transistors in memory tiers

Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a semiconductor material, a pillar extending through the semiconductor material, a select gate located along a first portion of the pillar, memory cells located along a second portion of the pillar, and transistors coupled to the select gate through a portion of the semiconductor material. ... Micron Technology Inc

09/06/18 / #20180254245

Wiring with external terminal

Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a pad formation area including a plurality of pads disposed at an edge of the apparatus; a peripheral circuit area including a plurality of circuit blocks coupled to a memory cell array, each circuit block of the plurality of circuit blocks including a via disposed at a side opposite to the pad formation area with respect to each circuit block; and a plurality of conductors, each conductor coupling the via to the corresponding pad, and crossing over, at least in part, an area in the peripheral circuit area that is outside the circuit block comprising the via.. ... Micron Technology Inc

09/06/18 / #20180254214

Integrated circuits having parallel conductors and their formation

Integrated circuits, as well as methods of their formation, include a first conductive structure at a first level of the integrated circuit, a second conductive structure at a second level of the integrated circuit, a first conductor at a third level of the integrated circuit between the first level and the second level, a second conductor at the third level and parallel to the first conductor, and a third conductor at the third level and parallel to the first conductor and to the second conductor. The first conductive structure is in physical and electrical contact with the first conductor and the second conductor. ... Micron Technology Inc

09/06/18 / #20180254086

Apparatus having memory arrays and having trim registers associated with memory array access operation commands

Apparatus include an external controller, a memory storing trim settings corresponding to a plurality of modes of operation, and a memory device. The memory device includes an array of memory cells, an internal controller, and a trim register array. ... Micron Technology Inc

09/06/18 / #20180254075

Apparatuses and methods for providing an indicator of operational readiness of various circuits of a semiconductor device following power up

Apparatuses and methods for providing an indicator of operational readiness of various circuits of a semiconductor device following power up are described in the present disclosure. An example apparatus includes a first circuit configured to receive a supply voltage and further configured to provide an active first signal responsive to the supply voltage exceeding a threshold voltage. ... Micron Technology Inc

09/06/18 / #20180254074

Apparatuses and methods for chip identification in a memory package

Apparatuses, methods, memory packages, and semiconductor chips are disclosed. An example apparatus includes a semiconductor chip including a layer identification setting path circuit configured to receive respective input signals from a plurality of input layer identification setting paths. ... Micron Technology Inc

09/06/18 / #20180254071

Apparatuses and methods for storing a data value in a sensing circuitry element

The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a first data value with a sense amplifier of a sensing circuitry element, moving a second data value from a first storage location of a compute component to a second storage location of the compute component, and storing, in the first storage location, a third data value resulting from a logical operation performed on the first data value and the second data value. ... Micron Technology Inc

09/06/18 / #20180253679

Methods and apparatuses for determining real-time location information of rfid devices

An apparatus is described. The apparatus includes an antenna array configured to detect one or more radio frequency signals from one or more radio emitters and an integrated circuit chip coupled to the array of antennas. ... Micron Technology Inc

09/06/18 / #20180253243

Obfuscation-enhanced memory encryption

The present disclosure includes apparatuses and methods for obfuscation-enhanced memory encryption. An example method comprises performing a write operation, wherein the write operation includes transmitting a number of write transactions received from a host along with a number of spurious transactions to a memory, and wherein the number of spurious transactions are transmitted at a particular rate among the number of received write transactions.. ... Micron Technology Inc

08/23/18 / #20180241383

Apparatuses and methods for duty cycle adjustment

Apparatuses, duty cycle adjustment circuits, adjustment circuits, and methods for duty cycle adjustment are disclosed herein. An example duty cycle adjustment circuit may be configured to receive a signal and adjust a duty cycle of the signal a first amount using a coarse adjustment. ... Micron Technology Inc

08/23/18 / #20180240785

Stacked semiconductor die assemblies with die support members and associated systems and methods

Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. ... Micron Technology Inc

08/23/18 / #20180240782

Stacked semiconductor die assemblies with die substrate extensions

Stacked semiconductor die assemblies with die substrate extensions are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first die mounted to the package substrate, and a second die mounted to the first die. ... Micron Technology Inc

08/23/18 / #20180240534

Memory apparatus with post package repair

Apparatuses for memory repair for a memory device are described. An example apparatus includes: a non-volatile storage element that stores information; a storage latch circuit coupled to the non-volatile storage element and stores latch information; and a control circuit that, in a first repair mode, receives first repair address information, provides the first repair address information to the non-volatile storage element, and further transmits the first repair address information from the non-volatile storage element to the storage latch circuit. ... Micron Technology Inc

08/23/18 / #20180240511

Semiconductor device

Apparatuses and methods for refreshing memory cells of a semiconductor device are described. An example apparatus includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command; and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. ... Micron Technology Inc

08/23/18 / #20180240510

Apparatuses and methods for compute in data path

The present disclosure includes apparatuses and methods for compute in data path. An example apparatus includes an array of memory cells. ... Micron Technology Inc

08/23/18 / #20180240509

Apparatuses and methods to reverse data stored in memory

Apparatuses and methods are provided for reversing data stored in memory. An example apparatus comprises an array of memory cells, a first plurality of sensing components corresponding to a respective first plurality of columns of the array, a second plurality of sensing components corresponding to a respective second plurality of columns of the array, and a plurality of shared input/output (i/o) lines (which may be referred to as sio lines). ... Micron Technology Inc

08/23/18 / #20180239712

Memory array page table walk

An example memory array page table walk can include using an array of memory cells configured to store a page table. The page table walk can include using sensing circuitry coupled to the array. ... Micron Technology Inc

08/23/18 / #20180239672

Error code calculation on sensing circuitry

Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are coupled to sense lines. ... Micron Technology Inc

08/23/18 / #20180239531

Apparatuses and methods for in-memory operations

The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. ... Micron Technology Inc

08/16/18 / #20180233657

Magnetoresistive structures, semiconductor devices, and related systems

Magnetic memory cells, methods of fabrication, semiconductor device structures, and memory systems are disclosed. A magnetic cell core includes at least one magnetic region (e.g., a free region or a fixed region) configured to exhibit a vertical magnetic orientation, at least one oxide-based region, which may be a tunnel junction region or an oxide capping region, and at least one magnetic interface region, which may comprise or consist of iron (fe). ... Micron Technology Inc

08/16/18 / #20180233200

Apparatus, systems, and methods to operate a memory

Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing the logic level in response to a read current flowing through the selected string to a data line. Additional apparatus, systems, and methods are disclosed.. ... Micron Technology Inc

08/16/18 / #20180233198

Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same

A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. ... Micron Technology Inc

08/16/18 / #20180233197

Efficient utilization of memory die area

Methods, systems, and apparatus that support efficient utilization of die area for cross-point memory architecture are described. A memory array may include active memory cells overlying each portion of the substrate that includes certain types of support circuitry, such as decoders and sense amplifiers. ... Micron Technology Inc

08/16/18 / #20180233180

Input buffer circuit

Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and second intermediate voltages responsive to first and second input voltages; first and second voltage terminals; a circuit node; a first transistor coupled between the first voltage terminal and the circuit node and is turned on responsive to at least one of the first and second intermediate voltages; a second amplifier including first and second inverters, at least one of the first and second inverters being coupled between the circuit node and the second voltage terminal; and first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter.. ... Micron Technology Inc

08/16/18 / #20180233177

Active boundary quilt architecture memory

Methods, systems, and apparatus that increase available memory or storage using active boundary areas in quilt architecture are described. A memory array may include memory cells overlying each portion of a substrate layer that includes certain types of support circuitry, such as decoders and sense amplifiers. ... Micron Technology Inc

08/16/18 / #20180232289

Data encoding using spare channels

Implementations of encoding techniques are disclosed. The encoding technique, such as a data bus inversion (dbi) technique, is implementable in a vertically-stacked memory module, but is not limited thereto. ... Micron Technology Inc

08/16/18 / #20180232169

Solid state storage device with quick boot from nand media

Several embodiments of memory devices and related methods for initializing such memory devices based on initialization information on stored in nand-based memory media. In one embodiment, a memory device can include a controller operably coupled to the memory media. ... Micron Technology Inc

08/16/18 / #20180229421

Molding compound including a carbon nano-tube dispersion

A molding compound comprising a resin, a filler, and a carbon nano-tube dispersion is disclosed. The carbon nano-tube dispersion achieves a low average agglomeration size in the molding compound thereby providing desirable electro-mechanical properties and laser marking compatibility. ... Micron Technology Inc

08/09/18 / #20180227158

Wireless devices and systems including examples of mixing coefficient data specific to a processing mode selection

Examples described herein include systems and methods which include wireless devices and systems with examples of mixing input data with coefficient data specific to a processing mode selection. For example, a computing system with processing units may mix the input data for a transmission in a radio frequency (rf) wireless domain with the coefficient data to generate output data that is representative of the transmission being processed according to a specific processing mode selection. ... Micron Technology Inc

08/09/18 / #20180226570

Semiconductor structures and devices and methods of forming semiconductor structures and magnetic memory cells

A magnetic cell includes a magnetic region formed from a precursor magnetic material comprising a diffusive species and at least one other species. An amorphous region is proximate to the magnetic region and is formed from a precursor trap material comprising at least one attracter species having at least one trap site and a chemical affinity for the diffusive species. ... Micron Technology Inc

08/09/18 / #20180226428

Memory cells comprising a programmable field effect transistor having a reversibly programmable gate insulator

A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different vt's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. ... Micron Technology Inc

08/09/18 / #20180226427

Integrated structures comprising vertical channel material and having conductively-doped semiconductor material directly against lower sidewalls of the channel material, and methods of forming integrated structures

Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. ... Micron Technology Inc

08/09/18 / #20180226406

Apparatuses including buried digit lines

Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material in the trenches, filling the trenches with a mask material, removing mask the mask material in the trenches to expose a portion of the metal material, and removing the exposed portion of the metal material. A plurality of conductive contacts is formed in direct contact with the metal material in the buried digit line end region. ... Micron Technology Inc

08/09/18 / #20180226387

Semiconductor device assembly with through-package interconnect and associated systems, devices, and methods

Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. ... Micron Technology Inc

08/09/18 / #20180226333

Semiconductor package and method for fabricating the same

A semiconductor package including at least one semiconductor device, a first redistribution layer, a first molding compound, a second molding compound, conductive vias and a second redistribution layer. The first redistribution layer is disposed beneath the semiconductor device and electrically connected to the semiconductor device. ... Micron Technology Inc

08/09/18 / #20180226127

Apparatuses and methods for comparing data patterns in memory

The present disclosure includes apparatuses and methods related to comparing data patterns in memory. An example method can include comparing a number of data patterns stored in a memory array to a target data pattern. ... Micron Technology Inc

08/09/18 / #20180226121

Apparatuses and methods for refresh control

Apparatuses and methods of for refresh control of a semiconductor device are described. An example apparatus includes a command control circuit that provides a plurality of pulses on a first control signal in series responsive to a plurality of refresh commands issued in series; a signal generation circuit that produces a plurality of pulses on a second control signal in sequence; and a refresh control circuit that receives two or more of the plurality of pulses on the first control signal during a period of time between one pulse and a succeeding pulse of the plurality of pulses on the second control signal, disables refresh operations responsive to at least one of the two or more of the plurality of first control signal and executes a refresh operation responsive to remaining one or more pulses of the two or more of the plurality of pulses on the first control signal.. ... Micron Technology Inc

08/09/18 / #20180226116

Pre-writing memory cells of an array

Methods, systems, and devices for operating a memory cell or memory cells are described. Cells of a memory array may be pre-written, which may include writing the cells to one state while a sense component is isolated from digit lines of the array. ... Micron Technology Inc

08/09/18 / #20180226107

Voltage generation circuit

Disclosed are apparatuses and methods for controlling gate-induced drain leakage current in a transistor device. An apparatus may include a first biasing circuit stage configured to provide a biasing voltage on a biasing signal line, the biasing voltage based on a current through a first resistor associated with the first biasing circuit stage, a voltage generation circuit stage coupled to the first biasing circuit stage, the voltage generation circuit stage having an output transistor that is coupled to the biasing signal line through a gate terminal of the output transistor, and an output line coupled to the voltage generation circuit stage and configured to provide an output voltage signal having a steady-state voltage that is less than a power supply voltage by an amount that corresponds to a voltage drop across the first resistor associated with the first biasing circuit stage.. ... Micron Technology Inc

08/09/18 / #20180225322

Merge tree modifications for maintenance operations

Systems and techniques for merge tree modifications for maintenance operations are described herein. A request for a kvs tree is received. ... Micron Technology Inc

08/09/18 / #20180225321

Merge tree garbage metrics

Systems and techniques for collecting and using merge tree garbage metrics are described herein. A kvset is created for a node in a kvs tree. ... Micron Technology Inc

08/09/18 / #20180225316

Stream selection for multi-stream storage devices

Systems and techniques for stream selection from multi-stream storage devices. Notification of a kvs tree write request for a multi-stream storage device is received. ... Micron Technology Inc

08/09/18 / #20180225315

Kvs tree

A kvs tree and operations thereon are described herein. A key-value set (kvset) is received to store in a key-value data structure on at least one machine readable medium. ... Micron Technology Inc

08/09/18 / #20180225056

Configurable operating mode memory device and methods of operation

Memory devices, and methods of operating similar memory devices, include an array of memory cells comprising a plurality of access lines each configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines, and a controller having a plurality of selectively-enabled operating modes and configured to selectively operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells.. . ... Micron Technology Inc

08/09/18 / #20180224614

Apparatus providing simplified alignment of optical fiber in photonic integrated circuits

A structure for optically aligning an optical fiber to a photonic device and method of fabrication of same. The structure optically aligns an optical fiber to the photonic device using a lens between the two which is moveable by actuator heads. ... Micron Technology Inc

08/02/18 / #20180219153

Semiconductor constructions, methods of forming memory, and methods of forming vertically-stacked structures

Some embodiments include constructions having electrically conductive bitlines within a stack of alternating electrically conductive wordline levels and electrically insulative levels. Cavities extend into the electrically conductive wordline levels, and phase change material is within the cavities. ... Micron Technology Inc

08/02/18 / #20180219021

Memory arrays, and methods of forming memory arrays

Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. ... Micron Technology Inc

08/02/18 / #20180219020

Integrated structures and nand memory arrays

Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include primary regions of a first vertical thickness, and terminal projections of a second vertical thickness which is greater than the first vertical thickness. ... Micron Technology Inc

08/02/18 / #20180219017

Nand memory arrays

Some embodiments include a nand memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. ... Micron Technology Inc

08/02/18 / #20180219002

Semiconductor device assembly with through-mold cooling channel formed in encapsulant

Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. ... Micron Technology Inc

08/02/18 / #20180218767

Apparatuses and methods for distributing row hammer refresh events across a memory device

Apparatuses and methods for distributing row hammer refresh events across a memory device is disclosed. In one embodiment, the present disclosure is directed to an apparatus that includes a first memory configured to receive a sequential series of refresh commands and to replace a first of the sequential refresh commands with a row hammer refresh operation once during a refresh steal cycle, a second memory configured to receive the sequential series of refresh commands at to replace a second of the sequential refresh command with a row hammer refresh operation once during a refresh steal cycle, wherein the first of the sequential refresh commands and the second of the sequential refresh commands are different commands.. ... Micron Technology Inc

08/02/18 / #20180218765

Integrated memory assemblies comprising multiple memory array decks

Some embodiments include an integrated memory assembly having a first memory array deck over a second memory array deck. A first series of conductive lines extends across the first memory array deck, and a second series of conductive lines extends across the second memory array deck. ... Micron Technology Inc

08/02/18 / #20180217960

Methods and apparatuses for differential signal termination

According to one embodiment, an apparatus comprises a differential signaling bus, a tristate transmitter connected with the differential signaling bus, the tristate transmitter configured to provide a signal on the differential signaling bus responsive to a corresponding control signal, a receiver, a pair of differential inputs of the receiver connected with the differential signaling bus and configured to receive the signal from the differential signaling bus, and a termination circuit configured to couple a first differential input of the pair of differential inputs to a first voltage source and to couple a second differential input of the pair of differential inputs to a second voltage source, wherein the first and second voltage sources have different voltage levels.. . ... Micron Technology Inc

08/02/18 / #20180217782

Buffer operations in memory

Apparatuses and methods for performing buffer operations in memory are provided. One example method can include storing second page data and third page data on a buffer while programming first page data during a first pass programming operation and programming the second page data and the third page data from the buffer to the array of memory cells during a second pass programming operation.. ... Micron Technology Inc

08/02/18 / #20180217773

Memory device configuration commands

Apparatuses and methods for configuring a memory device using configuration commands are provided. One example method can include executing a first command while the memory device is in a ready state to configure the memory device to a particular mode and executing a second command to perform a first operation while the memory device is in the particular mode.. ... Micron Technology Inc

07/26/18 / #20180212516

Charge pumps and methods of operating charge pumps

Methods of operating a charge pump, and charge pumps configured to perform similar methods, involve monitoring a level of a supply voltage of the charge pump, and turning off an oscillator of the charge pump responsive to the level of the supply voltage dropping below a certain level, wherein turning off the oscillator comprises setting an inverter in a ring oscillator loop of the oscillator to a steady state output.. . ... Micron Technology Inc

07/26/18 / #20180211896

Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components

Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. ... Micron Technology Inc

07/26/18 / #20180211868

Methods for isolating portions of a loop of pitch-multiplied material and related structures

Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. ... Micron Technology Inc

07/26/18 / #20180211714

Apparatus configured to program memory cells using an intermediate level for multiple data states

Apparatus including an array of memory cells and a controller configured to apply a particular programming pulse to a plurality of memory cells having a first subset of memory cells having respective desired data states that are lower than a particular data state and a second subset of memory cells having respective desired data states that are higher than or equal to the particular data state, to at least partially inhibit each memory cell of the first subset of memory cells from programming while not inhibiting any memory cell of the second subset of memory cells from programming and while applying the particular programming pulse, then to apply a subsequent programming pulse while not inhibiting any memory cell of the first subset of memory cells from programming other than any memory cell of the first subset of memory cells having its respective desired data state equal to a lowest data state, and while not inhibiting any memory cell of the second subset of memory cells from programming.. . ... Micron Technology Inc

07/26/18 / #20180211711

Apparatus and methods of operating memory for negative gate to body conditions

Methods of operating a memory, and apparatus so configured, include applying a first voltage level to a first voltage node connected to a first end of a string of series-connected memory cells, applying a second voltage level to a second voltage node connected to a second end of the string, applying a third voltage level less than the first and second voltage levels to a control gate of a first memory cell of the string while applying the first and second voltage levels to the first and second voltage nodes, and applying a fourth voltage level less than the third voltage level to a control gate of a second memory cell of the string while applying the third voltage level to the control gate of the first memory cell, wherein the first memory cell is closer to the first voltage node than the second memory cell.. . ... Micron Technology Inc

07/26/18 / #20180211710

Memory device including multiple gate-induced drain leakage current generator circuits

Some embodiments include apparatuses and methods of using and forming such apparatuses. An apparatus among the apparatuses includes first and second conductive materials located in respective first and second levels of the apparatus, a pillar including a length extending between the first and second conductive materials, memory cells and control lines located along the pillar, a first select gate and a first select line located along the pillar between the first conductive material and the memory cells, a second select gate and a second select line located along the pillar between the first conductive material and the first select line, a first transistor and a first transistor gate line located along the pillar between the first conductive material and the first select line, and a second transistor and a second transistor gate line located along the pillar between the first conductive material and the first transistor.. ... Micron Technology Inc

07/26/18 / #20180211695

Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters

Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. ... Micron Technology Inc

07/26/18 / #20180210847

Memory protocol with command priority

The present disclosure includes apparatuses and methods related to a memory protocol with command priority. An example apparatus can execute a command that includes a read identification (rid) number based on a priority assigned to the rid number in a register. ... Micron Technology Inc

07/26/18 / #20180210660

Multidimensional contiguous memory allocation

The present disclosure is related to multidimensional contiguous memory allocation. Multidimensional contiguous memory allocation can include receiving an allocation request for an amount of memory that is contiguous in a multiple dimensions of the memory and determining whether the memory includes a region corresponding to the requested amount that is a candidate as being unallocated based on information indicating a maximum number of contiguous unallocated allocable portions of the memory. ... Micron Technology Inc

07/26/18 / #20180210655

Hybrid memory drives, computer system, and related method for operating a multi-mode hybrid drive

A multi-mode hybrid memory drive comprises a bulk memory device and a removable cache memory device. A controller of the bulk memory device may be configured to operate the bulk memory device in either a stand-alone mode or a hybrid mode responsive to detecting the removable cache memory device being coupled with a cache port of the bulk memory device. ... Micron Technology Inc

07/26/18 / #20180210653

Partially written block treatment

The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. ... Micron Technology Inc

07/19/18 / #20180204880

Thermal insulation for three-dimensional memory arrays

Methods, systems, and devices for a three-dimensional memory array are described. Memory cells may transform when exposed to elevated temperatures, including elevated temperatures associated with a read or write operation of a neighboring cell, corrupting the data stored in them. ... Micron Technology Inc

07/19/18 / #20180204879

Thermal insulation for three-dimensional memory arrays

Methods, systems, and devices for a three-dimensional memory array are described. Memory cells may transform when exposed to elevated temperatures, including elevated temperatures associated with a read or write operation of a neighboring cell, corrupting the data stored in them. ... Micron Technology Inc

07/19/18 / #20180204851

Memory arrays and methods of fabricating integrated structures

Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. ... Micron Technology Inc

07/19/18 / #20180204849

Memory cells, integrated structures and memory arrays

Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. ... Micron Technology Inc

07/19/18 / #20180204803

Interconnect structure with nitrided barrier

Semiconductor device interconnect structures comprising nitrided barriers are disclosed herein. In one embodiment, an interconnect structure includes a conductive material at least partially filling an opening in a semiconductor substrate, and a nitrided barrier between the conductive material and a sidewall in the opening. ... Micron Technology Inc

07/19/18 / #20180204799

Conductive structures, systems and devices including conductive structures and related methods

Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. ... Micron Technology Inc

07/19/18 / #20180204630

Apparatuses and methods for high speed writing test mode for memories

Apparatuses and methods are provided for a high speed writing test mode for memories. An example apparatus includes a memory core, a data terminal coupled to a data receiver, a read buffer coupled between the data terminal and the memory core, and a write buffer coupled between the data receiver and the memory core. ... Micron Technology Inc

07/19/18 / #20180204608

Apparatuses and methods for providing internal clock signals of different clock frequencies in a memory device

Apparatuses and methods for providing internal clock signals of different clock frequencies in a semiconductor device are described in the present application. An example apparatus includes a read command buffer and a read data output circuit. ... Micron Technology Inc

07/19/18 / #20180203671

Signed division in memory

Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a first access line and a number of sense lines. ... Micron Technology Inc

07/19/18 / #20180203613

Memory device including mixed non-volatile memory cell types

Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a conductive line, non-volatile memory cells of a first memory cell type, the non-volatile memory cells coupled in series among each other, and an additional non-volatile memory cell of a second memory cell type coupled to the conductive line and coupled in series with the non-volatile memory cells of the first memory cell type. ... Micron Technology Inc

07/12/18 / #20180198642

Computerized apparatus with a high speed data bus

A computerized apparatus configured for high-speed data transactions between components thereof. In one embodiment, the computerized apparatus includes a high-speed ring data bus apparatus with a plurality of nodes, and associated application apparatus in data communication with at least one of the nodes. ... Micron Technology Inc

07/12/18 / #20180198063

Memory cells, semiconductor devices including the memory cells, and methods of operation

Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is included between the cell material and the ion-source material. ... Micron Technology Inc

07/12/18 / #20180197949

Integrated memory

Some embodiments include an integrated memory having an array of capacitors. The array has edges. ... Micron Technology Inc

07/12/18 / #20180197942

Methods of forming an array of capacitors, methods of forming an array of memory cells individually comprising a capacitor and a transistor, arrays of capacitors, and arrays of memory cells individually comprising a capacitor and a transistor

A method of forming an array of capacitors comprises forming elevationally-extending and longitudinally-elongated capacitor electrode lines over a substrate. Individual of the capacitor electrode lines are common to and a shared one of two capacitor electrodes of individual capacitors longitudinally along a line of capacitors being formed. ... Micron Technology Inc

07/12/18 / #20180197870

Memory cells and methods of forming a capacitor

A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. ... Micron Technology Inc

07/12/18 / #20180197869

Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors

A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in support material. An elevational mid-portion of individual of the conductive linings is removed to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings. ... Micron Technology Inc

07/12/18 / #20180197864

Memory cells, arrays of two transistor-one capacitor memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry

A two transistor-one capacitor memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. ... Micron Technology Inc

07/12/18 / #20180197862

Memory cell, an array of memory cells individually comprising a capacitor and a transistor with the array comprising rows of access lines and columns of digit lines, a 2t-1c memory cell, and methods of forming an array of capacitors and access transistors there-above

A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material. The trenches individually comprise longitudinally-spaced masked portions and longitudinally-spaced openings in the trenches longitudinally between the masked portions. ... Micron Technology Inc

07/12/18 / #20180197735

Silicon chalcogenate precursors and methods of forming the silicon chalcogenate precursors

A silicon chalcogenate precursor comprising the chemical formula of si(xr1)nr24-n, where x is sulfur, selenium, or tellurium, r1 is hydrogen, an alkyl group, a substituted alkyl group, an alkoxide group, a substituted alkoxide group, an amide group, a substituted amide group, an amine group, a substituted amine group, or a halogen group, each r2 is independently hydrogen, an alkyl group, a substituted alkyl group, an alkoxide group, a substituted alkoxide group, an amide group, a substituted amide group, an amine group, a substituted amine group, or a halogen group, and n is 1, 2, 3, or 4. Methods of forming the silicon chalcogenate precursor, methods of forming silicon nitride, and methods of forming a semiconductor structure are also disclosed.. ... Micron Technology Inc

07/12/18 / #20180197620

Setting a default read signal based on error correction

The present disclosure includes apparatuses and methods related to setting a default read signal based on error correction. A number of methods can include reading a page of data from a group of memory cells with a first discrete read signal and error correcting at least one codeword of the page of data as read with the first discrete read signal. ... Micron Technology Inc

07/12/18 / #20180197595

Apparatuses and methods for a memory device with dual common data i/o lines

Apparatuses are presented for a semiconductor device utilizing dual i/o line pairs. The apparatus includes a first i/o line pair coupled to a first local i/o line pair. ... Micron Technology Inc

07/12/18 / #20180197583

Methods and apparatuses for providing a program voltage responsive to a voltage determination

Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. ... Micron Technology Inc

07/12/18 / #20180196757

Virtual address table

The present disclosure includes apparatuses and methods related to virtual address tables. An example method comprises generating an object file that comprises: an instruction comprising a number of arguments; and an address table comprising a number of indexed address elements. ... Micron Technology Inc

07/12/18 / #20180196743

Directed sanitization of memory

The present disclosure includes apparatuses and methods for directed sanitization of memory. One example method comprises, responsive to receiving a sanitization command, performing a deterministic garbage collection operation on a memory, wherein performing the deterministic garbage collection operation results in physical erasure of all invalid data stored on the memory without losing valid data stored on the memory.. ... Micron Technology Inc

07/12/18 / #20180196705

Identifying asynchronous power loss

Apparatus include controllers configured to iteratively program a group of memory cells to respective desired data states; determine whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells; and if a power loss to the apparatus is indicated, to change the desired data state of the particular memory cell before continuing with the programming. Apparatus further include controllers configured to read a particular memory cell of a last written page of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and to mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.. ... Micron Technology Inc

07/12/18 / #20180196614

Error correction

An example apparatus for error correction can include an array of memory cells and a controller. The controller can be configured to perform a dummy read on a portion of data stored in the array. ... Micron Technology Inc

07/12/18 / #20180195049

Arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, methods of forming a tier of an array of memory cells, and methods of forming an array of memory cells individually comprising a capacitor and an elevationally-extending transistor

A method of forming a tier of an array of memory cells within an array area, the memory cells individually comprising a capacitor and an elevationally-extending transistor, the method comprising using two, and only two, sacrificial masking steps within the array area of the tier in forming the memory cells. Other methods are disclosed, as are structures independent of method of fabrication.. ... Micron Technology Inc

07/05/18 / #20180192517

Apparatus and methods for via connection with reduced via currents

Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. ... Micron Technology Inc

07/05/18 / #20180191528

Testing impedance adjustment

Methods of operating integrated circuit devices include generating a voltage level at a particular node in response to a first voltage level applied to a termination device and a second voltage level applied to a reference resistance; determining whether a plurality of available resistance values of the termination device satisfy a criterion that each available resistance value is either less than a resistance value of the reference resistance, or each available resistance value is greater than the resistance value of the reference resistance; and, when the plurality of available resistance values of the termination device satisfy the criterion, determining whether a voltage level generated at the particular node for a particular available resistance value of the plurality of available resistance values is between a voltage level of a first reference voltage and a voltage level of a second reference voltage.. . ... Micron Technology Inc

07/05/18 / #20180190873

Solid state transducer dies having reflective features over contacts and associated systems and methods

Systems and methods for improved light emitting efficiency of a solid state transducer (sst), for example light emitting diodes (led), are disclosed. One embodiment of an sst die in accordance with the technology includes a reflective material disposed over electrical connectors on a front side of the die. ... Micron Technology Inc

07/05/18 / #20180190862

Solid state lighting devices with dielectric insulation and methods of manufacturing

Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. ... Micron Technology Inc

07/05/18 / #20180190761

Mim capacitor with enhanced capacitance

A metal-insulator-metal (mim) capacitor is disclosed. The mim capacitor includes a substrate having a first dielectric layer thereon and a bottom electrode embedded in the first dielectric layer. ... Micron Technology Inc

07/05/18 / #20180190717

Memory devices, systems, and methods of forming arrays of memory cells

Memory devices include an array of memory cells including magnetic tunnel junction regions. The array of memory cells includes access lines extending in a first direction and data lines extending in a second direction transverse to the first direction. ... Micron Technology Inc

07/05/18 / #20180190713

Magnetic memory device with grid-shaped common source plate, system, and method of fabrication

Magnetic memory devices include an array of magnetic memory cells including magnetic tunnel junction regions. The array of magnetic memory cells includes access lines extending in a column direction and data/sense lines extending in a row direction transverse to the column direction. ... Micron Technology Inc

07/05/18 / #20180190620

Interconnect structures with intermetallic palladium joints and associated systems and methods

Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. ... Micron Technology Inc

07/05/18 / #20180190613

Wiring with external terminal

Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a connection wiring of a ring-shape having comprising a hole and a conductive layer surrounding the hole, the conductive layer including a first connection point and a second connection point that are located so that a straight line between the first connection point and the second connection point crosses over the hole; an external terminal coupled to the first connection point of the conductive layer of the connection wiring; and an internal circuit coupled to the second connection point of the conductive layer of the connection wiring.. ... Micron Technology Inc

07/05/18 / #20180190587

Semiconductor device structures including stair step structures, and related semiconductor devices

A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. ... Micron Technology Inc

07/05/18 / #20180190582

Semiconductor package with embedded mim capacitor, and method of fabricating thereof

An interposer includes a first redistribution layer, an organic substrate, a capacitor, a hard mask layer, a conductive pillar, and a second redistribution layer. The organic substrate is on the first redistribution layer. ... Micron Technology Inc

07/05/18 / #20180190571

Semiconductor device having through-silicon-via and methods of forming the same

Semiconductor devices having a through-silicon-via and methods of forming the same are described herein. As an example, a semiconductor device may include a substrate material, a through-silicon-via protrusion extending from the substrate material, a first dielectric material formed on the substrate material, a second dielectric material formed on the first dielectric material, and an interconnect formed on the through-silicon-via protrusion, where the interconnect formed is in an opening in the second dielectric material.. ... Micron Technology Inc

07/05/18 / #20180190531

Semiconductor package structures including redistribution layers

A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. ... Micron Technology Inc

07/05/18 / #20180190368

Timing based arbiter systems and circuits for zq calibration

Systems and apparatuses are provided for an arbiter circuit for timing based zq calibration. An example system includes a resistor and a plurality of chips. ... Micron Technology Inc

07/05/18 / #20180190367

Apparatuses and methods for memory testing and repair

Some embodiments include apparatuses and methods having a first interface to communicate with a processing unit, a second interface to communicate with a memory device, and a module coupled to the first and second interfaces. In at least one of the embodiments, the module can be configured to obtain information stored in the memory device and perform at least one of testing and repairing of a memory structure of the memory device based at least in part on the information.. ... Micron Technology Inc

07/05/18 / #20180190349

Accessing memory cells in parallel in a cross-point array

Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. ... Micron Technology Inc

07/05/18 / #20180190347

Programming memories with multi-level pass signal

Methods of operating a memory include applying a first voltage level to control gates of a plurality of memory cells selected to be programmed while applying a second voltage level to a respective data line for each memory cell of the plurality of memory cells; increasing the voltage level applied to the respective data line for memory cells of a first subset of memory cells to a third voltage level then increasing the voltage level applied to the control gates of the plurality of memory cells to a fourth voltage level; increasing the voltage level applied to the respective data line for each memory cell of a second subset of memory cells of the plurality of memory cells to a fifth voltage level then; and after increasing the voltage level applied to the respective data line for each memory cell of the second subset of memory cells to the fifth voltage level, increasing the voltage level applied to the control gates of the plurality of memory cells to a sixth voltage level.. . ... Micron Technology Inc

07/05/18 / #20180190342

Oscillator controlled random sampling method and circuit

Various embodiments comprise methods and apparatuses for selecting a randomly-chosen seed row from among a stream of available data in a memory system. A refresh operation is then performed on at least one selected row of memory in the memory system based on the randomly-chosen seed row. ... Micron Technology Inc

07/05/18 / #20180190337

Ground reference scheme for a memory cell

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. ... Micron Technology Inc

07/05/18 / #20180190334

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. ... Micron Technology Inc

07/05/18 / #20180189031

Multiplication operations in memory

Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. ... Micron Technology Inc

07/05/18 / #20180188996

Apparatuses and methods for data transfer from sensing circuitry to a controller

The present disclosure describes data transfer in a memory device from sensing circuitry to controller. An example apparatus includes a controller coupled to a memory device. ... Micron Technology Inc

07/05/18 / #20180188965

Write command overlap detection

The present disclosure includes methods and apparatuses that include write command overlap detection. A number of embodiments include receiving an incoming write command and comparing a logical address of the incoming write command to logical addresses of a number of write commands in a queue using a tree data structure, wherein a starting logical address and/or an ending logical address of the incoming write command and a starting logical address and/or an ending logical address of each of the number of write commands are associated with nodes in the tree data structure.. ... Micron Technology Inc

07/05/18 / #20180188647

Methods of forming photonic device structures and electronic devices

A method of forming a photonic device structure comprises forming a photoresist over a photonic material over a substrate. The photoresist is exposed to radiation through a gray-tone mask to form at least one photoexposed region and at least one non-photoexposed region of the photoresist. ... Micron Technology Inc

06/28/18 / #20180182765

Methods of forming memory arrays

Some embodiments include a method of forming a memory array. A wordline is formed to extend along a first direction, and along a rail of semiconductor material. ... Micron Technology Inc

06/28/18 / #20180182764

Memory arrays comprising ferroelectric capacitors

Some embodiments include a memory array which has rows of fins. Each fin has a first pedestal, a second pedestal and a trough between the first and second pedestals. ... Micron Technology Inc

06/28/18 / #20180182763

Memory arrays

Some embodiments include a memory array having memory cells arranged in rows and columns. The rows extend along a first direction and the columns extend along a second direction, with an angle between the first and second directions being less than 90°. ... Micron Technology Inc

06/28/18 / #20180182762

Memory arrays

Some embodiments include a memory array having rows of fins. Each fin has at least one channel region. ... Micron Technology Inc

06/28/18 / #20180182761

Memory devices, memory arrays, and methods of forming memory arrays

Some embodiments include a memory device. The device has a fin with a first source/drain region, a second source/drain region and a channel region. ... Micron Technology Inc

06/28/18 / #20180182457

Apparatuses and methods including memory access in cross point memory

Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. ... Micron Technology Inc

06/28/18 / #20180181464

Apparatuses and methods for selective determination of data error repair

Apparatuses and methods are described for selective determination of data error repair. An example apparatus includes a memory array and a controller coupled to the memory array. ... Micron Technology Inc

06/21/18 / #20180176443

Method and apparatus providing pixel array having automatic light control pixels and image capture pixels

A pixel array uses two sets of pixels to provide accurate exposure control. One set of pixels provide continuous output signals for automatic light control (alc) as the other set integrates and captures an image. ... Micron Technology Inc

06/21/18 / #20180175145

Memory arrays

The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. ... Micron Technology Inc

06/21/18 / #20180175085

Elevated pocket pixels, imaging devices and systems including the same and method of forming the same

An elevated photosensor for image sensors and methods of forming the photosensor. The photosensor may have light sensors having indentation features including, but not limited to, v-shaped, u-shaped, or other shaped features. ... Micron Technology Inc

06/21/18 / #20180175059

Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells

A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. ... Micron Technology Inc

06/21/18 / #20180175039

Conductive structures, wordlines and transistors

Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 ev, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 ev, and is shaped as an upwardly-opening container. ... Micron Technology Inc

06/21/18 / #20180175017

Apparatuses and methods for semiconductor circuit layout

Apparatuses including circuit layout regions of a semiconductor device and methods of designing the circuit layout regions of a semiconductor device are described. An example apparatus includes a first layout region including a first transistor area including at least one first transistor, at least one contact in proximity to the first transistor area, and a first resistor area comprising at least one first resistor coupled to the at least one first transistor. ... Micron Technology Inc

06/21/18 / #20180174993

Uniform electrochemical plating of metal onto arrays of pillars having different lateral densities and related technology

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. ... Micron Technology Inc

06/21/18 / #20180174960

Memory devices, semiconductor devices and related methods

Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures. ... Micron Technology Inc

06/21/18 / #20180174943

Semiconductor die assembly having heat spreader that extends through underlying interposer and related technology

A semiconductor die assembly in accordance with an embodiment of the present technology includes a first semiconductor die, a package substrate underlying the first semiconductor die, an interposer between the package substrate and the first semiconductor die, and a second semiconductor die between the package substrate and the interposer. The semiconductor die assembly further comprises a heat spreader including a cap thermally coupled to the first semiconductor die at a first elevation, and a pillar thermally coupled to the second semiconductor die at a second elevation different than the first elevation. ... Micron Technology Inc

06/21/18 / #20180174926

Semiconductor devices comprising nitrogen-doped gate dielectric, and methods of forming semiconductor devices

Some embodiments include semiconductor devices having first transistors of a first channel type and having second transistors of a second channel type. The first transistors include a first gate electrode, a first nitrogen-doped gate dielectric layer and a first high-k material. ... Micron Technology Inc

06/21/18 / #20180174902

Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods

Semiconductor devices having interconnects incorporating negative expansion (nte) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. ... Micron Technology Inc

06/21/18 / #20180174630

Modified decode for corner turn

Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an array of memory cell and decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element. ... Micron Technology Inc

06/21/18 / #20180174625

Apparatuses, circuits, and methods for biasing signal lines

Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. ... Micron Technology Inc

06/21/18 / #20180174622

Power delivery circuitry

A memory device may include a memory system and an energy storage device. Additionally, the energy storage device may supply a first power to the memory system when a second power from a power supply is eliminated or insufficient.. ... Micron Technology Inc

06/21/18 / #20180173621

Unaligned data coalescing

The present disclosure includes methods and systems for coalescing unaligned data. One method includes receiving a first write command associated with a first unaligned portion of data, receiving a second write command associated with a second unaligned portion of data, and coalescing the first unaligned portion of data and the second unaligned portion of data, wherein coalescing includes writing the first unaligned portion of data and the second unaligned portion of data to a page in a memory device.. ... Micron Technology Inc

06/21/18 / #20180173499

Multiplication operations in memory

Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. ... Micron Technology Inc

06/21/18 / #20180173267

Methods and apparatuses including a process, voltage, and temperature independent current generator circuit

Apparatuses, methods, and current generators that generate current are described. An example apparatus includes a current source configured to provide a current. ... Micron Technology Inc

06/14/18 / #20180167194

Wireless devices and systems including examples of cross correlating wireless transmissions

Examples described herein include systems and methods which include wireless devices and systems with examples of cross correlation including symbols indicative of radio frequency (rf) energy. An electronic device including a statistic calculator may be configured to calculate a statistic including the cross-correlation of the symbols. ... Micron Technology Inc

06/14/18 / #20180167055

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. ... Micron Technology Inc

06/14/18 / #20180167030

Apparatuses and methods for temperature independent oscillators

Apparatuses and methods for temperature independent oscillator circuits are disclosed herein. An example apparatus may include a pulse generator circuit configured to provide a periodic pulse based on the charging and discharging of a capacitor and further based on a reference voltage. ... Micron Technology Inc

06/14/18 / #20180166811

Board edge connector

Apparatuses and methods for forming serial advanced technology attachment (sata) board edge connectors with electroplated hard gold contacts. One example method can include forming a tie bar on an inner layer of a printed circuit board (pcb), forming a trace on an outer layer of the pcb, forming a via, wherein the via electrically couples the tie bar to the trace, forming a contact coupled to the trace on the outer layer, and sending an electrical charge from the tie bar through the via and the trace to the contact to electroplate the contact.. ... Micron Technology Inc

06/14/18 / #20180166629

Phase change memory stack with treated sidewalls

Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. ... Micron Technology Inc

06/14/18 / #20180166464

Integrated structures and methods of forming vertically-stacked memory cells

Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. ... Micron Technology Inc

06/14/18 / #20180166317

Semiconductor with through-substrate interconnect

Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. ... Micron Technology Inc

06/14/18 / #20180166151

Ferroelectric memory cell recovery

Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell that is fatigued due to repeated access (read or write) operations. ... Micron Technology Inc

06/14/18 / #20180166138

Resistance variable element methods and apparatuses

Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a first data line voltage and a first control gate voltage, and then performs a second operation on a second resistance variable element using the common source voltage, a second data line voltage and a second control gate voltage. Additional apparatus and methods are described.. ... Micron Technology Inc

06/14/18 / #20180165440

System and method for controlling user access to an electronic device

A method and system for authenticating a user to access a computer system. The method comprises communicating security information to the computer system, and providing the computer system with an implicit input. ... Micron Technology Inc

06/07/18 / #20180159933

Memory network methods, apparatus, and systems

Apparatus and systems may include a first node group include a first network node coupled to a memory, the first network node including a first port, a second port, a processor port, and a hop port. Network node group may include a second network node coupled to a memory, the second network node including a first port, a second port, a processor port, and a hop port, the hop port of the second network node coupled to the hop port of the first network node and configured to communicate between the first network node and the second network node. ... Micron Technology Inc

06/07/18 / #20180159692

Solid state storage device with command and control access

Several embodiments of memory devices and systems with command and control access are described herein. In one embodiment, a memory device includes a controller having a processor and a memory component operably coupled to the processor. ... Micron Technology Inc

06/07/18 / #20180158800

Apparatus and method of power transmission sensing for stacked devices

Apparatuses for supplying power supply voltage in a plurality of dies are described. An example apparatus includes: a circuit board; a regulator on the circuit board that regulates a first voltage; a semiconductor device on the circuit board that receives the first voltage through a power line in the circuit board. ... Micron Technology Inc

06/07/18 / #20180158778

Packaged semiconductor assemblies and methods for manufacturing such assemblies

Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. ... Micron Technology Inc

06/07/18 / #20180158751

Semiconductor device packages with direct electrical connections and related methods

Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. ... Micron Technology Inc

06/07/18 / #20180158527

Volatile memory architecutre in non-volatile memory devices and related controllers

In some embodiments, one register of a non-volatile memory can be used for read operations and another register of the non-volatile memory can be used for programming operations. For instance, a cache register of a nand flash memory can be used in connection with read operations and a data register of the nand flash memory can be used in connection with programming operations. ... Micron Technology Inc

06/07/18 / #20180158504

Apparatuses and methods for controlling refresh operations

An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. ... Micron Technology Inc

06/07/18 / #20180158502

Dynamic reference voltage determination

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first value may be written to a first memory cell and a second value may be written to a second memory cell. ... Micron Technology Inc

06/07/18 / #20180158501

Dynamic adjustment of memory cell digit line capacitance

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. ... Micron Technology Inc

06/07/18 / #20180157439

Memory protocol

The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can execute a read command that includes a first chunk of data and a second chunk of data by assigning a first read identification (rid) number to the first chunk of data and a second rid number to the second chunk of data, sending the first chunk of data and the first rid number to a host, and sending the second chunk of data and the second rid number to the host. ... Micron Technology Inc

05/31/18 / #20180152330

Wireless devices and systems including examples of mixing input data with coefficient data

Examples described herein include systems and methods which include wireless devices and systems with examples of mixing input data with coefficient data. For example, a computing system with processing units may mix the input data for a transmission in a radio frequency (rf) wireless domain with the coefficient data to generate output data that is representative of the transmission being processed according to the wireless protocol in the rf wireless domain. ... Micron Technology Inc

05/31/18 / #20180151798

Multiferroic magnetic tunnel junction devices

Some embodiments include a magnetic tunnel junction device having a first magnetic electrode, a second magnetic electrode, and a tunnel insulator material between the first and second magnetic electrodes. A tungsten-containing material is directly against one of the magnetic electrodes. ... Micron Technology Inc

05/31/18 / #20180151415

Forming array contacts in semiconductor memories

Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. ... Micron Technology Inc

05/31/18 / #20180151207

Memory device with write data bus control

Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.. ... Micron Technology Inc

05/31/18 / #20180151206

Apparatuses for modulating threshold voltages of memory cells

Apparatuses for increasing the voltage budget window of a memory array are described. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. ... Micron Technology Inc

05/31/18 / #20180151201

Interconnections for 3d memory

Apparatuses and methods for interconnections for 3d memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. ... Micron Technology Inc

05/31/18 / #20180150625

System and method for controlling user access to an electronic device

A method and system for authenticating a user to access a computer system. The method comprises communicating security information to the computer system, and providing the computer system with an implicit input. ... Micron Technology Inc

05/24/18 / #20180146146

Method, apparatus and system providing a storage gate pixel with high dynamic range

A method, apparatus and system are described providing a high dynamic range pixel. An integration period has multiple sub-integration periods during which charges are accumulated in a photosensor and repeatedly transferred to a storage node, where the charges are accumulated for later transfer to another storage node for output.. ... Micron Technology Inc

05/24/18 / #20180145254

Methods of forming resistive memory elements

A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising longitudinally extending, columnar grains of crystalline material, an ion reservoir material over the buffer material, and a second electrode over the ion reservoir material. A memory cell, a memory device, an electronic system, and a method of forming a resistive memory element are also described.. ... Micron Technology Inc

05/24/18 / #20180145250

Method, system, and device for l-shaped memory component

Embodiments disclosed herein may relate to forming reduced size storage components in a cross-point memory array. In an embodiment, a storage cell comprising an l-shaped storage component having an approximately vertical portion extending from a first electrode positioned below the storage material to a second electrode positioned above and/or on the storage component. ... Micron Technology Inc

05/24/18 / #20180145112

Semiconductor devices with seed and magnetic regions and methods of fabrication

A magnetic cell core includes a seed region with a plurality of magnetic regions and a plurality of nonmagnetic regions thereover. The seed region provides a template that enables formation of an overlying nonmagnetic region with a microstructure that enables formation of an overlying free region with a desired crystal structure. ... Micron Technology Inc

05/24/18 / #20180145029

Methods of forming semiconductor device structures including staircase structures

A semiconductor device structure comprises stacked tiers each comprising a conductive structure and an insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and an opening laterally adjacent a first side of the at least one staircase structure and extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. Conductive structures of the stacked tiers laterally extend from the steps of the at least one staircase structure completely across a second side of the at least one staircase structure opposing the first side to form continuous conductive paths laterally extending completely across the stacked tiers. ... Micron Technology Inc

05/24/18 / #20180144937

Methods of patterning a target layer

A method of forming patterns includes the steps of providing a substrate on which a target layer and a hard mask layer are formed; forming a plurality of first resist patterns on the hard mask layer; performing a tilt-angle ion implant process to form a first doped area and a second doped area in the hard mask layer between adjacent first resist patterns; removing the first resist patterns; coating a directed self-assembly (dsa) material layer onto the hard mask layer; performing a self-assembling process of the dsa material layer to form repeatedly arranged block copolymer patterns in the dsa material layer; removing undesired portions from the dsa material layer to form second patterns on the hard mask layer; transferring the second patterns to the hard mask layer to form third patterns; and etching the target layer through the third patterns.. . ... Micron Technology Inc

05/24/18 / #20180144927

Semiconductor structures comprising silicon nitride and related methods

Methods of forming silicon nitride. Silicon nitride is formed on a substrate by atomic layer deposition at a temperature of less than or equal to about 275° c. ... Micron Technology Inc

05/24/18 / #20180144796

Memory and electronic devices with reduced operational energy in chalcogenide material

Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. ... Micron Technology Inc

05/24/18 / #20180144795

Variable resistance memory stack with treated sidewalls

Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming a memory stack out of a plurality of elements. ... Micron Technology Inc

05/24/18 / #20180144792

Memory cells, memory systems, and memory programming methods

Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. ... Micron Technology Inc

05/24/18 / #20180144791

Determining soft data for fractional digit memory cells

Apparatuses and methods for determining soft data for fractional digit memory cells are provided. One example apparatus can include a controller to determine states of memory cells of a group of memory cells operated as fractional digit memory cells, and determine soft data based, at least partially, on dimensions to which particular memory cells correspond with respect to the group of memory cells, determined states of the memory cells with respect to a state adjacent a state corresponding to a swapping shell, and whether a particular memory cell is a candidate for swapping.. ... Micron Technology Inc

05/24/18 / #20180144783

Cell-based reference voltage generation

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first state and a second ferroelectric memory cell may be initialized to a different state. ... Micron Technology Inc

05/24/18 / #20180144779

Control lines to sensing components

Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might include an array of memory cells. ... Micron Technology Inc

05/24/18 / #20180143908

Continuous page read for memory

Subject matter disclosed herein relates to techniques to read memory in a continuous fashion.. . ... Micron Technology Inc

05/24/18 / #20180143875

Monitoring error correction operations performed in memory

The present disclosure includes apparatuses and methods for monitoring error correction operations performed in memory. A number of embodiments include a memory and circuitry configured to determine a quantity of erroneous data corrected during an error correction operation performed on soft data associated with a sensed data state of a number of memory cells of the memory, determine a quality of soft information associated with the erroneous data corrected during the error correction operation performed on the soft data, and determine whether to take a corrective action on the sensed data based on the quantity of the erroneous data corrected during the error correction operation and the quality of the soft information associated with the erroneous data corrected during the error correction operation.. ... Micron Technology Inc

05/24/18 / #20180143784

Buffer operations in memory

Apparatuses and methods for performing buffer operations in memory are provided. One example method can include storing second page data and third page data on a buffer while programming first page data during a first pass programming operation and programming the second page data and the third page data from the buffer to the array of memory cells during a second pass programming operation.. ... Micron Technology Inc

05/24/18 / #20180143765

Data storage management

A method of managing a plurality of storage devices. The method comprises at a first device connected to the plurality of storage devices via a switch, receiving an indication of a plurality of logical disks, each logical disk being provided by a respective one of the plurality of storage devices. ... Micron Technology Inc

05/17/18 / #20180138406

Dual resistive-material regions for phase change memory devices

In various examples, dual resistive-material regions for a phase change material region are fabricated by initially forming a resistive material. Prior to forming the phase change material region over the resistive material, at least an upper portion of the resistive material is exposed to an implantation or plasma that increases the resistance of an upper portion of the resistive material relative to the remainder, or bulk, of the resistive material. ... Micron Technology Inc

05/17/18 / #20180138400

Conductive hard mask for memory device formation

Methods, systems, and devices for memory arrays that use a conductive hard mask during formation and, in some cases, operation are described. A hard mask may be used to define features or components during the numerous material formation and removal steps used to create memory cells within a memory array. ... Micron Technology Inc

05/17/18 / #20180138399

Phase change memory cell with constriction structure

Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. ... Micron Technology Inc

05/17/18 / #20180138398

Phase change memory cell with constriction structure

Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. ... Micron Technology Inc

05/17/18 / #20180138242

Cross-point memory and methods for fabrication of same

The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. ... Micron Technology Inc

05/17/18 / #20180138241

Three-dimensional memory apparatus and method of manufacturing the same

A three dimensional (3d) memory array and method of manufacturing the same are described. The 3d memory array may include an electrode plane and a memory material disposed through and coupled to the electrode plane. ... Micron Technology Inc

05/17/18 / #20180138240

Three-dimensional memory apparatuses and methods of use

A three dimensional (3d) memory array is disclosed. The 3d memory array may include an electrode plane and a memory material disposed through and coupled to the electrode plane. ... Micron Technology Inc

05/17/18 / #20180138239

Array of cross point memory cells and methods of forming an array of cross point memory cells

An array of cross point memory cells comprises spaced elevationally inner first lines, spaced elevationally outer second lines which cross the first lines, and a multi-resistive state region elevationally between the first and second lines where such cross. Individual of the multi-resistive state regions comprise elevationally outer multi-resistive state material and elevationally inner multi-resistive state material that are electrically coupled to one another. ... Micron Technology Inc

05/17/18 / #20180138238

Memory arrays and methods of forming memory arrays

Some embodiments include a memory array which has a first series of access/sense lines extending along a first direction, and a second series of access/sense lines over the first series of access/sense lines and extending along a second direction which crosses the first direction. Memory cells are vertically between the first and second series of access/sense lines. ... Micron Technology Inc

05/17/18 / #20180138196

Apparatuses and methods for forming multiple decks of memory cells

Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. ... Micron Technology Inc

05/17/18 / #20180138182

Conductive structures, wordlines and transistors

Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 ev, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 ev, and is shaped as an upwardly-opening container. ... Micron Technology Inc

05/17/18 / #20180138033

Removal of metal

Methods of removing metal from a portion of a substrate include exposing the substrate to a reducing environment comprising at least one reducing agent and at least one oxidizing agent, determining whether metal remaining on the portion of the substrate is less than or equal to a particular level, and exposing the substrate to an oxidizing environment comprising at least one oxidizing agent and at least one reducing agent if the metal remaining on the portion of the substrate is deemed to be greater than the particular level.. . ... Micron Technology Inc

05/17/18 / #20180137922

Apparatus and methods including establishing a negative body potential in a memory cell

Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell prior to initiating a sensing operation on the memory cell, in response to a timer, or during an access operation of another memory cell.. . ... Micron Technology Inc

05/17/18 / #20180137921

Access line management in a memory device

Memory devices including an array of memory cells, a plurality of access lines selectively coupled to respective pluralities of memory cells of the array of memory cells, a plurality of first registers, a second register, a first multiplexer, a second multiplexer, and a decoder configured to selectively connect a corresponding access line to a selected voltage source of a plurality of voltage sources in response to the output of the second multiplexer, wherein the second multiplexer is configured to pass a selected one of the output of the second register and the output of the first multiplexer to its output, and wherein the first multiplexer is configured to pass a selected one of the outputs of the plurality of first registers to its output.. . ... Micron Technology Inc

05/17/18 / #20180137917

Sequential write and sequential write verify in memory device

Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory cell, and performing a second stage of the operation after the first stage to determine whether each of the first and second memory cells reaches a target state. The first memory cell is included in a first memory cell string coupled to a data line through a first select transistor. ... Micron Technology Inc

05/17/18 / #20180137908

Writing to cross-point non-volatile memory

Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. ... Micron Technology Inc

05/17/18 / #20180137907

Parallel access techniques within memory sections through section independence

A memory device having a plurality sections of memory cells, such as ferroelectric memory cells (hybrid ram (hram) cells) may provide for concurrent access to memory cells within independent sections of the memory device. A first memory cell may be activated, and it may be determined that a second memory cell is independent of the first memory cell. ... Micron Technology Inc

05/17/18 / #20180137906

Techniques for sensing logic values stored in memory cells using sense amplifiers that are selectively isolated from digit lines

Methods, systems, and devices for operating a an electronic memory apparatus are described. A logic value stored in a ferroelectric random access memory (feram) cell is read onto a first sensing node of a sense amplifier. ... Micron Technology Inc

05/17/18 / #20180137905

Memory cells and semiconductor devices including ferroelectric materials

Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. ... Micron Technology Inc

05/17/18 / #20180137899

Two-step data-line precharge scheme

Apparatus and methods are disclosed, including an apparatus having a first transistor configured to be coupled to a first bit line, and a control circuit configured to supply a gate of the first transistor with a first voltage to turn on the first transistor, and to supply the gate of the first transistor with a second voltage higher than the first voltage to strengthen a current drive capability of the first transistor.. . ... Micron Technology Inc

05/17/18 / #20180137416

Methods and systems for data analysis in a state machine

A device includes a match element that includes a first data input configured to receive a first result, wherein the first result is of an analysis performed on at least a portion of a data stream by an element of a state machine. The match element also includes a second data input configured to receive a second result, wherein the second result is of an analysis performed on at least a portion of the data stream by another element of the state machine. ... Micron Technology Inc

05/17/18 / #20180136873

Data transfer techniques for multiple devices on a shared bus

Direct data transfer between devices having a shared bus may be implemented with reduced involvement from a controller associated with the devices. A controller, a source memory device, and a target memory device may be coupled with a shared bus. ... Micron Technology Inc

05/17/18 / #20180136871

Apparatuses and methods for memory alignment

The present disclosure includes apparatuses and methods related to memory alignment. An example method comprises performing an alignment operation on a first byte-based memory element and a second byte-based memory element such that a padding bit of the first byte-based memory element is logically adjacent to a padding bit of the second byte-based memory element and a data bit of the first byte-based memory element is logically adjacent to a data bit of the second byte-based memory element.. ... Micron Technology Inc

05/17/18 / #20180136855

Searching data in parallel using processor-in-memory devices

A method includes comparing, in parallel, a data pattern with data stored into a plurality of columns of memory cells, and in response to detecting the data pattern in the data stored into a particular column of memory cells of the plurality of columns of memory cells, storing in a memory cell of the particular column a value indicative of at least one of an occurrence of the data pattern or a position of the data pattern in the data stored into the particular column.. . ... Micron Technology Inc

05/17/18 / #20180136845

Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation

Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. ... Micron Technology Inc

05/17/18 / #20180136707

Power management

Apparatus facilitating peak power management include a plurality of dies, with each such die comprising an array of memory cells, a controller for performing access operations on the array of memory cells, and a counter configured to be responsive to a clock signal. A particular die of a first subset of dies of the plurality of dies comprises a clock generator for generating the clock signal. ... Micron Technology Inc

05/10/18 / #20180130948

Apparatuses including electrodes having a conductive barrier material and methods of forming same

Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. ... Micron Technology Inc

05/10/18 / #20180130815

Transistors having dielectric material containing non-hydrogenous ions and methods of their fabrication

Methods for fabricating a transistor include forming a dielectric material adjacent to a semiconductor, introducing non-hydrogenous ions into the dielectric material, and forming a control gate adjacent to the dielectric material. Transistors include source/drain regions in a semiconductor, a dielectric material adjacent to the semiconductor and containing non-hydrogenous ions, and a control gate adjacent to the dielectric material. ... Micron Technology Inc

05/10/18 / #20180130807

Transistors and memory arrays

Some embodiments include a transistor having a semiconductor material with a trench extending downwardly therein. The semiconductor material has a first post region on one side of the trench and a second post region on an opposing side of the trench. ... Micron Technology Inc

05/10/18 / #20180130773

Semiconductor die assemblies having molded underfill structures and related technology

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate carrying the first and second semiconductor dies. The second semiconductor die includes a first peripheral portion extending laterally outward beyond a first edge surface of the first semiconductor die. ... Micron Technology Inc

05/10/18 / #20180130739

Wiring with external terminal

Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a pad formation area including a plurality of pads disposed at an edge of the apparatus; a peripheral circuit area including a plurality of circuit blocks coupled to a memory cell array, each circuit block of the plurality of circuit blocks including a via disposed at a side opposite to the pad formation area with respect to each circuit block; and a plurality of conductors, each conductor coupling the via to the corresponding pad, and crossing over, at least in part, an area in the peripheral circuit area that is outside the circuit block comprising the via.. ... Micron Technology Inc

05/10/18 / #20180130738

Apparatuses including stair-step structures and methods of forming the same

Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. ... Micron Technology Inc

05/10/18 / #20180130700

Stair step formation using at least two masks

Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. ... Micron Technology Inc

05/10/18 / #20180130536

Methods and apparatuses including an asymmetric assist device

Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. ... Micron Technology Inc

05/10/18 / #20180130530

Systems, methods and devices for programming a multilevel resistive memory cell

Embodiments disclosed herein may relate to programming a multi-level memory cell with programming pulse sequences that comprise forward-biased and reverse-biased programming pulses.. . ... Micron Technology Inc

05/10/18 / #20180130515

Apparatuses and methods for compute components formed over an array of memory cells

The present disclosure includes apparatuses and methods related to compute components formed over an array of storage elements. An example apparatus comprises a base substrate material and an array of memory cells formed over the base substrate material. ... Micron Technology Inc

05/10/18 / #20180130513

Multi-level storage in ferroelectric memory

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. In some examples, multi-level accessing, sensing, and other operations for ferroelectric memory may be based on sensing multiple charges, including a first charge associated with a dielectric of the memory cell and a second charge associated with a polarization of the memory cell. ... Micron Technology Inc

05/10/18 / #20180130508

Apparatuses and methods for power efficient driver circuits

An apparatus comprising is disclosed. The apparatus a driver circuit configured to selectively provide a first supply voltage to an output node in a first operating mode and to selectively provide a second supply voltage to the output node in a second operating mode, based on one or more enable signals.. ... Micron Technology Inc

05/10/18 / #20180129575

Memory management

The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.. ... Micron Technology Inc

05/10/18 / #20180129450

Non-volatile memory module architecture to support memory error correction

Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. ... Micron Technology Inc

05/10/18 / #20180129442

Systems and methods for providing file information in a memory system protocol

A controller of a memory device controls placement of data blocks by receiving, from a host electronic device, one or more commands of a memory system protocol. The commands include a write command with blocks of data to be stored in the memory device and contextual file system data for the blocks of data. ... Micron Technology Inc

05/10/18 / #20180129424

Data relocation in hybrid memory

The present disclosure includes apparatuses, methods, and systems for data relocation in hybrid memory. A number of embodiments include a memory, wherein the memory includes a first type of memory and a second type of memory, and a controller configured to identify a subset of data stored in the first type of memory to relocate to the second type of memory based, at least in part, on a frequency at which an address corresponding to the subset of data stored in the first type of memory has been accessed during program operations performed on the memory.. ... Micron Technology Inc

05/10/18 / #20180129423

Memory operations on data

The present disclosure includes apparatuses and methods related to memory operations on data. An example method can include executing an operation by writing a first managed unit to a second managed unit, and placing the first managed unit in a free state, wherein the first managed unit is located at a particular distance from the second managed unit.. ... Micron Technology Inc

05/03/18 / #20180123577

Apparatuses for reducing off state leakage currents

Apparatuses for reducing leakage currents during an off state for transistors is described herein. An example apparatus includes a switch having an input node and an output node. ... Micron Technology Inc

05/03/18 / #20180123574

Apparatus and method for instant-on quadra-phase signal generator

Apparatuses are provided for a quadra-phase clock signal generator. An example apparatus includes a first delay circuit configured to receive a first input clock signal generating a first delayed clock signal. ... Micron Technology Inc

05/03/18 / #20180123573

Adjustable delay circuit for optimizing timing margin

The present invention relates to timing margin adjustment circuits using adjustable delay circuits. An example adjustable delay circuit may include a signal line, an output circuit, and a plurality of delay circuits. ... Micron Technology Inc

05/03/18 / #20180123039

Clamp elements for phase change memory arrays

Clamp elements, memories, apparatuses, and methods for forming the same are disclosed herein. An example memory may include an array of memory cells and a plurality of clamp elements. ... Micron Technology Inc

05/03/18 / #20180123037

Methods, apparatuses, and circuits for programming a memory device

Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.. . ... Micron Technology Inc

05/03/18 / #20180123036

Semiconductor structures including multi-portion liners

A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. ... Micron Technology Inc

05/03/18 / #20180123035

Memory arrays and methods of forming memory cells

Some embodiments include methods of forming memory cells. A series of rails is formed to include bottom electrode contact material. ... Micron Technology Inc

05/03/18 / #20180122917

Transistors, memory cells and semiconductor constructions

Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. ... Micron Technology Inc

05/03/18 / #20180122860

Constructions comprising stacked memory arrays

Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. ... Micron Technology Inc

05/03/18 / #20180122859

Arrays of memory cells and methods of forming an array of memory cells

An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. ... Micron Technology Inc

05/03/18 / #20180122858

Array of memory cells

A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. ... Micron Technology Inc

05/03/18 / #20180122817

Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors

A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in insulative-comprising material. An elevational mid-portion of individual of the conductive linings is removed to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings. ... Micron Technology Inc

05/03/18 / #20180122816

Cell disturb prevention using a leaker device

Various embodiments comprise apparatuses and methods of forming the apparatuses. In one embodiment, an exemplary apparatus includes a plurality of memory cells. ... Micron Technology Inc

05/03/18 / #20180122808

Methods and apparatuses including an active area of a tap intersected by a boundary of a well

Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. ... Micron Technology Inc

05/03/18 / #20180122798

Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors

A method of forming an array comprising pairs of vertically opposed capacitors comprises forming an upwardly-open conductive lining in individual capacitor openings in insulative-comprising material. An elevational mid-portion of individual of the conductive linings is removed to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings. ... Micron Technology Inc

05/03/18 / #20180122762

Semiconductor devices with underfill control features, and associated systems and methods

Semiconductor devices with underfill control features, and associated systems and methods. A representative system includes a substrate having a substrate surface and a cavity in the substrate surface, and a semiconductor device having a device surface facing toward the substrate surface. ... Micron Technology Inc

05/03/18 / #20180122482

Shielded vertically stacked data line architecture for memory

Apparatuses and methods are disclosed, including an apparatus that includes first and second strings of vertically stacked memory cells, and first and second pluralities of vertically stacked data lines. A data line of the first plurality of data lines is coupled to the first string through a first select device. ... Micron Technology Inc

05/03/18 / #20180122481

Apparatus and methods including source gates

Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.. ... Micron Technology Inc

05/03/18 / #20180122477

Semiconductor device and error correction method

A device with error correction is provided. The device includes a plurality of memory cells, and reference read write circuit, a plurality of sense amplifiers, and an error-correction code control block. ... Micron Technology Inc

05/03/18 / #20180122476

Rram, and methods of storing and retrieving information for rram

Some embodiments include methods of storing and retrieving data for an rram array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. ... Micron Technology Inc

05/03/18 / #20180122475

Rram, and methods of storing and retrieving information for rram

Some embodiments include methods of storing and retrieving data for an rram array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. ... Micron Technology Inc

05/03/18 / #20180122474

Systems having a resistive memory device

Systems having a resistive memory device having control circuitry configured to build a data word from remapped data bits from a received data word such that pairs of data bits are mapped to adjacent locations in the built data word, the control circuitry further configured to program the built data word to memory cells coupled to a selected data line such that, during a same program operation, pairs of adjacent memory cells along the selected data line are programmed with the pairs of data.. . ... Micron Technology Inc

05/03/18 / #20180122473

Methods of programming memories having a shared resistance variable material

Methods for programming data to an array of memory cells having a first memory cell, a second memory cell that is adjacent to the first memory cell in a first direction along a first axis, and a third memory cell that is adjacent to the first memory cell in a second direction along a second axis.. . ... Micron Technology Inc

05/03/18 / #20180122472

Apparatuses including memory cells and methods of operation of same

Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first polarity and read with a read pulse having a second polarity. ... Micron Technology Inc

05/03/18 / #20180122468

Apparatuses including memory cells and methods of operation of same

Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first polarity and read with a read pulse having a second polarity. ... Micron Technology Inc

05/03/18 / #20180122465

Apparatuses and methods for sensing a phase-change test cell and determining changes to the test cell resistance due to thermal exposure

A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. ... Micron Technology Inc

05/03/18 / #20180122464

Apparatuses and methods for sensing a phase-change test cell and determining changes to the test cell resistance due to thermal exposure

A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. ... Micron Technology Inc

05/03/18 / #20180122452

Half density ferroelectric memory and operation

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. ... Micron Technology Inc

05/03/18 / #20180122443

Apparatuses and methods involving accessing distributed sub-blocks of memory cells

Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. ... Micron Technology Inc

05/03/18 / #20180122439

Methods and apparatuses for command shifter reduction

Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. ... Micron Technology Inc

05/03/18 / #20180121356

Apparatuses and methods for providing data to a configurable storage area

Apparatuses and methods for providing data to a configurable storage area are described herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. ... Micron Technology Inc

05/03/18 / #20180121128

Apparatuses and methods for single level cell caching

Methods and apparatuses for single level cell caching are described, according to one example, a method includes receiving, at a memory device, a first set of data to be stored in a lower page of multilevel memory cells, storing the first set of data in a page of single level memory cells, storing the first set of data in the lower page of the multilevel memory cells, receiving, at the memory device, a second set of data to be stored in an upper page of the multilevel memory cells, and storing the second set of data directly in the upper page of the multilevel memory cells.. . ... Micron Technology Inc

05/03/18 / #20180120505

Apparatuses and methods for photonic communication and photonic addressing

Apparatuses and methods for photonic communication and photonic addressing are disclosed herein. An example apparatus includes a plurality of photonic sources, a plurality of memory die, a logic die. ... Micron Technology Inc

05/03/18 / #20180120405

Memory arrays

Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. ... Micron Technology Inc

04/19/18 / #20180108708

Resistive memory cell structures and methods

Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first resistance variable material and a second resistive memory cell comprising a second resistance variable material that is different than the first resistance variable material.. ... Micron Technology Inc

04/19/18 / #20180108670

Methods of forming an array of elevationally-extending strings of memory cells, methods of forming polysilicon, elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor, and electronic components comprising polysilicon

A method of forming poly silicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first poly silicon-comprising material. ... Micron Technology Inc

04/19/18 / #20180108645

Apparatuses and methods for forming die stacks

Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base die onto the temporary adhesive, curing the temporary adhesive, forming a die stack that includes the base die, activating a release layer disposed on the substrate, wherein the release layer is between the substrate and the temporary adhesive, removing the die stack from the substrate, and removing the temporary adhesive from the die stack.. ... Micron Technology Inc

04/19/18 / #20180108592

Stacked semiconductor die assemblies with high efficiency thermal paths and molded underfill

Semiconductor die assemblies having high efficiency thermal paths and molded underfill material. In one embodiment, a semiconductor die assembly comprises a first die and a plurality of second dies. ... Micron Technology Inc

04/19/18 / #20180108486

Devices comprising a capacitor and support material that laterally supports the capacitor

A device comprises a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is elongated and extends elevationally. ... Micron Technology Inc

04/19/18 / #20180108429

Test mode circuit for memory apparatus

Apparatuses for error detection and correction for a semiconductor device are described. An example apparatus includes: at least one memory cell array including a plurality of memory cells; and a control circuit that receives read data from the plurality of memory cells, compares the read data with reference data, and further provides an error signal. ... Micron Technology Inc

04/19/18 / #20180108420

Apparatuses and methods for transistor protection by charge sharing

Apparatuses and methods for protecting transistors through charge sharing are disclosed herein. An example apparatus includes a transistor comprising a gate node and a bulk node, a charge sharing circuit coupled between the gate and bulk nodes, and logic. ... Micron Technology Inc

04/19/18 / #20180108415

Methods and apparatus for pattern matching

Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. ... Micron Technology Inc

04/19/18 / #20180108398

Circuit and layout for single gate type precharge circuit for data lines in memory device

Some embodiments include apparatus and methods using a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region; a first channel region located between a portion of the first diffusion region and a portion of the third diffusion region; a second channel region located between the portion of the third diffusion region and a portion of the second diffusion region; a third channel region located between the portion of the second diffusion region and a portion of the fourth diffusion region; and a gate located over the first, second, and third channel regions. The first and second diffusion regions are located on a first side of the gate. ... Micron Technology Inc

04/19/18 / #20180108397

Apparatuses and methods to perform logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logic operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. ... Micron Technology Inc

04/19/18 / #20180108396

Method and apparatus for decoding commands

Method and apparatuses for of decoding commands for a semiconductor device are described. An example method includes receiving a portion of a command at first and second clock cycles: validating the portion of the command received at the first and second clock cycles at a third clock cycle when a chip select signal indicates a first state and continuing to receive the remaining portion of the command at the third clock cycle and a fourth clock cycle so that the command can be completely received by the semiconductor device by the fourth clock cycle; and invalidating the portion of the command received at the first and second clock cycles at the third clock cycle when the chip select signal indicates a second state different from the first state, so that a new command can be input to the semiconductor device at the third clock cycle.. ... Micron Technology Inc

04/19/18 / #20180108393

Offset compensation for ferroelectric memory cell sensing

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Offsets in the threshold voltage of switching components (e.g., transistors) connected to digit lines may be compensated by using various operating techniques or additional circuit components, or both. ... Micron Technology Inc

04/19/18 / #20180108385

Memory device including current generator plate

Some embodiments include an apparatus and methods using a first conductive material located in a first level of an apparatus (e.g., a memory device); a second conductive material located in a second level of the apparatus; pillars extending between the first and second levels and contacting the first and second conductive materials; memory cells located along the pillars; first select gates located in a third level of the apparatus between the first and second levels, with each of the first select gates being located along a segment of a respective pillar among the pillars; second select gates located in a fourth level of the apparatus between the first and third levels; and a conductive plate located in a fifth level of the apparatus between the first and fourth levels, with each of the pillars extending through the conductive plate.. . ... Micron Technology Inc

04/19/18 / #20180108384

Providing power availability information to memory

The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. ... Micron Technology Inc

04/19/18 / #20180107603

Memory having a static cache and a dynamic cache

The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (slc) cache and a second portion configured to operate as a dynamic slc cache when the entire first portion of the memory has data stored therein.. ... Micron Technology Inc

04/19/18 / #20180107595

Apparatuses and methods for an operating system cache in a solid state device

The present disclosure includes apparatuses and methods for an operating system cache in a solid state device (ssd). An example apparatus includes the ssd, which includes an in-ssd volatile memory, a non-volatile memory, and an interconnect that couples the non-volatile memory to the in-ssd volatile memory. ... Micron Technology Inc

04/19/18 / #20180107433

Apparatuses and methods for configuring i/os of memory for hybrid memory modules

Apparatuses, hybrid memory modules, memories, and methods for configuring i/os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. ... Micron Technology Inc

04/19/18 / #20180107202

System and method for detecting fault events

A detection method includes: aligning, by a processor, first data with second data according to steps, in which the first data and the second data are associated with equipment for fabricating semiconductor devices; determining, by the processor, a first virtual area according to the first data; determining, by the processor, a second virtual area according to the second data; and displaying, by a display, a result of comparing the first virtual area and the second virtual area, to distinguish whether a fault event exists during the process.. . ... Micron Technology Inc

04/12/18 / #20180103555

Electronic device structures and methods of making

Electronic device structures may include a sleeve member including a cavity extending from a first end of a body toward a second, opposite end, and an opening in communication with the cavity at the first end of the sleeve member. A frame configured to engage an electronic device member, such as a substrate bearing electronic components, may be sized and shaped to be positioned at least partially in the cavity. ... Micron Technology Inc

04/12/18 / #20180102653

Apparatuses and methods for removing defective energy storage cells from an energy storage array

Apparatuses and methods for removing a defective energy storage cell from an energy storage array is described. An apparatus includes an energy storage array including a plurality of energy storage cells, and a cell removal circuit coupled to the energy storage array. ... Micron Technology Inc

04/12/18 / #20180102374

Ferroelectric capacitor, ferroelectric field effect transistor, and method used in forming an electronic component comprising conductive material and ferroelectric material

A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. ... Micron Technology Inc

04/12/18 / #20180102366

Semiconductor memory device having coplanar digit line contacts and storage node contacts in memory array and method for fabricating the same

A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. ... Micron Technology Inc

04/12/18 / #20180102313

Wafer level package utilizing molded interposer

A molded interposer includes a layer of first molding compound having a first side and a second side opposite to the first side; a first redistribution layer (rdl) structure disposed on the first side; a second redistribution layer (rdl) structure disposed on the second side; a plurality of metal vias embedded in the layer of first molding compound for electrically connecting the first rdl structure with the second rdl structure; and a passive device embedded in the layer of first molding compound.. . ... Micron Technology Inc

04/12/18 / #20180102311

Semiconductor package utilizing embedded bridge through-silicon-via interconnect component

A semiconductor package includes a resin molded package substrate comprising a resin molded core, a plurality of metal vias in the resin molded core, a front-side rdl structure, and a back-side rdl structure. A bridge tsv interconnect component is embedded in the resin molded core. ... Micron Technology Inc

04/12/18 / #20180102273

Semiconductor device release during pick and place operations, and associated systems and methods

Systems and methods for releasing semiconductor devices during pick and place operations are disclosed. A representative system for handling semiconductor dies comprises a support member positioned to carry at least one semiconductor die releasably attached to a support substrate. ... Micron Technology Inc

04/12/18 / #20180102158

Reprogrammable non-volatile ferroelectric latch for use with a memory controller

Methods, systems, and apparatuses related to a reprogrammable non-volatile latch are described. A latch may include ferroelectric cells, ferroelectric capacitors, a sense component, and other circuitry and components related to ferroelectric memory technology. ... Micron Technology Inc

04/12/18 / #20180102157

Compensating for variations in selector threshold voltages

Methods, systems, and devices are described for operating a memory array. A first voltage may be applied to a memory cell to activate a selection component of the memory cell prior to applying a second voltage to the memory cell. ... Micron Technology Inc

04/12/18 / #20180102153

Semiconductor device including a clock adjustment circuit

Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.. . ... Micron Technology Inc

04/12/18 / #20180102147

Shifting data in sensing circuitry

The present disclosure is related to shifting data using sensing circuitry. An example apparatus can include a first sensing component and a second sensing component. ... Micron Technology Inc

04/12/18 / #20180102146

Read threshold voltage selection

Apparatuses and methods for read threshold voltage selection are provided. One example method can include setting a first soft read threshold voltage and a second soft read threshold voltage based on a difference between a first number of memory cells that are read as being programmed to a first state when read using a first threshold voltage and a second number of memory that are read as being programmed to the first state when read using another threshold voltage.. ... Micron Technology Inc

04/12/18 / #20180101427

Apparatuses and methods for comparing a current representative of a number of failing memory cells

Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. ... Micron Technology Inc

04/12/18 / #20180101209

Power interrupt management

The present disclosure includes methods for operating a memory system, and memory systems. One such method includes updating transaction log information in a transaction log using write look ahead information; and updating a logical address (la) table using the transaction log.. ... Micron Technology Inc

04/12/18 / #20180101204

Temperature update for a memory device

Methods, systems, and devices for operating a ferroelectric memory cell or cells and, more particularly, a temperature update for a memory device are described. A memory array may be operated according to a timing cycle that includes a first interval for performing a first type of operation and a second interval for performing a second type of operation, where a duration of the first interval is greater than a duration of the second type of interval. ... Micron Technology Inc

04/05/18 / #20180096734

Selectors on interface die for memory device

Apparatuses including an interface chip that interfaces with dice through memory channels are described. An example apparatus includes: an interface chip that interfaces with a plurality of dice through a plurality of memory channels, each of the dice comprising a plurality of memory cells, and the interface chip comprising a test circuit. ... Micron Technology Inc

04/05/18 / #20180096722

Two-part programming methods

Memory devices include control logic configured to set a first start program voltage and a first stop program voltage, to load actual first data for cells to be programmed to a level greater than or equal to a first level, and to load inhibit data for cells to be programmed to a level less than a second level. After programming the cells to be programmed to the level greater than or equal to the first level, the control logic is further configured to set a second start program voltage and a second stop program voltage, to load inhibit data for the cells programmed to the level greater than or equal to the first level, and to load actual second data for the cells to be programmed to the level less than the second level, wherein the first level is one level higher than the second level.. ... Micron Technology Inc

04/05/18 / #20180096213

Analyzing data using a hierarchical structure

Apparatus, systems, and methods for analyzing data are described. The data can be analyzed using a hierarchical structure. ... Micron Technology Inc

04/05/18 / #20180095687

Methods and related devices for operating a memory array

Methods of operating memory arrays, as well as the memory arrays, are described. In various embodiments, a method includes determining a pattern to be written to a memory array, the pattern comprising both data bits having sensitive information to be stored and data bits having a state that is unimportant to the sensitive information to be stored, and writing the pattern to the memory array. ... Micron Technology Inc

04/05/18 / #20180095486

Systems and apparatuses for a configurable temperature dependent reference voltage generator

Systems and apparatuses for a configurable, temperature dependent reference voltage generator are provided. An example apparatus includes control logic configured receive temperature data, and produce a signal, based on the temperature data, indicative of the temperature data, a temperature dependence and a temperature slope. ... Micron Technology Inc

03/29/18 / #20180090679

Methods of forming an array of cross point memory cells

A method of forming an array of cross point memory cells comprises forming spaced conductive lower electrode pillars for individual of the memory cells being formed along and elevationally over spaced lower first lines. Walls cross elevationally over the first lines and between the electrode pillars that are along the first lines. ... Micron Technology Inc

03/29/18 / #20180090651

Vertical light emitting devices with nickel silicide bonding and methods of manufacturing

Various embodiments of light emitting devices, assemblies, and methods of manufacturing are described herein. In one embodiment, a method for manufacturing a lighting emitting device includes forming a light emitting structure, and depositing a barrier material, a mirror material, and a bonding material on the light emitting structure in series. ... Micron Technology Inc

03/29/18 / #20180090557

Apparatuses and methods for semiconductor circuit layout

Apparatuses including compensation capacitors are described. An example apparatus includes: first, second and third capacitors arranged such that the second capacitor is sandwiched between the first and third capacitors, each of the first, second and third capacitors including first and second electrodes. ... Micron Technology Inc

03/29/18 / #20180090223

Reclaimable semiconductor device package and associated systems and methods

Several embodiments of reclaimable semiconductor device packages and assemblies are disclosed herein. A semiconductor device assembly (100) includes a package (101) having a housing (102) and a package contact (104) arranged to receive a signal indicative of a reclamation state. ... Micron Technology Inc

03/29/18 / #20180090208

3d vertical nand memory device including multiple select lines and control lines having different vertical spacing

Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a pillar including a length, a memory cell string and control lines located along a first segment of the pillar, and select lines located along a second segment of the pillar. ... Micron Technology Inc

03/29/18 / #20180090206

Memory systems and memory programming methods

Memory systems and memory programming methods are described. In one arrangement, a memory system includes a memory cell configured to have a plurality of different memory states, an access circuit coupled with the memory cell and configured to provide a first signal to a memory element of the memory cell to program the memory cell from a first memory state to a second memory state, and a current source coupled with the memory cell and configured to generate a second signal which is provided to the memory element of the memory cell after the first signal to complete programming of the memory cell from the first memory state to the second memory state.. ... Micron Technology Inc

03/29/18 / #20180090204

Apparatuses and methods for current limitation in threshold switching memories

Apparatuses and methods for limiting current in threshold switching memories are disclosed. An example apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. ... Micron Technology Inc

03/29/18 / #20180089469

Secure subsystem

An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the secure operations. ... Micron Technology Inc

03/29/18 / #20180089113

System and method for individual addressing

In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. ... Micron Technology Inc

03/29/18 / #20180089019

Validation of a symbol response memory

Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. ... Micron Technology Inc

03/29/18 / #20180088850

Apparatuses and methods to change data category values

The present disclosure includes apparatuses and methods to change data category values. An example is a memory device that includes an array having a plurality of sequences of memory cells, where each of the respective sequences of memory cells includes a plurality of designated subsets of memory cells, and the array includes a counter corresponding to one of the plurality of designated subsets of memory cells. ... Micron Technology Inc

03/22/18 / #20180083653

Apparatuses and methods for staircase code encoding and decoding for storage devices

An apparatus is provided. The apparatus comprises a first syndrome computation circuit configured to receive a codeword having a plurality of rows and a plurality of columns and further configured to compute a first syndrome for at least a portion of a first component codeword of the codeword. ... Micron Technology Inc

03/22/18 / #20180083011

Semiconductor devices, memory dies and related methods

A semiconductor substrate is provided. Active areas and trench isolation regions are formed. ... Micron Technology Inc

03/22/18 / #20180083010

Method of forming semiconductor device including tungsten layer

A method of forming a semiconductor device includes forming a tungsten layer over a semiconductor substrate in a first chamber, transferring the substrate over which the tungsten layer is formed from the first chamber to a second chamber without exposing into an atmosphere including oxygen, and forming a silicon nitride layer on the tungsten layer in the second chamber.. . ... Micron Technology Inc

03/22/18 / #20180082983

Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture

Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the same pin assignments as the first die bond pads. ... Micron Technology Inc

03/22/18 / #20180082940

Methods of forming a semiconductor device structure including a stair step structure, and related semiconductor devices

A method of forming a semiconductor device structure comprises forming a stack structure over a substrate, the stack structure comprising tiers each independently comprising a sacrificial structure and an insulating structure and longitudinally adjacent the sacrificial structure. A masking structure is formed over a portion of the stack structure. ... Micron Technology Inc

03/22/18 / #20180082756

Comparison operations in memory

Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. ... Micron Technology Inc

03/22/18 / #20180082730

Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, methods of writing to and reading from a memory cell, and computer systems

Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. ... Micron Technology Inc

03/22/18 / #20180082728

Compensation for threshold voltage variation of memory cell components

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Before reading a memory cell, the voltage on an access line of the memory cell may be initialized to a value associated with the threshold voltage of a switching component in electronic communication with the memory cell. ... Micron Technology Inc

03/22/18 / #20180082721

Apparatus of offset voltage adjustment in input buffer

Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes an input pad, an input buffer including a first input node and a second input node, a switch that couples the first input node and the second input node in an active state and further decouples the first input node and the second input node in an inactive state, a control circuit that provides a signal causing the switch to be in the active state or an inactive state. ... Micron Technology Inc

03/22/18 / #20180082719

Data shifting

The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. ... Micron Technology Inc

03/22/18 / #20180081774

Storing memory array operational information in nonvolatile subarrays

Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in analyzing errors in the operation of memory array. ... Micron Technology Inc

03/22/18 / #20180081753

Apparatuses and methods for generating probabilistic information with current integration sensing

Methods and apparatuses for generating probabilistic information for error correction using current integration are disclosed. An example method comprises sensing a first plurality of memory cells based on a first sense threshold, responsive to sensing the first plurality of cells, associating a first set of probabilistic information with the first plurality of memory cells, sensing a second plurality of memory cells based on a second sense threshold, responsive to sensing the second plurality of memory cells, associating a second set of probabilistic information with the second plurality of memory cells, and performing an error correction operation on the first and second pluralities of memory cells based, at least in part, on the first and second values.. ... Micron Technology Inc

03/22/18 / #20180081543

Memory devices and electronic systems having a hybrid cache with static and dynamic cells, and related methods

A memory device having a memory controller is configured to operate a hybrid cache including a dynamic cache including xlc blocks and a static cache including the slc blocks. The memory controller is configured to disable at least one of the static cache or the dynamic cache. ... Micron Technology Inc

03/15/18 / #20180076710

Apparatuses and methods for mixed charge pumps with voltage regulator circuits

Apparatuses and methods for mixed charge pumps with voltage regulator circuits is disclosed. An example apparatus comprises a first charge pump circuit configured to provide a first voltage, a second charge pump circuit configured to provide a second voltage, a plurality of coupling circuits configured to voltage couple and current couple the first voltage and the second voltage to a common node to provide a regulated voltage, and a feedback circuit configured to regulate the first voltage and the second voltage based on the regulated voltage.. ... Micron Technology Inc

03/15/18 / #20180076209

Integrated assemblies and methods of forming integrated assemblies

Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region are majority doped with a same dopant type. ... Micron Technology Inc

03/15/18 / #20180076173

Semiconductor device including two or more chips mounted over wiring substrate

A semiconductor device includes a composite chip mounted over the a wiring substrate, the composite chip including a first area, a second area that is provided independently from the first area, and a third area including a first material between the first and second areas. The first area including a first circuit formed in the first area, and the second area including a second circuit formed in the second area. ... Micron Technology Inc

03/15/18 / #20180075922

Semiconductor device including fuse circuit

Disclosed here is a semiconductor device that comprises plurality of input nodes configured to be supplied with input signals, a decoder coupled to the input nodes, the decoder configured to decode the input signals and output decoded sepals, and a plurality of fuse circuits provided correspondingly with the decoded signals and configured to be programmed responsive to the decoded signals, respectively. . ... Micron Technology Inc

03/15/18 / #20180075920

Apparatuses and methods for flexible fuse transmission

Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. ... Micron Technology Inc

03/15/18 / #20180075913

Memory devices for reading memory cells of different memory planes

Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to memory cells in different memory planes, and multiplexers to selectively couple a corresponding table to a page buffer for output of a code from an identified code-containing row of the corresponding tables for each of the different memory planes, with each code corresponding to a data state of one of the memory cells.. . ... Micron Technology Inc

03/15/18 / #20180075899

Apparatuses and methods for shift decisions

The present disclosure includes apparatuses and methods for shift decisions. An example apparatus includes a memory device. ... Micron Technology Inc

03/15/18 / #20180075165

Methods and devices for saving and/or restoring a state of a pattern-recognition processor

Systems and methods are disclosed for saving and restoring the search state of a pattern-recognition processor. Embodiments include a pattern-recognition processor having a state variable array and a state variable storage array stored in on-chip memory (on-silicon memory with the processor). ... Micron Technology Inc

03/15/18 / #20180074754

Updating a register in memory

The present disclosure includes apparatuses and methods updating a register in memory. An example includes an array of memory cells; and a controller coupled to the array of memory cells configured to perform logical operations on data stored in the array of memory cells using a register that is updated to access the data stored in the array of memory cells.. ... Micron Technology Inc

03/15/18 / #20180074740

Memory device configuration commands

Apparatuses and methods for configuring a memory device using configuration commands are provided. A method can include executing a first command while the memory device is in a ready state to configure the memory device to a particular mode and executing a second command to perform a first operation while the memory device is in the particular mode.. ... Micron Technology Inc

03/08/18 / #20180069015

Drain select gate formation methods and apparatus

Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (sgd) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the sgd transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the sgd transistor. Additional apparatus and methods are disclosed.. ... Micron Technology Inc

03/08/18 / #20180068737

Erasing memory segments in a memory block of memory cells using select gate control line voltages

A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile nand architecture memory device during an erase operation. The memory block of memory cells includes a plurality of memory segments and a corresponding plurality of first select gate control lines. ... Micron Technology Inc

03/08/18 / #20180068724

Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices

Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. ... Micron Technology Inc

03/08/18 / #20180068723

Oxide based memory

Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory cell includes forming a first electrode, forming a tunnel barrier, wherein a first portion of the tunnel barrier includes a first material and a second portion of the tunnel barrier includes a second material, forming an oxygen source, and forming a second electrode.. ... Micron Technology Inc

03/08/18 / #20180068705

Redundancy array column decoder for memory

Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other memory cells of the array. ... Micron Technology Inc

03/08/18 / #20180068696

Tracking and correction of timing signals

Various embodiments include apparatus and methods to track and/or correct timing signals. Timing signals generated from an interface can be compared to the timing signals returned to the interface. ... Micron Technology Inc

03/08/18 / #20180068694

Invert operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. ... Micron Technology Inc

03/08/18 / #20180067661

Memory wear leveling

Systems and methods for intra-sector re-ordered wear leveling include: detecting, in a memory device, a high wear sub-sector having a high wear level, the sub-sector residing in a first sector; determining a second sector of the memory device having a low wear level; swapping the first sector with the second sector; and re-ordering a position of at least one sub-sector of the first sector, the second sector, or both.. . ... Micron Technology Inc

03/08/18 / #20180067656

Computing reduction and prefix sum operations in memory

The present disclosure includes apparatuses and methods for computing reduction and prefix sum operations in memory. A number of embodiments include processing circuitry configured to compute a reduction operation on data stored in a group of memory cells by splitting the data into a plurality of elements, copying each of the plurality of elements into elements that are wider than before being copied, and performing a logical operation associated with the reduction operation on each of the copied elements.. ... Micron Technology Inc

03/01/18 / #20180063452

Anti-eclipse circuitry with tracking of floating diffusion reset level

Imagers and associated devices and systems are disclosed herein. In one embodiment, an imager includes a pixel array and control circuitry operably coupled to the pixel array. ... Micron Technology Inc

03/01/18 / #20180062640

Systems, methods, and apparatuses for temperature and process corner sensitive control of power gated domains

Apparatuses and methods for temperature and process corner sensitive control of power gated domains are described. An example apparatus includes an internal circuit; a power supply line; and a power gating control circuit which responds, at least in part, to a first change from a first state to a second state of a control signal to initiate supplying a power supply voltage from the power supply line to the internal circuit, and continue supplying the power supply voltage from the power supply line to internal circuit for at least a timeout period from a second change from the second state to the first state of the control signal, in which the timeout period represent temperature dependency.. ... Micron Technology Inc

03/01/18 / #20180062629

Apparatus and method for instant-on quadra-phase signal generator

Apparatuses are provided for a quadra-phase clock signal generator. An example apparatus includes a first delay circuit configured to receive a first input clock signal generating a first delayed clock signal. ... Micron Technology Inc

03/01/18 / #20180061886

Methods of forming magnetic memory cells, and methods of forming arrays of magnetic memory cells

Methods of forming a magnetic memory cell are disclosed. The method comprises forming a magnetic cell core material over a substrate, wherein forming the magnetic cell core comprises forming a first magnetic region over the substrate, forming a tunnel barrier material over the first magnetic region, and forming a second magnetic region over the tunnel barrier material. ... Micron Technology Inc

03/01/18 / #20180061840

Memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry

A memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. ... Micron Technology Inc

03/01/18 / #20180061837

Memory cells and memory arrays

Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. ... Micron Technology Inc

03/01/18 / #20180061836

Memory cells and memory arrays

Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. ... Micron Technology Inc

03/01/18 / #20180061835

Memory cells and memory arrays

Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. ... Micron Technology Inc

03/01/18 / #20180061834

Memory cells and memory arrays

Some embodiments include a memory cell having first and second transistors and first and second capacitors. The first capacitor is vertically displaced relative to the first transistor. ... Micron Technology Inc

03/01/18 / #20180061665

Methods of forming semiconductor device structures including two-dimensional material structures

A method of forming a semiconductor device structure comprises forming at least one 2d material over a substrate. The at least one 2d material is treated with at least one laser beam having a frequency of electromagnetic radiation corresponding to a resonant frequency of crystalline defects within the at least one 2d material to selectively energize and remove the crystalline defects from the at least one 2d material. ... Micron Technology Inc

03/01/18 / #20180061635

Methods of forming nanostructures using self-assembled nucleic acids, and nanostructures thereof

A method of forming a nanostructure comprises forming a directed self-assembly of nucleic acid structures on a patterned substrate. The patterned substrate comprises multiple regions. ... Micron Technology Inc

03/01/18 / #20180061497

Temperature compensation in memory sensing

Sense circuits and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.. . ... Micron Technology Inc

03/01/18 / #20180061483

A temperature-dependent refresh circuit configured to increase or decrease a count value of a refresh timer according to a self-refresh signal

Systems and apparatuses for memory devices utilizing a continuous self-refresh timer are provided. An example apparatus includes a self-refresh timer configured to generate a signal periodically, wherein a period of the signal is based on a self-refresh refresh time interval, wherein the self-refresh refresh time interval is dependent on temperature information. ... Micron Technology Inc

03/01/18 / #20180061481

Memory arrays

Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. ... Micron Technology Inc

03/01/18 / #20180061480

Semiconductor device

A semiconductor device includes an equalizing circuit and a control circuit. The equalizing circuit executes an operation of pre-charging the signal input/output line pair used for data inputting/outputting and an operation of equalizing it independently of each other. ... Micron Technology Inc

03/01/18 / #20180061477

Apparatuses and methods including two transistor-one capacitor memory and for accessing same

Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. ... Micron Technology Inc

03/01/18 / #20180061475

Device having multiple switching buffers for data paths controlled based on io configuration modes

A device includes a first data terminal, a second data terminal, a first switching buffer coupled between a data node and the first data terminal and a second switching buffer coupled between the data node and the second data terminal. The first switching buffer and the second switching buffer are arranged such that a distance between the first switching buffer and the second data terminal is shorter than a distance between the second switching buffer and the second data terminal and that a distance between the first switching buffer and the first data terminal is shorter than a distance between the second switching buffer and the first data terminal.. ... Micron Technology Inc

03/01/18 / #20180061471

Apparatuses and methods including ferroelectric memory and for accessing ferroelectric memory

Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. ... Micron Technology Inc

03/01/18 / #20180061470

Full bias sensing in a memory array

Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be timed to allow residual charge of a middle electrode between the cell and a selection component to discharge. ... Micron Technology Inc

03/01/18 / #20180061469

Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory

Apparatuses and methods are disclosed that in ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. ... Micron Technology Inc

03/01/18 / #20180061468

Ferroelectric memory cells

Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. ... Micron Technology Inc

03/01/18 / #20180061460

Sense amplifier constructions

A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transistor. ... Micron Technology Inc

03/01/18 / #20180060268

Systems, devices, and methods for selective communication through an electrical connector

Electrical systems and related methods are disclosed. An electrical system comprises an electronic device configured to communicate through an electrical connector using one of a plurality of different communication protocols responsive to receiving an indication of the one of the plurality of different communication protocols through the electrical connector from another electronic device. ... Micron Technology Inc

03/01/18 / #20180060234

Multiple data channel memory module architecture

According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.. . ... Micron Technology Inc

03/01/18 / #20180060069

Apparatus and methods related to microcode instructions

The present disclosure includes apparatuses and methods related to microcode instructions. One example apparatus comprises a memory storing a set of microcode instructions. ... Micron Technology Inc

03/01/18 / #20180059958

Hybrid memory device

Methods, systems, and devices for a hybrid memory device are described. The hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. ... Micron Technology Inc

03/01/18 / #20180059764

Apparatuses for reducing clock path power consumption in low power dynamic random access memory

Apparatus and methods of reducing clock path power consumption are described herein. According to one embodiment, an example apparatus includes a clock control circuit. ... Micron Technology Inc

02/22/18 / #20180053708

Semiconductor package and fabrication method thereof

A semiconductor package includes an interconnect component surrounded by a molding compound. The interconnect component comprises a first rdl structure. ... Micron Technology Inc

02/22/18 / #20180053552

Segmented memory and operation

Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of the plurality of strings is selectively connected to a common data line through a corresponding respective select gate. A first set of access lines are each coupled to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. ... Micron Technology Inc

02/22/18 / #20180053538

Apparatuses and methods for adjusting delay of command signal path

Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and provides a complementary pair of second and third clock signals having a second frequency that is half the first frequency; a first delay circuit that receives the second clock signal and provides a delayed second clock signal responsive to the second clock signal; and a second delay circuit that receives the third clock signal and provides a delayed third clock signal responsive to the third clock signal. ... Micron Technology Inc

02/15/18 / #20180048234

Analog assisted digital switch regulator

A device includes a digital switch regulator to supply an output voltage and a first current to a load based on a reference voltage. The device also includes an analog circuit to supply a second current to the load in addition to the first current based on a duty cycle of the digital switch regulator.. ... Micron Technology Inc

02/15/18 / #20180047896

Memory cell with independently-sized electrode

Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. ... Micron Technology Inc

02/15/18 / #20180047783

Memory devices and memory device forming methods

Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.. ... Micron Technology Inc

02/15/18 / #20180047747

Three dimensional memory and methods of forming the same

Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. ... Micron Technology Inc

02/15/18 / #20180047739

Methods of forming an array of elevationally-extending strings of memory cells comprising a programmable charge storage transistor and arrays of elevationally-extending strings of memory cells comprising a programmable charge storage transistor

An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. ... Micron Technology Inc

02/15/18 / #20180047460

Methods and apparatus for providing redundancy in memory

Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data. Apparatus include memory control circuitry configured to select a portion of data for mapping to a different address in response to an address indicating a defective memory cell, and further configured to select a different portion of data for a particular row than for a different row, wherein the particular row and the different row are associated with the same columns of the memory array.. ... Micron Technology Inc

02/15/18 / #20180047446

Memory sense amplifiers and memory verification methods

Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.. ... Micron Technology Inc

02/15/18 / #20180047438

Semiconductor memory device including output buffer

An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.. . ... Micron Technology Inc

02/15/18 / #20180047434

Apparatuses including multiple read modes and methods for same

Apparatuses and methods including multiple read modes for reading data from a memory are described. An example apparatus includes a memory including a first read mode and a second read mode. ... Micron Technology Inc

02/15/18 / #20180047432

Semiconductor layered device with data bus

Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (tsvs) provided in one of the first semiconductor chip and the second semiconductor chip. ... Micron Technology Inc

02/15/18 / #20180046461

Smallest or largest value element determination

Examples of the present disclosure provide apparatuses and methods for smallest value element or largest value element determination in memory. An example method comprises: storing an elements vector comprising a plurality of elements in a group of memory cells coupled to an access line of an array; performing, using sensing circuitry coupled to the array, a logical operation using a first vector and a second vector as inputs, with a result of the logical operation being stored in the array as a result vector; updating the result vector responsive to performing a plurality of subsequent logical operations using the sensing circuitry; and providing an indication of which of the plurality of elements have one of a smallest value and a largest value.. ... Micron Technology Inc

02/15/18 / #20180046405

Apparatuses and methods for data movement

The present disclosure includes apparatuses and methods for data movement. An example apparatus comprises a memory device. ... Micron Technology Inc

02/15/18 / #20180046375

Sequential memory access operations

Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.. . ... Micron Technology Inc

02/15/18 / #20180043450

Connection verification technique

Some embodiments of the present invention are generally directed to testing connections of a memory device to a circuit board or other device. In one embodiment, a memory device that is configured to facilitate continuity testing between the device and a printed circuit board or other device is disclosed. ... Micron Technology Inc

02/08/18 / #20180040626

Vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure and method of forming a vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure

A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. ... Micron Technology Inc

02/08/18 / #20180040624

Replacement control gate methods and apparatuses

Disclosed are memory structures and methods for forming such structures. An example method forms a vertical string of memory cells by forming an opening in interleaved tiers of dielectric tier material and nitride tier material, forming a charge storage material over sidewalls of the opening and recesses in the opening to form respective charge storage structures within the recesses. ... Micron Technology Inc

02/08/18 / #20180040592

Interconnect structure with improved conductive properties and associated systems and methods

Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. ... Micron Technology Inc

02/08/18 / #20180040582

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a system comprises a semiconductor component including an interposer substrate, a microelectronic die over the interposer substrate, and a connection structure composed of a volume of solder material between the interposer substrate and the microelectronic die. ... Micron Technology Inc

02/08/18 / #20180040377

Multi-deck memory device and operations

Some embodiments include apparatuses and methods using a substrate, a first memory cell block including first memory cell strings located over the substrate, first data lines coupled to the first memory cell strings, a second memory cell block including second memory cell strings located over the first memory cell block, second data lines coupled to the second memory cell strings, first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus, and second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry. No conductive path of the first and second conductive paths is shared by the first and second memory cell blocks.. ... Micron Technology Inc

02/08/18 / #20180040370

Apparatuses including multi-level memory cells and methods of operation of same

Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. ... Micron Technology Inc

02/08/18 / #20180039572

Methods and apparatuses for requesting ready status information from a memory

Methods and apparatuses are disclosed for requesting ready status information from a memory. One example apparatus includes a memory and a host coupled to the memory. ... Micron Technology Inc

02/08/18 / #20180039535

Proactive corrective actions in memory based on a probabilistic data structure

The present disclosure includes apparatuses and methods for proactive corrective actions in memory based on a probabilistic data structure. A number of embodiments include a memory, and circuitry configured to input information associated with a subset of data stored in the memory into a probabilistic data structure and proactively determine, at least partially using the probabilistic data structure, whether to take a corrective action on the subset of data stored in the memory.. ... Micron Technology Inc

02/08/18 / #20180039484

Apparatuses and methods for random number generation

The present disclosure includes apparatuses and methods for random number generation. An example method includes operating a sense amplifier of a memory device to perform sensing a first voltage on a first sense line coupled to the sense amplifier and sensing a second voltage on a complementary second sense line coupled to the sense amplifier. ... Micron Technology Inc

02/08/18 / #20180039414

Hybrid memory drives, computer system, and related method for operating a multi-mode hybrid drive

A multi-mode hybrid memory drive comprises a bulk memory device and a removable cache memory device. A controller of the bulk memory device may be configured to operate the bulk memory device in either a stand-alone mode or a hybrid mode responsive to detecting the removable cache memory device being coupled with a cache port of the bulk memory device. ... Micron Technology Inc

02/01/18 / #20180034514

Method and apparatus for inductive coupling signal transmission

Method and apparatuses for of transmitting data between semiconductor chips are described. An example apparatus includes a first semiconductor chip and a second semiconductor chip. ... Micron Technology Inc

02/01/18 / #20180034482

Apparatuses and methods for interleaved bch codes

An example methods for interleaved bch codes can include encoding a plurality of portions of data using a first generator polynomial to obtain a plurality of respective bch codewords. The method can include encoding an additional bch codeword based at least in part on a second plurality of portions of data and the plurality of bch codewords using a second generator polynomial. ... Micron Technology Inc

02/01/18 / #20180034480

Apparatuses and methods for integrated interleaved reed-solomon encoding and decoding

One example of integrated interleaved reed-solomon decoding can include computing a number of syndromes for each of a number of interleaves and correcting a number of erasures in each of the number of interleaves.. . ... Micron Technology Inc

02/01/18 / #20180033962

Textured memory cell structures

The present disclosure includes textured memory cell structures and method of forming the same. In one or more embodiments, a memory cell includes a buffer portion formed on an amorphous portion and an active portion formed on the buffer portion, wherein the active portion is textured with a single out of plane orientation.. ... Micron Technology Inc

02/01/18 / #20180033909

Solid-state transducer devices with optically-transmissive carrier substrates and related systems, methods, and devices

Semiconductor device assemblies having solid-state transducer (sst) devices and associated semiconductor devices, systems, and are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a support substrate, a transfer structure, and a plurality semiconductor structures between the support substrate and the transfer structure. ... Micron Technology Inc

02/01/18 / #20180033781

Methods of manufacturing multi-die semiconductor device packages and related assemblies

Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first semiconductor die facing the carrier wafer. One or more additional semiconductor die may be stacked on the first semiconductor die on a side of the first semiconductor die opposite the carrier wafer to form a stack of semiconductor dice. ... Micron Technology Inc

02/01/18 / #20180033780

Semiconductor devices comprising protected side surfaces and related methods

Methods of protecting semiconductor devices may involve cutting partially through a thickness of a semiconductor wafer to form trenches between stacks of semiconductor dice on regions of integrated circuitry of the semiconductor wafer. A protective material may be dispensed into the trenches and to a level at least substantially the same as a height of the stacks of semiconductor dice. ... Micron Technology Inc

02/01/18 / #20180033641

Uniform back side exposure of through-silicon vias

Systems and methods for uniform back side exposure of through-silicon vias (tsvs) are disclosed. In one embodiment, a semiconductor device comprises a substrate having a front side with circuit elements formed thereon, and a back side opposite the front side. ... Micron Technology Inc

02/01/18 / #20180033623

Methods of processing a substrate, methods of patterning a substrate, and methods of forming a hole pattern in a substrate

A method for processing a substrate is provided. The method comprises forming a patterned photoresist over a first material, the patterned photoresist comprising island portions and shaped spaces surrounding the island portions. ... Micron Technology Inc

02/01/18 / #20180033479

Apparatuses and methods for operations in a self-refresh state

The present disclosure includes apparatuses and methods for performing operations by a memory device in a self-refresh state. An example includes an array of memory cells and a controller coupled to the array of memory cells. ... Micron Technology Inc

02/01/18 / #20180033467

Variable page size architecture

Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. ... Micron Technology Inc

02/01/18 / #20180032458

Accessing status information

The present disclosure includes apparatuses and methods related to accessing status information. One example apparatus comprises a host and a memory device coupled to the host. ... Micron Technology Inc

02/01/18 / #20180032456

Methods and systems for devices with self-selecting bus decoder

Disclosed are methods and devices, among which is a device including a self-selecting bus decoder. In some embodiments, the device may be coupled to a microcontroller, and the self-selecting bus decoder may determine a response of the peripheral device to requests from the microcontroller.. ... Micron Technology Inc

02/01/18 / #20180032453

Impedance adjustment in a memory device

Methods include configuring termination devices of a driver circuit of a memory device, storing a first plurality of trim values representative of the configuration of the termination devices of the driver circuit, transferring a second plurality of trim values to a different memory device, and configuring a plurality of termination devices of a driver circuit of the different memory device in response to the second plurality of trim values. Methods further include determining configuration information corresponding to a configuration of a particular driver circuit of a memory device adjusted to a desired impedance, storing a first set of trim values representative of the configuration information, and adjusting an impedance of a different driver circuit of the memory device in response to the first set of trim values and a correction factor representative of expected differences in characteristics between the particular driver circuit and the different driver circuit.. ... Micron Technology Inc

02/01/18 / #20180031224

Solid state lights with cooling structures

A solid state lighting (ssl) with a solid state emitter (sse) having thermally conductive projections extending into an air channel, and methods of making and using such ssls. The thermally conductive projections can be fins, posts, or other structures configured to transfer heat into a fluid medium, such as air. ... Micron Technology Inc

01/25/18 / #20180026622

Apparatuses and methods for reducing off state leakage currents

Apparatuses and methods for reducing leakage currents during an off state for transistors are described herein. An example apparatus includes a switch having an input node and an output node. ... Micron Technology Inc

01/25/18 / #20180026015

Interconnect structure with redundant electrical connectors and associated systems and methods

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. ... Micron Technology Inc

01/25/18 / #20180025789

Shared error detection and correction memory

Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.. ... Micron Technology Inc

01/25/18 / #20180025770

Semiconductor device

A semiconductor device according to an aspect of the present invention has: a plurality of memory cells mc, a plurality of word lines wl each coupled to a corresponding one of the plurality of memory cells mc; and a control circuit that intermittently monitors accesses to the plurality of word lines wl, stores/erases some captured row-addresses in a first number of registers, and detects, by comparison with stored addresses, in response to a first number of accesses to one of the word lines wl in a first period of time. According to the present invention, access histories can be precisely analyzed by a small-scale circuit configuration, and measures against, for example, the row hammer problem, etc. ... Micron Technology Inc

01/25/18 / #20180025768

Utilization of data stored in an edge section of an array

An example apparatus includes a memory device having first sensing circuitry positioned adjacent an edge of an edge array section and selectably coupled to a row memory cells, the first sensing circuitry including a first sense amplifier selectably coupled via a first sense line to a first memory cell in the row and via a second sense line to the first memory cell. The example apparatus includes second sensing circuitry positioned at an opposite edge of the edge array section and selectably coupled to the row via a third sense line, the second sensing circuitry including a second sense amplifier selectably coupled via the third sense line to a second memory cell in the row. ... Micron Technology Inc

01/25/18 / #20180025760

Apparatuses and methods including nested mode registers

Apparatuses and methods for nested mode registers to extend mode register functionality are disclosed. An example apparatus comprises a mode register configured to store address information and write data, a plurality of nested mode registers coupled to the mode register and configured to store the write data, and a decoder circuit coupled to the mode register and the plurality of nested mode registers and configured to selectively enable a nested mode register of the plurality of nested mode registers to store the write data based, at least in part, on the address information.. ... Micron Technology Inc

01/25/18 / #20180025759

Shifting data in sensing circuitry

The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith. ... Micron Technology Inc

01/25/18 / #20180025758

Apparatuses and methods for storing a data value in a sensing circuitry element

The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a first data value with a sense amplifier of a sensing circuitry element, moving a second data value from a first storage location of a compute component to a second storage location of the compute component, and storing, in the first storage location, a third data value resulting from a logical operation performed on the first data value and the second data value. ... Micron Technology Inc

01/25/18 / #20180025134

Software distribution method and apparatus

The present invention provides for a method and apparatus for distributing digital information, such as software applications, to application users. By providing the digital information on unused memory space of a computer system, and providing a process for authorizing access to the information, the information can be efficiently and cost effectively transferred to users. ... Micron Technology Inc

01/25/18 / #20180024966

Autonomous memory architecture

An autonomous memory device in a distributed memory sub-system can receive a database downloaded from a host controller. The autonomous memory device can pass configuration routing information and initiate instructions to disperse portions of the database to neighboring die using an interface that handles inter-die communication. ... Micron Technology Inc

01/25/18 / #20180024926

Apparatuses and methods for transferring data

The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises a cache coupled to an array of memory cells and a controller. ... Micron Technology Inc

01/25/18 / #20180024841

Adaptive routing to avoid non-repairable memory and logic defects on automata processor

Systems and methods for utilizing a defect map to configure an automata processor in order to avoid defects when configuring the automata processor. A system includes automata processor having a state machine lattice. ... Micron Technology Inc

01/25/18 / #20180024772

Memory device including concurrent suspend states for different operations

Some embodiments include apparatuses and methods using memory cells and a control unit to suspend an erase operation performed on a first portion of the memory cells and to suspend a program operation performed on a second portion of the memory cells while the erase operation is suspended. The control unit includes register circuitry to store status information indicating that the program operation is suspended while the erase operation is suspended.. ... Micron Technology Inc

01/25/18 / #20180024769

Apparatuses and methods for write address tracking

Apparatuses and methods are provided for write address tracking. An example apparatus can include an array of memory cells and a cache coupled to the array. ... Micron Technology Inc

01/25/18 / #20180024304

Methods and systems for hermetically sealed fiber to chip connections

Disclosed are methods of providing a hermetically sealed optical connection between an optical fiber and an optical element of a chip and a photonic-integrated chip manufactured using such methods.. . ... Micron Technology Inc

01/18/18 / #20180019255

Elevationally-extending string of memory cells individually comprising a programmable charge storage transistor and method of forming an elevationally-extending string of memory cells individually comprising a programmable charge storage transistor

An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material. ... Micron Technology Inc

01/18/18 / #20180019245

Methods of forming an elevationally extending conductor laterally between a pair of conductive lines

A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. ... Micron Technology Inc

01/18/18 / #20180019157

Methods of forming one or more covered voids in a semiconductor substrate

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. ... Micron Technology Inc

01/18/18 / #20180019014

Data storage with data randomizer in multiple operating modes

Methods of operating a memory include programming a particular portion of a data state to a memory cell with a data randomizer in a first operating mode, and programming a remaining portion of the data state to the memory cell with the data randomizer in a second operating mode different than the first operating mode.. . ... Micron Technology Inc

01/18/18 / #20180017617

Fault isolation system and method for detecting faults in a circuit

The present invention provides a method and a fault isolation system for detecting errors in an integrated circuit. One feature of the present invention is using a movable second probe to scan and acquire an output signal through the vias or metal line structure of a diagnostic area along a detecting line, so as to find the fault location precisely, and another feature of the present invention is using a cutter in conjunction with the above method to narrow down the fault range. ... Micron Technology Inc

01/11/18 / #20180013451

Apparatuses and methods for layer-by-layer error correction

One example of layer-by-layer error correction can include iteratively error correcting the codeword on a layer-by-layer basis with the first error correction circuit in a first mode and determining on the layer-by-layer basis whether a number of parity errors in a particular layer is less than a threshold number of parity errors. The codeword can be transferred to a second error correction circuit when the number of parity errors is less than the threshold number of parity errors. ... Micron Technology Inc

01/11/18 / #20180013044

Solid state optoelectronic device with preformed metal support substrate

A wafer-level process for manufacturing solid state lighting (“ssl”) devices using large-diameter preformed metal substrates is disclosed. A light emitting structure is formed on a growth substrate, and a preformed metal substrate is bonded to the light emitting structure opposite the growth substrate. ... Micron Technology Inc

01/11/18 / #20180012865

Thermal transfer structures for semiconductor die assemblies

Several embodiments of the present technology are described with reference to a semiconductor die assembly and processes for manufacturing the assembly. In some embodiments of the present technology, a semiconductor die assembly includes a stack of semiconductor dies attached to a thermal transfer structure (also known as a “heat spreader,” “lid,” or “thermal lid”). ... Micron Technology Inc

01/11/18 / #20180012660

Memory device including multiple select gates and different bias conditions

Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. ... Micron Technology Inc

01/11/18 / #20180012636

Scan chain operation in sensing circuitry

Examples include apparatuses and methods related to scan chain operation in sensing circuitry. A number of embodiments include an apparatus comprising an array of memory cells coupled to sensing circuitry having a sense amplifier and a compute component, the sensing circuitry to receive a scan vector and perform a scan chain operation on the scan vector.. ... Micron Technology Inc

01/11/18 / #20180012634

Memory device including current generator plate

Some embodiments include an apparatus and methods using a first conductive material located in a first level of an apparatus (e.g., a memory device); a second conductive material located in a second level of the apparatus; pillars extending between the first and second levels and contacting the first and second conductive materials; memory cells located along the pillars; first select gates located in a third level of the apparatus between the first and second levels, with each of the first select gates being located along a segment of a respective pillar among the pillars; second select gates located in a fourth level of the apparatus between the first and third levels; and a conductive plate located in a fifth level of the apparatus between the first and fourth levels, with each of the pillars extending through the conductive plate.. . ... Micron Technology Inc

01/11/18 / #20180011252

Active alignment of optical fiber to chip using liquid crystals

Devices and systems to perform optical alignment by using one or more liquid crystal layers to actively steer a light beam from an optical fiber to an optical waveguide integrated on a chip. An on-chip feedback mechanism can steer the beam between the fiber and a grating based waveguide to minimize the insertion loss of the system.. ... Micron Technology Inc

01/04/18 / #20180006636

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a clock generator circuit configured to provide first and second clock signals responsive to an input clock signal. ... Micron Technology Inc

01/04/18 / #20180006218

Memory cell structures

The present disclosure includes memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode, a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode, and a storage element between the first electrode and the electrode contact portion of the second electrode.. ... Micron Technology Inc

01/04/18 / #20180006217

Cross-point memory and methods for fabrication of same

The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. ... Micron Technology Inc

01/04/18 / #20180006087

Method for base contact layout, such as for memory

Embodiments disclosed herein may relate to forming a base contact layout in a memory device.. . ... Micron Technology Inc

01/04/18 / #20180006084

Solid state transducer devices with separately controlled regions, and associated systems and methods

Solid state transducer devices with independently controlled regions, and associated systems and methods are disclosed. A solid state transducer device in accordance with a particular embodiment includes a transducer structure having a first semiconductor material, a second semiconductor material and an active region between the first and second semiconductor materials, the active region including a continuous portion having a first region and a second region. ... Micron Technology Inc

01/04/18 / #20180006044

Ferroelectric memory and methods of forming the same

Ferroelectric memory and methods of forming the same are provided. An example memory cell can include a buried recessed access device (brad) formed in a substrate and a ferroelectric capacitor formed on the brad.. ... Micron Technology Inc

01/04/18 / #20180005995

Layout of transmission vias for memory device

Apparatuses and methods for supplying power to a plurality of dies are described. An example apparatus includes: a substrate; first, second and third memory cell arrays arranged in line in a first direction in the substrate; a first set of through electrodes arranged between the first and second memory cell arrays, each of the first set of through electrodes penetrating through the substrate, the first set of through electrodes including first and second through electrodes; and a second set of through electrodes arranged between the second and third memory cell arrays, each of the second set of through electrodes penetrating through the substrate, the second set of through electrodes including third and fourth through electrodes.. ... Micron Technology Inc

01/04/18 / #20180005983

Package-on-package semiconductor device assemblies including one or more windows and related methods and packages

Semiconductor device packages for incorporation into semiconductor device assemblies may include a substrate including an array of electrically conductive elements located on a lower surface of the substrate. A window may extend through the substrate from the lower surface to an upper surface of the substrate. ... Micron Technology Inc

01/04/18 / #20180005909

Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices

Microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a packaged microelectronic device can include an interposer substrate with a plurality of interposer contacts. ... Micron Technology Inc

01/04/18 / #20180005710

Soft post package repair of memory devices

Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. ... Micron Technology Inc

01/04/18 / #20180005690

Oscillator controlled random sampling method and circuit

Various embodiments comprise methods and apparatuses for selecting a randomly-chosen seed row from among a stream of available data in a memory system. A refresh operation is then performed on at least one selected row of memory in the memory system based on the randomly-chosen seed row. ... Micron Technology Inc

01/04/18 / #20180005683

Ferroelectric memory cell apparatuses and methods of operating ferroelectric memory cells

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. ... Micron Technology Inc

01/04/18 / #20180005682

Writing to cross-point non-volatile memory

Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. ... Micron Technology Inc

01/04/18 / #20180005681

Cell performance recovery using cycling techniques

Methods, systems, and devices for memory array operation are described. A series of pulses may be applied to a fatigued memory cell to improve performance of memory cell. ... Micron Technology Inc

01/04/18 / #20180005680

Dynamic adjustment of memory cell digit line capacitance

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. ... Micron Technology Inc

01/04/18 / #20180005671

Apparatuses and methods for performing intra-module databus inversion operations

Apparatuses, memory modules, and methods for performing intra-module data bus inversion operations are described. An example apparatus include a memory module comprising a data bus inversion (dbi) and buffer circuit and a plurality of memories. ... Micron Technology Inc

01/04/18 / #20180005669

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. ... Micron Technology Inc

01/04/18 / #20180004596

Error correction code event detection

Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ecc) operation during sensing of the memory cells used to store the data. ... Micron Technology Inc

01/04/18 / #20180003905

Apparatus providing simplified alignment of optical fiber in photonic integrated circuits

A structure for optically aligning an optical fiber to a protonic device and method of fabrication of same. The structure optically aligns an optical fiber to the protonic device using a lens between the two which is moveable by actuator heads. ... Micron Technology Inc








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