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Nanya Technology Corp patents (2015 archive)


Recent patent applications related to Nanya Technology Corp. Nanya Technology Corp is listed as an Agent/Assignee. Note: Nanya Technology Corp may have other listings under different names/spellings. We're not affiliated with Nanya Technology Corp, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "N" | Nanya Technology Corp-related inventors


09/24/15 / #20150270830

Three dimensional integrated circuit and method for controlling the same

A three dimensional integrated circuit includes a master circuit, a slave circuit, and a through-silicon via (tsv). The master circuit is configured to receive and process an input data, a data strobe signal (dqs) and an input command to output a writing data signal to a master die. ... Nanya Technology Corp

09/17/15 / #20150262634

Power generator for data line of memory apparatus

The invention provides the power generator includes a bias voltage generator and a voltage clamping circuit. The bias voltage generator receives a reference voltage and generates a bias voltage according to the reference voltage. ... Nanya Technology Corp

08/27/15 / #20150243344

Method for clock control in dynamic random access memory devices

A circuit in dynamic random access memory devices includes a command extension circuit. The command extension circuit is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle clock command signal from a command decoding circuit. ... Nanya Technology Corp

07/23/15 / #20150206836

Method of forming an interconnect structure with high process margins

A method of forming an interconnect structure with high process margin. The present invention provides higher aligning margin for the connection of via parts and line parts. ... Nanya Technology Corp

07/23/15 / #20150206789

Method of modifying polysilicon layer through nitrogen incorporation for isolation structure

The present disclosure relates to a method of modifying a polysilicon layer, which includes the following steps. A polysilicon layer is provided. ... Nanya Technology Corp

07/23/15 / #20150206575

Counter based design for temperature controlled refresh

A dram includes: a temperature sensor for monitoring a temperature operating condition of the dram; and a binary counter coupled to the temperature sensor, for receiving external commands to perform a refresh operation, and incrementing a count upon each received external command, wherein the refresh operation will be selectively skipped according to a value of the binary counter. The binary counter is activated to a first mode when the temperature sensor determines the temperature operating condition of the dram goes below a first threshold and activated to a second mode when the temperature sensor determines the temperature operating condition of the dram goes below a second threshold lower than the first threshold.. ... Nanya Technology Corp

07/23/15 / #20150205340

Memory device and control method

A memory device and a control method are disclosed herein. The memory device includes a delay locked loop module, a memory bank module and a control module. ... Nanya Technology Corp

07/23/15 / #20150203753

Liquid etchant composition, and etching process in capacitor process of dram using the same

An etching process in a capacitor process for dram is described. A substrate is provided, which has thereon a silicon layer and metal electrodes in the silicon layer. ... Nanya Technology Corp

07/16/15 / #20150200163

Chip package

A chip of a chip package comprises a substrate having a chip circuit, a chip selection terminal connecting to the chip circuit, multiple first conductors separated at different levels by multiple insulation layers, multiple first vertical connections respectively connecting to the first conductors and extending to a substrate surface, multiple second vertical connections respectively connecting to the first conductors and extending to a surface of the insulation layers, a third vertical connection electrically connecting to the chip selection terminal and extending to the substrate surface, a fourth vertical connection formed through the insulation layers and the substrate, a second conductor formed on the surface of the insulation layers and connecting to the fourth vertical connection, multiple first pads respectively connecting to the first vertical connections and the third vertical connection, and multiple second pads respectively connecting to the second vertical connections.. . ... Nanya Technology Corp

07/09/15 / #20150194390

Method for forming crack stop structure

A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. ... Nanya Technology Corp

07/02/15 / #20150187703

Box-in-box overlay mark

A box-in-box overlay mark is described, including an inner box region and an outer box region surrounding the same, dense narrow trenches in the previous layer in the inner box region and the outer box region, x- and y-directional linear photoresist patterns defining a rectangle over the narrow trenches in the inner box region, and x- and y-directional linear patterns defining another rectangle in the outer box region. At least the narrow trenches in the inner box region are orientated in a direction different from the x-direction and the y-direction. ... Nanya Technology Corp

06/25/15 / #20150179822

Semiconductor device capable of reducing influences of adjacent word lines or adjacent transistors and fabricating method thereof

A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. ... Nanya Technology Corp

06/04/15 / #20150155367

Method for fabricating a recessed channel access transistor device

A trench extends from a main surface of a semiconductor substrate to a predetermined depth. A gate oxide layer is formed in the trench. ... Nanya Technology Corp

05/07/15 / #20150123280

Silicon buried digit line access device and method of forming the same

An access device includes a plurality of first digit lines (dl) trenches extending along a first direction, buried digit lines between each dl trench, second and third trenches separating the digit lines, a filling material filling the digit line trenches comprising airgaps in each second trench, a plurality of word line (wl) trenches extending along a second direction, metal word lines deposited on the walls of the word line trenches, a filling material filling the word line trenches.. . ... Nanya Technology Corp

05/07/15 / #20150123195

Recessed channel access transistor device and fabrication method thereof

A recessed channel access transistor device is provided. A semiconductor substrate having thereon a trench is provided. ... Nanya Technology Corp

04/30/15 / #20150117127

Random access memory and method of adjusting read timing thereof

A method of adjusting read timing of a random access memory. The method includes providing a column address strobe (cas) value for defining an cas latency (cl) of the random access memory; generating a shift margin according to the cas latency and a reference latency; generating a read command for accessing the random access memory; dynamically generating a column select (cs) signal and adjusting output timing of the cs signal according to the shift margin, after the read command is generated.. ... Nanya Technology Corp

04/30/15 / #20150115462

Integrated circuit device

An integrated circuit device includes a substrate, at least one transistor, at least one metal layer, a conductive pillar, and a connecting structure. The substrate has at least one via passing therethrough. ... Nanya Technology Corp

04/23/15 / #20150111377

Memory process

A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. ... Nanya Technology Corp

04/09/15 / #20150097296

Multi-die stack structure

A multi-die stack structure including n dies stacked vertically is described. N is an integer larger than or equal to 2. ... Nanya Technology Corp

04/09/15 / #20150097228

Method for manufacturing semiconductor device

Provided is a method for fabricating a semiconductor device, which includes the following steps. First, a substrate having at least one transistor is provided. ... Nanya Technology Corp

03/26/15 / #20150084205

Chip package and method for forming the same

A semiconductor device comprises a plurality of conductors for connecting another semiconductor device. Each conductor connects to a chip select pad within the semiconductor device through an upper vertical connection formed through an insulation layer formed on a substrate or connected to a straight vertical connection formed through the substrate and the insulation layer. ... Nanya Technology Corp

03/19/15 / #20150076698

Semiconductor device and method of fabricating the same

The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. ... Nanya Technology Corp

03/05/15 / #20150067197

Data pattern generation for i/o training and characterization

A memory structure that can perform characterization of output data paths without accessing the main memory array includes: a plurality of output data paths; a plurality of registers coupled to the output data paths. The registers include: at least a first pattern register and a second pattern register, for respectively storing a first data pattern and a second data pattern; and at least a first mapping register, for storing a plurality of binary values, wherein each binary value indicates whether the first data pattern or the second data pattern should be mapped to a corresponding output data path.. ... Nanya Technology Corp

03/05/15 / #20150064893

Method for forming trench mos structure

A method for forming a trench mos structure. First, a substrate, an epitaxial layer, a doping region and a doping well are provided. ... Nanya Technology Corp

03/05/15 / #20150064805

Method for fabricating magnetoresistive random access memory element

A magnetoresistive random access memory (mram) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer.. . ... Nanya Technology Corp

03/05/15 / #20150063051

Low power protection circuit

The present invention provides the low power protection circuit including a first voltage detector, a pulse generating circuit, a sr latch, and an output logic operation circuit. The low power protection circuit is adapted for a dynamic random access memory (dram) with dual operating voltages. ... Nanya Technology Corp

02/26/15 / #20150056810

Method for semiconductor cross pitch doubled patterning process

The present invention provides a method of cross double pitch patterning for forming a contact printing mask. First, a first, a second and a third layer a successively deposited; a photoresist is deposited on the third layer, and then trimmed into a first pre-pattern, on which an oxide layer is deposited. ... Nanya Technology Corp

02/19/15 / #20150048894

Delay line ring oscillation apparatus

The delay line degradation protection architecture as build-in ring oscillation apparatus includes a two gates logical circuit, a buffer, a clock input buffer and a delay lock loop circuit. The two gates logical circuit receives a clock enable signal, specific mode signal, and delayed clock output signal. ... Nanya Technology Corp

02/19/15 / #20150048886

Temperature detecting apparatus, switch capacitor apparatus and voltage integrating circuit thereof

The invention provides a temperature detecting apparatus, a switch capacitor apparatus and a voltage integrating circuit. The voltage integrating circuit includes an operating amplifier, a capacitor and a current source. ... Nanya Technology Corp

02/19/15 / #20150048880

Glitch filter and filtering method

A glitch filter is disclosed herein. The glitch filter includes a high glitch filter circuit, a low glitch filter and a control circuit. ... Nanya Technology Corp

02/19/15 / #20150048373

Method and layout for detecting die cracks

A method of detecting a crack in a semiconductor die is provided. The method includes the following steps. ... Nanya Technology Corp

02/12/15 / #20150046738

Data buffer system and power control method

A data buffer system includes a plurality of data buffer modules and a plurality of switching units. The data buffer module is configured for buffering a corresponding data signal. ... Nanya Technology Corp

02/12/15 / #20150044852

Method of forming rram structure

An rram includes a resistive layer including a dielectric layer and surplus oxygen ions or nitrogen ions from a treatment on the dielectric layer after the dielectric layer is formed. When the rram is applied with a voltage, the oxygen ions or nitrogen ions occupy vacancies in the dielectric layer to increase resistance of the resistive layer. ... Nanya Technology Corp

02/12/15 / #20150041182

Package substrate and chip package using the same

A package substrate is disclosed. The package substrate includes a base layer and a dam structure or a dent structure on at least one side of the base layer. ... Nanya Technology Corp

02/05/15 / #20150037961

Method for fabricating semiconductor device

Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. ... Nanya Technology Corp

01/08/15 / #20150008431

Method and layout for detecting die cracks

. . A method of detecting a crack in a semiconductor die is provided. The method includes the following steps. ... Nanya Technology Corp








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