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Nanya Technology Corp patents (2018 archive)


Recent patent applications related to Nanya Technology Corp. Nanya Technology Corp is listed as an Agent/Assignee. Note: Nanya Technology Corp may have other listings under different names/spellings. We're not affiliated with Nanya Technology Corp, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "N" | Nanya Technology Corp-related inventors


 new patent  Method of recognizing wafer

A method includes obtaining image information including a first vector by capturing an image of a first wafer, wherein the first wafer is known to be a good product; obtaining image information including a second vector by capturing an image of a second wafer, wherein the second wafer is known to be a defective product; calculating a projection vector based on a covariance matrix associated with the first vector and the second vector; obtaining image information including a third vector by capturing an image of a third wafer under a test; projecting each of the first vector, the second vector and the third vector onto the projection vector; and classifying the third wafer as either the good product or the defective product based on the projected first vector, the projected second vector and the projected third vector.. . ... Nanya Technology Corp

 new patent  Circuitry

A circuitry includes a source circuit; a first circuit; a second circuit; and a data-distributing circuit including: a receiving circuit configured to receive a first datum for the first circuit via a first and second front line, and to receive from the source circuit a second datum for the second circuit via a third front line and a fourth front line; and a forwarding circuit configured to receive one of the first datum and the second datum via a first intermediate line and a second intermediate line, to receive a target address associated with the one of the first datum and the second datum via a third intermediate line, and, according to the target address, provide the one of the first datum and the second datum to one of the first circuit and the second circuit.. . ... Nanya Technology Corp

Semiconductor package and method for preparing the same

A semiconductor package includes a first device and a bump structure disposed over the first device. In some embodiments, the first device has a first upper surface and a first side, wherein the first upper surface and the first side form a first corner of the first device. ... Nanya Technology Corp

System and method for blowing a fuse

A system includes a fuse pump; a fuse that can be blown by the fuse pump; and a voltage source configured to provide a first voltage only if the fuse pump is enabled to blow the fuse, the fuse pump blowing the fuse when the first voltage serves as a supply voltage of the fuse pump. If the first voltage serves as a supply voltage of the fuse pump, a first consumed time is required to blow the fuse. ... Nanya Technology Corp

Three dimensional integrated circuit package and method for manufacturing thereof

A three dimensional integrated circuit (3dic) package includes a redistribution layer, a plurality of semiconductor chips and a plurality of electrical bumpers. The redistribution layer has a first surface and a second surface. ... Nanya Technology Corp

Semiconductor structure and a manufacturing method thereof

A semiconductor structure includes a first package including a substrate and a die disposed over the substrate and electrically connected to the substrate by a first conductive bump; a second package disposed over the first package and electrically connected to the substrate by a second conductive bump; and an adhesive disposed between the die and the second package.. . ... Nanya Technology Corp

Semiconductor package

A semiconductor package includes a first device; a second device laterally adjacent to the first device; a molding member encapsulating the first device and the second device; and a lateral bump structure implementing a lateral signal path between the first device and the second device. A portion of the molding member is disposed between the first device and the second device.. ... Nanya Technology Corp

Method for preparing a wafer level chip-on-chip semiconductor structure

A method for preparing a wafer level chip-on-chip semiconductor structure. The semiconductor structure includes a first semiconductor device; at least one conductive member disposed over the first semiconductor device; a second semiconductor device disposed over the first semiconductor device; a molding member disposed over the first semiconductor device; and a redistribution layer (rdl) disposed over the second semiconductor device and the at least one conductive member. ... Nanya Technology Corp

Wafer level chip-on-chip semiconductor structure

A semiconductor structure includes a first semiconductor device; at least one conductive member disposed over the first semiconductor device; a second semiconductor device disposed over the first semiconductor device; a molding member disposed over the first semiconductor device; and a redistribution layer (rdl) disposed over the second semiconductor device and the at least one conductive member. The molding member surrounds the second semiconductor device and the at least one conductive member. ... Nanya Technology Corp

Semiconductor stacking structure and method for manufacturing thereof

A semiconductor stacking structure is provided. The semiconductor stacking structure includes a substrate and at least one conductor. ... Nanya Technology Corp

Stacked package structure and manufacturing method thereof

A stacked package structure includes a first package structure having a first surface and a second surface opposite to the first surface. The first package structure includes a least one first die having a first active region disposed at a bottom of the first die; a first redistribution layer disposed on the top surface of the first die; and a plurality of first bumps disposed on the bottom surface of the first active region.. ... Nanya Technology Corp

Semiconductor package and manufacturing method thereof

A semiconductor package includes a package substrate, a first semiconductor chip, a second semiconductor chip, and a top interposer. The first semiconductor chip and the second semiconductor chip are disposed on the package substrate. ... Nanya Technology Corp

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface and a recess recessed from the first surface towards the second surface; a conductive layer disposed over the first surface and within the recess; and a passivation disposed over the first surface and partially covering the conductive layer, wherein the conductive layer disposed within the recess is exposed from the passivation.. . ... Nanya Technology Corp

Method for forming semiconductor package

A method of fabricating semiconductor packages includes providing an interposer layer having a first surface and a second surface opposite to the first surface, in which the interposer layer includes through interposer vias embedded inside, and the through interposer vias extended from the first surface toward the second surface, in which through interposer vias are patterned to form repetitive polygonal-packing units, and part of the through interposer vias can be grouped within at least two distinct said polygonal-packing units; subsequently, forming at least one redistribution layer on the first surface to form terminals on a surface of the redistribution layer away from the interposer layer, in which the terminals are selectively connected to the through interposer vias respectively; and then disposing at least one semiconductor chip on the redistribution layer, wherein the semiconductor chip includes active surfaces electrically connected to the terminals respectively.. . ... Nanya Technology Corp

05/03/18 / #20180122653

Semiconductor structure

A semiconductor structure includes a substrate; a chip disposed over the substrate; and a molding disposed over the substrate and surrounding the chip at a molding temperature. The warpage of the substrate is convex or about zero at the molding temperature or 10° c. ... Nanya Technology Corp

04/05/18 / #20180096974

Semiconductor package and manufacturing method thereof

A semiconductor package includes a semiconductor chip, an interposer, a first redistribution layer, and a molding compound. The semiconductor chip has a first surface and a second surface opposite to the first surface and at least one sidewall connected to the first surface and the second surface. ... Nanya Technology Corp

04/05/18 / #20180096907

Semiconductor package and method for forming the same

A method for forming semiconductor packages includes disposing at least one flow hindering supporter onto a substrate, in which the substrate has at least one active region and at least one gap region surrounded the active region, the flow hindering supporter is located on the gap region; subsequently, disposing at least one die structure onto the active region of the substrate respectively; and then injecting a molding compound flowed into the gap region, to mold the flow hindering supporter and the die structure with the molding compound.. . ... Nanya Technology Corp

03/22/18 / #20180082967

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface and a recess recessed from the first surface towards the second surface; a conductive layer disposed over the first surface and within the recess; and a passivation disposed over the first surface and partially covering the conductive layer, wherein the conductive layer disposed within the recess is exposed from the passivation.. . ... Nanya Technology Corp

03/22/18 / #20180082963

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate; a pad disposed over the substrate; a first passivation disposed over the substrate, partially covering the pad, and including a protrusion protruded from the first passivation and away from the substrate; a conductive layer disposed over the first passivation and a portion of the pad exposed from the first passivation; and a second passivation disposed over the conductive layer, wherein the conductive layer disposed over the protrusion is exposed from the second passivation.. . ... Nanya Technology Corp

03/22/18 / #20180082934

Semiconductor package and method for fabricating the same

A method of fabricating semiconductor packages includes providing an interposer layer having a first surface and a second surface opposite to the first surface, in which the interposer layer includes through interposer vias embedded inside, and the through interposer vias extended from the first surface toward the second surface, in which through interposer vias are patterned to form repetitive polygonal-packing units, and part of the through interposer vias can be grouped within at least two distinct said polygonal-packing units; subsequently, forming at least one redistribution layer on the first surface to form terminals on a surface of the redistribution layer away from the interposer layer, in which the terminals are selectively connected to the through interposer vias respectively; and then disposing at least one semiconductor chip on the redistribution layer, wherein the semiconductor chip includes active surfaces electrically connected to the terminals respectively.. . ... Nanya Technology Corp

02/08/18 / #20180040575

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface; a pad disposed over the first surface; a first passivation disposed over the first surface and partially covering the pad; a redistribution layer (rdl) disposed over the first passivation, and including a conductive line extending over the first passivation and a second passivation partially covering the conductive line. The conductive line includes a via portion coupled with the pad and extended within the first passivation towards the pad, and a land portion extended over the first passivation, wherein the land portion includes a plurality of first protrusions protruded away from the first passivation.. ... Nanya Technology Corp

01/18/18 / #20180019174

Semiconductor device and method for manufacturing the same

One aspect of the present disclosure provides a semiconductor device. In some embodiments, the semiconductor device includes an integrated circuit die, at least one conductive terminal disposed on the integrated circuit die, a frame positioned on the integrated circuit die, wherein the frame substantially exposes the at least one conductive terminal, and at least one conductive bump positioned in the frame, wherein the at least one conductive bump electrically connects the at least one conductive terminal.. ... Nanya Technology Corp

01/18/18 / #20180015569

Chip and method of manufacturing chips

A method of manufacturing chips from a semiconductor wafer having a plurality of streets on a front surface of the semiconductor wafer is provided. The method includes: forming a plurality of crack stopping structures on the semiconductor wafer at locations respectively aligned with intersections of the streets; irradiating a laser beam focused inside the semiconductor wafer along the streets to induce cracks; and breaking the irradiated semiconductor wafer along the cracks to the crack stopping structures, so as to separate the irradiated semiconductor wafer into the chips.. ... Nanya Technology Corp








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