Real Time Touch



new TOP 200 Companies filing patents this week

new Companies with the Most Patent Filings (2010+)




Real Time Touch

Netspeed Systems patents


Recent patent applications related to Netspeed Systems. Netspeed Systems is listed as an Agent/Assignee. Note: Netspeed Systems may have other listings under different names/spellings. We're not affiliated with Netspeed Systems, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "N" | Netspeed Systems-related inventors


Cost management against requirements for the generation of a noc

Example implementations as described herein are directed to systems and methods for processing a noc specification for a plurality of performance requirements of a noc, and generating a plurality of nocs, each of the plurality of nocs meeting a first subset of the plurality of performance requirements. For each of the plurality of nocs, the example implementations involve presenting a difference between an actual performance of the each of the plurality of nocs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of nocs.. ... Netspeed Systems

Cost management against requirements for the generation of a noc

Example implementations as described herein are directed to systems and methods for processing a noc specification for a plurality of performance requirements of a noc, and generating a plurality of nocs, each of the plurality of nocs meeting a first subset of the plurality of performance requirements. For each of the plurality of nocs, the example implementations involve presenting a difference between an actual performance of the each of the plurality of nocs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of nocs.. ... Netspeed Systems

Cost management against requirements for the generation of a noc

Example implementations as described herein are directed to systems and methods for processing a noc specification for a plurality of performance requirements of a noc, and generating a plurality of nocs, each of the plurality of nocs meeting a first subset of the plurality of performance requirements. For each of the plurality of nocs, the example implementations involve presenting a difference between an actual performance of the each of the plurality of nocs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of nocs.. ... Netspeed Systems

Buffer sizing of a noc through machine learning

The present disclosure is directed to buffer sizing of noc link buffers by utilizing incremental dynamic optimization and machine learning. A method for configuring buffer depths associated with one or more network on chip (noc) is disclosed. ... Netspeed Systems

Extracting features from a noc for machine learning construction

The present disclosure is directed to extracting features from a noc for machine learning construction. Example implementations include a method for generating a network on chip (noc), wherein the method can extract at least one feature from a noc specification to derive at least one of: grid features, traffic features and topological features associated with the noc. ... Netspeed Systems

Infrastructure to apply machine learning for noc construction

The present disclosure is directed to machine learning (ml) based network-on-chip (noc) construction. Example implementations of the present disclosure utilize a ml process for making decisions to evaluate whether a noc design finally obtained is optimized for a desired implementation during construction of a noc. ... Netspeed Systems

Strategies for noc construction using machine learning

Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating/constructing noc based on one or more strategies that are selected by a machine-learning engine (mle) from a plurality of available strategies based on an input noc specification. In an aspect, the method can include the steps of processing a network on chip (noc) specification through a process to generate a vector for a plurality of noc generation strategies, wherein the vector is indicative of which strategies from the plurality of noc generation strategies are to be used to generate the noc to meet a quality metric; and generating the noc by using the strategies from the plurality of noc generation strategies indicated by the vector as the strategies to be used to generate the noc, wherein the process is generated through a machine learning process that is trained for the plurality of noc generation strategies.. ... Netspeed Systems

Metrics to train machine learning predictor for noc construction

The present disclosure is directed to machine learning (ml) based network-on-chip (noc) construction. Methods, systems, and computer readable mediums of the present disclosure utilize a ml process for making decisions to evaluate whether a noc design finally obtained is actually the most optimal and efficient one or not during construction of a noc. ... Netspeed Systems

Interface virtualization and fast path for network on chip

Example implementations described herein are directed to a configurable network on chip (noc) element that can be configured with a bypass that permits messages to pass through the noc without entering the queue or arbitration. The configurable noc element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.. ... Netspeed Systems

Traffic mapping of a network on chip through machine learning

In example implementations of the present disclosure, there is a processing of a specification and/or other parameters to generate a noc with traffic flows that meet the specification requirements. In example implementations, the specification is processed to determine the characteristics of the noc to be generated, the characteristics of the traffic flow (e.g. ... Netspeed Systems

Traffic mapping of a network on chip through machine learning

In example implementations of the present disclosure, there is a processing of a specification and/or other parameters to generate a noc with traffic flows that meet the specification requirements. In example implementations, the specification is processed to determine the characteristics of the noc to be generated, the characteristics of the traffic flow (e.g. ... Netspeed Systems

Traffic mapping of a network on chip through machine learning

In example implementations of the present disclosure, there is a processing of a specification and/or other parameters to generate a noc with traffic flows that meet the specification requirements. In example implementations, the specification is processed to determine the characteristics of the noc to be generated, the characteristics of the traffic flow (e.g. ... Netspeed Systems

Interface virtualization and fast path for network on chip

Example implementations described herein are directed to a configurable network on chip (noc) element that can be configured with a bypass that permits messages to pass through the noc without entering the queue or arbitration. The configurable noc element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.. ... Netspeed Systems

Interface virtualization and fast path for network on chip

Example implementations described herein are directed to a configurable network on chip (noc) element that can be configured with a bypass that permits messages to pass through the noc without entering the queue or arbitration. The configurable noc element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.. ... Netspeed Systems

06/28/18 / #20180183715

System and method for network on chip construction through machine learning

In example implementations of the present disclosure, processing of a specification and/or other parameters generates a noc with flows that meet specification requirements. In example implementations, the specification is processed to determine the characteristics of the noc to be generated, the characteristics of flow (e.g. ... Netspeed Systems

06/28/18 / #20180183672

System and method for grouping of network on chip (noc) elements

Aspects of the present disclosure are directed to systems, methods and computer readable medium for reducing the number of unique routers/network elements/module instances on a network on chip to get a simplified noc rtl without effecting the behavior and performance of noc. According to an example implementation of the present disclosure, plurality of noc elements of a given noc can be grouped together to form one or more groups, and one or more superset noc elements/module instances encompassing capabilities/functionalities of plurality of individual noc elements of said one or more groups can be determined/created for each of the said one or more groups. ... Netspeed Systems

06/28/18 / #20180181192

Systems and methods for facilitating low power on a network-on-chip

Aspects of the present disclosure are directed to a power specification and network on chip (noc) having a power supervisor (ps) unit. The specification is utilized to generate a noc with power domains and clock domains. ... Netspeed Systems

06/28/18 / #20180181191

Systems and methods for facilitating low power on a network-on-chip

Aspects of the present disclosure are directed to a power specification and network on chip (noc) having a power supervisor (ps) unit. The specification is utilized to generate a noc with power domains and clock domains. ... Netspeed Systems

06/28/18 / #20180181190

Systems and methods for facilitating low power on a network-on-chip

Aspects of the present disclosure are directed to a power specification and network on chip (noc) having a power supervisor (ps) unit. The specification is utilized to generate a noc with power domains and clock domains. ... Netspeed Systems

06/28/18 / #20180181174

Automatic generation of power management sequence in a soc or noc

Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for soc and noc architectures from a given input specification having one or a combination of noc design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.. . ... Netspeed Systems

06/28/18 / #20180181173

Automatic generation of power management sequence in a soc or noc

Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for soc and noc architectures from a given input specification having one or a combination of noc design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.. . ... Netspeed Systems

06/07/18 / #20180159786

Interface virtualization and fast path for network on chip

Example implementations described herein are directed to a configurable network on chip (noc) element that can be configured with a bypass that permits messages to pass through the noc without entering the queue or arbitration. The configurable noc element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.. ... Netspeed Systems

03/15/18 / #20180074572

Systems and methods for facilitating low power on a network-on-chip

Aspects of the present disclosure are directed to a power specification and network on chip (noc) having a power supervisor (ps) unit. The specification is utilized to generate a noc with power domains and clock domains. ... Netspeed Systems

01/18/18 / #20180019949

Qos in a system with end-to-end flow control and qos aware buffer allocation

The present disclosure is directed to quality of service (qos) and handshake protocols to facilitate endpoint bandwidth allocation among one or more agents in a network on chip (noc) for an endpoint agent. The qos policy and handshake protocols may involve the use of credits for buffer allocation which are sent to agents in the noc to compel the acceptance of data and the allocation of an appropriate buffer. ... Netspeed Systems

09/14/17 / #20170264533

Streaming bridge design with host interfaces and network on chip (noc) layers

Systems and methods described herein are directed to streaming bridge design implementations that help interconnect and transfer transaction packets between multiple source and destination host interfaces through a network on chip (noc) interconnect, which includes a plurality of noc router layers and virtual channels (vcs) connecting the router layers. Implementations are configured to support a variety of different traffic profiles, each having a different set of traffic flows. ... Netspeed Systems

08/10/17 / #20170230253

Generating physically aware network-on-chip design from a physical system-on-chip specification

Different example implementations of the present disclosure relates to methods and computer readable mediums for automatically generating physically aware noc design and physically aware noc specification based on one or more of given soc architectural details, physical information of soc, traffic specification, power profile and one or more constraints. The method includes steps of receiving input information, determining the location/position of different noc agents, interconnecting channels, pins, i/o interfaces, physical/virtual boundaries, number of layers, size/depth/width of different channels at different time, and locating/configuring the different noc agents, interconnecting channels, pins, i/o interfaces, and physical/virtual boundaries.. ... Netspeed Systems

08/10/17 / #20170228481

Verification low power collateral generation

Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating transition state specifications that include information regarding low power behavior of a system on chip (soc) and/or a network on chip (noc). Such transition state specifications can enable verification of switching behavior when elements/components of a soc/noc or a subset thereof switch from one power profile to another, or when the elements/components switch in stable states of power based on inputs such as voltages, clocks, power domains, and traffic.. ... Netspeed Systems

06/15/17 / #20170171115

Automatic buffer sizing for optimal network-on-chip design

The present disclosure relates to automatic sizing of noc channel buffers of one or more virtual channels to optimize noc design, soc design, and to meet defined performance objectives. The present disclosure further relates to a noc element such as a router or a bridge having input ports associated with input virtual channels, and output ports associated with output virtual channels, wherein, aspects of the present disclosure enable sizing of any or a combination of the width of the input virtual channel(s), width of the output virtual channel(s), buffer(s) associated with input virtual channels, and buffer(s) associated with output virtual channels. ... Netspeed Systems

06/08/17 / #20170163574

Automatic buffer sizing for optimal network-on-chip design

The present disclosure relates to automatic sizing of noc channel buffers of one or more virtual channels to optimize noc design, soc design, and to meet defined performance objectives. The present disclosure further relates to a noc element such as a router or a bridge having input ports associated with input virtual channels, and output ports associated with output virtual channels, wherein, aspects of the present disclosure enable sizing of any or a combination of the width of the input virtual channel(s), width of the output virtual channel(s), buffer(s) associated with input virtual channels, and buffer(s) associated with output virtual channels. ... Netspeed Systems

04/20/17 / #20170111283

Congestion control and qos in noc by regulating the injection traffic

Systems and methods described herein are directed to solutions for noc interconnects that provide congestion avoidance and end-to-end uniform and weighted-fair allocation of resource bandwidths among various contenders in a mesh or torus interconnect. The example implementations are fully distributed and involve using explicit congestion notification messages or local congestion identification for congestion detection. ... Netspeed Systems

04/13/17 / #20170103332

Clock gating for system-on-chip elements

An aspect of the present disclosure provides a hardware element in a network on chip (noc), wherein the hardware element includes a clock gating circuit configures one or more neighboring hardware elements to activate before receiving new incoming data and to sleep after a defined number of cycles, wherein the defined number of cycles can be counted from a cycle having non-receipt of incoming data and/or having a clearance of all data within an input queue of a source hardware element.. . ... Netspeed Systems

04/06/17 / #20170097672

Hardware and software enabled implementation of power profile management instructions in system on chip

Aspects of the present disclosure relate to a method and system for hybrid and/or distributed implementation of generation and/or execution of power profile management instructions. An embodiment of the present disclosure provides a hardware element of a soc/noc that can be configured to generate and/or execute power profile management instructions using a hybrid combination of software and hardware, wherein the hardware element can be run in parallel with other hardware elements of the soc/noc to generate and execute power profile management instructions for different segments or regions of the soc/noc for efficient and safe working thereof.. ... Netspeed Systems

03/02/17 / #20170063734

Automatic buffer sizing for optimal network-on-chip design

The present disclosure relates to automatic sizing of noc channel buffers of one or more virtual channels to optimize noc design, soc design, and to meet defined performance objectives. The present disclosure further relates to a noc element such as a router or a bridge having input ports associated with input virtual channels, and output ports associated with output virtual channels, wherein, aspects of the present disclosure enable sizing of any or a combination of the width of the input virtual channel(s), width of the output virtual channel(s), buffer(s) associated with input virtual channels, and buffer(s) associated with output virtual channels. ... Netspeed Systems

03/02/17 / #20170063697

Qos in a system with end-to-end flow control and qos aware buffer allocation

The present disclosure is directed to quality of service (qos) and handshake protocols to facilitate endpoint bandwidth allocation among one or more agents in a network on chip (noc) for an endpoint agent. The qos policy and handshake protocols may involve the use of credits for buffer allocation which are sent to agents in the noc to compel the acceptance of data and the allocation of an appropriate buffer. ... Netspeed Systems

03/02/17 / #20170063693

Heterogeneous channel capacities in an interconnect

Systems and methods involving construction of a system interconnect in which different channels have different widths in numbers of bits. Example processes to construct such a heterogeneous channel noc interconnect are disclosed herein, wherein the channel width may be determined based upon the provided specification of bandwidth and latency between various components of the system.. ... Netspeed Systems

03/02/17 / #20170063639

Generation of network-on-chip layout based on user specified topological constraints

In an aspect, the present disclosure provides a method that comprises automatic generation of a noc from specified topological information based on projecting noc elements of the noc onto a grid layout. In an aspect, the specified topological information, including specification of putting constraints on positions/locations of noc elements and links thereof, can be input by a user in real space, and can then be projected on the grid layout.. ... Netspeed Systems

03/02/17 / #20170063634

Heterogeneous soc ip core placement in an interconnect to optimize latency and interconnect performance

Systems and methods described herein are directed to solutions for network on chip (noc) interconnects that automatically and dynamically determines the position of hosts of various size and shape in a noc topology based on the connectivity, bandwidth and latency requirements of the system traffic flows and certain performance optimization metrics such as system interconnect latency and interconnect cost. The example embodiments selects hosts for relocation consideration and determines a new possible position for them in the noc based on the system traffic specification, shape and size of the hosts and by using probabilistic function to decide if the relocation is carried out or not. ... Netspeed Systems

03/02/17 / #20170063626

System and method for grouping of network on chip (noc) elements

Aspects of the present disclosure are directed to systems, methods and computer readable medium for reducing the number of unique routers/network elements/module instances on a network on chip to get a simplified noc rtl without effecting the behavior and performance of noc. According to an example implementation of the present disclosure, plurality of noc elements of a given noc can be grouped together to form one or more groups, and one or more superset noc elements/module instances encompassing capabilities/functionalities of plurality of individual noc elements of said one or more groups can be determined/created for each of the said one or more groups. ... Netspeed Systems

03/02/17 / #20170063625

Configurable router for a network on chip (noc)

Example implementations described herein are directed to a configurable building block, such as a router, for implementation of a network on chip (noc). The router is parameterized by a software layer, which can include the number of virtual channels for a port, the number of ports, the membership information of the virtual channels, clock domain, and so forth. ... Netspeed Systems

03/02/17 / #20170063618

Clock gating for system-on-chip elements

An aspect of the present disclosure provides a hardware element in a network on chip (noc), wherein the hardware element includes a clock gating circuit configures one or more neighboring hardware elements to activate before receiving new incoming data and to sleep after a defined number of cycles, wherein the defined number of cycles can be counted from a cycle having non-receipt of incoming data and/or having a clearance of all data within an input queue of a source hardware element.. . ... Netspeed Systems

03/02/17 / #20170063610

Hierarchical asymmetric mesh with virtual routers

A network-on-chip configuration includes a first plurality of cores arranged in a two-dimensional mesh; a first plurality of routers, each of the first plurality of routers associated with a corresponding local one of the first plurality of cores, each of the first plurality of routers having a plurality of directional ports configured to provide connections to other ones of the first plurality of routers; a second plurality of cores disposed around a periphery of the two-dimensional mesh arrangement; and a second plurality of routers, each of the second plurality of routers associated with a corresponding local one of the second plurality of cores, and having a directional port configured to provide a connection to a neighboring one of the first plurality of routers.. . ... Netspeed Systems

03/02/17 / #20170063609

Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip

Aspects of the present disclosure relates to methods, computer readable mediums, and noc architectures/systems/constructions that can automatically mark and configure some channel of a noc as store-and-forward channels, and other channels of the noc as cut-through channels, and can further resize the buffers/channels based on the given noc specification and associated traffic profile. An aspect of the present disclosure relates to a method for configuring a first set of plurality of channels of a noc as store-and-forward channels, and configuring a second set of plurality of channels of the noc as cut-through channels based on the determination of idle cycles in a given noc specification and associated traffic profile.. ... Netspeed Systems

03/02/17 / #20170063564

Supporting multicast in noc interconnect

Example implementations are directed to more efficiently delivering a multicast message to multiple destination components from a source component. Multicast environment is achieved with transmission of a single message from a source component, which gets replicated in the noc during routing towards the destination components indicated in the message. ... Netspeed Systems

03/02/17 / #20170061058

Automatic pipelining of noc channels to meet timing and/or performance

Systems and methods for automatically generating a network on chip (noc) interconnect architecture with pipeline stages are described. The present disclosure includes example implementations directed to automatically determining the number and placement of pipeline stages for each channel in the noc. ... Netspeed Systems

03/02/17 / #20170061053

System level simulation in network on chip architecture

Systems and methods for performing multi-message transaction based performance simulations of soc ip cores within a network on chip (noc) interconnect architecture by accurately imitating full soc behavior are described. The example implementations involve simulations to evaluate and detect noc behavior based on execution of multiple transactions at different rates/times/intervals, wherein each transaction can contain one or more messages, with each message being associated with a source agent and a destination agent. ... Netspeed Systems

03/02/17 / #20170061041

Automatic performance characterization of a network-on-chip (noc) interconnect

Aspects of the present disclosure are directed to methods, systems, and non-transitory computer readable medium for automatically characterizing performance of a system-on-chip (soc) and/or network-on-chip (noc) with respect to latency and throughput attributes of one or more traffic flows/profiles under varying traffic load conditions. The characterization of performance may involve a plot representative of latency and throughput, depending on the desired implementation.. ... Netspeed Systems

03/02/17 / #20170060809

Automatic generation of physically aware aggregation/distribution networks

Aspects of the present disclosure provide systems and methods for automatic generation of physically aware aggregation/distribution networks that enable optimized arrangement of a plurality of hardware elements, and provide positions and connectivity for one or more intermediate hardware elements. One or more intermediate hardware elements can be configured to aggregate signals/commands/messages/data from their corresponding hardware elements or from other intermediate hardware elements, and send the aggregated signals/commands/messages/data to a root hardware element that acts as a communication interface for the network. ... Netspeed Systems

03/02/17 / #20170060805

Transaction expansion for noc simulation and noc design

Methods and example implementations described herein are generally directed to interconnect architecture, and more specifically, to generation of one or more expanded transactions for conducting simulations and/or noc design. Aspects of the present disclosure include processing of input traffic specification that is given in terms of groups of hosts, requests, and responses to the requests, in order to generate one or more appropriate/correct expanded transactions that can be simulated.. ... Netspeed Systems

03/02/17 / #20170060212

Hardware and software enabled implementation of power profile management instructions in system on chip

Aspects of the present disclosure relate to a method and system for hybrid and/or distributed implementation of generation and/or execution of power profile management instructions. An embodiment of the present disclosure provides a hardware element of a soc/noc that can be configured to generate and/or execute power profile management instructions using a hybrid combination of software and hardware, wherein the hardware element can be run in parallel with other hardware elements of the soc/noc to generate and execute power profile management instructions for different segments or regions of the soc/noc for efficient and safe working thereof.. ... Netspeed Systems

03/02/17 / #20170060204

Automatic generation of power management sequence in a soc or noc

Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for soc and noc architectures from a given input specification having one or a combination of noc design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.. . ... Netspeed Systems








ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009



###

This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Netspeed Systems in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Netspeed Systems with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

###