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Optimum Semiconductor Technologies Inc patents

Recent patent applications related to Optimum Semiconductor Technologies Inc. Optimum Semiconductor Technologies Inc is listed as an Agent/Assignee. Note: Optimum Semiconductor Technologies Inc may have other listings under different names/spellings. We're not affiliated with Optimum Semiconductor Technologies Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "O" | Optimum Semiconductor Technologies Inc-related inventors

Variable translation-lookaside buffer (tlb) indexing

A processor includes a translation lookaside buffer (tlb) comprising a plurality of ways, wherein each way is associated with a respective page size, and a processing core, communicatively coupled to the tlb, to execute an instruction associated with a virtual memory page, identify a first way of the plurality of ways, wherein the first way is associated with a first page size, determine an index value using the virtual memory page and the first page size for the first way, determine, using the index value, a first tlb entry of the first way, and translate, using a memory address translation stored in the first tlb entry, the first virtual memory page to a first physical memory page.. . ... Optimum Semiconductor Technologies Inc

Implementation of register renaming, call-return prediction and prefetch

A processor includes a plurality of physical registers and a processor core, communicatively coupled to the plurality of physical registers, the processor core to execute a process comprising a plurality of instructions to responsive to issuance of a call instruction for out-of-order execution, identify, based on a head pointer of the plurality of physical registers, a first physical register of the plurality of physical registers, store a return address in the first physical register, wherein the first physical register is associated with a first identifier, store, based on an out-of-order pointer of a call stack associated with the process, the first identifier in a first entry of the call stack, and increment, modulated by a length of the call stack, the out-of-order pointer of the call stack to point to a second entry of the call stack.. . ... Optimum Semiconductor Technologies Inc

Implementing atomic primitives using cache line locking

A processor comprising a cache, the cache comprising a cache line, an execution unit to execute an atomic primitive to responsive to executing a read instruction to retrieve a data item from a memory location, cause to store a copy of the data item in the cache line, execute a lock instruction to lock the cache line to the processor, execute at least one instruction while the cache line is locked to the processor, and execute an unlock instruction to cause the cache controller to release the cache line from the processor.. . ... Optimum Semiconductor Technologies Inc

Floating point instruction format with embedded rounding rule

A processor including a first storage to store a first data item, a second storage, and an execution unit comprising a logic circuit encoding an instruction, the instruction comprising a first field to store an identifier of the first storage, a second field to store an identifier of the second storage, and a third field to store an identifier representing a rounding rule, wherein the execution unit is to execute the instruction to generate a second data item based on the first data item, round the second data item according to the rounding rule specified by the instruction, and store the rounded second data item in the second storage.. . ... Optimum Semiconductor Technologies Inc

Video image alignment for video stabilization

A system and method relate to calculating a first edge map associated with a reference video frame, generating a second edge map associated with an incoming video frame, generating an offset between the reference video frame and the video frame based on a first frequency domain representation of the first edge map and a second frequency domain representation of the second edge map, translating locations of a plurality of pixels of the incoming video frame according to the calculated offset to align the incoming video frame with respect to the reference video frame, and transmitting the aligned video frame to a downstream device.. . ... Optimum Semiconductor Technologies Inc

Monolithic dual band antenna

A monolithic dual band antenna is provided. The monolithic dual band antenna includes a first layer comprising a high frequency band antenna. ... Optimum Semiconductor Technologies Inc

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009


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