Real Time Touch



new TOP 200 Companies filing patents this week

new Companies with the Most Patent Filings (2010+)




Real Time Touch

Powertech Technology Inc patents


Recent patent applications related to Powertech Technology Inc. Powertech Technology Inc is listed as an Agent/Assignee. Note: Powertech Technology Inc may have other listings under different names/spellings. We're not affiliated with Powertech Technology Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "P" | Powertech Technology Inc-related inventors


Manufacturing method of package structure

A manufacturing method of a packaging structure is provided. First, a carrier is provided. ... Powertech Technology Inc

Package structure and manufacturing method thereof

A manufacturing method of a package structure includes at least the following steps. A plurality of conductive connectors are formed on a circuit layer. ... Powertech Technology Inc

Semiconductor device package with stress relief layer

A semiconductor device package includes an encapsulation layer, a die, a stress relief layer, and a redistribution layer. The encapsulation layer has an opening, and the die is disposed in the opening of the encapsulation layer. ... Powertech Technology Inc

Method of fabricating packaging layer of fan-out chip package

A method of fabricating a packaging layer of an fan-out chip package comprising: disposing a chip on a temporary carrier; forming an encapsulation on the temporary carrier to encapsulate the chip; grinding the encapsulation and the chip to form a back surface of the chip and a back surface of the encapsulation; debonding the encapsulation and the chip from the temporary carrier; forming a first passivation layer on the active surface of the chip and the peripheral surface of the encapsulation; patterning the first passivation layer to form fan-in openings and fan-out openings on the first passivation layer; forming a redistribution layer on the first passivation layer; forming a second passivation layer on the first passivation layer and the redistribution wiring layer; forming vertical connectors within the encapsulation to correspondingly couple to the fan-out pads; and disposing a plurality of dummy terminals on the dummy pattern.. . ... Powertech Technology Inc

Package-on-package structure and manufacturing method thereof

A pop structure includes a circuit board, a bottom package structure, a top package structure, and a metal frame structure. The circuit board has a plurality of signal pads and dummy pads. ... Powertech Technology Inc

Stacked type chip package structure and manufacturing method thereof

A stacked-type chip package structure includes a first chip, first terminals, a first redistribution layer, a first encapsulant, a second chip, second terminals, a second redistribution layer and through pillars. Each first chip includes a first active surface and first pads located on the first active surface. ... Powertech Technology Inc

Chip package structure and manufacturing method thereof

A chip package structure includes a chip, an encapsulant, a dielectric layer and a patterned circuit layer. The chip includes an active surface and a plurality of pads disposed on the active surface. ... Powertech Technology Inc

Semiconductor package structure and manufacturing method thereof

A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. ... Powertech Technology Inc

Chip package structure and manufacturing method thereof

A chip package structure includes a semiconductor component, a plurality of conductive pillars, an encapsulant and a redistribution layer. The semiconductor component includes a plurality of pads. ... Powertech Technology Inc

Slide plate valve

Provided is a slide plate valve, comprising a valve body and a valve core component comprising a valve plate (3) and a support frame (2), wherein at least one support member (4) is disposed on the top portion of the support frame (2) and sleeved with an elastic member (7) thereon, and one end of the elastic member (7) is connected to a pressing plate (5) disposed on a top end of the support member (4), and the other end of the elastic member (7) is connected to a limiting plate (6) slidably disposed on the support member. The slide plate valve avoids the problem of getting stuck.. ... Powertech Technology Inc

Method and device of pop stacking for preventing bridging of interposer solder balls

A first semiconductor package of a pop structure has a first body and a plurality of first solder balls. A second semiconductor package of the pop structure has a second body and a plurality of second solder balls. ... Powertech Technology Inc

Fan-out wafer level package structure

A fan-out wafer level package structure includes a chip, a molding compound, at least one circuit layer, and at least one dielectric layer. The molding compound encapsulates the chip. ... Powertech Technology Inc

Package-on-package structure and manufacturing method thereof

A pop structure includes a first package structure, an interposer, and a second package structure. The first package structure includes a first carrier, a first chip, conductive structures, and a first insulation encapsulation. ... Powertech Technology Inc

Heat-dissipating semiconductor package for lessening package warpage

A heat-dissipating semiconductor package includes a substrate, a chip, a first encapsulation body, a second encapsulation body and a heat sink. The substrate has an inner surface. ... Powertech Technology Inc

11/23/17 / #20170338128

Manufacturing method of package structure

A manufacturing method of a package structure is provided. The method includes the following steps. ... Powertech Technology Inc

10/26/17 / #20170309597

Manufacturing method of package structure

A manufacturing method of a package structure includes at least the following steps. At least one first die is disposed over a carrier. ... Powertech Technology Inc

10/05/17 / #20170287874

Stacked chip package structure and manufacturing method thereof

A stacked chip package structure includes a first chip, pillar bumps, a first encapsulant, a first redistribution layer, a second chip, a second encapsulant, a second redistribution layer and a through via. The pillar bumps are disposed on a plurality of first pads of the first chip respectively. ... Powertech Technology Inc

10/05/17 / #20170287870

Stacked chip package structure and manufacturing method thereof

A stacked chip package structure includes a first chip, stud bumps, a second chip, pillar bumps, an encapsulant and conductive vias. The first stud bumps are respectively disposed on a plurality of first pads of the first chip, wherein each first stud bump includes a rough surface, and the rough surface of each first stud bump is rougher than a top surface of each first pad. ... Powertech Technology Inc

09/07/17 / #20170256471

Wafer level chip scale package having continuous through hole via configuration and fabrication method thereof

A wafer level chip scale package (wlcsp) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (thv). The device chip is attached to the carrier chip. ... Powertech Technology Inc

08/10/17 / #20170229426

Fan-out back-to-back chip stacked packages and the method for manufacturing the same

Disclosed is a fan-out back-to-back chip stacked package, comprising a back-to-back stack of a first chip and a second chip, an encapsulant, a plurality of vias disposed in the encapsulant, a first redistribution layer and a second redistribution layer. The encapsulant encapsulates the sides of the first chip and the sides of the second chip simultaneously and has a thickness not greater than the chip stacked height to expose a first active surface of the first chip and a second active surface of the second chip. ... Powertech Technology Inc

08/10/17 / #20170229425

Manufacturing method of wafer level package structure

A manufacturing method of a wafer level package structure includes the following steps. A chip is disposed on a supporting board, wherein the chip includes an active surface and a back surface opposite to the active surface, and a plurality of pads on the active surface, and the back surface of the chip is adhered to the supporting board through a die attach film (daf). ... Powertech Technology Inc

07/06/17 / #20170194293

Fan-out multi-chip package and its fabricating method

A fan-out multi-chip package has a first redistribution layer and a plurality of chips encapsulated in an encapsulant. A dielectric layer and a second redistribution layer are formed on the encapsulant. ... Powertech Technology Inc

07/06/17 / #20170194231

Ball grid array package with protective circuitry layout and a substrate utilized in the package

Disclosed is a bga package with protective circuitry layouts to prevent cracks of the bottom circuit in the specific area of the substrate leading to package failure and to enhance packaging yield of bga packages. A chip is disposed on the upper surface of the substrate. ... Powertech Technology Inc

06/29/17 / #20170186737

Thin fan-out multi-chip stacked packages and the method for manufacturing the same

A fan out type multi-chip stacked package includes a chip stacked assembly having a plurality of chips vertically stacked. The electrodes of the chips and one active surface among all active surfaces are not covered by the stacked chips. ... Powertech Technology Inc

06/29/17 / #20170186711

Structure and method of fan-out stacked packages

A fan-out stacked packages are formed by stacking a plurality of tiers followed by singulation process. Each tier comprises a plurality of units. ... Powertech Technology Inc

06/29/17 / #20170186678

Fan-out chip package and its fabricating method

A fan-out chip package comprises a chip, an encapsulating layer, a first passivation layer, a redistribution wiring layer, a second passivation layer, and a plurality of vertical connectors. The encapsulation encapsulates the sides of the chip. ... Powertech Technology Inc

04/27/17 / #20170118106

Testing device and testing method

A testing device of high-frequency memory comprises a transfer interface, a tester and a socket group. The tester is electrically connected to the socket group via the transfer interface. ... Powertech Technology Inc

04/27/17 / #20170117263

Molded interconnecting substrate and the method for manufacturing the same

A molded interconnecting substrate has an embedded redistribution layer (rdl), an embossed rdl, a plurality of conductive pillars encapsulated in a molding core, and a chip also encapsulated in the molded core. The conductive pillars are disposed on the external pads of the embedded rdl. ... Powertech Technology Inc

04/20/17 / #20170110439

Package structure and manufacturing method thereof

Provided is a package structure including a substrate, n dies, n first pads, n vertical wires, and a second pad. The n dies are stacked alternatively on the substrate, so as to form a multi-die stack structure. ... Powertech Technology Inc

04/20/17 / #20170110416

Chip package having a protection piece compliantly attached on a chip sensing surface

Disclose is a chip package having an adhesive protection piece compliantly attached on the chip sensing surface, comprising a substrate, a main chip disposed on the substrate, an adhesive protection piece covering the main chip and an encapsulant encapsulating the main chip. The main chip has a chip sensing surface facing to a direction away from the substrate and a connection terminal electrically connected to the substrate. ... Powertech Technology Inc

03/23/17 / #20170084513

Semiconductor package

A semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer is provided. The insulating layer has an accommodating opening. ... Powertech Technology Inc

02/23/17 / #20170053898

Semiconductor package with pillar-top-interconnection (pti) configuration and its mis fabricating method

Disclosed is a semiconductor package with pillar-top-interconnection (pti) configuration, comprising a redistribution layer (rdl) formed on a carrier plane, a plurality of metal pillars disposed on the rdl, a chip bonded onto the rdl, and a molding core. The molding core is formed on the carrier plane and has a bottom surface defined by the carrier plane so that the rdl is embedded inside the molding core. ... Powertech Technology Inc

02/16/17 / #20170047295

Carrier substrate

A carrier substrate includes an insulation encapsulation, first conductive patterns, second conductive patterns, at least one first dummy pattern, and at least one second dummy pattern. The carrier substrate has a first layout region and a second layout region. ... Powertech Technology Inc

02/16/17 / #20170047277

Semiconductor structure

Provided is a semiconductor structure including a first die and a second die. The first die has a first conductive structure embedded in a dielectric layer. ... Powertech Technology Inc

02/02/17 / #20170033084

Multi-chip package having encapsulation body to replace substrate core

A multi-chip package having no substrate is presented. The multi-chip package includes a chip stacked assembly, a first redistribution layer, a plurality of wire bonds, a plurality of metal pillars, an encapsulation, a second redistribution layer, and a plurality of vertical interposers. ... Powertech Technology Inc

01/12/17 / #20170011983

Semiconductor package and manufacturing method thereof

A semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer is provided. The insulating layer has an accommodating opening. ... Powertech Technology Inc








ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009



###

This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Powertech Technology Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Powertech Technology Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

###