Real Time Touch



new TOP 200 Companies filing patents this week

new Companies with the Most Patent Filings (2010+)




Real Time Touch

Sandisk Corporation patents


Recent patent applications related to Sandisk Corporation. Sandisk Corporation is listed as an Agent/Assignee. Note: Sandisk Corporation may have other listings under different names/spellings. We're not affiliated with Sandisk Corporation, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Sandisk Corporation-related inventors


 new patent  Multi-gate vertical field effect transistor with channel strips laterally confined by gate dielectric layers, and method of making thereof

A matrix rail structure is formed over a substrate. The matrix rail structure includes a pair of lengthwise sidewalls that extend along a first horizontal direction and comprises, or is at least partially subsequently replaced with, a set of at least one gate electrode rail extending along the first horizontal direction and straight-sidewalled gate dielectrics. ... Sandisk Corporation

 new patent  Three-dimensional memory device with enhanced mechanical stability semiconductor pedestal and method of making thereof

After formation of an alternating stack of insulating layers and sacrificial material layers, a memory opening can be formed through the alternating stack, which is subsequently filled with a columnar semiconductor pedestal portion and a memory stack structure. Breakage of the columnar semiconductor pedestal portion under mechanical stress can be avoided by growing a laterally protruding semiconductor portion by selective deposition of a semiconductor material after removal of the sacrificial material layers to form backside recesses. ... Sandisk Corporation

 new patent  Read threshold adjustment with feedback information from error recovery

A storage device with a memory may optimize the setting of a read threshold or read level. A feedback mechanism may be used responsive to there being a read retry error for providing the read threshold from the read retry. ... Sandisk Corporation

 new patent  Word line contact regions for three-dimensional non-volatile memory

Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. ... Sandisk Corporation

Ecc decoder having adjustable parameters

A device includes a non-volatile memory, a traffic analyzer, and a parameter adjuster. The traffic analyzer is configured to generate a traffic type indicator based on one or more read requests from an access device to access data at the non-volatile memory. ... Sandisk Corporation

Select transistors with tight threshold voltage in 3d memory

Disclosed herein is a 3d memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. ... Sandisk Corporation

Semiconductor device including dual pad wire bond interconnection

A semiconductor device is disclosed including semiconductor die formed with a row of functional die bond pads and an adjacent row of dummy die bond pads. The functional die bond pads may be electrically connected to the integrated circuits formed within the semiconductor die. ... Sandisk Corporation

System and method of managing data in a non-volatile memory having a staging sub-drive

A system and method is disclosed for managing data in a non-volatile memory. The system may include a non-volatile memory having multiple non-volatile memory sub-drives, including a staging sub-drive to receive all data from a host and a plurality of other sub-drives each associated with a respective data temperature range. ... Sandisk Corporation

Systems and methods of adjusting an interface bus speed

A device includes a first latch configured to be coupled to a bus and configured to receive a data signal and a clock signal. The device also includes a delay element configured to generate a delayed version of the data signal or a delayed version of the clock signal. ... Sandisk Corporation

Ber model evaluation

A memory system is configured to perform a test operation to determine a deviation of a target storage location's bit error rate response relative to a model. The memory system determines the deviation level by measuring data sets stored in the target storage location to determine an actual bit error rate value and another actual parameter value used to estimate bit error rate. ... Sandisk Corporation

Methods, systems and computer readable media for intelligent fetching of data storage device commands from submission queues

Systems and methods for intelligent fetching of data storage device commands from submission queues are provided. One such method involves fetching commands from one or more submission queues, monitoring characteristics of the commands including a command type, predicting a next command based on the monitored command characteristics, monitoring a resource state of a data storage device, selecting a submission queue based on the predicted next command and the resource state, fetching a command from the selected submission queue, and providing the command from the selected submission queue to command processing logic.. ... Sandisk Corporation

Meta-groups in non-volatile storage based on performance times

Technology is described herein for performing memory array operations in multiple memory dies in parallel. The memory dies, or groups of non-volatile memory cells on the memory dies, may exhibit different performance times for memory array operations. ... Sandisk Corporation

Three-dimensional memory devices containing inter-tier dummy memory cells and methods of making the same

A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first memory opening fill structure extending through the first alternating stack and including a first memory film and a first vertical semiconductor channel, a joint-level electrically conductive layer overlying the first alternating stack, at least one joint-level doped semiconductor portion contacting a top surface of the first vertical semiconductor channel and located within, and electrically isolated from, the joint-level electrically conductive layer, a second alternating stack of second insulating layers and second electrically conductive layers located over the joint-level electrically conductive layer, and a second memory opening fill structure extending through the second alternating stack and including a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and vertically extends into the at least one joint-level doped semiconductor portion.. . ... Sandisk Corporation

Non-volatile memory with multi-pass programming

A non-volatile memory system implements a multi-pass programming process that includes separately programming groups of memory cells in a common block by performing programming for memory cells that are connected to two adjacent word lines and are part of a first group of memory cells followed by performing programming for other memory cells that are also connected to the two adjacent word lines and are part of a second group of memory cells.. . ... Sandisk Corporation

06/28/18 / #20180181462

Adaptive hard and soft bit decoding

Technology is described herein for operating non-volatile storage. In one embodiment, the memory system tracks which adjustments to default values for hard bit read reference voltages are most frequently successful to decode data in non-volatile memory cells. ... Sandisk Corporation

06/28/18 / #20180181321

Shared data storage system with high availability and hot plugging

A shared storage system includes a plurality of storage processors. A first storage processor of the plurality of storage processors is coupled with a shared storage device having a plurality of storage devices. ... Sandisk Corporation

06/28/18 / #20180181304

Non-volatile storage system with in-drive data analytics

A solid state drive (or other non-volatile storage device) includes a plurality of non-volatile storage elements arranged in blocks (or other units). Blocks (or other units) can be individually switched between analytics mode and i/o mode. ... Sandisk Corporation

06/21/18 / #20180175834

Duty cycle correction scheme for complementary signals

A complementary signal path may include an amplifier circuit configured to receive a pair of complementary input signals and a data alignment circuit configured to output a pair of complementary output signals in response to the pair of complementary input signals. A control circuit may detect duty cycle distortion in the pair of complementary output signals and perform a duty cycle correction process to remove the distortion. ... Sandisk Corporation

06/21/18 / #20180175054

Non-volatile memory with reduced variations in gate resistance

A three-dimensional non-volatile memory comprises a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over a substrate. Higher word lines are implemented to be thicker than lower word lines in order to reduce variation in resistance among word lines.. ... Sandisk Corporation

06/21/18 / #20180175006

Semiconductor device including die bond pads at a die edge

A semiconductor device is disclosed that is formed with die bond pads at an edge of the semiconductor die. The die bond pads may be formed partially in a kerf area between semiconductor die on a wafer. ... Sandisk Corporation

06/21/18 / #20180174996

Wire bonded wide i/o semiconductor device

A wide i/o semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide i/o semiconductor device. ... Sandisk Corporation

06/21/18 / #20180174983

Semiconductor device including corner recess

A semiconductor die is disclosed including corner recesses to prevent cracking of the semiconductor die during fabrication. Prior to dicing the semiconductor die from the wafer, recesses may be formed in the wafer at corners between any pair of semiconductor die. ... Sandisk Corporation

06/21/18 / #20180174668

Memory with bit line short circuit detection and masking of groups of bad bit lines

Techniques and memory devices are provided in which bit line short circuits are detected and groups of bit lines are masked off. A process tests groups of bit lines which are connected to a sense circuit. ... Sandisk Corporation

06/21/18 / #20180173655

Multi-channel memory operations based on bit error rates

In an illustrative example, a device includes a memory and a controller that is coupled to the memory and that is configured to communicate with the memory using at least a first channel and a second channel. The controller includes a bit error rate (ber) estimator configured to estimate a first ber corresponding to the first channel and a second ber corresponding to the second channel. ... Sandisk Corporation

06/21/18 / #20180173619

System and method for distributed logical to physical address mapping

In a storage device having a storage controller and multiple memory channels, each memory channel has a memory channel controller. The storage controller, in response to a host command to perform a respective read operation at a logical address specified by the host command, identifies the memory channel based on the specified logical address, and also identifies a portion of logical to physical address mapping information corresponding to the logical address. ... Sandisk Corporation

06/21/18 / #20180173447

Dynamic read table generation

Apparatuses, systems, methods, and computer program products are disclosed for dynamic read table generation. One apparatus includes a set of non-volatile storage cells. ... Sandisk Corporation

06/21/18 / #20180173444

Partially de-centralized latch management architectures for storage devices

A storage device may utilize de-centralized latch management to remove functions from the device controller to the memory die. Nand die located on a common bus may share a pool of latches with one die acting as a proxy or manager for the other die. ... Sandisk Corporation

06/14/18 / #20180166559

Methods and apparatus for three-dimensional nonvolatile memory

A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, the word line including a first portion including a first conductive material and a second portion including a second conductive material, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, the semiconductor material layer disposed adjacent the second portion of the word line, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line.. . ... Sandisk Corporation

06/14/18 / #20180166463

Charge storage region in non-volatile memory

Disclosed herein is a non-volatile storage system with memory cells having a charge storage region that may be configured to store a higher density of charges (e.g., electrons) in the middle than nearer to the control gate or channel. The charge storage region has a middle charge storage material that stores a higher density of charges than two outer charge storage materials that are nearer to the control gate or channel, in one aspect. ... Sandisk Corporation

06/14/18 / #20180165150

Pipeline delay detection during decoding by a data storage device

A method of operation of a data storage device includes inputting data to a decoder of the data storage device. The method further includes sending a command to a memory of the data storage device in response to an indication of a pipeline delay associated with a decoding process to decode the data. ... Sandisk Corporation

06/07/18 / #20180159560

Ecc and read adjustment based on dynamic memory error model estimation

A device includes a memory and a controller coupled to the memory. The controller is configured to determine a first count of bits of a representation of data that are estimated to be erroneous and a second count of bits of the representation of data that have high estimated reliability and are estimated to be erroneous. ... Sandisk Corporation

06/07/18 / #20180159553

Ecc decoder with multiple decoding modes

A device includes a low density parity check (ldpc) decoder that configured to receive a representation of a codeword. The ldpc decoder includes a message memory configured to store decoding messages, multiple data processing units (dpus), a control circuit, and a reording circuit. ... Sandisk Corporation

06/07/18 / #20180159033

Low power barrier modulated cell for storage class memory

Systems and methods for providing a barrier modulated cell (bmc) structure that may comprise a reversible resistance-switching memory element within a memory array are described. The bmc structure may include a barrier layer comprising a layer of amorphous germanium or amorphous silicon germanium paired with a conductive metal oxide, such as titanium dioxide (tio2), strontium titanate (srtio3), or a binary metal oxide. ... Sandisk Corporation

06/07/18 / #20180158947

Vertical transistors with sidewall gate air gaps and methods therefor

A method is provided that includes forming a first vertically-oriented transistor above a substrate, the first vertically-oriented transistor comprising a first sidewall gate disposed in a first direction, forming a second vertically-oriented transistor above the substrate, the second vertically-oriented transistor including a second sidewall gate disposed in the first direction, and forming an air gap chamber above the substrate disposed between the first sidewall gate and the second sidewall gate, and extending in the first direction, the air gap chamber including an air gap.. . ... Sandisk Corporation

06/07/18 / #20180158873

Three-dimensional devices with wedge-shaped contact region and method of making thereof

A wedge-shaped contact region can be employed to provide electrical contacts to multiple electrically conductive layers in a three-dimensional device structure. A cavity including a generally wedge-shaped region and a primary region is formed in a dielectric matrix layer over a support structure. ... Sandisk Corporation

06/07/18 / #20180158834

3d nand device with five-folded memory stack structure configuration

A three-dimensional semiconductor device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack and arranged in at least five rows that extend along a first horizontal direction, contact via structures arranged in a same number of rows as the memory stack structures and overlying the memory stack structures, each of the contact via structures being electrically connected to a semiconductor channel of a respective memory stack structure, bit lines contacting a respective contact via structure and extending along a second horizontal direction that is different from the first horizontal direction, and a pair of wall-shaped via structures extending through the alternating stack and laterally extending along the first horizontal direction.. . ... Sandisk Corporation

06/07/18 / #20180158531

Pulsed control line biasing in memory

In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be applied to various control lines in a memory device such as a word line, bit line and/or source line, in a program, verify, read or erase operation. ... Sandisk Corporation

06/07/18 / #20180157587

Randomly writable memory device and method of operating thereof

A method of writing data to a dna strand comprises cutting an address block of a selected address-data block unit of the dna strand to form first and second dna strings, and inserting a replacement address-data block that includes a replacement data segment between the first dna string and the second dna string to provide a rewritten dna strand having valid address followed by valid data and an invalid address followed by invalid data.. . ... Sandisk Corporation

05/31/18 / #20180151589

Three-dimensional memory device having passive devices at a buried source line level and method of making thereof

A layer stack including a lower semiconductor layer, a lower dielectric layer, and a spacer material layer is formed over a semiconductor substrate, and the spacer material layer is patterned to form spacer line structures. An upper dielectric layer and an upper semiconductor layer are formed, followed by formation of an alternating stack of insulating layers and spacer material layers. ... Sandisk Corporation

05/31/18 / #20180151588

Three-dimensional memory device with discrete self-aligned charge storage elements and method of making thereof

A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers over a substrate. A material layer stack containing, from outside to inside, an aluminum oxide tunneling dielectric layer, a silicon-containing tunneling dielectric layer, and a vertical semiconductor channel is formed within the memory opening. ... Sandisk Corporation

05/31/18 / #20180151497

Three-dimensional array device having a metal containing barrier and method of making thereof

A three-dimensional memory device includes driver transistors containing boron doped semiconductor active regions, device contact via structures in physical contact with the boron doped semiconductor active regions, the device contact via structures containing at least one of tantalum, tungsten, and cobalt, and a three-dimensional memory array located over the driver transistors and including an alternating stack of insulating layers and electrically conductive layers and memory structures vertically extending through the alternating stack.. . ... Sandisk Corporation

05/31/18 / #20180150400

Latch caching of sequential data

Technology is described herein for caching residual data in latches during a write operation of non-volatile storage. When writing data at the request of a host, it is possible for there to be some residual data that cannot be programmed at two (or more) bits per memory cell into a page of memory cells, given the programming scheme being used. ... Sandisk Corporation

05/31/18 / #20180150221

Methods, systems and computer readable media for intelligent fetching of data storage device commands from submission queues

Methods, systems, and computer readable media for intelligent fetching of storage device commands from submission queues are disclosed. On method is implemented in a data storage device including a controller and a memory. ... Sandisk Corporation

05/31/18 / #20180150117

Data storage device for a device accessory

An apparatus includes a first interface of an accessory of a wireless device. The first interface is configured to communicate with the wireless device using a wired communication technique. ... Sandisk Corporation

05/17/18 / #20180138292

Methods and apparatus for three-dimensional nonvolatile memory

A method is provided that includes forming a bit line above a substrate, forming a word line above the substrate, and forming a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a non-volatile memory material coupled in series with an isolation element. ... Sandisk Corporation

05/17/18 / #20180138194

Three-dimensional memory device having select gate electrode that is thicker than word lines and method of making thereof

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack having a memory array region and a contact region containing stepped surfaces, and memory stack structures having a semiconductor channel and a memory film extending through the memory array region of the alternating stack. The electrically conductive layers include a drain select gate electrode and word lines, where the drain select gate electrode is thicker than each of the word lines.. ... Sandisk Corporation

05/17/18 / #20180138193

Three-dimensional memory device having a multilevel drain select gate electrode and method of making thereof

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each memory stack structure includes a memory film and a vertical semiconductor channel. ... Sandisk Corporation

05/17/18 / #20180138189

Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof

A three-dimensional memory device including self-aligned drain select level electrodes is provided. Memory stack structures extend through an alternating stack of insulating layers and spacer material layers. ... Sandisk Corporation

05/17/18 / #20180137309

Storage system and method for providing gray levels of read security

A storage system and method for providing gray levels of read security are provided. In one embodiment, a storage system is provided comprising a memory and a controller in communication with the memory. ... Sandisk Corporation

05/17/18 / #20180136878

Interface for non-volatile memory

Apparatuses, systems, methods, and computer program products are disclosed for accessing non-volatile memory. An apparatus includes one or more memory die. ... Sandisk Corporation

05/17/18 / #20180136877

Command control for multi-core non-volatile memory

Apparatuses, systems, and methods are disclosed for controlling commands for non-volatile memory. An apparatus includes one or more memory die. ... Sandisk Corporation

05/17/18 / #20180136851

Command queue for storage operations

Apparatuses, systems, methods, and computer program products are disclosed for queueing commands for storage operations. An apparatus includes a command queue configured to queue storage commands received at a storage device and a controller for the storage device. ... Sandisk Corporation

05/17/18 / #20180136843

Interface for non-volatile memory

Apparatuses, systems, methods, and computer program products are disclosed for accessing non-volatile memory. An apparatus includes one or more memory die. ... Sandisk Corporation

05/17/18 / #20180136840

Storage operation queue

Apparatuses, systems, methods, and computer program products are disclosed for queuing storage operations. An integrated circuit memory element receives a storage operation command associated with a bank of storage locations of a memory element. ... Sandisk Corporation

05/10/18 / #20180130812

Three-dimensional memory device with electrically isolated support pillar structures and method of making thereof

A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings are formed through the first tier structure. ... Sandisk Corporation

05/10/18 / #20180129564

Method and decoder to adjust an error locator polynomial based on an error parity

A method of operation of a decoder includes receiving first data at the decoder. The method further includes generating second data at the decoder based on the first data. ... Sandisk Corporation

05/10/18 / #20180129558

Optimizing reclaimed flash memory

A memory system or flash card may optimize usage of reclaimed memory. The optimization may include lists for uncorrectable error correction code (uecc) and correctable error correction code (cecc) that can be used along with a dual programming scheme. ... Sandisk Corporation

05/10/18 / #20180129448

Method and system for write amplification analysis

A method and system for write amplification analysis are provided. In one embodiment, a method is provided that is performed in a computing device. ... Sandisk Corporation

05/10/18 / #20180129431

Storage system and method for temperature throttling for block reading

A storage system and method for temperature throttling for block reading are provided. In one embodiment, a storage system is provided comprising a memory comprising a plurality of word lines and a controller in communication with the memory. ... Sandisk Corporation

05/10/18 / #20180129428

Method and apparatus for wear-levelling non-volatile memory

Apparatus and method for performing wear leveling are disclosed. An ordered list of references to each of a set of memory blocks is stored. ... Sandisk Corporation

05/03/18 / #20180123570

Loop delay optimization for multi-voltage self-synchronous systems

A clock-receiving system may receive a host clock signal on a communications bus from a clock-sending system. Circuitry of a critical path of the clock-receiving system may communicate the clock signal to a multiplexer configured directly behind output driver circuitry. ... Sandisk Corporation

05/03/18 / #20180122906

Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device

The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. ... Sandisk Corporation

05/03/18 / #20180122905

Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device

Sacrificial semiconductor material portions are connected by a sacrificial semiconductor line extending along a different horizontal direction and protruding into an underlying source conductive layer. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through the sacrificial semiconductor material portions. ... Sandisk Corporation

05/03/18 / #20180122904

Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device

A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. ... Sandisk Corporation

05/03/18 / #20180122814

Non-volatile memory with reduced program speed variation

A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top to the bottom of the memory hole. ... Sandisk Corporation

05/03/18 / #20180122489

Erase for partially programmed blocks in non-volatile memory

An erase operation includes one or more erase depth checks to detect the occurrence of shallow erased memory cells at the end of an erase process. Memory cells are subjected to erase and erase verification until erase verification success is achieved. ... Sandisk Corporation

05/03/18 / #20180120166

Multi-level temperature detection with offset-free input sampling

An electronic system may include a controller that measures a plurality of temperatures of the electronic system. Each of the plurality of temperatures may be indicated by one of a plurality of temperature voltages, each of which is generated across the same voltage-generation circuit. ... Sandisk Corporation

04/19/18 / #20180108671

Three-dimensional memory device with leakage reducing support pillar structures and method of making thereof

Memory openings and support openings can be formed through an alternating stack of insulating layers and sacrificial material layers. A set of dielectric layers and at least one semiconductor material layer can be sequentially deposited in each of the memory openings and the support openings. ... Sandisk Corporation

04/19/18 / #20180107417

Systems and methods for efficient power state transitions

A memory device may be configured to leverage memory resources of a host computing device to efficiently transition between different power states. In some embodiments, the memory device stores resume data within a host memory buffer (hmb) before transitioning to a low-power state, and uses the resume data stored within the hmb to resume operation from the low-power state. ... Sandisk Corporation

04/12/18 / #20180102375

Select transistors with tight threshold voltage in 3d memory

Disclosed herein is a 3d memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. ... Sandisk Corporation

04/12/18 / #20180102344

Non-volatile memory system with wide i/o memory die

A non-volatile storage system includes a plurality of memory dies and an interface circuit. Each memory die includes a wide i/o interface electrically coupled to another wide i/o interface of another memory die of the plurality of memory dies. ... Sandisk Corporation

04/05/18 / #20180097009

Three-dimensional memory device having drain select level isolation structure and method of making thereof

A layer stack including an alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of memory stack structures, backside trenches are formed through the layer stack. ... Sandisk Corporation

04/05/18 / #20180095508

Airflow guide assembly and enclosure

In an electronics system, an adjustable airflow guide assembly and methods of deploying it facilitate dissipating heat. The assembly includes an extendable plate having a first coupling capable of rotatably attaching the extendable plate to a chassis, a link, including a second coupling, capable of translatably attaching the link to the chassis, and a third coupling capable of rotatably attaching the link to the extendable plate. ... Sandisk Corporation

03/29/18 / #20180090373

Three-dimensional memory device containing word lines formed by selective tungsten growth on nucleation controlling surfaces and methods of manufacturing the same

A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.. . ... Sandisk Corporation

03/29/18 / #20180090213

Configuration parameter management for non-volatile data storage

Apparatuses, systems, and methods are disclosed for managing configuration parameters for non-volatile data storage. A control module is configured to limit erase dwell times for blocks of a non-volatile memory medium to satisfy a threshold. ... Sandisk Corporation

03/29/18 / #20180089024

Non-volatile memory with read modes

A non-volatile memory system receives a request to read data. That request includes a quality of service indication. ... Sandisk Corporation

03/22/18 / #20180083764

Tuning circuitry and operations for non-source-synchronous systems

A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. ... Sandisk Corporation

03/15/18 / #20180075919

Block health monitoring using threshold voltage of dummy memory cells

Techniques are provided for measuring the endurance of a set of data memory cells by evaluating the threshold voltage (vth) of associated dummy memory cells. A cell has a high endurance or good data retention if it is able to maintain the charges. ... Sandisk Corporation

03/15/18 / #20180074891

Storage system and method for reducing xor recovery time

A storage system and method for reducing xor recovery time are provided. In one embodiment, a storage system is provides comprising a memory and a controller. ... Sandisk Corporation

03/08/18 / #20180067800

System and method for protecting firmware integrity in a multi-processor non-volatile memory system

A system and method is disclosed for managing firmware in a non-volatile memory system having a multi-processor controller. The controller may be configured with a plurality of processors. ... Sandisk Corporation

03/08/18 / #20180067799

System and method for detecting and correcting mapping table errors in a non-volatile memory system

A system and method is disclosed for detecting and correcting for errors in mapping table information stored in volatile memory of a non-volatile memory system. The method may include checking for mapping entry errors when retrieving mapping data for the non-volatile memory from a volatile memory cache. ... Sandisk Corporation

03/08/18 / #20180067684

Data storage at an access device

A device includes a non-volatile memory, first circuitry configured to communicate with the non-volatile memory, and second circuitry configured to communicate with an access device. The second circuitry is configured to retrieve data and metadata associated with the data from a volatile memory of the access device based on a request for the data. ... Sandisk Corporation

03/01/18 / #20180062970

Methods, systems, and computer readable media for utilizing loopback operations to identify a faulty subsystem layer in a multilayered system

Methods, systems, and computer readable media for utilizing loopback operations to identify a faulty subsystem layer in a multilayered system are disclosed. One method includes executing a plurality of loopback operations at a respective plurality of loopback points positioned among subsystem layers of a multilayered system and detecting a failed loopback operation among the plurality of loopback operations. ... Sandisk Corporation

03/01/18 / #20180062666

Column-layered message-passing ldpc decoder

In an illustrative example, a decoder includes a variable node unit (vnu) that includes a variable-to-check lookup table circuit configured to output a variable-to-check message corresponding to a check node. The vnu also includes a hard-decision lookup table circuit configured to output a hard decision value corresponding to a variable node. ... Sandisk Corporation

03/01/18 / #20180061850

Three-dimensional memory device with angled word lines and method of making thereof

A mesa structure is formed over peripheral devices on a substrate. An alternating stack of insulating layers and spacer material layers is formed over the substrate and the mesa structure. ... Sandisk Corporation

03/01/18 / #20180061505

Leakage current detection in 3d memory

Technology is described herein for detecting a leakage current between a block select line and a conductive region that exists in multiple blocks of memory cells in a plane. The conductive region may be shared by at least one memory cell in multiple blocks. ... Sandisk Corporation

03/01/18 / #20180060232

Flush command consolidation

A data storage device includes a write cache, a non-volatile memory and a controller coupled to the write cache and to the non-volatile memory. The controller is configured to, responsive to receiving a plurality of flush commands, write all data from the write cache to the non-volatile memory while executing fewer than all of the plurality of flush commands.. ... Sandisk Corporation

03/01/18 / #20180060230

Dynamic anneal characteristics for annealing non-volatile memory

Apparatuses, systems, methods, and computer program products are disclosed for annealing non-volatile memory. A controller identifies one or more life cycle characteristics of a non-volatile storage element. ... Sandisk Corporation

03/01/18 / #20180059976

Storage system with integrated components and method for use therewith

A storage system with integrated components and method for use therewith are provided. In one embodiment, a storage system is provided comprising a plurality of non-volatile memory devices; a controller in communication with the plurality of non-volatile memory devices; a plurality of data buffers in communication with the controller and configured to store data sent between the controller and an input/output bus; and a command and address buffer configured to store commands and addresses sent from a host, wherein the command and address buffer is further configured to synchronize data flow into and out of the plurality of data buffer; wherein at least two of the above components are integrated with each other.. ... Sandisk Corporation

03/01/18 / #20180059945

Media controller with response buffer for improved data bus transmissions and method for use therewith

A media controller with response buffer for improved data bus transmissions and method for use therewith are provided. In one embodiment, a storage system is provided comprising a plurality of non-volatile memory devices; a controller in communication with the plurality of non-volatile memory devices; a plurality of data buffers in communication with the controller and configured to store data sent between the controller and an input/output bus; a command and address buffer configured to store commands and addresses sent from a host, wherein the command and address buffer is further configured to synchronize data flow into and out of the plurality of data buffer; and a response buffer configured to store a ready signal sent from the controller after the controller reads data from the plurality of non-volatile memory devices in response to a read command from the host.. ... Sandisk Corporation

03/01/18 / #20180059944

Storage system with several integrated components and method for use therewith

A storage system with several integrated components and method for use therewith are provided. In one embodiment, a storage system comprising: a plurality of non-volatile memory devices; a controller in communication with the plurality of non-volatile memory devices; a plurality of data buffers in communication with the controller and configured to store data sent between the controller and an input/output bus; and a command and address buffer configured to store commands and addresses sent from a host, wherein the command and address buffer is further configured to synchronize data flow into and out of the plurality of data buffer; wherein at least three of the above components are integrated with each other.. ... Sandisk Corporation

03/01/18 / #20180059943

Media controller and method for management of cpu-attached non-volatile memory

A media controller and method for management of cpu-attached non-volatile memory are provided. In one embodiment, a storage system is provided comprising a plurality of non-volatile memory devices and a controller in communication with the plurality of non-volatile memory devices. ... Sandisk Corporation

03/01/18 / #20180059933

Electrically-buffered nv-dimm and method for use therewith

An electrically-buffered nv-dimm and method for use therewith are provided. In one embodiment, a storage system is provided comprising a plurality of non-volatile memory devices; a controller in communication with the plurality of non-volatile memory devices; a plurality of data buffers in communication with the controller and configured to store data sent between the controller and an input/output bus; and a command and address buffer configured to store commands and addresses sent from a host, wherein the command and address buffer is further configured to synchronize data flow into and out of the plurality of data buffers.. ... Sandisk Corporation

02/22/18 / #20180053562

Non-volatile memory with read disturb detection for open blocks

A non-volatile memory system includes technology for detecting read disturb in open blocks. In one embodiment, the system determines whether a particular block of non-volatile memory cells has been subjected to a minimum number of open block read operations and performs sensing operations for memory cells connected to an open word line of the particular block. ... Sandisk Corporation

02/15/18 / #20180047706

Vertical semiconductor device

A semiconductor device vertically mounted on a medium such as a printed circuit board, and a method of its manufacture, are disclosed. The semiconductor device includes a stack of semiconductor die having contact pads which extend to an active edge of the die aligned on one side of the stack. ... Sandisk Corporation

02/15/18 / #20180046527

Memory system with a weighted read retry table

A storage device with a memory may utilize an optimized read retry operation. A read retry table includes a number of read retry cases with updated read thresholds. ... Sandisk Corporation

02/15/18 / #20180046231

Adaptive temperature and memory parameter throttling

A storage device with a memory may modify throttling to reduce cross temperature effects. The decision to throttle may be based on a memory device temperature (i.e. ... Sandisk Corporation

02/08/18 / #20180041411

Method and system for interactive aggregation and visualization of storage system operations

A method and system for interactive aggregation and visualization of storage system operations are provided. In one embodiment, the method is performed by a server in communication with a client and comprises: receiving, from the client, data regarding storage system operations that were performed by a storage system over time, wherein each storage system operation is classified according to an operation type; receiving, from the client, a size of a graph to be displayed on the client's display device to visualize the storage device operations, wherein the size of the graph is defined by a number of tiles; for each tile, aggregating the storage system operations by operation type and identifying a dominant operation type; and sending, to the client, the identified dominant operation type for each tile. ... Sandisk Corporation

02/08/18 / #20180040627

Ridged word lines for increasing control gate lengths in a three-dimensional memory device

After formation of a memory opening through an alternating stack of insulating layers and sacrificial material layers, a blocking dielectric having a greater thickness at levels of the insulating layers than at levels of the sacrificial material layers is formed around, or within, the memory opening. A memory stack structure is formed within the memory opening. ... Sandisk Corporation

02/08/18 / #20180040623

Three-dimensional memory device with semicircular metal-semiconductor alloy floating gate electrodes and methods of making thereof

Azimuthally-split metal-semiconductor alloy floating gate electrodes can be formed by providing an alternating stack of insulating layers and spacer material layers, forming a dielectric separator structure extending through the alternating stack, and forming memory openings that divides the dielectric separator structure into a plurality of dielectric separator structures. The spacer material layers are formed as, or are replaced with, electrically conductive layers, which are laterally recessed selective to the insulating layers and the plurality of dielectric separator structures to form a pair of lateral cavities at each level of the electrically conductive layers in each memory opening. ... Sandisk Corporation

02/08/18 / #20180039541

Data relocation

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured, during execution of a relocation operation that includes storage of data to a memory buffer of an access device and retrieval of the data including data bits and first error correction code (ecc) parity bits from the memory buffer, to generate second ecc parity bits based on the data bits from the memory buffer and to compare the first ecc parity bits to the second ecc parity bits.. ... Sandisk Corporation

02/08/18 / #20180039538

Data integrity

A device includes a memory device and a controller. The controller is configured to receive data to be stored in the non-volatile memory and to store a first copy of the data and a second copy of the data to a volatile memory. ... Sandisk Corporation

02/01/18 / #20180034477

Decoder with parallel decoding paths

A device includes a memory configured to store syndromes, a first data processing unit coupled to the memory, and a second data processing unit coupled to the memory. The first data processing unit is configured to process a first value corresponding to a first symbol of data to be decoded. ... Sandisk Corporation

02/01/18 / #20180033798

Non-volatile memory with reduced variations in gate resistance

A three-dimensional non-volatile memory comprises a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over a substrate. Higher word lines are implemented to be thicker than lower word lines in order to reduce variation in resistance among word lines.. ... Sandisk Corporation

02/01/18 / #20180033794

Non-volatile memory with reduced program speed variation

A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top to the bottom of the memory hole. ... Sandisk Corporation

02/01/18 / #20180033646

Three-dimensional memory device containing composite word lines including a metal silicide and an elemental metal and method of making thereof

Word lines for a three-dimensional memory device can be formed by forming a stack of alternating layers comprising insulating layers and sacrificial material layers and memory stack structures vertically extending therethrough. Backside recesses are formed by removing the sacrificial material layers through a backside via trench. ... Sandisk Corporation

02/01/18 / #20180032396

Generalized syndrome weights

A device includes a memory device and a controller. The controller is configured to determine, based on data read from the memory device, a first count of bits of the data that are associated with at least a first number of unsatisfied parity checks of the data and a second count of bits of the data that are associated with at least a second number of unsatisfied parity checks of the data. ... Sandisk Corporation

02/01/18 / #20180032282

Systems and methods of memory reads

A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured to initiate a read operation to retrieve data from the non-volatile memory. ... Sandisk Corporation

02/01/18 / #20180032122

System and method for adjusting device performance based on sensed host current sourcing capability

A system and method is disclosed for an electronic device, such as a non-volatile memory associated with a host, to determine a current sourcing capability of the host and to adjust performance characteristics of the electronic device based on the determined current sourcing capability. The system may include an input current source testing circuit, device function circuitry and a controller configured to determine a current sourcing capability of a host with the input current source testing circuit, select a device performance parameter associated with the determined current sourcing capability and operate the device function circuitry according to the device performance parameter until detecting a power-off event. ... Sandisk Corporation

01/25/18 / #20180026646

Multiple-output oscillator circuits

A phase-locked loop (pll) circuit may be configured to generate a plurality of oscillating signals based on a single control voltage generated based on a phase difference between an input signal and a feedback signal. One of the plurality of oscillating signals may be used to generate the feedback signal.. ... Sandisk Corporation

01/25/18 / #20180025777

High-reliability memory read technique

A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured, based on a metric associated with a portion of the non-volatile memory, to store a read technique indicator that indicates that the portion is to be read using a high-reliability read technique.. ... Sandisk Corporation

01/25/18 / #20180025776

System and method for burst programming directly to mlc memory

Apparatus and method for performing burst mode programming in a memory system are disclosed. A memory system may program data in different modes, such as normal mode programming and burst mode programming. ... Sandisk Corporation

01/25/18 / #20180024950

Ring bus architecture for use in a memory module

Ring bus architectures for use in a memory module are disclosed. A memory module may include a primary ring bus; a ring bus controller positioned on the primary ring bus; a secondary ring bus in communication with the primary ring bus via a first bus bridge; and a tertiary ring bus in communication with the secondary ring bus via a second bus bridge. ... Sandisk Corporation

01/25/18 / #20180024948

Bad column management with data shuffle in pipeline

Systems and methods for controlling data flow and data alignment using data expand and compress circuitry arranged between a variable data rate bi-directional first in, first out (fifo) buffer and one or more memory arrays to compensate for bad column locations within the one or more memory arrays are described. The bi-directional fifo may have a variable data rate with the array side and a fixed data rate with a serializer/deserializer (serdes) circuit that drives input/output (i/o) circuitry. ... Sandisk Corporation

01/25/18 / #20180024920

System and method for tracking block level mapping overhead in a non-volatile memory

A system and method is disclosed for tracking block mapping overhead in a non-volatile memory. The system may include a non-volatile memory having multiple memory blocks and a processor configured to track a block level mapping overhead for closed blocks of the multiple memory blocks. ... Sandisk Corporation

01/25/18 / #20180024880

Bad column handling in flash memory

In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ecc encoding. Locations of bad columns are indicated to a soft-input ecc decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns.. ... Sandisk Corporation

01/25/18 / #20180024777

Selectively throttling host reads for read disturbs in non-volatile memory system

The various implementations described herein include systems, methods, and/or devices used to selectively throttle host reads in memory devices. The method includes: (1) identifying a storage location in the non-volatile memory system with high read disturbs vulnerable to reliability issues, (2) determining if the identified storage location is being throttled for host reads, (3) in accordance with a determination that the identified storage location does not satisfy the predefined read throttling criteria, initiate execution of a read operation, otherwise, enqueue read commands for deferred execution.. ... Sandisk Corporation

01/25/18 / #20180024581

Space and power-saving multiple output regulation circuitry

Regulator circuitry may include a plurality of output circuits to generate a plurality of regulated output voltages. The regulator circuitry may include a single operational amplifier and a single feedback loop for regulation, which may reduce space and power consumed by the regulator circuitry. ... Sandisk Corporation

01/25/18 / #20180024375

Reticle with reduced transmission regions for detecting a defocus condition in a lithography process

A reticle for a semiconductor lithography process includes a glass plate having regions with a reduced optical transmission factor. The regions may include arrays of elements comprising defects such as cracks or voids which are formed by laser pulses. ... Sandisk Corporation

01/18/18 / #20180019256

Selective tungsten growth for word lines of a three-dimensional memory device

Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. ... Sandisk Corporation

01/18/18 / #20180019228

Fan out semiconductor device including a plurality of semiconductor die

A semiconductor package is disclosed including a number of stacked semiconductor die, electrically connected to each other with wire bonds. The stacked semiconductor die are provided in a mold compound such that a spacing exists between a top die in the die stack and a surface of the mold compound. ... Sandisk Corporation

01/18/18 / #20180018101

Methods, systems, and computer readable media for write classification and aggregation using host memory buffer (hmb)

A method for write aggregation using a host memory buffer includes fetching write commands and data specified by the write commands from a host over a bus to a non-volatile memory system coupled to the host. Writing the data specified by the write commands from the non-volatile memory system over the bus to the host. ... Sandisk Corporation

01/11/18 / #20180012667

Word line dependent pass voltages in non-volatile memory

Sensing in non-volatile memory is performed using bias conditions that are dependent on the position of a selected memory cell within a group of non-volatile memory cells. During sensing, a selected memory cell receives a reference voltage while the remaining memory cells receive a read or verify pass voltage. ... Sandisk Corporation

01/04/18 / #20180006054

Methods and apparatus for three-dimensional nand non-volatile memory devices with side source line and mechanical support

A method of fabricating a monolithic three dimensional memory structure is provided. The method includes forming a stack of alternating word line and dielectric layers above a substrate, forming a source line above the substrate, forming a memory hole extending through the alternating word line and dielectric layers and the source line, and forming a mechanical support element on the substrate adjacent to the memory hole.. ... Sandisk Corporation

01/04/18 / #20180006049

Three-dimensional memory device containing annular etch-stop spacer and method of making thereof

A monolithic three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, an insulating cap layer overlying the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers and overlying the insulating cap layer, memory openings extending through the second alternating stack, the insulating cap layer, and the first alternating stack, memory stack structures located within the memory openings, and annular spacers located within the insulating cap layer and laterally surrounding a respective one of the memory stack structures.. . ... Sandisk Corporation

01/04/18 / #20180006041

Method of making three-dimensional semiconductor memory device having uniform thickness semiconductor channel

A method of manufacturing a semiconductor device includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a substrate, forming a memory opening through the stack, forming a layer stack including a memory material layer, a tunneling dielectric layer, and a first semiconductor material layer in the memory opening, forming a protective layer over the first semiconductor channel layer, physically exposing a semiconductor surface underneath the layer stack by anisotropically etching horizontal portions of the protective layer and the layer stack at a bottom portion of the memory opening, removing a remaining portion of the protective layer selective to the first semiconductor channel layer, and forming a second semiconductor channel layer on the first semiconductor channel layer.. . ... Sandisk Corporation

01/04/18 / #20180005974

Semiconductor device including interconnected package on package

A semiconductor device is disclosed including at least first and second vertically stacked and interconnected semiconductor packages. Signal communication between the second semiconductor package and a host device occurs through the first semiconductor package.. ... Sandisk Corporation

01/04/18 / #20180004981

Preventing access of a host device to malicious data in a portable device

A storage device comprising a memory, a controller, and a host interface operative to connect with a host. The memory containing data locations access to which are controllable by a protection application which is executable on a host. ... Sandisk Corporation

12/28/17 / #20170374186

Mobile device with unified media-centric user interface

A mobile device with a unified media-centric user interface is provided. In one embodiment, the user interface contains one or more of the following features: a unified view of the home screen, navigating between various storage locations, dragging items to collection/folder, pinch and zoom feature, stats shown for each file type, storage usage view from the app, manual and automatic backup, and magic move (keeping a low-resolution version of the original files while moving). ... Sandisk Corporation

12/28/17 / #20170373197

Three-dimensional memory device with amorphous barrier layer and method of making thereof

Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. ... Sandisk Corporation

12/28/17 / #20170373087

Offset backside contact via structures for a three-dimensional memory device

Die cracking of a three dimensional memory device may be reduced by adding offsets to backside contact via structures. Each backside contact via structure can include laterally extending portions that extend along a first horizontal direction adjoined by adjoining portions that extend along a horizontal direction other than the first horizontal direction. ... Sandisk Corporation

12/28/17 / #20170373086

Amorphous silicon layer in memory device which reduces neighboring word line interference

Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. ... Sandisk Corporation

12/28/17 / #20170373079

Three dimensional memory device containing multilayer wordline barrier films and method of making thereof

Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. ... Sandisk Corporation

12/28/17 / #20170373078

Inter-plane offset in backside contact via structures for a three-dimensional memory device

A three-dimensional memory device includes a plurality of planes, each having a respective alternating stack, strings of memory stack structures which extends through the respective alternating stack, and backside contact via structures vertically extending through the respective alternating stack, extending generally along the first horizontal direction, and laterally separating neighboring pairs of strings of memory stack structures along a second horizontal direction. A first plane includes a first plurality of strings that are laterally spaced apart along the second horizontal direction by a first plurality of backside contact via structures. ... Sandisk Corporation

12/28/17 / #20170372789

Erase speed based word line control

Apparatuses, systems, methods, and computer program products are disclosed for erase depth control. One apparatus includes a block of non-volatile storage cells. ... Sandisk Corporation

12/28/17 / #20170371755

Non-volatile memory with dynamic repurpose of word line

A non-volatile memory system includes a plurality of non-volatile data memory cells arranged into groups of data memory cells, a plurality of select devices connected to the groups of data memory cells, a selection line connected to the select devices, a plurality of data word lines connected to the data memory cells, and one or more control circuits connected to the selection line and the data word lines. The one or more control circuits are configured to determine whether the select devices are corrupted. ... Sandisk Corporation

12/28/17 / #20170371744

Non-volatile storage system using two pass programming with bit error control

A first phase of a programming process is performed to program data into a set of non-volatile memory cells using a set of verify references and allowing for a first number of programming errors. After completing the first phase of programming, an acknowledgement is provided to the host that the programming was successful. ... Sandisk Corporation

12/28/17 / #20170371588

Storage system and method for burst mode management using transfer ram

A storage system uses consumption of transfer ram as a trigger to enter and exit burst mode. In one embodiment, the storage system stores, in volatile memory, data to be written in non-volatile memory; monitors an allocation level of the volatile memory to determine a first amount of time that the allocation level is at a first level and a second amount of time that the allocation level is at second level; enters burst mode when a ratio of the first amount of time and the second amount of time is above a first threshold; and exits burst mode when the ratio of the first amount of time and the second amount of time is below a second threshold. ... Sandisk Corporation

12/28/17 / #20170371559

Systems and methods for optimizing media read times

The various embodiments described herein include methods, systems, and devices for optimizing media read times. In one aspect, a method is performed at a device at a storage device with one or more processors and memory coupled to the one or more processors. ... Sandisk Corporation

12/21/17 / #20170365613

Three-dimensional memory device having epitaxial germanium-containing vertical channel and method of making thereof

An alternating stack of insulating layers and spacer material layers is formed over a semiconductor substrate. Memory openings are formed through the alternating stack. ... Sandisk Corporation

12/21/17 / #20170365349

Dynamic tuning of first read countermeasures

Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage (vth) of a memory cell can shift depending on when the read operation occurs. Countermeasures are provided for a first read situation in which a memory is read after a power on event or after a long delay since a last read. ... Sandisk Corporation

12/21/17 / #20170364276

Storage system and method for dynamic duty cycle correction

A storage system and method for dynamic duty cycle correction are disclosed. In one embodiment, a controller of a storage system provides a clock signal to the memory, receives the clock signal back from the memory, monitors the duty cycle of the clock signal received back from the memory, and in response to the duty cycle of the clock signal received back from the memory not meeting a target value, adjusts the duty cycle of the clock signal provided to the memory so that the duty cycle of the clock signal received back from the memory better meets the target value. ... Sandisk Corporation

12/14/17 / #20170358594

Method of forming a staircase in a semiconductor device using a linear alignmnent control feature

A linear mark extending perpendicular to a primary step direction of stepped terrace for a three-dimensional memory device can be employed as a reference feature for aligning a trimming material layer before initiating an etch-and-trim process sequence. The linear mark can be formed as a linear trench or a linear rail structure. ... Sandisk Corporation

12/14/17 / #20170358593

Within-array through-memory-level via structures and method of making thereof

A semiconductor structure includes a memory-level assembly located over a substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack. Each of the at least one an alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion located in the opening contacts a sidewall of the respective electrically conductive layers. ... Sandisk Corporation

12/14/17 / #20170358365

Cell current based bit line voltage

Apparatuses, systems, methods, and computer program products are disclosed for read level determination. A block of non-volatile storage cells has a plurality of bit lines. ... Sandisk Corporation

12/14/17 / #20170358354

Three-dimensional nand non-volatile memory and dram memory devices on a single substrate

A method is provided that includes forming a three-dimensional nand stacked non-volatile memory array on a substrate, and forming a dram memory array on the substrate. The three-dimensional nand stacked non-volatile memory array and the dram memory array are formed using a single integrated circuit fabrication process.. ... Sandisk Corporation

12/07/17 / #20170352678

Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof

Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. ... Sandisk Corporation

12/07/17 / #20170352669

Three-dimensional memory device having multilayer word lines containing selectively grown cobalt or ruthenium and method of making the same

A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulating layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulating layers, a backside blocking dielectric layer may be formed in the backside recesses and sidewalls of the memory stack structures. ... Sandisk Corporation

12/07/17 / #20170352430

Non-volatile memory with customized control of injection type of disturb during program verify for improved program performance

A non-volatile memory system includes one or more control circuits configured to program memory cells and verify the programming. The verifying of the programmed memory cells includes applying one or more voltages to perform boosting of a channel region associated with unselected memory cells, allowing the boosting of the channel region for a portion of time while applying the one or more voltages, preventing/interrupting the boosting of the channel region while applying the one or more voltages for a duration of time based on position of a memory cell selected for verification, applying a compare signal to the memory cell selected for verification, and performing a sensing operation for the memory cell selected for verification in response to the compare signal.. ... Sandisk Corporation

12/07/17 / #20170351439

Systems and methods for managing storage endurance

Storage divisions of a non-volatile storage medium may have a writable state and an unwritable state. Storage divisions may be reclaimed by, inter alia, resetting the storage division from an unwritable state to a writable state. ... Sandisk Corporation








ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009



###

This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Sandisk Corporation in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Sandisk Corporation with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

###