Real Time Touch



new TOP 200 Companies filing patents this week

new Companies with the Most Patent Filings (2010+)




Real Time Touch

Semiconductor Manufacturing International Corp patents


Recent patent applications related to Semiconductor Manufacturing International Corp. Semiconductor Manufacturing International Corp is listed as an Agent/Assignee. Note: Semiconductor Manufacturing International Corp may have other listings under different names/spellings. We're not affiliated with Semiconductor Manufacturing International Corp, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Semiconductor Manufacturing International Corp-related inventors


 new patent  Semiconductor structure and fabrication method thereof

Semiconductor structures and fabrication methods thereof are provided. An exemplary semiconductor structure includes a base substrate having a first well and a second well region; a first insulation layer over the base substrate and dividing the second well region into a first region adjacent to the first well region, a second region away from the first well region and a third region under the first insulation layer; a gate structure over the base substrate in the first well region and the first region of the second well region; a first mask gate structure on a portion of the second region adjacent to the first region; a first stress layer on the first well region at a side of gate structure away from the first insulation layer; and a second stress layer on the second well regions at a side of the mask gate structure away from the isolation layer.. ... Semiconductor Manufacturing International Corp

 new patent  Semiconductor structure and fabrication method thereof

Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming a dummy gate structure over the base substrate; forming source/drain regions having source/drain doping ions in the base substrate at both sides of the dummy gate structure; forming a dielectric layer on the source/drain regions and covering the side surfaces of the dummy gate structure; removing the dummy gate structure to form an opening in the dielectric layer; performing one or more of a first ion implantation process, for implanting first barrier ions in the base substrate toward the source region to form a first barrier layer under the opening, and a second ion implantation process, for implanting second barrier ions in the base substrate toward the source region to form a second barrier layer under the opening; and forming a gate structure in the opening.. ... Semiconductor Manufacturing International Corp

 new patent  Flash memory device and fabrication method thereof

Flash memory devices and fabrication methods thereof are provided. An exemplary method includes providing discrete bit lines on a semiconductor substrate, a first dielectric layer on top surfaces of the bit lines, and a floating gate structure on the first dielectric layer, trenches being formed between adjacent bit lines and on the semiconductor substrate; forming a sacrificial layer with a top surface above the top surfaces of the bit lines in the trenches; forming a second dielectric layer on top and side surfaces of the floating gate structure and the top surface of the sacrificial layer; forming a control gate structure on the second dielectric layer; removing portions of the second dielectric layer, the floating gate structure and the first dielectric layer to expose a portion of the sacrificial layer; and removing the sacrificial layer from the adjacent bit lines and the semiconductor substrate, thereby forming air gaps.. ... Semiconductor Manufacturing International Corp

 new patent  Semiconductor structure and fabrication method thereof

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate, and forming an interlayer dielectric layer on the base substrate and having an opening exposing surface portions of the base substrate. ... Semiconductor Manufacturing International Corp

 new patent  Memory and fabrication method thereof

A memory and a method for fabricating the memory are provided. The method includes forming a plurality of first gate structures on a base substrate. ... Semiconductor Manufacturing International Corp

 new patent  Deposition method

A deposition method relating to semiconductor technology is presented. The deposition method includes: conducting a first deposition in a reaction chamber at a first deposition temperature; conducting a cool-down process on the reaction chamber, and conducting a second deposition during the cool-down process. ... Semiconductor Manufacturing International Corp

Semiconductor devices and fabrication methods thereof

A semiconductor device includes a base substrate including an nmos region and a pmos region. The pmos region includes a first p-type region and a second p-type region. ... Semiconductor Manufacturing International Corp

Testing structure, and fabrication and testing methods thereof

Testing structures, and their fabrication methods and testing methods are provided. An exemplary testing structure includes a base substrate containing a well region; a first doped epitaxial region in the well region and having a doping type same as a doping type of the well region; a dielectric layer on the base substrate and covering the well region and the first doped epitaxial region; a first contact plug passing through the dielectric layer and electrically connected with the first well region; and a second contact plug and a third contact plug. ... Semiconductor Manufacturing International Corp

Semiconductor structure and fabrication method thereof

A semiconductor structure and a fabrication method are provided. The fabrication method includes forming a first dielectric layer on a base substrate, the first dielectric layer containing an opening exposing a surface portion of the base substrate; forming an initial gate dielectric layer on the surface portion of the base substrate and on a sidewall surface of the opening in the first dielectric layer; forming a gate dielectric layer by removing a portion of the initial gate dielectric layer from the sidewall surface of the opening, such that a top surface of the gate dielectric layer on the sidewall surface is lower than a top surface of the first dielectric layer; forming a gate electrode on the gate dielectric layer to fill the opening, a portion of the gate electrode being formed on a portion of the sidewall surface of the first dielectric layer; and forming a second dielectric layer on the gate electrode and on the first dielectric layer.. ... Semiconductor Manufacturing International Corp

Capacitor, image sensor circuit and fabrication methods thereof

A capacitor, an image sensor circuit and fabricating methods are provided. The method includes providing a base substrate including a trench region and a body region adjacent to the trench region. ... Semiconductor Manufacturing International Corp

Wafer structure and spray apparatus

A wafer structure and a spray apparatus are provided. An exemplary wafer structure includes a wafer having a central region and a peripheral region surrounding the central region; an interlayer dielectric layer on a surface of the wafer in the central region not in the peripheral region; a buffer layer on the surface of the wafer in the peripheral region not in the central region; and a glue layer on the interlayer dielectric layer and the buffer layer. ... Semiconductor Manufacturing International Corp

Packaging structure and fabrication method thereof

A packaging structure and a method for fabricating the packaging structure are provided. The packaging structure includes a base substrate including a solder pad body region and a trench region adjacent to and around the solder pad body region. ... Semiconductor Manufacturing International Corp

Semiconductor device and fabrication method thereof

A semiconductor device and a fabrication method are provided. The fabrication method includes providing a base substrate including a core region having a first gate structure formed thereon, and an edge region having a second gate structure formed thereon; forming a source/drain doped layer, in the core region of the base substrate on both sides of the first gate structure, and in the edge region of the base substrate on both sides of the second gate structure, respectively, the source/drain doped layer including first ions; and doping the second ions in the source/drain doped layer in the edge region, the second ions having a conductivity type opposite to the first ions.. ... Semiconductor Manufacturing International Corp

Physical unclonable function (puf) chip and fabrication method thereof

A physical unclonable function (puf) chip and a fabrication method are provided. The fabrication method includes: forming an array of spaced electrode plates on a top metal connection layer of a nude chip, while forming the top metal connection layer; forming a deposition layer, on the top metal connection layer between adjacent electrode plates; forming openings between adjacent electrode plates in a row, each opening having a circumference tangent to the adjacent electrode plates; coating a conductive coating layer on the nude chip, the conductive coating layer including conductive particles with randomly distributed size; and packaging the nude chip to provide the puf chip.. ... Semiconductor Manufacturing International Corp

06/28/18 / #20180181152

Low dropout regulator (ldo) circuit

The present disclosure relates to the technical field of semiconductors, and discloses a low dropout regulator (ldo) circuit. The ldo circuit includes a first adjustment pipe, a second adjustment pipe, a first error amplifier, and a second error amplifier. ... Semiconductor Manufacturing International Corp

06/28/18 / #20180180664

Self-heating effect apparatus and test method

A self-heating effect apparatus includes a memory and a processor. The processor is coupled to the memory and configured to process a self-heating effect model for characterizing a heat flow network of devices. ... Semiconductor Manufacturing International Corp

06/21/18 / #20180175208

Flash memory structure

A method is provided for fabricating a flash memory structure. The method includes providing a substrate; and forming a gate structure and a hard mask layer. ... Semiconductor Manufacturing International Corp

06/21/18 / #20180175151

Fin-type semiconductor device

Fin-type semiconductor device is provided. The semiconductor device includes: a semiconductor substrate and an insulating layer on sidewalls of the plurality of fins. ... Semiconductor Manufacturing International Corp

06/21/18 / #20180175098

Image sensor and manufacturing method therefor

The present disclosure relates to the technical field of semiconductors, and discloses an image sensor and a manufacturing method therefor. The method includes: providing a semiconductor structure, where the semiconductor structure includes: a semiconductor substrate, and a first active region located on the semiconductor substrate, the first active region including a first doped region and a second doped region abutting against the first doped region, and the second doped region being located at an upper surface of the first active region; forming a semiconductor layer on an upper surface of the second doped region; and forming a contact connected to the semiconductor layer. ... Semiconductor Manufacturing International Corp

06/21/18 / #20180175082

Image sensor and manufacturing method therefor

The present disclosure relates to the technical field of semiconductors, and discloses an image sensor and a manufacturing method therefor. The image sensor includes: a semiconductor substrate; a first active region located on the semiconductor substrate; a doped semiconductor layer located on the first active region; and a contact located on the semiconductor layer, where the first active region includes: a first doped region and a second doped region abutting against the first doped region, wherein the second doped region is located at an upper surface of the first active region, and wherein the second doped region is formed by dopants in the semiconductor layer that are annealed to be diffused to a surface layer of the first doped region. ... Semiconductor Manufacturing International Corp

06/21/18 / #20180175015

Method for fabricating damascene structure using fluorocarbon film

A method for manufacturing an interconnect structure includes providing a metal interconnect layer, forming a dielectric layer on the metal interconnect layer, forming a fluorocarbon layer on the dielectric layer, forming a patterned hardmask layer on the fluorocarbon layer, etching the fluorocarbon layer and the dielectric layer using the patterned hardmask layer as a mask to form a trench in the dielectric layer and a through-hole through the dielectric layer to the metal interconnect layer, forming a metal layer filling the trench and the through-hole, and planarizing the metal layer until the planarized metal layer has an upper surface that is flush with an upper surface of the fluorocarbon layer. The interconnect structure thus formed has an improved reliability.. ... Semiconductor Manufacturing International Corp

06/21/18 / #20180174921

Semiconductor structure and fabrication method thereof

A semiconductor structure and a fabrication method are provided. The fabrication method includes providing a substrate, including a first region and a second region; forming a first doped region in the first region of the substrate, the first doped region having first doping ions; forming a second doped region in the second region of the substrate, the second doped region having second dopant ions with a conductivity type opposite to the first doping ions; forming a first metallide on a surface of the first doped region having the first doping ions; and forming a second metallide on a surface of the second doped region having the second doping ions, the second metallide and the first metallide being made of different materials.. ... Semiconductor Manufacturing International Corp

06/21/18 / #20180174909

Hybrid integrated semiconductor tri-gate and split dual-gate finfet devices and method for manufacturing

A method for making a tri-gate finfet and a dual-gate finfet includes providing a semiconductor on insulator (soi) wafer having a semiconductor layer over an insulator layer. The method further includes forming a hard mask on the semiconductor layer and patterning the hard mask to form first and second cap portions. ... Semiconductor Manufacturing International Corp

06/21/18 / #20180172967

Integrated rotary structure and fabrication method thereof

Integrated rotary structure and fabrication method thereof are provided. An integrated rotary structure includes a cylinder material. ... Semiconductor Manufacturing International Corp

06/14/18 / #20180166573

N-type fin field-effect transistor

The present disclosure provides n-type fin field-effect transistors. An n-type fin field-effect transistor includes a semiconductor substrate; at least one fin having a first side surface and a second side surface formed over the semiconductor substrate; a gate structure crossing over the fin and formed over the semiconductor substrate; and a source region and a drain region respectively formed on top of the fin at two sides of the gate structure by an ion implantation process on one of the first side surface and the second side surface of the fin at two sides of the gate structure and a thermal annealing process to diffuse doping ions into the other of the first side surface and the second side surface of the fin.. ... Semiconductor Manufacturing International Corp

06/14/18 / #20180166569

Semiconductor structure and fabricating method thereof

In accordance with some embodiments of the present disclosure, a semiconductor structure and a fabricating method thereof are provided. The method for forming a semiconductor structure comprises: forming a base substrate; forming a gate structure on the base substrate; forming openings in the base substrate on both sides of the gate structure; forming a barrier layer on sidewalls of the openings adjacent to the gate structure; and forming a doped layer in the openings, and forming a source region or a drain region in the doped layer.. ... Semiconductor Manufacturing International Corp

06/14/18 / #20180166391

Interconnect structure having a graphene layer

An interconnect structure includes a substrate, a dielectric layer on the substrate, a metal interconnect layer in the dielectric layer and in contact with the substrate, the metal interconnect layer having an upper surface flush with an upper surface of the dielectric layer, and a graphene layer on the metal interconnect layer. The graphene layer insulates a metal from air and prevents the metal from being oxidized by oxygen in the air, thereby increasing the queue time for the cmp process and the device reliability.. ... Semiconductor Manufacturing International Corp

06/14/18 / #20180166342

Semiconductor device and fabrication method thereof

A semiconductor device and a fabrication method are provided. The fabrication method includes providing a base substrate including a first region for forming a first transistor and a second region for forming a second transistor, the first transistor having a working current less than the second transistor. ... Semiconductor Manufacturing International Corp

06/14/18 / #20180166283

Semiconductor structure and fabrication method thereof

A semiconductor structure and a fabrication method are provided. The fabrication method includes providing a base substrate including a substrate and a plurality of discrete fins on the substrate; forming a support layer at least partially on sidewalls of the fins; ion implanting the fins through the support layer to form an ion doped region by an ion implantation process; removing the support layer to expose sidewalls of the fins.. ... Semiconductor Manufacturing International Corp

06/07/18 / #20180158929

Semiconductor device and fabrication method thereof

A semiconductor device and a fabrication method are provided. The method includes providing a substrate; forming a gate structure film on the substrate; forming a patterned mask structure on the gate structure film, where the patterned mask structure includes a first mask layer at least including a first material layer and a second mask layer on the first mask layer; forming a gate structure on the substrate by etching the gate structure film using the patterned mask structure as an etch mask, where the first material layer has an etching rate smaller than the second mask layer; and forming a spacer at least on a sidewall of the gate structure.. ... Semiconductor Manufacturing International Corp

06/07/18 / #20180158928

Semiconductor device and manufacturing method therefor

The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method may include: providing a semiconductor structure, where the semiconductor structure includes a semiconductor fin and an interlayer dielectric layer covering the semiconductor fin, the interlayer dielectric layer having an opening exposing a part of the semiconductor fin; forming a data storage layer at a bottom portion and a side surface of the opening; and filling a conductive material layer in the opening on the data storage layer. ... Semiconductor Manufacturing International Corp

06/07/18 / #20180158832

Semiconductor memory device

A method is provided for fabricating a semiconductor memory device. The method includes providing a substrate and forming a stacked layer on the substrate, where the stacked layer includes a tunneling dielectric layer and a floating gate layer sequentially formed on the substrate. ... Semiconductor Manufacturing International Corp

06/07/18 / #20180158831

Mask read-only memory device

A mask read-only memory (m-rom) device is provided. In an m-rom device, a first layer having a first type doping is formed in a substrate. ... Semiconductor Manufacturing International Corp

06/07/18 / #20180158813

Electrostatic discharge protection structure and fabricating method thereof

In accordance with some embodiments of the disclosed subject matter, an electrostatic discharge protection structure and a fabricating method thereof are provided.. . ... Semiconductor Manufacturing International Corp

06/07/18 / #20180158744

Semiconductor structure and fabrication method thereof

Semiconductor structures and fabrication methods thereof are provided. An exemplary semiconductor structure includes a semiconductor substrate having a device region and a protective region around the device region; a seal ring structure on the semiconductor substrate in the protective region; an electrical interconnect structure on the semiconductor substrate in the device region; an interlayer dielectric layer entirely covering the protective region on the seal ring structure and the electrical interconnect structure; a solder pad electrically connected with the electrical interconnect structure passing through a portion of the interlayer dielectric layer in the device region; a passivation layer on the interlayer dielectric layer and exposing the solder pad; and a conducive wire connected to the solder pad and across over a portion of the passivation layer in the protective region.. ... Semiconductor Manufacturing International Corp

06/07/18 / #20180158724

Semiconductor device and fabrication method thereof

A semiconductor device and a method for fabricating the semiconductor device are provided. The method includes forming a first composite structure, including a plurality of first composite layers, on a substrate, and forming a second composite structure, including a plurality of second composite layers on a surface portion of the first composite structure. ... Semiconductor Manufacturing International Corp

05/31/18 / #20180152801

Semiconductor device and manufacture thereof

A semiconductor device and its manufacturing method are presented. The manufacturing method includes providing a substrate structure; forming a first metal layer on the substrate structure; forming a second metal layer on the first metal layer; forming a first oxide layer on the second metal layer at a first temperature; and conducting the remaining manufacturing processes including thermal processes at a second temperature that is higher than the first temperature. ... Semiconductor Manufacturing International Corp

05/31/18 / #20180152791

Mems microphone having reduced leakage current and method of manufacturing the same

A microphone includes a substrate, an opening extending through the substrate, a first electrode plate layer on the opening, a second electrode plate layer spaced apart from the first electrode plate layer, a support structure layer on the substrate including an electrode attachment portion operable to attach the second electrode plate layer and a stopper operable to block contact between the first electrode plate layer and the second electrode plate layer, a cavity delineated by the support structure layer, the first electrode plate layer, and the substrate, and a conductive material layer on the support structure layer and spaced apart from the second electrode plate layer. The microphone has a significantly lower leakage current than conventional semiconductor microphones.. ... Semiconductor Manufacturing International Corp

05/31/18 / #20180151801

Semiconductor random access memory and manufacturing method thereof

The present disclosure discloses a resistive random access memory (rram) and a method for manufacture the rram. The method includes: providing a bottom interconnection layer; forming a bottom dielectric layer above the bottom interconnection layer, the bottom dielectric layer comprising a via through the bottom dielectric layer that exposes a portion of the bottom interconnection layer; and forming a bottom electrode layer in the via, the bottom electrode layer including a first electrode selectively grown above the bottom interconnection layer. ... Semiconductor Manufacturing International Corp

05/31/18 / #20180151696

Semiconductor device and manufacture thereof

A semiconductor device and its manufacturing method are presented. The manufacturing method includes providing a semiconductor structure comprising a substrate, at least one source region on the substrate, an interlayer dielectric layer covering a portion of the source region and having a cavity on the source region, and a pseudo gate insulation layer at the bottom of the cavity covering a portion of the source region; forming a barrier layer in the cavity; forming a loss reduction region in the interlayer dielectric layer by conducting an ion implantation process comprising silicon ion or carbon ion; removing the barrier layer; removing the pseudo gate insulation layer to expose a portion of the source region; and forming a gate structure on the exposed portion of the source region. ... Semiconductor Manufacturing International Corp

05/31/18 / #20180151575

Semiconductor structure and fabrication method thereof

Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate having an n-type logic region including a first and a second n-type threshold voltage region, a p-type logic region including a first and a second p-type threshold voltage region, a pull-up transistor region and an adjacent pull-down transistor region; forming a gate dielectric layer; forming a first work function layer on the gate dielectric layer; removing portions of the first work function layer; forming a second work function layer on remaining first work function layer and exposed portions of the gate dielectric layer; removing a portion of the second work function layer; forming an n-type work function layer on remaining second work function layer and exposed portion of the gate dielectric layer in the second n-type threshold voltage region; and forming a gate electrode layer on the n-type work function layer.. ... Semiconductor Manufacturing International Corp

05/31/18 / #20180151574

Semiconductor structure, static random access memory, and fabrication method thereof

A semiconductor structure, a method for fabricating the semiconductor structure and a static random access memory are provided. The method includes providing a base substrate including a substrate and a plurality of discrete fins on the substrate. ... Semiconductor Manufacturing International Corp

05/31/18 / #20180151573

Semiconductor structures and fabrication methods thereof

A method for fabricating a semiconductor device includes forming a gate dielectric layer on a base substrate including an n-type logic region, a p-type logic region, a first pull down transistor (pdt) region, a second pdt region, and a pass gate transistor (pgt) region, forming a first work function layer (wfl) in the first n-type threshold-voltage (tv) region, the p-type logic region, the second pdt region, and the pgt region, forming a second wfl on the first wfl in the first p-type tv region, and forming a third wfl on the second wfl in the first p-type tv region, the first wfl in the second p-type tv region, and the gate dielectric layer in the second n-type tv region and the first pdt region. The thickness of the third wfl is smaller than the thickness of the first wfl. ... Semiconductor Manufacturing International Corp

05/31/18 / #20180151572

Semiconductor structure, static random access memory and fabrication method thereof

A semiconductor structure, a method for fabricating the semiconductor structure, and a static random access memory are provided. The method includes providing a base substrate including a substrate and a plurality of discrete fins on the substrate. ... Semiconductor Manufacturing International Corp

05/31/18 / #20180151535

Wafer bonding structure and wafer bonding method

Wafer bonding methods and wafer bonding structures are provided. An exemplary wafer bonding method includes providing a first wafer; forming a first interlayer dielectric layer and a first bonding layer passing through the first interlayer dielectric layer on the surface of the first wafer; providing a second wafer; forming a second interlayer dielectric layer and a second bonding layer passing through the second interlayer dielectric layer on surface of the second wafer; forming a self-assembling layer on at least one of a surface of the first interlayer dielectric layer and a surface of the second interlayer dielectric layer; and bonding the first wafer with the second wafer, the first bonding layer and the second bonding layer being fixed with each other, and the first interlayer dielectric layer and the second interlayer dielectric layer being fixed with each other by the self-assembling molecular layer.. ... Semiconductor Manufacturing International Corp

05/31/18 / #20180151505

Interconnection structures and fabrication methods thereof

A method for fabricating an interconnection structure includes providing a substrate, forming a dielectric layer on the substrate, forming a conductive structure in the dielectric layer, forming a cap layer doped with silicon on the conductive structure and the dielectric layer, and performing an annealing process on the conductive structure and the cap layer. During the annealing process, the silicon ions in the cap layer react with the material of the conductive structure and form chemical bonds. ... Semiconductor Manufacturing International Corp

05/31/18 / #20180151488

Interconnect structure and manufacturing method thereof

A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate and a first dielectric layer on the substrate and having an opening for a first interconnect layer extending to the substrate, forming a first mask layer on a portion of the first dielectric layer spaced apart from the opening, forming a first metal layer filling the opening and covering a portion of the first dielectric layer not covered by the first mask layer, removing the first mask layer, forming a second dielectric layer on the first dielectric layer and on the first metal layer and having a trench for a second interconnect layer, the trench exposing a portion of the first metal layer; and forming a second metal layer filling the trench and in contact with the exposed portion of the first metal layer.. . ... Semiconductor Manufacturing International Corp

05/31/18 / #20180151451

Sram devices and fabrication methods thereof

A method for fabricating an sram device includes providing a base substrate including a pull up transistor (put) region and a pull down transistor (pdt) region, forming a gate dielectric layer, forming a first work function (wf) layer using a p-type wf material, removing the first wf layer formed in the pdt region, forming a second wf layer using a p-type wf material on the first wf layer in the put region and on the gate dielectric layer in the pdt region, removing the second wf layer formed in the pdt region, forming a third wf layer using an n-type wf material on the top and the sidewall surfaces of the second wf layer in the put region, the sidewall surface of the first wf layer in the put region, and the gate dielectric layer in the pdt region, and forming a gate electrode layer on the third wf layer.. . ... Semiconductor Manufacturing International Corp

05/31/18 / #20180151426

Method of flat cu forming with partial cu plating

A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate and a dielectric layer on the substrate, the dielectric layer having an opening extending to the substrate. The method further includes forming a mask layer on at least one portion of the dielectric layer, forming a metal layer filling the opening and covering portions of dielectric layer not covered by the mask layer, removing the mask layer, and planarizing the metal layer so that an upper surface of a remaining portion of the metal layer is flush with an upper surface of the dielectric layer. ... Semiconductor Manufacturing International Corp

05/31/18 / #20180151383

Semiconductor structure and fabrication method thereof

Semiconductor structures and fabrication methods are provided. The semiconductor structure includes a base including first, second, third, and fourth regions, used for first, second, third, and fourth transistors, respectively. ... Semiconductor Manufacturing International Corp

05/31/18 / #20180149985

Mask cooling apparatus and mask cooling method

Mask cooling apparatus and mask cooling methods are provided. An exemplary mask cooling apparatus includes a cooler, having a cooling region, a coolant inlet region and a coolant outlet region; cooling channels, disposed in the cooling region of the cooler and used to contact with the mask; coolant inlet channels, disposed in the coolant inlet region and used to introduce a coolant in the cooling channels; and coolant outlet channels, disposed in the coolant outlet region and used to drain the coolant out from the cooling channels.. ... Semiconductor Manufacturing International Corp

05/24/18 / #20180145699

Current source and digital to analog converter

The present disclosure relates to the technical field of semiconductors, and discloses a current source and a digital to analog convertor. The current source includes a current output circuit and an impedance gain circuit which is configured to increase output impedance of the current output circuit. ... Semiconductor Manufacturing International Corp

05/24/18 / #20180145182

A semiconductor device and manufacturing method thereof

A semiconductor device and its manufacturing method are presented. The manufacturing method entails: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region that are mutually exclusive from one another, with a first oxide layer on the first and the second regions; conducting a nitriding process on the semiconductor substrate to form a nitride barrier layer on the first oxide layer on the first and the second regions; removing the first oxide layer on the second region; and conducting an oxidation process to form a second oxide layer on the second region.. ... Semiconductor Manufacturing International Corp

05/24/18 / #20180145172

Semiconductor device and manufacturing method therefor

The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The method includes: providing a substrate structure, where the substrate structure includes: a substrate having a first device region and a second device region, a first dummy gate structure at the first device region, a second dummy gate structure at the second device region, and an ldd region below the first dummy gate structure. ... Semiconductor Manufacturing International Corp

05/24/18 / #20180145156

Finfet with improved gate dielectric

A semiconductor device includes a substrate structure comprising a substrate and a plurality of fins on the substrate. Each of the fins includes a fluorine-doped top portion.. ... Semiconductor Manufacturing International Corp

05/24/18 / #20180145069

Semiconductor resistor and manufacturing method therefor

The present disclosure relates to a technical field of semiconductors and discloses a semiconductor resistor and a manufacturing method therefor. The method includes: providing a substrate structure, where the substrate structure includes a substrate having a well region and a fin structure in the well region, and where the fin structure includes a semiconductor fin and an insulating layer at a surface of the semiconductor fin; forming a first dummy gate structure and a second dummy gate structure at two end portions of the fin structure, respectively; forming a mask layer having a first opening and a second opening, where the first opening exposes the first dummy gate structure and a part of the fin structure that abuts against the first dummy gate structure, and the second opening exposes the second dummy gate structure and a part of the fin structure that abuts against the second dummy gate structure; etching an exposed part of the fin structure that abuts against the first dummy gate structure using the mask layer as a mask and etching an exposed part of the fin structure that abuts against the second dummy gate structure using the mask layer as a mask, so as to form a first recess and a second recess; removing the mask layer, and epitaxially growing a semiconductor material in the first recess and the second recess, so as to respectively form a first contact area and a second contact area; and forming a first contact connected to the first contact area and a second contact connected to the second contact area.. ... Semiconductor Manufacturing International Corp

05/24/18 / #20180144990

Method of finfet contact formation

A method of manufacturing a semiconductor device includes providing a substrate structure, which includes a substrate, one or more semiconductor fins on the substrate, a gate structure on each fin, an active region located in said fins, and an interlayer dielectric layer covering at the active region. The method includes forming a hard mask layer over the interlayer dielectric layer and the gate structure, and using an etch process with a patterned etch mask, forming a first contact hole extending through the hard mask layer and extending into a portion of the interlayer dielectric layer, using patterned a mask. ... Semiconductor Manufacturing International Corp

05/24/18 / #20180144987

Fin field-effect transistor and fabrication method thereof

Finfet structures and fabrication methods thereof are provided. An exemplary fabrication method includes forming a semiconductor substrate and a plurality of fins. ... Semiconductor Manufacturing International Corp

05/24/18 / #20180144986

Fin cut process and fin structure

A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, semiconductor fins extending in a first direction on the substrate, a hardmask layer on the semiconductor fins, and an isolation region surrounding the semiconductor fins and having an upper surface flush with the hardmask layer, the isolation region including a first region on a side of the semiconductor fins in the first direction and a second region on a side of the semiconductor fins in a second direction different from the first direction. The method also includes removing the hardmask layer, etching a portion of the first region above the semiconductor fins, forming a mask layer on the semiconductor fins and a remaining first region, etching the second region such that an upper surface of the remaining second region is lower than an upper surface of the semiconductor fins, and removing the mask layer.. ... Semiconductor Manufacturing International Corp

05/24/18 / #20180144947

Photomask manufacturing method

A photomask manufacturing method relating to semiconductor technology is presented. The manufacturing method involves providing a substrate structure comprising an etch material layer, a first sacrificial layer on a portion of the etch material layer, and a photomask layer on an upper surface of the etch material layer and on an upper surface and a side surface of the first sacrificial layer; forming a second sacrificial layer covering the photomask layer on the etch material layer and on the side surface of the first sacrificial layer; etching the photomask layer not covered by the second sacrificial layer to expose the first sacrificial layer; removing the first sacrificial layer and the second sacrificial layer; and removing the photomask layer on the etch material layer. ... Semiconductor Manufacturing International Corp

05/24/18 / #20180144803

Nonvolatile memories and reading methods thereof

A nonvolatile memory includes a first array bank coupled to a first bit-line, a second array bank coupled to a second bit-line, a pre-charging circuit, a first selection circuit, a second selection circuit, and a sense amplifier. An address enable signal sent to the first selection circuit controls whether the pre-charging circuit needs to pre-charge the first bit-line and the second bit-line. ... Semiconductor Manufacturing International Corp

05/17/18 / #20180138297

Cylindrical germanium nanowire device

A semiconductor device includes a substrate, a cavity in the substrate, and a germanium (ge) nanowire suspending in the cavity.. . ... Semiconductor Manufacturing International Corp

05/17/18 / #20180138184

Dynamic random access memory and fabrication method thereof

Dynamic random access memory (dram) and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming an interlayer dielectric layer over the base substrate; forming an opening passing through the interlayer dielectric layer; and forming a memory structure, having a first conductive layer, a memory medium layer on the first conductive layer, and a second conductive layer on the memory medium layer, in the opening.. ... Semiconductor Manufacturing International Corp

05/17/18 / #20180138183

Dynamic random access memory and fabrication method thereof

Dynamic random access memory (dram) and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming a gate structure over the base substrate; forming doped source/drain regions in the base substrate at two sides of the gate structure, respectively; forming an interlayer dielectric layer over the gate structure, the base substrate and the doped source/drain regions; forming a first opening, exposing one of the doped source/drain regions at one side of the gate structure, in the interlayer dielectric layer; and forming a memory structure in the first opening and on the one of doped source/drain regions.. ... Semiconductor Manufacturing International Corp

05/17/18 / #20180138087

Semiconductor structure and method for forming the same

Various embodiments provide semiconductor structures and methods for forming the same. In an exemplary structure, a substrate has a device region, a seal ring region surrounding the device region, and a dielectric layer disposed thereon. ... Semiconductor Manufacturing International Corp

05/17/18 / #20180138045

Semiconductor structures and fabrication methods thereof

A method for fabricating a semiconductor structure includes providing a base structure, forming a dielectric layer on the base structure, forming a plurality of openings in the dielectric layer, forming a gate dielectric layer on bottom and sidewall surfaces of each opening, and forming an aluminum-containing work function layer on the gate dielectric layer in each opening. Along the direction from the gate dielectric layer to the top of the opening, the atomic concentration of aluminum atoms in the aluminum-containing work function layer decreases. ... Semiconductor Manufacturing International Corp

05/17/18 / #20180137911

Retention voltage generation circuit and electronic apparatus

Retention voltage generation circuits and electronic apparatus are provided. An exemplary retention voltage generation circuit includes a driving circuit, configured to generate driving currents; a first retention voltage generation circuit, configured to generate a first retention voltage, the first retention voltage being substantially equal to a threshold voltage of an nmos transistor in a power-consumption circuit; a second retention voltage generation circuit, configured to generate a second retention voltage, the second retention voltage being substantially equal to a threshold voltage of a pmos transistor in the power-consumption circuit; and a retention voltage selection circuit, coupled to the first retention voltage generation circuit and the second retention voltage generation circuit, and configured to receive the driving currents, wherein retention voltage selection circuit is configured to select a higher voltage from the first retention voltage and the second retention voltage as a retention voltage to drive the power-consumption circuit to operate at a retention mode.. ... Semiconductor Manufacturing International Corp

05/10/18 / #20180130893

Semiconductor device and fabrication method thereof

Semiconductor devices and fabrication methods thereof are provided. An exemplary semiconductor device includes a base substrate; a gate structure group, having a plurality of gate structures, formed over the base substrate; first source/drain doping regions formed in the base substrate between adjacent gate structures; second source/drain doping regions formed in the base substrate at two sides of the gate structure group, respectively; a first conductive layer formed on a surface of each of the first source/drain doping regions. ... Semiconductor Manufacturing International Corp

05/10/18 / #20180130710

Fin field-effect transistor and fabrication method thereof

Fin field-effect transistors (finfets) and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate having a plurality of fins; forming gate structures over the base substrate; forming a photoresist film having a plurality of exposure regions and non-exposure regions over the base substrate, the fins and the gate structures, wherein the exposure regions have first regions above the top surfaces of the gate structures and second regions below the top surfaces of the gate structures; performing an exposure process to the photoresist film; performing a post-baking process to cause photoacid in the second regions of the exposure regions to diffuse into portions of the photoresist film below the top surfaces of the gate structures in the non-exposure regions; developing exposed photoresist film to form photoresist layers; and performing a function doping process to the fins using the photoresist layers as a mask.. ... Semiconductor Manufacturing International Corp

05/10/18 / #20180130704

Semiconductor device and fabrication method thereof

Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming gate structures over the base substrate; forming doped source/drain regions in the base substrate at two sides of each of the gate structures; forming an oxide layer on each of the doped source/drain regions; forming a metal layer on the oxide layer; and performing a reactive thermal annealing process, such that the metal layer reacts with a material of the oxide layer and a material of the doped source/drain regions to form a metal contact layer on each of the doped source/drain regions. ... Semiconductor Manufacturing International Corp

05/10/18 / #20180130660

Semiconductor device having interconnect structure

Various embodiments provide semiconductor devices. A base including a substrate and an interlayer dielectric layer is provided. ... Semiconductor Manufacturing International Corp

05/10/18 / #20180129237

Bandgap reference circuit and method of using the same

A bandgap reference circuit and method of using the same are provided. The bandgap reference circuit includes a startup component; an output component; and a bandgap core component coupled there-between. ... Semiconductor Manufacturing International Corp

05/03/18 / #20180123550

Balun structure

A balun structure is provided. The balun structure includes a substrate, a first coil structure and a second coil structure having a spiral shape and on the substrate. ... Semiconductor Manufacturing International Corp

05/03/18 / #20180122948

Method to improve finfet device performance

A method for manufacturing a semiconductor device includes providing a substrate structure having pmos and nmos regions. The pmos region includes a first region, a first gate structure on the first region, and first source and drain regions on opposite sides of the first gate structure. ... Semiconductor Manufacturing International Corp

05/03/18 / #20180122896

Novel channel stop imp for the finfet device

A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, a semiconductor fin on the substrate, and an isolation region on opposite sides of the semiconductor fin, the isolation region having an upper surface substantially flush with an upper surface of the at least one semiconductor fin. The method also includes implanting ions into the substrate structure to form a doped region in the semiconductor fin and in the isolation region, etching back the isolation region to expose a portion of the semiconductor fin, and performing an annealing process to activate the implanted ions in the doped region. ... Semiconductor Manufacturing International Corp

05/03/18 / #20180122855

Magnetic random access memory and manufacture thereof

A magnetic random access memory and its manufacturing method related to semiconductor techniques. The magnetic random access memory comprises a word line, a bit line, and a memory unit positioned between the word line and the bit line, wherein the memory unit comprises a fixture layer connecting the bit line, a free layer connecting the word line, and an insulation layer positioned between the fixture layer and the free layer. ... Semiconductor Manufacturing International Corp

05/03/18 / #20180122823

Flash memory device and manufacture thereof

A flash memory device and its manufacturing method are presented. The flash memory device includes a substrate; a memory unit on the substrate, comprising a channel structure, wherein the channel structure comprises, sequentially from inner to outer of the channel structure, a channel layer comprising a first component substantially perpendicular to an upper surface of the substrate and a second component on the first component, a tunnel insulation layer wrapped around the channel layer, a charge capture layer wrapped around the tunnel insulation layer, and a blocking layer wrapped around the charge capture layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure with a topmost gate structure wrapped around the second component; and a channel contact component connecting to, and forming a schottky contact with, the second component of the channel layer. ... Semiconductor Manufacturing International Corp

05/03/18 / #20180122806

Method to improve the high k quality for finfet

A method of manufacturing a semiconductor device includes providing a substrate structure including pmos and nmos regions having respective first and second trenches, a high-k dielectric layer in the first and second trenches, and a first p-type work function adjustment layer on the high-k dielectric layer, sequentially forming first and second protective layers and a mask layer on the substrate structure, removing a portion of the mask layer exposing a portion of the second protective layer on the nmos region, removing the exposed portion of the second protective layer on the nmos region exposing a portion of the first protective layer on the nmos region, removing the mask layer exposing the second protective layer on the pmos region, removing portions of the first protective layer and first p-type work function adjustment layer on the nmos region and removing the second and first protective layers on the pmos region.. . ... Semiconductor Manufacturing International Corp

05/03/18 / #20180122704

Dummy gate structures and manufacturing methods thereof

A semiconductor device includes a semiconductor substrate, a fin protruding from the semiconductor substrate, a trench on opposite sides of the fin, a first insulator layer partially filling the trench, a second insulator layer on the fin, a plurality of dummy gate structures for the fin and including a first dummy gate structure on the first insulator layer and a second dummy gate structure on the second insulator layer, the first dummy gate structure adjacent to a portion of the second insulator layer on a side surface of the one or more fins, a spacer on side surfaces of the dummy gate structures, and a source or drain in the fin and between the dummy gate structures. The fin protrudes from the first insulator layer. ... Semiconductor Manufacturing International Corp

05/03/18 / #20180122701

Semiconductor structure and fabrication method thereof

A semiconductor structure and a fabrication method are provided. A fabrication method includes providing a substrate including an nmos region and a pmos region; forming a first high-k gate dielectric layer on the nmos region of the substrate; forming an interfacial layer on the pmos region of the substrate; forming a second high-k gate dielectric layer on the interfacial layer and the first high-k gate dielectric layer; forming a metal layer on the second high-k gate dielectric layer.. ... Semiconductor Manufacturing International Corp

05/03/18 / #20180122678

Wafer alignment method and apparatus for overlay measurement

A substrate alignment device includes a plurality of state detection units, each of which is configured to move from a standby position to a detection position for detecting a positional state of a substrate and return back from the detection position back to the standby position, and a multidimensional robot arm configured to receive and support the substrate, transfer the substrate to a substrate detection site, and adjust the substrate in at least one orientation or position according to the detected positional state of the substrate to position the substrate to a target position for overlay mark measurements.. . ... Semiconductor Manufacturing International Corp

05/03/18 / #20180122669

Overlay measurement method and apparatus

An apparatus for detecting a mark having first and second stripe groups on a substrate includes a detection module moveable over a surface of the substrate. The detection module includes a detection unit and a positioning unit configured to align the detection unit with the mark. ... Semiconductor Manufacturing International Corp

05/03/18 / #20180122668

Apparatus and method for detecting overlay mark with bright and dark fields

An apparatus for detecting a mark on a substrate is provided. The mark has a first stripe group and a second stripe group disposed in parallel to each other. ... Semiconductor Manufacturing International Corp

05/03/18 / #20180122636

Manufacturing method of semiconductor device

The present disclosure is directed to a manufacturing method of a semiconductor device. The manufacturing method includes: providing an initial structure including a to-be-etched material layer and a mask structure located on the to-be-etched material layer, the mask structure including a hydrophilic first mask layer; patterning the mask structure to form a patterned mask structure; etching the to-be-etched material layer by using the patterned mask structure as a mask; performing hydrophobic processing on the first mask layer; and performing cleaning processing. ... Semiconductor Manufacturing International Corp

05/03/18 / #20180122437

Memory decoding system

A memory decoding system includes a memory decoding reference current module. The memory decoding reference current module includes: a first reference current unit connected to one end of a second reference bit line; a second reference current unit connected to one end of a first reference bit line; a third reference current unit connected to one end of a third reference bit line; a first reference nmos transistor, a source of which is connected to the second reference bit line; a second reference nmos transistor, a source of which is connected to a drain of the first reference nmos transistor; and a gate of the first reference nmos transistor and a gate of the second nmos transistor are connected to a logic high level.. ... Semiconductor Manufacturing International Corp

05/03/18 / #20180121345

Structures of bottom select transistor for embedding 3d-nand in beol and methods

A flash memory device includes a substrate, an electrode layer on a portion of the substrate, the electrode layer being a work function adjusting layer or a metal silicide layer, and a memory cell. The memory cell includes a channel structure on the electrode layer and having, from the inside to the outside in this order, a channel layer in contact with the electrode layer, a tunneling insulator layer surrounding the channel layer, a charge trapping layer surrounding the tunneling insulator layer, and a barrier layer surrounding the charge trapping layer, and a plurality of gate structures surrounding the channel structure along an axial direction of the channel structure. ... Semiconductor Manufacturing International Corp

04/19/18 / #20180108745

Semiconductor structures and fabrication methods thereof

A method for fabricating a semiconductor structure includes providing a base structure including an nmos region, forming an interlayer dielectric layer on the base structure with a plurality of openings formed in the nmos region through the interlayer dielectric layer, forming a high-k dielectric layer on a bottom and sidewall surfaces of each opening of the nmos region, forming an n-type work function layer on the high-k dielectric layer in each opening of the nmos region, forming a diffusion barrier layer on the n-type work function layer, performing a hydrogenation process on the diffusion barrier layer, and forming a metal gate electrode on the diffusion barrier layer to fill up each opening in the nmos region. The disclosed method and semiconductor structure improve the ability of the barrier layer to protect the n-type work function layer, and thus improve the electrical performance of the semiconductor device.. ... Semiconductor Manufacturing International Corp

04/19/18 / #20180108698

Cmos image sensor

A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate having a front side and a back side and a pixel region having a plurality of pixels in the front side, each pixel including a sensor element, forming a metal reflective layer in the front side of the substrate and on the pixel region, thinning the back side of the substrate, doping the thinned back side of the substrate with a dopant, and laser annealing the doped back side of the substrate. The sensor element is configured to receive incident light to the thinned back side of the semiconductor substrate. ... Semiconductor Manufacturing International Corp

04/19/18 / #20180108667

Flash memory device and manufacture thereof

A flash memory device and its manufacturing method, which is related to semiconductor techniques. The flash memory device comprises: a substrate; and a memory unit on the substrate, comprising: a channel structure on the substrate, wherein the channel structure comprise, in an order from inner to outer of the channel structure, a channel layer, an insulation layer wrapped around the channel layer, and a charge capture layer wrapped around the insulation layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure, wherein there exist cavities between neighboring gate structures; a support structure supporting the gate structures; and a plurality of gate contact components each contacting a gate structure. ... Semiconductor Manufacturing International Corp

04/19/18 / #20180108575

Finfet device and fabrication method thereof

A method for fabricating a fin-fet device includes forming fin structures on a substrate and an isolation structure to cover a portion of sidewall surfaces of the fin structures, forming gate structures to cover a portion of sidewall and top surfaces of the fin structures, forming doped source/drain regions in the fin structures, forming a metal layer on the doped source/drain regions and the gate structures, performing a reaction annealing process to convert the metal layer formed on the doped source/drain regions into a metal contact layer and then removing the unreacted metal layer, forming a dielectric layer on the metal contact layer and the gate structures with a top surface higher than the top surfaces of the gate structures, forming a plurality of vias through the dielectric layer above the metal contact layer, and forming a plurality of conductive plugs by filling the vias.. . ... Semiconductor Manufacturing International Corp

04/19/18 / #20180108574

Finfet device and fabrication method thereof

A finfet device and fabrication method thereof is provided. The fabrication method include: providing a semiconductor substrate with a fin protruding from the semiconductor substrate, and a gate structure across a length portion of the fin and covering a portion of the fin; etching a partial thickness of the fin on both sides of the gate structure to form grooves; forming a doped layer in a bottom and sidewalls of the grooves; annealing the doped layer to allow the doping ions to diffuse into the fin and to form a lightly doped source/drain region; removing the doped layer after the annealing; and forming epitaxial layers to fill up the grooves.. ... Semiconductor Manufacturing International Corp

04/19/18 / #20180108573

Fin-fet devices and fabrication methods thereof

A method for fabricating a fin-fet device includes providing a base structure and a plurality of fin structures protruding from the base structure. Along a direction perpendicular to the surface of the base structure and from the bottom to the top of each fin structure, the width of the fin structure perpendicular to the length direction of the fin structure decreases. ... Semiconductor Manufacturing International Corp

04/19/18 / #20180108569

Semiconductor apparatus and manufacturing method

A semiconductor apparatus and its manufacturing method are presented. The method entails providing a substrate structure comprising a substrate, one or more fins positioned along a first direction on the substrate, and a separation region surrounding the fins. ... Semiconductor Manufacturing International Corp

04/12/18 / #20180102437

Fin-fet devices and fabrication methods thereof

A fin-fet device and its fabrication method are provided. The method for fabricating the fin-fet device includes forming a plurality of fin structures on a substrate, forming an isolation film on the substrate between neighboring fin structures, removing a portion of the isolation film to form an initial isolation layer with a top surface of the initial isolation layer lower than top surfaces of the fin structures, and implanting doping ions into the initial isolation layer. ... Semiconductor Manufacturing International Corp

04/12/18 / #20180102363

Semiconductor structure and fabrication method thereof

A semiconductor structure and a fabrication method are provided. A fabrication method includes providing a plurality of fins on a substrate including an nmos region and a pmos region adjacent to the nmos region; forming an n-type well in the pmos region and a p-type well in the nmos region of the substrate; forming a protective sidewall to cover an upper portion of a sidewall surface of each fin in each of the nmos region and pmos region and to expose a lower portion of the sidewall surface of each fin; removing a partial width of the lower portion of the fin using the protective sidewall as an etch mask; removing the protective sidewall; and forming an isolation structure at least by oxidizing the remaining lower portion of the fin and having a top surface lower than the neighboring upper portions of the fins.. ... Semiconductor Manufacturing International Corp

04/05/18 / #20180097082

Semiconductor device and manufacturing method therefor

The present disclosure relates to the technical field of semiconductor processes and discloses a semiconductor device and a manufacturing method therefor. The method includes: providing a substrate containing a first dielectric layer; forming a lower gate material layer on the first dielectric layer; patterning the lower gate material layer to form gate lines; depositing a second dielectric layer to cover the gate lines; planarizing the second dielectric layer; forming an insulating buffer material layer; patterning the insulating buffer material layer to form a patterned insulating buffer layer containing multiple separate portions, each separate portion extending to intersect one or more gate lines; selectively growing a graphene layer on the patterned insulating buffer layer; forming a third dielectric layer to cover the graphene layer and the second dielectric layer; and forming an upper gate electrode layer on the third dielectric layer. ... Semiconductor Manufacturing International Corp

04/05/18 / #20180097068

Semiconductor device and manufacturing method thereof

The present disclosure relates to the technical field of semiconductor technologies and discloses a semiconductor device and a manufacturing method therefor. The method includes forming a growth substrate by providing a substrate structure containing a sacrificial substrate, a first dielectric layer on the sacrificial substrate, and a plurality of recesses formed through the first dielectric layer and into the sacrificial substrate, by forming a buffer layer covering exposes surfaces of the plurality of recesses, by selectively growing a graphene layer on the buffer layer, and by filling the plurality of recesses with a second dielectric layer. ... Semiconductor Manufacturing International Corp

04/05/18 / #20180097067

Semiconductor device and manufacturing method therefor

The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a substrate structure including a substrate and a first material layer on the substrate, wherein a recess is formed in the substrate and the first material layer includes a nanowire; forming a base layer on the substrate structure; selectively growing a graphene layer on the base layer; forming a second dielectric layer on the graphene layer; forming an electrode material layer on the substrate structure to cover the second dielectric layer; defining an active region; and forming a gate by etching at least a portion of a stack layer to at least the second dielectric layer so as to form a gate structure surrounding an intermediate portion of the nanowire, where the gate structure includes a portion of the electrode material layer and the second dielectric layer. ... Semiconductor Manufacturing International Corp

04/05/18 / #20180097060

Top-down method for fabricating nanowire device

A method for manufacturing a semiconductor device includes providing a semiconductor substrate, performing an etch process on the semiconductor substrate to form a fin and a trench on opposite sides of the fin, forming an etch guide layer filling the trench, performing an etch process on the etch guide layer to expose a first portion of the fin, and selectively etching the exposed first portion of the fin to remove a portion of the exposed portion of the fin adjacent to an upper first surface of the etch guide layer to form a first nanowire. The method further includes repeating the etch process and the selectively etching process to sequentially form second and third nanowires, and forming a gate structure surrounding the nanowire. ... Semiconductor Manufacturing International Corp

04/05/18 / #20180096999

Semiconductor structures and fabrication methods thereof

A method for fabricating a semiconductor structure includes providing a substrate including a device region, an isolation region, and a transition region between the device region and the isolation region, forming a plurality of fin structures on the device region of the substrate, forming a plurality of dummy fin structures on the transition region of the substrate, and forming an isolation structure on the device region, the isolation region, and the transition region of the substrate. The isolation structure further covers a portion of sidewall surfaces of the fin structures and the dummy fin structures. ... Semiconductor Manufacturing International Corp

04/05/18 / #20180096958

Method for improving wire bonding strength of an image sensor

A method for manufacturing a bond pad structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, and a passivation layer on the first metal layer, the passivation layer having an opening extending to the first metal layer; and filling the opening of the passivation layer with a second metal layer. The bond pad structure has a significantly increased thickness compared with the thickness of the exposed portion of the first metal layer in the opening, thereby ensuring wire bonding reliability and yield.. ... Semiconductor Manufacturing International Corp

04/05/18 / #20180096857

Method for fluorocarbon film used as middle stop layer for porous low k film

A method for manufacturing an interconnect structure includes providing a metal interconnect layer, forming a first dielectric layer on the metal interconnect layer, forming a fluorocarbon layer on the first dielectric layer, forming a second dielectric layer on the fluorocarbon layer, and performing an etch process on the second dielectric layer using the fluorocarbon layer as an etch stop mask to form an opening. The interconnect structure thus formed has an improved uniformity and reduced parasitic capacitance.. ... Semiconductor Manufacturing International Corp

04/05/18 / #20180096712

Bandgap with system sleep mode

A method operates a bandgap voltage reference circuit that includes a bias circuit for receiving a feedback signal and outputting a bias signal, an amplifier for receiving the bias signal and outputting a first reference signal as the feedback signal, an output circuit for receiving the first reference signal and outputting a second reference signal, and an output switch for outputting the second reference signal as an output signal. The method includes, after powering up the bandgap voltage reference circuit, determining whether the output signal is stable, when the output signal is stable, turning off the output switch; turning off the bias circuit; and turning off the output circuit. ... Semiconductor Manufacturing International Corp

04/05/18 / #20180095122

Method for testing inter-layer connections

A method for testing inter-layer connections is presented. The method entails: providing a test semiconductor device, wherein the test semiconductor device comprises a two-port resistance network; measuring base input resistances on at least one of the first and the second ports of the test semiconductor device for different numbers of resistance links in a defect-free circumstance; obtaining a correspondence relationship between the number of resistance links and the base input resistances; measuring actual input resistances on at least one of the first and the second ports of the test semiconductor device; and determining a position of the resistance link corresponding to the actual input resistances based on the correspondence relationship, wherein the position of the resistance link determines the location of a defect. ... Semiconductor Manufacturing International Corp

03/22/18 / #20180080883

Defect inspection method and apparatus using micro lens matrix

A substrate surface defect detection device includes an optical waveguide for receiving first light and directing the received first light to a surface of a to be tested substrate, the optical waveguide having a first surface facing toward the substrate and a second surface facing away from the substrate, a microlens array disposed on the second surface of the optical waveguide, the microlens array including a plurality of microlenses arranged in an array for receiving second light from the surface of the to be tested substrate and converging the received second light to converged light, and an imaging component for receiving the converged light from the at least one microlens array for optical imaging. The substrate surface defect detection device requires significantly less time than conventional substrate surface defect detection devices.. ... Semiconductor Manufacturing International Corp

03/22/18 / #20180080880

Optical scattering measurement method and apparatus using micro lens matrix

An apparatus for detecting a defect on a surface of a substrate includes an optical microlens array disposed adjacent to the substrate and including an array of microlenses configured to direct light incident on a second surface of the optical microlens array to exit a first surface of the optical microlens array opposite the second surface for irradiating the surface of the substrate and converge light emitted from the irradiated surface of the substrate, and an imaging member including a plurality of imaging units configured to receive the converged light of the optical microlens array. Each of the imaging units corresponds to a microlens of the optical microlens array and includes a plurality of pixels and a light transmission opening for transmitting a portion of the incident light. ... Semiconductor Manufacturing International Corp

03/22/18 / #20180079159

Method and apparatus for assembling multilayer microlens array elements

A method for assembling a microlens array assembly including a set of microlens array elements having at least two array elements having a first array element and a second array element includes adsorbing the first array element using a mobile platform, adsorbing the second array element using a fixture platform, coarsely aligning the second array element with the first array element based on edges of the second array element and edges of the first array element, finely aligning the second array element with the first array element based on an array pattern of the second array element and an array pattern of the first array element, and attaching the second array element to the first array element. The method enables assembling of multiple microlens array elements.. ... Semiconductor Manufacturing International Corp

03/15/18 / #20180076284

Semiconductor device, related manufacturing method, and related electronic device

A semiconductor device may include the following elements: a first doped portion; a second doped portion; an enclosing member, which encloses both the first doped portion and the second doped portion; a first barrier, which directly contacts the first doped portion; a second barrier, which directly contacts the second doped portion; a dielectric member, which is positioned between the first barrier and the second barrier and directly contacts each of the first barrier and the second barrier; a third barrier, which directly contacts the first doped portion; and a device component, wherein a portion of the device component is positioned between the dielectric member and the third barrier.. . ... Semiconductor Manufacturing International Corp

03/08/18 / #20180069122

Semiconductor device

The present disclosure provides a fabrication method for forming a semiconductor device, including: forming a substrate, the substrate including first fins, second fins, and a first trench located in the substrate between a first fin and an adjacent fin; forming a first mask layer on the substrate, the first fins, and the second fins; and removing portions of the first mask layer neighboring a first trench to expose a portion of a top surface of a first fin and a portion of a top surface of the adjacent second fin to form a first opening, a portion of the top surface of the first fin covered by a remaining portion of the first mask layer being a first fin device region, a portion of the top surface of the second fin covered by a remaining portion of the first mask layer being a second fin device region.. . ... Semiconductor Manufacturing International Corp

03/08/18 / #20180069093

Semiconductor device layout structure and manufacturing method thereof

A semiconductor device includes a semiconductor substrate, a trench isolator portion in the semiconductor substrate, a dummy gate on the semiconductor substrate, a first doped region between the trench isolator portion and the dummy gate in the semiconductor substrate, and a first connecting member electrically connected the dummy gate with the first doped region. With the dummy gate electrically connected to the first doped region, a transistor including the dummy gate is turned off, thereby preventing the occurrence of current leakage and improving the reliability of a memory device having the semiconductor device.. ... Semiconductor Manufacturing International Corp

03/08/18 / #20180068961

Protection circuit and integrated circuit

Protection circuit and integrated circuit are provided. A protection circuit includes a discharge passage, configured to perform an electro-static discharge and a controller configured to blow out the electric fuse after the discharge passage fulfills electro-static discharge. ... Semiconductor Manufacturing International Corp

03/08/18 / #20180068888

Method for reducing cracks in a step-shaped cavity

A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a substrate and a multilayer film having a step-shaped portion on the substrate; forming a protective layer covering the step-shaped portion of the multilayer film; forming a capping layer having a plurality of steps on the protective layer covering the semiconductor substrate; and removing at least one layer of the multilayer film to form a cavity that is defined by the capping layer and a remaining multilayer film that has the at least one layer removed. The thus formed semiconductor device does not have cracks in the steps of the capping layer when performing an etch process, thereby improving the performance of the semiconductor device.. ... Semiconductor Manufacturing International Corp

03/08/18 / #20180068880

Die sorting apparatus and die sorting method

A die sorting apparatus includes a fixing mechanism for fixing a wafer having a plurality of dies, a positioning mechanism including an indicator for selecting a die of the wafer using die coordinates, an ejection mechanism below the wafer for applying a force to the selected die, a moving mechanism mechanically coupled to the positioning mechanism and the ejection mechanism for aligning the positioning mechanism with the ejection mechanism according to the die coordinates. The ejection mechanism includes an ejection shaft, a pin driven by the ejection shaft to apply the force to the selected die, and a pin driving device for moving the pin up and down through the ejection shaft. ... Semiconductor Manufacturing International Corp

03/08/18 / #20180068866

Semiconductor device and fabrication method thereof

Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming a plurality of fins on a surface of the semiconductor substrate; forming an isolation flowable layer covering the plurality of fins over the semiconductor substrate; performing a first annealing process to turn the isolation flowable layer into an isolation film; and forming first well regions and second well regions in the fins and the semiconductor substrate. ... Semiconductor Manufacturing International Corp

03/08/18 / #20180068864

Method for preventing excessive etching of edges of an insulator layer

A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a first insulator layer on the first semiconductor layer, forming a patterned second semiconductor layer on the first insulator layer, the patterned second semiconductor layer having an actual thickness greater than a target thickness and exposing a portion of the first insulator layer; forming a second insulator layer as a spacer on the exposed portion of the first insulator layer, and performing an etching process on the patterned second semiconductor layer until the second semiconductor layer has the target thickness and concurrently removing the second insulator layer. The method can eliminate capillary etching of the spacer in a subsequent removal of the first insulator layer.. ... Semiconductor Manufacturing International Corp

03/01/18 / #20180061981

Laterally diffused metal-oxide-semiconductor devices and fabrication methods thereof

The present disclosure provides a laterally diffused metal-oxide-semiconductor (ldmos) device. The ldmos device includes a plurality of fin structures formed on a substrate including a first device region, a second device region, and an isolation region sandwiched between the two regions. ... Semiconductor Manufacturing International Corp

03/01/18 / #20180061846

Semiconductor device and fabrication method thereof

Semiconductor devices and fabrication methods thereof are provided. An exemplary semiconductor device includes at least one finfet device. ... Semiconductor Manufacturing International Corp

03/01/18 / #20180061830

Semiconductor structure and fabrication method thereof

Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first region, a second region and an isolation region between the first region and the second region; forming a plurality of first fins on the semiconductor substrate in the first region and a plurality of second fins on the semiconductor substrate in the second region; forming an isolation structure, covering portions of side surfaces of the first fins and the second fins and with a top surface below the top surfaces of the first fins and the second fins, over the semiconductor substrate; and forming an isolation layer over the isolation structure in the isolation region and with a top surface coplanar or above the top surfaces of the first fins and the second fins.. ... Semiconductor Manufacturing International Corp

03/01/18 / #20180061824

Electrostatic discharge protection structure and fabricating method thereof

An electrostatic discharge protection structure and a fabricating method thereof are provided. The electrostatic discharge protection structure comprises: a substrate; multiple fin portions arranged on the substrate; a gate structure on the substrate across the fin portions, and on a portion of top surfaces and sidewalls of the fin portions; a first groove in the substrate and overlapping with a first extension pattern of the fin portions; a first doped epitaxial layer filled within the first groove, and being used as a source; a second groove in the substrate and overlapping with a second extension pattern of the fin portions; and a second doped epitaxial layer filled within the second groove, and being used as a drain.. ... Semiconductor Manufacturing International Corp

03/01/18 / #20180061716

Semiconductor device and fabrication method thereof

Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming an isolation layer in the base substrate; forming dummy gate structures on the base substrate at two sides of the isolation layer; forming an additional gate structure on the isolation layer and a first protective layer on surfaces of the additional gate structure and the dummy gate structures; forming an interlayer dielectric layer covering side surfaces of the dummy gate structures, the additional gate structure and the first protective layer over the base substrate; removing a portion of the first protective layer over the additional gate structure; forming a second protective layer on the additional gate structure; removing portions of the first protective layer over the dummy gate structures using the second protective layer as a mask; and removing the dummy gate structures to form openings in the interlayer dielectric layer.. ... Semiconductor Manufacturing International Corp

03/01/18 / #20180061714

Semiconductor structure and fabrication method thereof

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes forming a substrate including a plurality of initial fins, and forming an isolation layer on the substrate between the adjacent initial fins. ... Semiconductor Manufacturing International Corp

03/01/18 / #20180061502

Memory array, and method for reading, programming and erasing memory array

Memory arrays and reading, programming and erasing methods of the memory arrays are provided. An exemplary memory array includes a plurality of memory columns. ... Semiconductor Manufacturing International Corp

03/01/18 / #20180059533

Method for correcting target patterns and mask having corrected target patterns

Methods for correcting target patterns and masks having corrected target patterns are provided. An exemplary correction method includes dividing contours of target patterns into fragments; performing an optical proximity correction to obtain mask patterns; obtaining simulated exposure patterns; detecting the simulated exposure patterns to find out existence of at least one weak point; determining a correction window in the target patterns; comparing the target patterns in the correction window with the simulated exposure patterns to obtain a position error of each fragment; calculating an effect value of a correction value of each fragment in the correction window on position errors of all fragments in the correction window; determining the correction value of each fragment according to the effect value of the correction value in the correction window on position errors of all fragments and the position error of each fragment; and obtaining corrected target patterns using the correction value.. ... Semiconductor Manufacturing International Corp

02/15/18 / #20180047831

Semiconductor structure and fabrication method thereof

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a plurality of dummy gates on a substrate, a capping layer on each dummy gate, and a dielectric layer over the substrate, wherein the dielectric layer has a top surface above each dummy gate. ... Semiconductor Manufacturing International Corp

02/15/18 / #20180047829

Semiconductor structure and fabrication method thereof

The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a substrate having a first region and a second region; forming a trench in the substrate in the first region; forming a compensation doping region in a side surface of the trench adjacent to the second region; forming an isolation structure in the trench; forming a well region in the substrate in the second region; forming a drift region in the substrate in the first region; forming a gate structure over the substrate in a boundary region between the first region and the second region, and covering a portion of the isolation structure; and forming a source region in the well region at one side of the gate structure and a drain region in the drift region at another side of the gate structure.. ... Semiconductor Manufacturing International Corp

02/15/18 / #20180047724

Integrated semiconductor device and manufacturing method therefor

An integrated device includes a field effect transistor formed within and upon, an active region of a substrate and a resistor formed on an isolation region of the substrate. The field effect transistor includes a gate stacked structure having respective portions of a dielectric layer, a first conductive layer and a second conductive layer arranged in order from bottom to top. ... Semiconductor Manufacturing International Corp

02/15/18 / #20180047665

Semiconductor structure and fabrication method thereof

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate including a device region and a peripheral region. ... Semiconductor Manufacturing International Corp

02/15/18 / #20180047638

Semiconductor structures and fabrication methods thereof

A method for fabricating a semiconductor structure includes forming a plurality of dummy gate structures on a substrate. Each dummy gate structure includes a gate dielectric layer, a dummy gate electrode, and two sidewall spacers. ... Semiconductor Manufacturing International Corp

02/15/18 / #20180047632

Semiconductor structure and fabrication method thereof

Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate; forming gate structures over the base substrate; forming source/drain doping regions in the base substrate at two sides of each of the gate structures; forming an interlayer dielectric layer over the base substrate and the source/drain doping regions; forming a mask layer having a plurality of first openings there-through and over the interlayer dielectric layer, the first opening having a first length; performing a surface treatment process to remove portions of the mask layer from the first openings and to increase the first length of the first openings; forming contact through holes passing through the interlayer dielectric layer and exposing the source/drain doping regions using the mask layer with the first openings having the increased first length as an etching mask; and forming a contact via in each of the contact through holes.. ... Semiconductor Manufacturing International Corp

02/15/18 / #20180047631

Semiconductor structures and fabrication methods thereof

Semiconductor structure and fabrication method thereof are provided. An exemplary method includes providing a semiconductor substrate including a plurality of first fin structures, each having a first width, and a plurality of second fin structures, each having a second width greater than the first width. ... Semiconductor Manufacturing International Corp

02/15/18 / #20180047623

Semiconductor structure and fabrication method thereof

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes forming a base substrate, including a substrate, a gate structure on the substrate, source and drain doped regions in the substrate on both sides of the gate structure, and a dielectric layer on the substrate and on top of the gate structure. ... Semiconductor Manufacturing International Corp

02/15/18 / #20180047613

Semiconductor device and fabrication method thereof

A semiconductor device and a method for fabricating the semiconductor device are provided. The method includes providing a semiconductor substrate including a first region and a second region, and forming a plurality of fins on the semiconductor substrate in the first region and the second region. ... Semiconductor Manufacturing International Corp

02/08/18 / #20180040605

Electrostatic discharge protection device and method

. . An electrostatic discharge (esd) protection device includes a semiconductor substrate and a semiconductor fin located on the semiconductor substrate. The semiconductor fin includes a well region, a first doped region, and a second doped region. ... Semiconductor Manufacturing International Corp

02/08/18 / #20180040604

Diode design of finfet device

A method for manufacturing an electrostatic discharge (esd) protection device includes providing a semiconductor structure including a semiconductor substrate including a first region of a first conductivity type and a semiconductor fin on the semiconductor substrate; forming an electrode on the semiconductor fin; and performing a doping process on the semiconductor structure to forming a second region in the first region, the second region having a second conductivity type opposite the first conductivity type to form a pn junction in the semiconductor substrate. Since the pn junction is formed in the semiconductor substrate, it has a relatively large area to prevent local hot spots from occurring when a current flows through the esd protection device, thereby reducing performance degradation of a semiconductor device.. ... Semiconductor Manufacturing International Corp

02/08/18 / #20180038742

Method and device for temperature measurement of finfet devices

A semiconductor structure includes a semiconductor device that includes an active region having a semiconductor fin and a gate structure across the semiconductor fin. The gate structure includes a gate electrode. ... Semiconductor Manufacturing International Corp

02/01/18 / #20180033790

Increasing thickness of functional layer according to increasing recess area

A method of manufacturing a semiconductor device includes providing a substrate having first and second semiconductor fins, forming an insulating layer on the substrate having first and second recesses exposing a portion of the respective first and second semiconductor fins, forming a gate dielectric layer on the first and second recesses and the exposed portions of the first and second semiconductor fins, forming a first work function adjustment layer on the gate dielectric layer, forming a functional layer on the first function adjustment layer, and forming first and second gates on portions of the functional layer of the respective first and second semiconductor fins. The opening area of the first recess is larger than the opening area of the second recess. ... Semiconductor Manufacturing International Corp

02/01/18 / #20180033734

Method for fabricating cu interconnection using graphene

A method for manufacturing an interconnect structure includes providing a substrate structure comprising a substrate, a first dielectric layer on the substrate, and a metal interconnect line formed in the first dielectric layer and extending through to a surface of the substrate; removing a portion of the first dielectric layer on opposite sides of the metal interconnect line to expose a surface of the metal interconnect line and to form a recess; forming a graphene layer on the exposed surface of the metal interconnect line; and forming a second dielectric layer filling the recess and covering the graphene layer. The interconnect structure can prevent metal atoms of the metal interconnect line from diffusion into the first and second dielectric layers.. ... Semiconductor Manufacturing International Corp

02/01/18 / #20180033624

Semiconductor device, related manufacturing method, and related electronic device

A method for manufacturing a semiconductor device may include the following steps: preparing a first substrate; providing a first conductor, which is configured to electrically connect two elements associated with the first substrate; providing a second conductor on the first substrate, wherein the second conductor is electrically connected to the first conductor; preparing a second substrate; providing a third conductor, which is configured to electrically connect two elements associated with the second substrate; providing a fourth conductor on the second substrate, wherein the fourth conductor is electrically connected to the third conductor; providing a fifth conductor on the fourth conductor; and combining the fifth conductor with the second conductor through eutectic bonding.. . ... Semiconductor Manufacturing International Corp

01/11/18 / #20180012888

Semiconductor structure and fabrication method thereof

The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a plurality of fins on a semiconductor substrate; forming an anti-diffusion layer, containing anti-diffusion ions, in the fins; forming an anti-punch through layer, containing anti-punch through ions, in the fins, a top surface of the anti-punch through layer being below a top surface of the anti-diffusion layer, and the anti-diffusion layer preventing the anti-punch through ions from diffusing toward tops of the fins; and performing a thermal annealing process.. ... Semiconductor Manufacturing International Corp

01/11/18 / #20180012842

Semiconductor structures

A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate; forming an initial metal layer; simultaneously forming a plurality of discrete first metal layers and openings by etching the initial metal layer; forming a plurality of sidewalls covering the side surface of the first metal layers; and forming a plurality of second metal layers to fill the openings.. ... Semiconductor Manufacturing International Corp

01/11/18 / #20180012811

Semiconductor device and fabrication method thereof

Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes forming an interlayer dielectric layer on a base substrate; forming a plurality of first openings and second openings in the interlayer dielectric layer, one first opening connecting to a second opening, the one first opening being between the second opening and the base substrate; forming a high-k gate dielectric layer on side and bottom surfaces of the first openings and on side surfaces of the second openings; forming a cap layer, containing oxygen ions, on the high-k gate dielectric layer; forming an amorphous silicon layer on the cap layer at least on the bottoms of the first openings; performing a thermal annealing process on the amorphous silicon layer, the cap layer and the high-k dielectric; removing the amorphous silicon layer; and forming a metal layer, in the first openings and the second openings.. ... Semiconductor Manufacturing International Corp

01/11/18 / #20180012810

Semiconductor structures and fabrication methods thereof

A method for fabricating a semiconductor structure includes providing a base structure including a substrate, a dielectric layer formed on the substrate, a plurality of first openings formed in the dielectric layer in a first transistor region, and a plurality of second openings formed in the dielectric layer in a second transistor region. The method also includes forming a first work function layer an the dielectric layer covering bottom and sidewall surfaces of the first and the second openings, forming a first sacrificial layer in each first opening and each second opening with a top surface lower than the top surface of the dielectric layer, removing a portion of the first work function layer exposed by the first sacrificial layer, removing the first work function layer formed in each first opening, and forming a second work function layer and a gate electrode in each first opening and each second opening.. ... Semiconductor Manufacturing International Corp

01/11/18 / #20180012797

Method for reducing via rc delay

A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, a dielectric layer on the substrate and covering the first metal layer, and an opening extending to the first metal layer; forming a first barrier layer on a bottom and sidewalls of the opening with a first substrate bias; forming a second barrier layer on the first barrier layer with a second substrate bias, the second substrate bias being greater than the first substrate bias, the first and second barrier layers forming collectively a barrier layer; removing a portion of the barrier layer on the bottom and on the sidewalls of the opening by bombarding the barrier layer with a plasma with a vertical substrate bias; and forming a second metal layer filling the opening.. . ... Semiconductor Manufacturing International Corp

01/11/18 / #20180012765

Semiconductor device, related manufacturing method, and related electronic device

A semiconductor device may include the following elements: a first doped region; a second doped region, which contacts the first doped region; a third doped region, which contacts the first doped region; a first dielectric layer, which contacts the above-mentioned doped regions; a first gate member, which is conductive and comprises a first gate portion, a second gate portion, and a third gate portion, wherein the first gate portion contacts the first dielectric layer, wherein the second gate portion is positioned between the first gate portion and the third gate portion, and wherein a width of the second portion is unequal to a width of the third gate portion; a doped portion, which is positioned between the third gate portion and the third doped region; a second gate member; and a second dielectric layer, which is positioned between the third gate portion and the second gate member.. . ... Semiconductor Manufacturing International Corp

01/11/18 / #20180012664

Non-volatile memories and data reading methods thereof

A non-volatile memory (nvm) includes at least one memory unit region, each including a memory array and having first memory cells in the odd columns and second memory cells in the even columns. Corresponding to each memory unit region, the nvm includes a multiplexer including first bit line decoders and second bit line decoders, a comparator circuit including a first input terminal and a second input terminal, and a bias generation circuit generating a bias voltage. ... Semiconductor Manufacturing International Corp

01/04/18 / #20180006169

Method for fabricating nanopillar solar cell using graphene

. . A method of manufacturing a semiconductor device includes providing a substrate structure. The substrate structure includes a conductive layer and a plurality of nanopillars spaced apart from each other overlying the conductive layer. ... Semiconductor Manufacturing International Corp

01/04/18 / #20180006162

Finfet varactor

A varactor transistor includes a semiconductor fin having a first conductivity type, a plurality of gate structures separated from each other and surrounding a portion of the semiconductor fin. The plurality of gates structures include a dummy gate structure on an edge of the semiconductor fin, and a first gate structure spaced apart from the dummy gate structure. ... Semiconductor Manufacturing International Corp

01/04/18 / #20180006148

Ldmos transistor and fabrication method thereof

Lateral double-diffused mosfet transistor and fabrication method thereof are provided. A shallow trench isolation structure is formed in a semiconductor substrate. ... Semiconductor Manufacturing International Corp

01/04/18 / #20180006135

Epi integrality on source/drain region of finfet

A method for manufacturing a semiconductor device includes providing a substrate structure including a semiconductor fin on a substrate, and a trench isolation structure surrounding the fin and having an upper surface flush with an upper surface of the fin and including first and second trench isolation portions on opposite sides of the fin along the fin longitudinal direction, and third and fourth trench isolation portions on distal ends of the fin along a second direction intersecting the longitudinal direction; forming a patterned first hardmask layer having an opening exposing an upper surface of the third and fourth trench isolation portions; and forming a first insulator layer filling the opening to form an insulating portion including a portion of the first insulator layer in the opening and a portion of the trench isolation structure below the portion of the first insulator layer in the opening.. . ... Semiconductor Manufacturing International Corp

01/04/18 / #20180006127

Mos-varactor design to improve tuning efficiency

A gate stack structure for a mos varactor includes a substrate including a channel region, a high-k dielectric layer on the channel region of the substrate, a p-type work function adjustment layer on the high-k dielectric layer, an n-type work function adjustment layer on the p-type work function adjustment layer, and a metal gate on the n-type work function adjustment layer. The p-type work function adjustment layer includes a first portion and a second portion laterally adjacent to each other, the first portion having a thickness greater than a thickness of the second portion. ... Semiconductor Manufacturing International Corp








ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009



###

This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Semiconductor Manufacturing International Corp in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Semiconductor Manufacturing International Corp with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

###