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Sk Hynix Inc patents


Recent patent applications related to Sk Hynix Inc. Sk Hynix Inc is listed as an Agent/Assignee. Note: Sk Hynix Inc may have other listings under different names/spellings. We're not affiliated with Sk Hynix Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Sk Hynix Inc-related inventors


 new patent  Operating method of memory system

An operating method of a memory system includes: reading a first data from a particular data group among a plurality of data groups included in a memory device; performing a first error correction code (ecc) decoding for the first data; when the first ecc decoding fails, reading a plurality of the remaining data other than the first data from the particular data group; performing a second ecc decoding for the plurality of the remaining data; when the second ecc decoding fails, identifying data, to which the second ecc decoding fails, among the plurality of the remaining data; obtaining first and second soft read values respectively corresponding to the first data, to which the first ecc decoding fails, and the second data, to which the second ecc decoding fails; determining reliability of the first and second data based on the first and second soft read values; and correcting the first data based on the reliability of the first and second data.. . ... Sk Hynix Inc

 new patent  Error correction code (ecc) decoders sharing logic operations, memory controllers including the error correction code decoders, and methods of decoding error correction codes

An error correction code (ecc) decoder includes a finite state machine (fsm) controller and a shared logic circuit. The fsm controller generates a first control signal and a second control signal each corresponding to a certain state. ... Sk Hynix Inc

 new patent  Nonvolatile storage circuit and semiconductor memory device including the same

A nonvolatile storage circuit may include a nonvolatile storage unit configured to include fuse set groups respectively including a plurality of fuse sets and a flag fuse; a rupture control unit configured to program an input address to the fuse sets in a first program mode, and to program a same input address to a specific fuse set among the plurality of fuse sets in a specific fuse set group among the fuse set groups and to program the flag fuse of the specific fuse set group in a second program mode; and a boot-up control unit configured to control the address programmed in the fuse sets to be outputted as fuse data, and to control the address programmed in the specific fuse set to be outputted as fuse data of remaining fuse sets among the plurality of fuse sets in the specific fuse set group.. . ... Sk Hynix Inc

 new patent  Nonvolatile memory device including multiple planes

A nonvolatile memory device includes bit lines arranged in a first direction over a substrate; a memory cell array disposed between the substrate and the bit lines, and including a plurality of planes which are arranged in a second direction perpendicular to the first direction; page buffer circuits disposed between the substrate and the memory cell array; contact pads disposed between the substrate and the memory cell array, the contact pads being suitable for electrically coupling the bit lines and the page buffer circuits; and routing lines disposed at the same layer as the contact pads, and extending in the second direction, wherein the contact pads are disposed to overlap with at least two lines which are arranged in the second direction, and the routing lines are formed in a bent pattern to pass between the contact pads which are disposed to overlap with different lines.. . ... Sk Hynix Inc

 new patent  Multi-level ferroelectric memory device and method of manufacturing the same

A ferroelectric memory device may include a semiconductor substrate, a plurality of ferroelectric layers, a source, a drain and a gate. The semiconductor substrate may have a recess. ... Sk Hynix Inc

 new patent  Multi-level ferroelectric memory device and method of manufacturing the same

A ferroelectric memory device may include a semiconductor substrate, a plurality of ferroelectric layers, a source, a drain and a gate. The semiconductor substrate may have a recess. ... Sk Hynix Inc

 new patent  Semiconductor device having buried gate structure and method for manufacturing the same, memory cell having the same and electronic device having the same

A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer.. . ... Sk Hynix Inc

 new patent  E-fuse circuit

An electrical fuse (e-fuse) circuit is disclosed, which relates to a technology for processing a failed part of the e-fuse circuit. The e-fuse circuit may be configured to detect failed data and or store a failed address.. ... Sk Hynix Inc

 new patent  Semiconductor devices

A semiconductor device may be provided. The semiconductor device may include an error scrub control circuit and or an active period signal generation circuit. ... Sk Hynix Inc

 new patent  Semiconductor device

Disclosed is a semiconductor device, including a memory cell array including a plurality of memory cells, a read circuit suitable for generating read data corresponding to a read current flowing in a first direction through a selected memory cell of the plurality of memory cells, a reverse read control circuit suitable for generating a reverse read control signal corresponding to the read data, and a reverse current generation circuit suitable for generating a reverse current flowing in a second direction through the selected memory cell in response to the reverse read control signal.. . ... Sk Hynix Inc

 new patent  Semiconductor device and operating method thereof

A semiconductor memory device may include a memory cell array. The semiconductor memory device may include a peripheral circuit coupled to the memory cell array through word lines. ... Sk Hynix Inc

 new patent  Address mapping method of memory system

Disclosed is an address mapping method of a memory system. The address mapping method may include grouping adjacent memory cells into multiple cubes, from a plurality of memory cells respectively located at intersections of a plurality of row lines and a plurality of column lines; allocating most significant bit (msb) n bits of a physical address for identifying the cubes; allocating least significant bit (lsb) m bits of the physical address for designating locations of memory cells included in each of the cubes, m and n being positive integers; storing information about a mapping between a logical address and the (m+n)-bit physical address in a mapping table; and when the logical address in response to an external request is received, translating the logical address to the physical address based on the mapping table.. ... Sk Hynix Inc

 new patent  Memory system and operating method of the same

An memory system includes a memory device that includes a first memory block and a super memory block including simultaneously controllable second memory blocks and a controller including a memory, and suitable for storing a data corresponding to a command in the memory, deciding a type of the command and a type of the data, and controlling the memory device to write the data in the first memory block or the super memory block based on the type of the command and the type of the data.. . ... Sk Hynix Inc

 new patent  Semiconductor device

A semiconductor device includes a write read control circuit for outputting a write enable signal which is enabled in response to a write command, and a test mode signal; and an error correction circuit suitable for performing a calculation operation of determining an error information of input data in response to the write enable signal and then outputting an internal parity signal including the error information, and outputting internal data by delaying the input data in response to the write enable signal.. . ... Sk Hynix Inc

07/12/18 / #20180196712

 new patent  Apparatuses and methods for correcting errors and memory controllers including the apparatuses for correcting errors

An error correction apparatus may be provided. The error correction apparatus may be configured to perform a scrambling operation before an error correction code (ecc) operation is performed.. ... Sk Hynix Inc

07/12/18 / #20180196621

 new patent  Memory module, memory system and operating method of memory system

An operating method of memory system may include: transmitting a write command from a memory controller to a memory module; transmitting write data corresponding to the write command from the memory controller to the memory module; generating compressed data by compressing the write data in the memory module; writing the compressed data to one or more memory devices in the memory module; and transmitting unused r memory capacity information on the memory module to the memory controller from the memory module.. . ... Sk Hynix Inc

07/12/18 / #20180196620

 new patent  Data storage device and operating method thereof

A data storage device includes a plurality of nonvolatile memory devices; and a controller suitable for determining a write sequence for the nonvolatile memory devices, based on respective write times of the nonvolatile memory devices, and transmitting write commands sequentially in an interleaving manner to the nonvolatile memory devices according to the write sequence.. . ... Sk Hynix Inc

07/12/18 / #20180196616

 new patent  Memory device and memory module

A memory device may be provided. The memory device may include a plurality of memory banks, an at least one spare bank. ... Sk Hynix Inc

07/12/18 / #20180196602

 new patent  Data storage device and data processing system including the same

A data storage device includes a controller suitable for updating a first pointer based on a command inputted to a first queue included in a host device, and updating a second pointer based on a command execution completion report inputted to a second queue included in the host device, wherein the controller determines whether it is in an idle state based on the first pointer and the second pointer.. . ... Sk Hynix Inc

07/12/18 / #20180196464

 new patent  Semiconductor device

A semiconductor device includes a detection signal generation circuit generating a detection signal by detecting a phase difference of an input signal and an internal clock, and generating delayed input signals by delaying the input signal. The semiconductor device further includes an output enable signal generation circuit outputting an output enable signal by selecting one of the delayed input signals in response to the detection signal and latching the selected one of the delayed input signals in synchronization with the internal clock. ... Sk Hynix Inc

07/05/18 / #20180191971

Analog-to-digital converter and analog-to-digital conversion method

An analog-to-digital conversion method may include: generating an initial comparison signal by storing adjacent pixel signals and comparing the adjacent pixel signals, and generating a first control signal based on the generated initial comparison signal; generating a reference comparison signal by comparing the adjacent pixel signals based on the reference signal and a ramp-up signal switched according to the generated first control signal, and determining a ramping direction according to the generated reference comparison signal and generating a second control signal; and performing data conversion by selecting any one of the ramp-up signal and a ramp-down signal according to the generated second control signal, and by comparing the selected ramp signal with a ‘difference value between the adjacent pixel signals’.. . ... Sk Hynix Inc

07/05/18 / #20180191373

Error correction method of data storage device

An error correction code processing method includes performing a first encoding operation for a data group of a first direction; performing a second encoding operation for a data group of a second direction, wherein the data group of the first direction shares one or more data with the data group of the second direction; performing a first decoding operation of correcting an error included in the data group of the first direction; and performing a second decoding operation of correcting an error included in the data group of the second direction when the first decoding operation fails.. . ... Sk Hynix Inc

07/05/18 / #20180190498

Memory device and method of operating the same

Provided herein may be a memory device and a method of operating the same. The memory device may include a memory block including a plurality of pages, and peripheral circuits configured to sequentially program the pages. ... Sk Hynix Inc

07/05/18 / #20180190366

Semiconductor memory device and operating method thereof

A semiconductor memory device may include a memory core unit including a plurality of memory cells suitable for storing data, an error correction code (ecc) control unit suitable for detecting an error of the data to output a flag signal corresponding to a result of detection of the error, and an address control unit suitable for adjusting a refresh interval of at least one memory cell that stores data in which the error is detected, or repairing the memory cell among the memory cells, in response to the flag signal.. . ... Sk Hynix Inc

07/05/18 / #20180190358

Semiconductor memory device and method of operating the same

There may be provided a semiconductor memory device including a memory cell array, an erase count storage unit, and a control logic. The memory cell array may include a plurality of memory blocks. ... Sk Hynix Inc

07/05/18 / #20180190356

Semiconductor memory device and method of operating the same

Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a plurality of pages each including a plurality of memory cells, peripheral circuits configured to perform a program operation of a selected page among the plurality of pages and a control logic configured to control the peripheral circuits such that a main program operation is performed on the selected page and, when the main program operation is completed, a compensation program operation is performed on memory cells having lower threshold voltage retention characteristics compared to remaining memory cells, among the memory cells included in the selected page.. ... Sk Hynix Inc

07/05/18 / #20180190355

Semiconductor memory device and operating method thereof

A semiconductor memory device including a memory cell array including a plurality of memory blocks, a voltage generator applying operation voltages to a selected memory block, among the plurality of memory blocks, a control logic generating converted data by converting data bit sets respectively corresponding to at least one set of program states among a plurality of program states, during a program operation, and a read and write circuit temporarily storing the converted data and performing a program operation by controlling potential levels of bit lines of the memory cell array in accordance with stored converted data.. . ... Sk Hynix Inc

07/05/18 / #20180190354

Semiconductor device, operating method thereof and memory system

A method for operating a semiconductor device includes activating a first selection line coupled to a selected first memory string and deactivating a second selection line coupled to an unselected second memory string, applying a read voltage to a selected word line and a pass voltage to an unselected word line, and equalizing the selected word line and the unselected word line, wherein the second selection line is turned on during the equalizing of the selected and unselected word lines.. . ... Sk Hynix Inc

07/05/18 / #20180190330

Memory module capable of measuring temperature and system using the same

A memory module may be provided. The memory module may include a thermocouple and a temperature sensor. ... Sk Hynix Inc

07/05/18 / #20180189200

Memory system and operation method of the same

A memory system includes memory devices sharing a data bus and a control bus and controlling the memory devices through the control bus, wherein the memory devices have different latencies each other, and a controller transceiving a data with the memory devices through the data bus, wherein the controller may transceive a data with the memory devices during a time corresponding to a data burst length for a moment being the each latencies of the memory devices after transmitting same control signals to the memory devices.. . ... Sk Hynix Inc

07/05/18 / #20180189172

Data storage apparatus and operating method thereof

A data storage apparatus includes a nonvolatile memory device, a random-access memory including an address mapping table configured to store mapping information between a logical address received from a host apparatus and a physical address for the nonvolatile memory device, and a processor configured to generate a modified write logical address by changing a value of a specific bit among bits of a write logical address when a write request is received from the host apparatus, and store the modified write logical address in the address mapping table.. . ... Sk Hynix Inc

07/05/18 / #20180189153

Memory apparatus, memory module and semiconductor system capable of dynamic mirroring

A semiconductor system may include a host, a memory controller and a memory apparatus. The host may generate a mirror request when a program requiring a mirroring operation is executed. ... Sk Hynix Inc

07/05/18 / #20180189134

Semiconductor device

A semiconductor device includes a delay selection signal generation circuit, an internal read signal generation circuit, and an internal write signal generation circuit. The delay selection signal generation circuit generates a delay selection signal in response to an information code signal. ... Sk Hynix Inc

07/05/18 / #20180188962

Controller and operation method thereof

A controller includes a memory suitable for storing first data read from first memory blocks of a first super memory block included in a memory device; a rearranging unit suitable for rearranging the first data stored in the memory based on sequence-information of the first data stored in the memory; and a processor suitable for controlling the memory device to write the rearranged first data in a second super memory block of the memory device.. . ... Sk Hynix Inc

07/05/18 / #20180188958

Control logic, semiconductor memory device, and operating method

Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.. . ... Sk Hynix Inc

07/05/18 / #20180188957

Operating methods of nonvolatile memory device and data storage device including the same

A method for operating a data storage device including a nonvolatile memory device and a controller which controls the nonvolatile memory device includes the controller transmitting to the nonvolatile memory device one of a command, an address, seed data and data via a input/output line and first, second and third control signals via corresponding signal lines; and the nonvolatile memory device receiving any one of the transmitted command, the address, the seed data and the data depending on at least two of the first, second and third control signals.. . ... Sk Hynix Inc

06/28/18 / #20180183630

Receiving circuit, and semiconductor device and system configured to use the receiving circuit

A receiving circuit may include a decision feedback equalizer circuit and buffer. The buffer may be configured to receive an external signal and to generate an input signal. ... Sk Hynix Inc

06/28/18 / #20180183474

Symbol interference cancellation circuit and system including the same

A symbol interference cancellation circuit may include a ctle (continuous time linear equalizer) configured for cancelling a first post cursor component of an input signal according to a first weight application signal, and generating a pre-interference-cancelled signal; an interference cancellation circuit configured for cancelling second to fourth post cursor components of the pre-interference-cancelled signal according to second to fourth weight application signals, a sampling signal and output signals of shift registers, and generating an interference-cancelled signal; a sampling circuit configured for sampling the interference-cancelled signal based on a clock signal, and outputting the sampled interference-cancelled signal as the sampling signal; and the shift registers configured for shifting the sampling signal by a predetermined cycle of a clock bar signal which has a phase opposite to the clock signal, shifting the sampling signal by a predetermined cycle of the clock signal, and thereby providing shifted signals to the interference cancellation circuit.. . ... Sk Hynix Inc

06/28/18 / #20180183408

Common signal attenuation circuit and ramp signal generator using the same

A common signal attenuation circuit may include a sensing block suitable for sensing differential signals to generate sensed differential signals; a common signal generation block suitable for generating an common signal having a common voltage noise by combining the sensed differential signals; and an attenuation block suitable for adjusting the common voltage noise in the original common signal by combining the common signal having the adjusted common voltage noise to the differential signals.. . ... Sk Hynix Inc

06/28/18 / #20180183328

Charge pump circuit and voltage generating device including the same

A charge pump circuit may include: input units suitable for receiving a first input pulse signals and outputting second input pulse signals that are out of phase; an internal voltage generation unit suitable for generating an internal voltage by performing a voltage pumping operation in response to an external voltage and the second input pulse signals, and adjusting a well bias voltage at a power-up period and a normal operation period after the power-up period, in response to a switching control signal; and a switching control signal generation unit suitable for generating the switching control signal which is activated differently on the power-up period and the normal operation period.. . ... Sk Hynix Inc

06/28/18 / #20180182956

Electronic device and method for fabricating the same

An electronic device including a semiconductor memory. The semiconductor memory may include a variable resistance element. ... Sk Hynix Inc

06/28/18 / #20180182861

Semiconductor device and method for fabricating the same

A method for fabricating a semiconductor device includes: forming a semiconductor structure including a pattern; forming an epitaxial layer having a first dopant concentration in the pattern; forming in-situ an interface layer having a second dopant concentration higher than the first dopant concentration, over the epitaxial layer; forming a metal silicide layer over the interface layer; and forming a metal plug over the metal silicide layer.. . ... Sk Hynix Inc

06/28/18 / #20180182722

Semiconductor memory device including a dummy word line

A semiconductor memory device having dummy word lines is disclosed. In the semiconductor memory device, a number of dummy word lines are arranged at both ends of a cell mat.. ... Sk Hynix Inc

06/28/18 / #20180182468

Electronic device

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a plurality of first lines; a plurality of second lines; a plurality of memory cells disposed in respective intersection regions between the plurality of first lines and the plurality of second lines; a first test circuit configured to apply a stress pulse to a first selection line coupled to a defective memory cell among the plurality of memory cells during a first test period, in response to a first test control signal, the first selection line including any one of the plurality of first lines; and a control unit configured to generate the first test control signal based on a first test mode signal.. ... Sk Hynix Inc

06/28/18 / #20180182461

Semiconductor device and operating method thereof

A semiconductor device and or method of operating the same may be provided. The semiconductor device may include a pass circuit unit configured to connect global signal lines to signal lines to set voltage levels of the signal lines.. ... Sk Hynix Inc

06/28/18 / #20180182452

Memory system and operating method of memory system

A memory system may include: a memory device including a plurality of memory dies and suitable for performing, in the plurality of memory dies, command operations; and a controller suitable for: dividing sub-jobs of a command job corresponding to the command operations on a logical unit size basis; queuing the divided sub-jobs; and performing the queued sub-jobs to the memory dies with variable operating energy levels and operating clocks. The controller may monitor a status and a job load for at least one queued sub-job while performing the at least one queued sub-job to the memory dies, and interactively and dynamically adjusts an energy level and an operating clock for the at least one queued sub-job according to a result of the monitoring.. ... Sk Hynix Inc

06/28/18 / #20180182448

Sub word line driver of semiconductor memory device

A layout structure of a sub word line of a semiconductor memory device is disclosed. A sub word line driver of a semiconductor memory device includes: a plurality of first active regions arranged in a line shape in a first direction; a plurality of second active regions spaced apart from the plurality of first active regions a predetermined distance in a second direction, and arranged in a line shape in the first direction; a first main word line disposed over the first active regions, and formed in a diagonal direction in the first active regions; a second main word line disposed over the second active regions, and formed in a diagonal direction in the second active regions; and a pickup active region disposed between the first main word line and the second main word line.. ... Sk Hynix Inc

06/28/18 / #20180182447

Semiconductor memory apparatus

A semiconductor memory apparatus includes a driving voltage providing circuit suitable for selectively providing a first driving voltage, a second driving voltage, a third driving voltage, a ground voltage, and a precharge voltage to a first driving line and a second driving line in response to an active signal, a cell characteristic information signal, and a precharge signal. The semiconductor memory apparatus also includes a sense amplifier suitable for operating by being applied with voltages provided from the first and second driving lines.. ... Sk Hynix Inc

06/28/18 / #20180182445

Memory device, memory system including the same, and operation method thereof

A memory device may include first and second latch sections configured to respectively store a target address and a recent input address, a comparison unit configured to compare an input address with the target address and the recent input address respectively stored in the first and second latch sections, and output a resultant signal, a counting section configured to increase a count corresponding to the recent address stored in the second latch section in response to the resultant signal, and a control unit configured to check the count of the counting section and update the input address to the second latch section in response to the resultant signal.. . ... Sk Hynix Inc

06/28/18 / #20180182442

Semiconductor memory device

According to one embodiment, a semiconductor memory device comprises a first bank and a second bank. Each of the first bank and the second bank comprises a memory cell having a variable resistor element, a reference cell, a sense amplifier having a first input terminal electrically coupled to the memory cell and a second input terminal electrically coupled to the reference cell, and a first transistor electrically coupling the memory cell and the first input terminal of the sense amplifier. ... Sk Hynix Inc

06/28/18 / #20180182441

Semiconductor device and semiconductor system

Disclosed are a semiconductor device and a semiconductor system. The semiconductor device includes a command processing circuit for generating a write enable signal and a read enable signal in response to a command, a data strobe signal processing circuit for generating a data strobe signal in response to a clock and the read enable signal or for receiving the data strobe signal in response to the write enable signal and outputting a write data strobe signal, and a data processing circuit for converting analog data into digital data in response to the write data strobe signal and the write enable signal and converting the digital data into the analog data in response to the read enable signal.. ... Sk Hynix Inc

06/28/18 / #20180181856

Neuromorphic device including a synapse array with inverting circuits

A neuromorphic device may include: a pre-synaptic neuron; a synapse electrically connected with the pre-synaptic neuron through a row line; and a post-synaptic neuron electrically connected with the synapse through a column line. The post-synaptic neuron may include a first inverter, the first inverter comprising a first pull-up transistor and a first pull-down transistor, a body of the first pull-up transistor and a body of the first pull-down transistor being electrically connected with a first output node of the first inverter.. ... Sk Hynix Inc

06/28/18 / #20180181695

Electronic device and method for fabricating the same

An electronic device includes a semiconductor memory. The semiconductor memory includes first and second lower plugs, a first pad, a second pad, a first lower line, a second lower line, a first insulation pattern, a second insulation pattern, an upper plug, an upper line, and a plurality of variable resistance elements disposed at regions where the first and second lower lines overlap the upper line.. ... Sk Hynix Inc

06/28/18 / #20180181511

Dynamic termination circuit, semiconductor apparatus and system including the same

A semiconductor apparatus may include a receiver circuit and a termination circuit. The receiver circuit may be coupled to a receiving node, and configured to receive a signal transmitted through a signal transmission line. ... Sk Hynix Inc

06/28/18 / #20180181463

Semiconductor memory device including an error correction code circuit

A semiconductor memory device may be disclosed. The semiconductor memory device may include a first memory cell array region and a second memory cell array region, each of which includes memory cells. ... Sk Hynix Inc

06/28/18 / #20180181460

Data storage device and operatig method thereof

A data storage device includes a nonvolatile memory device including a first page group coupled to a first word line and a second page group coupled to a second word line, which is subsequent to the first word line in order of a write operation; and a controller suitable for, after an abnormal power-off during a write operation to the first page group, copying a first data stored in a weak page of the first page group to a stable page of the second page group when a first error correction operation to data stored in the first page group is a success.. . ... Sk Hynix Inc

06/28/18 / #20180181346

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of memory blocks which include pages; and a controller suitable for: performing command operations in response to commands, recording a count information of the respective memory blocks in a count information table according to the command operations, listing memory blocks satisfying a predetermined first condition in a source memory block candidate list by referring to the count information corresponding to a offset, and selecting as a source memory block a memory block satisfying a predetermined second condition among the memory blocks listed in the source memory block candidate list. The offset may indicate a difference between the count information of the respective memory blocks and an average of the count information.. ... Sk Hynix Inc

06/28/18 / #20180181326

Memory system and method for operating the same

A memory system includes: a memory device including a plurality of memory blocks; and a controller suitable for selecting one or more first memory blocks based on a predetermined condition among the plurality of the memory blocks in a booting section, and increasing a read reclaim count value of one or more second memory blocks among the one or more first memory blocks for which a number of failed bits of read data exceeds a predetermined threshold.. . ... Sk Hynix Inc

06/28/18 / #20180181325

Memory system and operating method thereof

A memory system includes a memory controller; a first memory module, the first memory module including first volatile memory devices; a second memory module, the second memory module including nonvolatile memory devices; a data bus for transmitting data between the memory controller and the first memory module and between the memory controller and the second memory module; a first control bus for transmitting first control signals between the memory controller and the first memory module and between the memory controller and the second memory module; a second control bus for transmitting second control signals between the memory controller and the first memory module; and a third control bus for transmitting third control signals between the memory controller and the second memory module, wherein, in a backup operation, the second control bus and the third control bus are electrically coupled.. . ... Sk Hynix Inc

06/28/18 / #20180181320

Controller and operation method thereof

A controller includes a calculation unit suitable for calculating a first criteria value, a second criteria value, and a valid page ratio of each of a plurality of first memory blocks included in a first memory block group a memory device of the memory system, a decision unit suitable for deciding as a copy candidate a first memory block having a valid page ratio equal to or smaller than the first criteria value; and a processor suitable for controlling the memory device to copy data of the copy candidate to a second memory block in the memory device when the valid page ratio of the copy candidate is equal to or smaller than the second criteria value.. . ... Sk Hynix Inc

06/28/18 / #20180181230

Sensing devices for sensing electrical characteristics

A sensing device may include an integrator configured to sense electrical characteristics of first and second nodes to generate an output voltage. A sensing device may include a switching portion configured to include a plurality of switches, wherein the plurality of switches operate to connect at least one of the plurality of switches to the first node and to connect the remaining switches of the plurality of switches to the second node during each of a plurality of successive switching cycles.. ... Sk Hynix Inc

06/21/18 / #20180175876

Analog-to-digital converters

An analog-to-digital converter adc may be provided. The adc may include a current driving circuit. ... Sk Hynix Inc

06/21/18 / #20180175844

Duty-cycle correction circuit and method

A duty-cycle correction circuit may include a delayed clock generation unit suitable for generating a plurality of delayed clocks by delaying a target clock by different delay values, an up/down signal generation unit suitable for selecting a delayed clock having a delay value corresponding to a first section of the target clock, and generating an up/down signal according to the lengths of a second section of the target clock and the first section of the selected delayed clock, a duty-cycle control code generation unit suitable for generating a duty-cycle control code in response to the up/down signal, a duty-cycle adjusting unit suitable for generating a duty-cycle correction clock by adjusting the duty-cycle of a source clock, and a control unit suitable for enabling the delayed clock generation unit during a duty-cycle correction period, and disabling the delayed clock generation unit during periods except for the duty-cycle correction period.. . ... Sk Hynix Inc

06/21/18 / #20180175053

Semiconductor device and method of manufacturing the same

Provided herein may be a semiconductor device and a method of manufacturing the same. The method of manufacturing the semiconductor device may include forming a tunnel insulating layer in a channel hole passing through a preliminary stack structure in which interlayer insulating layers and material layers are alternately stacked. ... Sk Hynix Inc

06/21/18 / #20180175042

Semiconductor device and method for fabricating the same

A method for fabricating a semiconductor device includes: forming a transistor in a semiconductor substrate; forming a capacitor including a hydrogen-containing top electrode over the transistor; and performing an annealing process for hydrogen passivation after the capacitor is formed.. . ... Sk Hynix Inc

06/21/18 / #20180175011

Semiconductor packages including heat transferring blocks and methods of manufacturing the same

A semiconductor package may be provided. The semiconductor package may include a first semiconductor chip and a second semiconductor chip disposed on an interconnection layer. ... Sk Hynix Inc

06/21/18 / #20180174905

Semiconductor device and method of manufacturing the semiconductor device

An interconnection structure of the semiconductor integrated circuit device may be provided. The interconnection structure may include a first conductive pattern, a second conductive pattern, a dielectric layer and a contact part. ... Sk Hynix Inc

06/21/18 / #20180174845

Semiconductor device having buried gate structure and method for fabricating the same

A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.. . ... Sk Hynix Inc

06/21/18 / #20180174664

Memory device

A memory device includes: a normal cell array; a parity cell array; a plurality of normal write drivers suitable for writing normal write data in the normal cell array; a plurality of parity write drivers suitable for writing parity write data corresponding to the normal write data, in the panty cell array; and an error injection circuit suitable for injecting error write data to at least one among the plurality of the normal write drivers and the plurality of the parity write drivers.. . ... Sk Hynix Inc

06/21/18 / #20180174662

Memory controller, memory system including the same and operating method thereof

A memory controller may include a detector configured for checking whether the number of bits having a first state among a plurality of bits constituting write data is less than a reference value. The memory controller may include an inverter configured for inverting/non-inverting the write data according to the check result of the detector. ... Sk Hynix Inc

06/21/18 / #20180174651

Electronic device

An electronic device including a semiconductor memory. The semiconductor memory may include a cell array including a plurality of resistive storage cells; a current code generation block suitable for generating a current code which has a value corresponding to an average value of current amounts of test currents respectively flowing through at least two first resistive storage cells among the plurality of resistive storage cells, in a test operation; and a sensing block suitable for comparing a read current flowing through a second resistive storage cell selected among the plurality of resistive storage cells with a reference current, and thereby sensing data of the second resistive storage cell, wherein the semiconductor memory is operable to adjust a current amount of at least one current flowing through the sensing block based on the value of the current code.. ... Sk Hynix Inc

06/21/18 / #20180174638

Semiconductor devices

A semiconductor device includes a counter control signal generation circuit and an access information generation circuit. The counter control signal generation circuit generates a count enablement signal, a reset signal and a count increment signal in response to a first row address selected as a target address and a second row address selected as a neighboring address. ... Sk Hynix Inc

06/21/18 / #20180174633

Semiconductor apparatus, semiconductor system, and training method

A semiconductor apparatus may be provided. The semiconductor apparatus may include a fine training circuit configured to generate a fine result signal based on a clock signal, a data strobe signal, and a command. ... Sk Hynix Inc

06/21/18 / #20180174632

Semiconductor device and semiconductor system

A semiconductor system includes a first semiconductor device and a first semiconductor device. The first semiconductor device outputs a clock, a chip selection signal and addresses. ... Sk Hynix Inc

06/21/18 / #20180174629

Memory system and method for operating the same

Provided herein may be a memory system and a method of operating the same. A semiconductor memory device may include a write protect pin mode setting unit configured to set, depending on a parameter value stored therein, a write protect pin of the semiconductor memory device as any one of an input pin and an output pin and a control logic configured to output, when the write protect pin serves as the output pin, internal state information of the semiconductor memory device to an external device.. ... Sk Hynix Inc

06/21/18 / #20180174628

Data storage device and operating method thereof

A data storage device includes a memory device suitable for storing and outputting data in synchronization with a strobe signal; and a controller suitable for delaying the strobe signal based on each of different test delay values, testing capture of the data by using a delayed strobe signal, and determining a delay value of the strobe signal based on a test result.. . ... Sk Hynix Inc

06/21/18 / #20180174045

Apparatus and method for recognizing information of neuromorphic device

A neuromorphic device according to various embodiments of the present disclosure includes a recognizing unit suitable for recognizing information based on a plurality of learned results to generate a plurality of recognition signals, a maximum value extracting unit suitable for respectively extracting values of the plurality of recognition signals and extracting a recognition signal having a maximum value among the plurality of recognition signals, and a control unit suitable for processing the information based on the to recognition signal having the maximum value.. . ... Sk Hynix Inc

06/21/18 / #20180174025

Apparatus and method for normalizing neural network device

A neural network device may include an input unit suitable for applying input signals to corresponding first lines, a calculating unit including memory elements cross-connected between the first lines and second lines, wherein the memory elements have respective weight values and generate product signals of input signals of corresponding first lines from among the plurality of first lines and weights to output the product signals to corresponding second lines from among the second lines, a drop-connect control unit including switches connected between the plurality of first lines and the plurality of memory elements, and suitable for randomly dropping a connection of an input signal applied to a corresponding memory element from among the plurality of memory elements, and an output unit connected to the plurality of second lines, and suitable for selectively activating signals of the plurality of second lines to apply the activated signals to the input unit and performing an output for the activated signals when the calculating unit performs generating of the product signals a set number of times.. . ... Sk Hynix Inc

06/21/18 / #20180173653

Electronic device

This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the pinned layer and the free layer, wherein the free layer may include a first magnetic layer; a second magnetic layer formed over the first magnetic layer; and a zirconium (zr)-containing material layer interposed between the first magnetic layer and the second magnetic layer.. ... Sk Hynix Inc

06/21/18 / #20180173650

Memory system and operating method thereof

A method for operating a memory system including a memory controller and a memory mudule, the method includes: by the memory controller, applying a read command to the memory module; by the memory module, determining whether the memory module is able to transfer the read data to the memory controller during a regulated section; by the memory module, notifying the memory controller by using a data strobe signal that the memory module is not able to transfer the read data to the memory controller during the regulated section; by the memory controller, applying a status check-out command to the memory module in response to the notification for checking out a status of the memory module; and by the memory module, transferring status information of the memory module to the memory controller in response to the status check-out command.. . ... Sk Hynix Inc

06/21/18 / #20180173462

Memory system and operation method thereof

Provided are a memory control device and a method. The memory control device may include a memory device, and a controller operatively coupled to the memory device. ... Sk Hynix Inc

06/21/18 / #20180173270

Semiconductor devices

A semiconductor device includes a phase comparison circuit, an output enablement signal generation circuit, and a data input/output (i/o) circuit. The phase comparison circuit compares a phase of a clock signal with a phase of a delay locked loop (dll) clock signal to generate a phase information signal. ... Sk Hynix Inc

06/21/18 / #20180172744

Capacitance sensing circuits

A capacitance sensing circuit includes a buffer circuit, a modulation circuit, and an integral circuit. The buffer circuit is coupled to an external capacitor through a touch-sensing pad, and includes a pull-up device and a pull-down device. ... Sk Hynix Inc

06/14/18 / #20180167574

Counting apparatus, analog-to-digital converter and image sensor including the same

A counting apparatus may include: a count control unit suitable for controlling a counting operation of a common value and a differential value of two pixel signals according to two neighboring output signals of a comparator unit; a counting unit suitable for counting a clock during a period corresponding to the common value and the differential value, according to control of the count control unit; and a memory unit suitable for storing count information from the counting unit and operation information from the count control unit.. . ... Sk Hynix Inc

06/14/18 / #20180166384

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate including a cell area, a first contact area, and a second contact area; a lower stacked structure extending over the second contact area from the cell area; an upper stacked structure extending over the first contact area from the cell area, the upper stacked structure leaving the second contact area open; n (n is a natural number of 2 or more) first group of stepped grooves penetrating at least one portion of the upper stacked structure in the first contact area; and m (m is a natural number equal to or smaller than n) second group of stepped grooves penetrating at least one portion of the lower stacked structure in the second contact area.. . ... Sk Hynix Inc

06/14/18 / #20180166152

Semiconductor device and semiconductor system including the same

A semiconductor device may include a repair address storage circuit, an address comparison circuit, and a word line selection circuit. The repair address storage circuit may store a first repair address and a second repair address. ... Sk Hynix Inc

06/14/18 / #20180166149

Semiconductor device and operating method thereof

A semiconductor device includes: a fuse set unit including a plurality of fuse sets, each fuse set including one or more address fuses and an enable fuse; a rupture control unit suitable for controlling the enable fuse of a selected fuse set to be programmed after the address fuses of the selected fuse set is programmed, during a program operation; a cell data verify unit suitable for repeatedly performing a verify and rupture operation on the selected fuse set during the program operation, determining whether read data from the selected fuse set is identical to target data corresponding to a rupture address through a final verify operation, and outputting fail information; and a fuse set control unit suitable for controlling the program operation to be performed on a different fuse set after the program operation on the selected fuse set is terminated, in response to the fail information.. . ... Sk Hynix Inc

06/14/18 / #20180166146

Semiconductor device and semiconductor system including the same

A semiconductor device may be provided. The semiconductor device may include a first oscillation signal generation circuit for generating a first oscillation signal. ... Sk Hynix Inc

06/14/18 / #20180166144

Semiconductor device, semiconductor system and operating method thereof

A semiconductor device includes an internal command generation circuit suitable for generating a first internal command, a second internal command, and a third internal command based on a command/address signal. The semiconductor device also includes a driving signal generation circuit suitable for enabling a fuse driving signal for reading fuse data from a nonvolatile memory circuit, where the fuse signal is enabled while the second internal command is inputted a predetermined number of times. ... Sk Hynix Inc

06/14/18 / #20180166119

Sub word line driver of semiconductor memory device

A layout structure of a sub word line driver for use in a semiconductor memory device may be disclosed. The sub word line driver may include a first active region through which first and second main word lines pass. ... Sk Hynix Inc

06/14/18 / #20180166117

Memroy device and operating method thereof

An operating method of a memory device including a plurality of memory cells may include: measuring data retention times of at least a portion of the plurality of memory cells; and optimizing a refresh operation on the plurality of memory cells using the measurement result.. . ... Sk Hynix Inc

06/14/18 / #20180166114

Electronic device

An electronic device including a semiconductor memory. The semiconductor memory includes a bit line; a source line; a plurality of resistive memory cells among which a selected memory cell forms a current path between the bit line and the source line; a read current supply unit configured to supply read current to the bit line in a read operation; a sense amplifier configured to generate read data in response to a voltage level of the bit line in the read operation; and a variable switch element configured to flow current from the source line to a ground terminal in the read operation, and be decreased in its resistance value as a voltage level of the source line is high.. ... Sk Hynix Inc

06/14/18 / #20180166112

Semiconductor device

A semiconductor device may be provided. The semiconductor device may operate in a 2n mode as well as a normal mode.. ... Sk Hynix Inc

06/14/18 / #20180166110

Semiconductor devices

A semiconductor device includes a flag signal generation circuit and a power-down signal generation circuit. The flag signal generation circuit generates a flag signal which is enabled in response to an operational frequency information signal. ... Sk Hynix Inc

06/14/18 / #20180166108

Semiconductor memory device, and signal line layout structure thereof

A memory device includes first and second memory blocks each including a memory cell array, a sub-word line drive region and a bit line sense amplifier region corresponding to the memory cell array, first and second data transmission lines disposed in the bit line sense amplifier region of each memory block, wherein the first and second data transmission lines extend on an identical row and transmit data of the memory cell array of the memory block, a row decoder configured to select one of the first and second memory blocks in response to a row address and enable a word line of the memory cell array included in the selected memory block, and a column decoder configured to generate, in response to a column address, first and second column select signals corresponding to the first and second data transmission lines of the bit line sense amplifier region.. . ... Sk Hynix Inc

06/14/18 / #20180166107

Semiconductor devices and semiconductor systems including the same

A semiconductor system includes a semiconductor device. The semiconductor device outputs a first group of data and a second group of data to a first group of input/output (i/o) lines and a second group of i/o lines in response to a command and an address. ... Sk Hynix Inc

06/14/18 / #20180166106

Nonvolatile memory device, nonvolatile memory system, and operating method of nonvolatile memory

A nonvolatile memory device may include a nonvolatile memory device may include a nonvolatile memory cell array; a peripheral circuit suitable for: activating an operation voltage in response to an operation voltage activation command, performing an operation to the nonvolatile memory cell array using the activated operation voltage in response to an operation command, and deactivating the activated operation voltage in response to an operation voltage deactivation command after the performing of the operation; and a control circuit suitable for controlling the peripheral circuit to execute an intervening operation during the activating of the operation voltage, the performing of the operation, and the deactivating of the activated operation voltage.. . ... Sk Hynix Inc

06/14/18 / #20180165187

Semiconductor system and method for operating the semiconductor system

A semiconductor system may include: a volatile memory device that stores an address mapping table including mapping information for a non-volatile memory device; and a control device suitable for reading one or more seed values from the volatile memory device before the address mapping table is stored, generating a plurality of random values based on the seed values, and initializing mapping information to the plurality of random values.. . ... Sk Hynix Inc

06/14/18 / #20180165151

Memory system and error correcting method of the same

An error correcting method of a memory system includes: reading data and an error correction code from a plurality of memory chips; correcting an error of the data based on the error correction code; determining whether or not a miscorrection occurs in the correcting of the error of the data; designating one memory chip among the plurality of the memory chips as a chip-killed memory chip when a miscorrection occurs; re-correcting the error of the data based on the error correction code in consideration of the designated chip-killed memory chip; and re-determining whether a miscorrection occurs in the re-correcting of the error of the data.. . ... Sk Hynix Inc

06/14/18 / #20180165149

Semiconductor device and operating method thereof

A semiconductor device includes: a control signal generation unit configured to generate a second control signal having a cycle shorter than a first control signal in response to a clock signal and the first control signal; a cyclic redundancy check (crc) control unit configured to perform a control to receive first and second data groups in response to the second control signal, and to output the first and second data groups with a time lag; and a crc operation unit configured to perform a cyclic redundancy check on each of the first and second data groups sequentially output through the crc control unit.. . ... Sk Hynix Inc

06/14/18 / #20180165098

Pipe latch circuit and data output circuit including the same

A pipe latch circuit includes: a pipe pipe latch control block suitable for controlling a plurality of pipe input signals and a plurality of pipe output signals to be activated sequentially or be divided into at least two groups and be activated sequentially by group, depending on a latency setting value, and outputting at least one pipe input signal and at least one pipe output signal; and a pipe latch block coupled between an input node and an output node, and suitable for storing data of the input node in response to the pipe input signal and outputting stored data to the output node in response to the pipe output signal.. . ... Sk Hynix Inc

06/14/18 / #20180165024

Semiconductor devices

A semiconductor device includes a group control circuit configured to generate a specified address and a control code in response to a row address and an active command, a comparison control signal generation circuit configured to generate a comparison control signal in response to the active command and a set code, and a target address generation circuit configured to output the specified address as a target address in response to the control code and the comparison control signal.. . ... Sk Hynix Inc

06/07/18 / #20180159543

Semiconductor device including dll and semiconductor system

A semiconductor system includes: a controller suitable for outputting an external clock signal and a command/address signal; and a semiconductor device suitable for selecting one of pre-stored code values of a delay control signal to output an initial value control signal according to the command/address signal, and outputting an internal clock signal by delaying the external clock signal by a predetermined time based on the delay control signal having an initial value that is set in response to the initial value control signal.. . ... Sk Hynix Inc

06/07/18 / #20180158868

Electronic device

An electronic device may be provided to include: first and second active regions arranged adjacent to each other in a second direction; a gate structure extended in the second direction; a first source region and a first drain region formed in the first active region; a second source region and a second drain region formed in the second active region; a source line contact formed over the first and second source regions and connected to the first and second source regions; a source line connected to the source line contact over the source line contact and extended in a first direction; first and second stacked structures formed over the first and second drain regions; and first and second bit lines formed over the first and second stacked structures, wherein the first and second bit lines are extended in the first direction.. . ... Sk Hynix Inc

06/07/18 / #20180158864

Image sensor including photodiodes having different sizes

Disclosed is an image sensor may include a pixel array having a central region and peripheral regions around the central region, one or more first unit pixels arranged in the peripheral regions. Each of the first unit pixels comprising a pair of left and right photodiodes. ... Sk Hynix Inc

06/07/18 / #20180158528

Control logic, semiconductor memory device, and method of operating the same

Provided herein may be a control logic, semiconductor memory device, method of operating the control logic, and or method of operating the semiconductor memory device. The semiconductor memory device may include a control logic. ... Sk Hynix Inc

06/07/18 / #20180158524

Non-volatile memory apparatus including voltage clamping circuit

A memory apparatus may be provided. The memory apparatus may include a global bit line configured to receive a drift current. ... Sk Hynix Inc

06/07/18 / #20180158523

Electronic device

An electronic device includes a semiconductor memory that includes: resistive storage cells; a reference resistance cell; a comparison block electrically coupled to the resistive storage cells and the reference resistance cell through first and second input terminals, to compare a cell current flowing through the first input terminal and a reference current flowing through the second input terminal; a first clamp part to control a maximum current amount of the cell current depending on a voltage level of a first node; a second clamp part to control a maximum current amount of the reference current depending on the voltage level of the first node; a voltage stabilization block to stabilize a voltage of the first node during a charging or a discharging period; and a switching part electrically coupled with the first node and the voltage stabilization block in the charging period or the discharging period.. . ... Sk Hynix Inc

06/07/18 / #20180158509

Semiconductor device

A semiconductor device includes an input clock generation circuit able to shift a write command in synchronization with a clock, and generating first and second input clocks. The semiconductor device also includes a write leveling control circuit able to divide a frequency of the clock in response to a write leveling control signal, and generating first to fourth write clocks. ... Sk Hynix Inc

06/07/18 / #20180158505

Semiconductor memory device and method for operating the same

Provided herein is a semiconductor memory device and a method for operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory blocks, each including dummy cells coupled to dummy word lines and normal memory cells coupled to normal word lines, a peripheral circuit configured to perform an erase operation on a memory block selected from among the plurality of memory blocks and control logic configured to control the peripheral circuit, during the erase operation, to apply a pre-program voltage pulse to the dummy word lines and the normal word lines, and to control application of dummy word line voltages to the dummy word lines based on erase-write (ew) cycling information while applying an erase voltage to a common source line of the selected memory block, wherein the ew cycling information indicates a number of erase-write cycles of the selected memory block.. ... Sk Hynix Inc

06/07/18 / #20180158493

Apparatus and method for controlling memory device

An apparatus for controlling a memory device may include: a table storing information of a plurality of read voltages; an error correction unit suitable for correcting an error of read data; and a processor functionally coupled to the rr table and the error correction unit. The processor selects a default read voltage among the plurality of read voltages from the table when a read fail for the memory device is recognized, sets a shift direction of the default read voltage based on the number of read cells of the memory device read by the default read voltage, and controls a read retry operation of the memory device based on at least one read voltage in the set shift direction in the table.. ... Sk Hynix Inc

06/07/18 / #20180157586

Data storage device and operating method thereof

A data storage device includes a memory device including a plurality of memory regions; and a controller suitable for selecting one or more candidate memory regions among the plurality of memory regions based on erase counts of the plurality of memory regions, determining an adjustment value based on the number of the candidate memory regions, selecting victim memory regions by the number that is equal to or less than the adjustment value among the candidate memory regions, and performing a garbage collection operation to the selected victim memory regions.. . ... Sk Hynix Inc

06/07/18 / #20180157546

Semiconductor memory device and method for operating the same

Provided herein may be a semiconductor memory device and a method for operating the same. The semiconductor memory device may include a memory cell array, a peripheral circuit, control logic, a status storage unit, and an operating characteristic checking unit. ... Sk Hynix Inc

06/07/18 / #20180157427

Memory system and operating method thereof

A memory system includes a wear-leveling module detecting a hot memory block among a plurality of memory blocks based on the number of times write operations are performed on each of the memory blocks, and moving data from the hot memory block to a spare memory block, a counting unit counting the number of data movement from the hot memory block to the spare memory block, on each of memory regions formed by grouping the plurality of memory blocks, and output data movement counts, a first detection unit selecting one from the plurality of memory regions based on the data movement count, and detecting a cold memory block among memory blocks included in the selected memory region, and a management unit moving data from the cold memory block to the hot memory block, and managing the cold memory block as the spare memory block.. . ... Sk Hynix Inc

06/07/18 / #20180157415

Apparatus and method for controlling memory device

A memory control apparatus may include a memory device including at least two memories respectively coupled to at least two channels, and a controller functionally coupled with the memory device. The controller may receive at least one command for performing a host task from a host, control the memory device to perform the host task with the memories based on the received command, and control the r memory device such that, when a trigger point of a device task for a memory of the memory device is recognized, a first memory of the memory device coupled with a corresponding channel performs the device task and a second memory of the memory device coupled with the other channel process the host task.. ... Sk Hynix Inc

05/31/18 / #20180152203

Error correction circuits and memory controllers including the same

An error correction circuit includes a syndrome calculator suitable for generating syndromes from an “n”-bit codeword for a single unit of time, an error location polynomial calculator suitable for generating error location polynomial coefficients based on the syndromes provided for the single unit of time, an error location calculator suitable for calculating error locations based on the error location polynomial coefficients for the single unit of time, and an error corrector suitable for correcting errors of the codeword based on the error locations for the single unit of time. The error correction circuit operates in a pipelining manner.. ... Sk Hynix Inc

05/31/18 / #20180152186

Internal voltage generation circuit

An internal voltage generation circuit includes a comparison circuit, a driving signal generation circuit and a driving circuit. The comparison circuit generates a comparison signal from an internal voltage in response to a reference voltage. ... Sk Hynix Inc

05/31/18 / #20180151509

Semiconductor apparatus and memory system

A semiconductor apparatus includes a chip id generation unit, a chip id transmission unit and a chip stack information generation unit. The chip id generation unit is configured to generate a chip id signal. ... Sk Hynix Inc

05/31/18 / #20180151251

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of memory blocks configured in a plurality of super memory blocks; and a controller suitable for detecting two or more bad super memory blocks each including at least one bad block among the super memory blocks, selecting at least one victim super memory block among the bad super memory blocks, and replacing the at least one bad block in each remaining bad super memory block with at least one normal block of the victim super memory block.. . ... Sk Hynix Inc

05/31/18 / #20180151250

Memory device

A memory device may include: a plurality of memory cells; a weak cell information storage unit suitable for storing a weak address and parity information corresponding to one or more weak cells having a shorter data retention time than a reference time, among the plurality of memory cells; an ecc (error correction code) circuit suitable for detecting and correcting an error bit of the one or more weak cells using the parity information; and a refresh control unit suitable for controlling the plurality of memory cells to be refreshed at a cycle equal to or more than the reference time.. . ... Sk Hynix Inc

05/31/18 / #20180151249

Data storage apparatus and operating method thereof

A data storage apparatus includes a nonvolatile memory device and a controller configured to determine whether or not one or more addresses of defective bit lines are included in an address of a write data to be written into the nonvolatile memory device or an address of a read data read from the nonvolatile memory device, and write the write data or read the read data by skipping the defective bit lines based on a determination result.. . ... Sk Hynix Inc

05/31/18 / #20180151230

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a voltage generator suitable for applying an erase voltage to a source line of at least one memory block selected from among the plurality of memory blocks during an erase operation, a read and write circuit suitable for applying an initial setting voltage, to bit lines of at least one memory block during the erase operation, and a control logic suitable for controlling the voltage generator and the read and write circuit to apply the initial setting voltage to the bit lines before applying the erase voltage to the source line.. . ... Sk Hynix Inc

05/31/18 / #20180151217

Semiconductor device

A semiconductor device may be provided. The semiconductor device may include a data input and output circuit (i/o) configured to selectively or simultaneously drive input and output lines according to a burst length and a location of a memory area selected by an address to allow the semiconductor device to receive or output data regardless of the burst length being changed.. ... Sk Hynix Inc

05/31/18 / #20180151216

Circuit for generating periodic signal and memory device including same

Provided is a periodic signal generation circuit including a clock generation unit suitable for generating first to nth clocks which have a basic period and have a phase increasing sequentially by a time interval obtained by dividing the basic period by “n”; a pulse generation unit suitable for generating first to nth periodic pulses having an equal pulse width and having a phase increasing sequentially by a time interval obtained by dividing the basic period by “n” by combining two or more clocks among the first to nth clocks; and a periodic signal generation unit suitable for generating a periodic signal by combining one or more periodic pulses among the first to nth periodic pulses depending on combination information.. . ... Sk Hynix Inc

05/31/18 / #20180151208

Semiconductor system

A semiconductor system may include a controller and a semiconductor memory device. The controller may provide an external command, an external address and a first external clock. ... Sk Hynix Inc

05/31/18 / #20180151205

Memory device, operating method thereof, and operating method of memory system including the same

A method for operating a memory device includes: receiving a write command; checking out whether a data strobe signal toggles or not after a given time passes from a moment when the write command is received; when the data strobe signal is checked out to be maintained at a uniform level, detecting voltage levels of a plurality of data pads; and performing an operation that is selected based on the voltage levels of the plurality of the data pads among a plurality of predetermined operations.. . ... Sk Hynix Inc

05/31/18 / #20180151204

Electronic device and method for driving the same

An electronic device includes a semiconductor memory. The semiconductor memory may include: a memory circuit comprising a plurality of memory cells; a read circuit configured to generate a first read data signal by reading data from a read target memory cell according to a first read control signal, the read target memory cell being among the plurality of memory cells; and a control circuit configured to control the read circuit to reread the data from the read target memory cell by generating a second read control signal, the second read control signal being based on a data value of the first read data signal.. ... Sk Hynix Inc

05/31/18 / #20180151197

Error correction code encoder, encoding method, and memory controller including the encoder

An error correction code (ecc) encoder includes a plurality of exclusive or (xor) gates configured to receive a “k”-bit original data in parallel and configured to perform a plurality of xor operations to the “k”-bit original data to output a “(n−k)”-bit parity data. The “k”-bit original data and the “(n−k)”-bit parity data form an “n”-bit codeword, “k” denotes a natural number and “n” denotes a natural number which is greater than “k”.. ... Sk Hynix Inc

05/31/18 / #20180150248

Memory device, semiconductor system including the same, and method for driving the semiconductor system

A semiconductor device includes at least one normal block suitable for storing normal data; at least one sample block suitable for storing sample data; a phenomenon analysis block suitable for generating at least one phenomenon analysis signal based on the sample data; and a control block suitable for controlling a level of reference data required when the normal data are read based on the at least one phenomenon analysis signal.. . ... Sk Hynix Inc

05/31/18 / #20180150247

Memory system and method for operating the same

Provided herein may be a memory system and a method of operating the memory system. The memory system may include a semiconductor device in which data are stored, and a memory controller for communicating with the semiconductor device, sequentially processing tasks included in a descriptor, detecting an error section by checking the tasks in reverse order when an error occurred in the tasks, and reprocessing the tasks included in the detected error section.. ... Sk Hynix Inc

05/31/18 / #20180150245

Data storage device and data processing system

A data processing system includes a host device; and a data storage device suitable for detecting a voltage drop state in the voltage received from the host device, changing a first key received from the host device to a second key when detecting the voltage drop state, generating a cyclical redundancy check (crc) data based on the second key, and transmitting the generated crc data to the host device.. . ... Sk Hynix Inc

05/31/18 / #20180150225

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of memory dies each having a plurality of memory blocks; and a controller suitable for performing one or more of data defragmentation and data remapping operations for a target transaction group in the memory device in response to a request message provided from a host, transmitting a completion message to the host as a response to the request message, and receiving an access to the transaction group, from the host.. . ... Sk Hynix Inc

05/31/18 / #20180150224

Memory system and operation method for the same

A memory system, may include: a memory device including a plurality of memory blocks each including a plurality of stacked word lines; and a controller suitable for dividing the plurality of word lines into two or more word line groups according to heights thereof, programming data of a relatively high access frequency into a word line group having word lines of relatively low physical heights and data of a relatively low access frequency into a word line group having word lines of relatively high physical heights among the word line groups included in each of the memory blocks.. . ... Sk Hynix Inc

05/31/18 / #20180150100

Training device and semiconductor system including the same

A training device may include a pattern generation circuit configured to generate a pattern signal in response to a read command, a delay calculation circuit configured to calculate a delay amount based on comparison results between a generation timing of the pattern signal and generation timings of pattern signals which are generated from one or more other training devices and transmitted to a corresponding training device, and a delay adjusting circuit configured to adjust a delay of a dq signal in a chip including the corresponding training device, based on the delay amount.. . ... Sk Hynix Inc

05/24/18 / #20180145705

Data mapping scheme for generalized product codes

Memory systems and operating methods thereof comprise a memory storage and an error control coding (ecc) unit. The memory storage stores data which is split into a plurality of data chunks. ... Sk Hynix Inc

05/24/18 / #20180145698

Analog-to-digital converter (adc) with improved power disturbance reduction

Disclosed herein is an analog-to-digital converter (adc) for converting an input analog voltage to an output digital code, the adc comprising a first node of the input analog voltage: nodes of a plurality of reference voltages; a plurality of comparators, inputs of each comparator being coupled to the first node and a node of a corresponding reference voltage of the plurality of reference voltages; a logic circuit block for receiving outputs of the plurality of comparators and generating the output digital code; and a voltage stabilizer, terminals of the voltage stabilizer being coupled with the first node and a node of a first reference voltage among the plurality of reference voltages.. . ... Sk Hynix Inc

05/24/18 / #20180145639

Amplifier for contorlling output range and multi-stage amplification device using the same

An amplifier includes a differential amplification block suitable for receiving and amplifying a first differential input signal and a second differential input signal; an output block suitable for determining an output signal according to a state of amplified signals outputted from the differential amplification block; and an output range restriction block suitable for controlling an output range of the output signal outputted from the output block based on a maximum clamping signal and a minimum clamping signal.. . ... Sk Hynix Inc

05/24/18 / #20180145087

Manufacturing method for semiconductor device

A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure, forming a reflective metal pattern in the first hole, filling an etch stop layer in the first hole and over the reflective metal pattern, forming a second stacked structure over the first stacked structure, and forming a second hole penetrating the second stacked structure to expose the etch stop layer.. . ... Sk Hynix Inc

05/24/18 / #20180144944

Methods of forming patterns using imprint process

A method for forming patterns is provided. The method includes forming a resist layer on a substrate, imprinting a convex pattern and a concave pattern on the resist layer using a template, forming a silicon diffusion layer containing silicon containing diffusion species in an upper portion of the convex pattern, and selectively removing a recessed portion of the resist layer under the concave pattern using the silicon diffusion layer as an etch mask.. ... Sk Hynix Inc

05/24/18 / #20180144813

Fail bit counter and semiconductor memory device having the same

Provided herein is a fail bit counter. The fail bit counter includes a pass/fail data receiver receiving pass/fail data indicating whether memory cells coupled to a bit line sequentially pass or fail, and a fail bit accumulator receiving a fail bit generation signal from the pass/fail data receiver, and accumulating and counting fail bits which are generated.. ... Sk Hynix Inc

05/24/18 / #20180144806

Memory system and operating method thereof

A memory system'may include: a nonvolatile memory device suitable for storing write-requested data; and a controller including a first volatile memory region suitable for storing meta-data for the write-requested data and a second volatile memory region suitable for storing a meta-log for the meta-data the controller may store the meta-data or the meta-log according to a logical address range of the meta-data.. . ... Sk Hynix Inc

05/24/18 / #20180144799

Phase change memory device capable of decreasing a disturbance

A phase change memory device may include a plurality of word lines, a plurality of bit lines, a phase change memory cell, and a discharging circuit. The word lines and the bit lines may intersect each other. ... Sk Hynix Inc

05/24/18 / #20180144798

Phase change memory device

A phase change memory device may be provided. The phase change memory device may include a plurality of mats, a row control block and a column control block. ... Sk Hynix Inc

05/24/18 / #20180144794

Cross point array type phase change memory device and method of driving the same

A phase change memory device may include a cross point array and a sensing circuit block. The cross point array may include a plurality of word lines, a plurality of bit lines and phase change memory cells. ... Sk Hynix Inc

05/24/18 / #20180144789

Semiconductor device, semiconductor system including the same and read and write operation method thereof

A semiconductor device may be provided. The semiconductor device may include a word line selector configured to generate an active signal for selecting a word line, based on a row address. ... Sk Hynix Inc

05/24/18 / #20180144785

Buffer circuit, semiconductor apparatus and system using the same

A buffer circuit may include first amplifier coupled to a first common node. The buffer circuit may include a second amplifier coupled to the first common node. ... Sk Hynix Inc

05/24/18 / #20180144781

Semiconductor memory device and method for operating the same

Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a delay code determining unit configured to output a final delay trim code reflecting process, voltage and temperature (pvt) conditions of the semiconductor memory device, using an internal clock generated for a reference time and a delay circuit configured to reflect a delay of a data line on a clock signal in response to the final delay trim code.. ... Sk Hynix Inc

05/24/18 / #20180143922

Data inversion circuit

A data inversion circuit in accordance with an embodiment may include a data input circuit and an inversion latch circuit. The data input circuit may output latch data by latching input data, perform a data inversion by performing a logical operation on the latch data and flag data, generate selective inversion data, and output data composed of multiple bits by aligning the selective inversion data. ... Sk Hynix Inc

05/24/18 / #20180143902

Data storage device and operating method thereof

A data storage device includes a storage medium including a plurality of memory units; and a controller suitable for performing a state determination operation to first memory units in order of a write sequence until a memory unit stored with an error-correction-failed data when a power supply is restored after an abnormal power-off, skipping the state determination operation to second memory units between the memory unit storing the error-correction-failed data and a pointed memory unit, performing the state determination operation to third memory units after the pointed memory unit in order of the write sequence, and performing a garbage collection operation to the first to third memory units based on a result of the state determination operation.. . ... Sk Hynix Inc

05/24/18 / #20180143899

Controller, memory system and operating method thereof

A controller includes a memory suitable for storing valid data of first data in a first data region and storing second data in a second data region, wherein the first data includes the valid data and dummy data; a translation unit suitable for performing a first translation operation of changing the first data to the valid data by eliminating the dummy data from the first data, performing a second translation operation of changing the valid data to the first data by adding the dummy data to the valid data, and exchanging the valid data with the memory; and a processor suitable for exchanging the first data with the translation unit, and exchanging the second data with the memory.. . ... Sk Hynix Inc








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