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Sk Hynix Inc patents


Recent patent applications related to Sk Hynix Inc. Sk Hynix Inc is listed as an Agent/Assignee. Note: Sk Hynix Inc may have other listings under different names/spellings. We're not affiliated with Sk Hynix Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Sk Hynix Inc-related inventors


Magnetic memory device

According to one embodiment, a magnetic memory device includes a magnetoresistive element, the magnetoresistive element including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. The first magnetic layer includes first and second sub-magnetic layers each containing at least iron (fe) and boron (b), and a concentration of boron (b) contained in the first sub-magnetic layer is different from a concentration of boron (b) contained in the second sub-magnetic layer.. ... Sk Hynix Inc

Mos capacitor and image sensor having the same

A mos capacitor may include: an isolation layer formed in a substrate and defining an active region; a first electrode formed in the active region, and including an impurity region spaced from the isolation layer; and a second electrode formed over the substrate overlapping the impurity region, and including a gate having a plurality of gate patterns adjacent to each other with a gap therebetween.. . ... Sk Hynix Inc

Nonvolatile memory device

A nonvolatile memory device includes a semiconductor substrate, a tunnel insulation layer disposed on the semiconductor substrate, a charge trap layer disposed on the tunnel insulation layer, and a control gate electrode disposed on the charge trap layer. The tunnel insulation layer includes an antiferroelectric material.. ... Sk Hynix Inc

Image sensor

An image sensor includes: a pixel array where a plurality of pixel groups are arrayed in two dimensions, wherein each of the plurality of the pixel groups includes: a first pixel suitable for sensing a first color signal that is color-separated through a first color filter; and a second pixel suitable for sensing a second color signal that is color-separated through a second color filter and has a longer wavelength than the first color signal, and a volume of a first color filter or a second color filter that is positioned in a peripheral area of the pixel array is different from a volume of a first color filter or a second color filter that is positioned in a central area of the pixel array.. . ... Sk Hynix Inc

Semiconductor device and method of manufacturing the same

Provided herein is a semiconductor device. The semiconductor device may include conductive layers each including a line, and a pad which is coupled with the line and has a thickness greater than that of the line, the conductive layers being stacked such that the pads are exposed; insulating layers interposed between the conductive layers; first spacers each of which is interposed between the pad of the corresponding upper conductive layer and the pad of the corresponding low conductive layer; and second spacers covering the respective first spacers.. ... Sk Hynix Inc

Semiconductor device and method of manufacturing the same

Provided herein may be a semiconductor device. The semiconductor device may include a stack, channel holes passing through the stack, dummy channel holes passing through the stack and disposed between the channel holes, a slit passing through the stack and the dummy channel holes.. ... Sk Hynix Inc

Ferroelectric memory device

A ferroelectric memory device includes a substrate, a ferroelectric structure having a first ferroelectric material layer, an electrical floating layer, and a second ferroelectric material layer sequentially stacked on the substrate, and a gate electrode layer disposed on the ferroelectric structure. A hysteresis loop of the second ferroelectric material layer differs from a hysteresis loop of the first ferroelectric material layer.. ... Sk Hynix Inc

Memory system with diagnose command and operating method thereof

A memory system and an operating method thereof include: at least a cpu configured to generate a special command; at least a pcie link coupled with the cpu, wherein the pcie link includes at least a pcie switch; and a plurality of memory devices connected with the pcie switch, wherein each of the plurality of memory devices includes a memory controller, an operational mode switch, and a plurality of memory components, and the operational mode switch is configured to perform a loopback from the memory controller corresponding to the special command at loopback operational mode.. . ... Sk Hynix Inc

Ferroelectric memory device and method of manufacturing the same

The ferroelectric memory device includes a substrate having a base doped region doped with a dopant of a first conductivity type and a trench disposed in the base doped region having an inner wall with a bottom and sidewalls. Also, the ferroelectric memory device includes a ferroelectric gate insulation layer, disposed along the inner wall of the trench, a gate electrode layer disposed on the ferroelectric gate insulation layer inside the trench, and a source region and a drain region, disposed in the substrate at respective ends of the trench and doped with a dopant of a second conductivity type. ... Sk Hynix Inc

Ferroelectric memory device and method of manufacturing the same

A ferroelectric memory device according to an embodiment includes a substrate, a ferroelectric gate insulation layer disposed along an inner wall of a trench formed in the substrate, and a gate electrode layer disposed on the ferroelectric gate insulation layer. The ferroelectric gate insulation layer has a variable thickness on the inner wall of the trench.. ... Sk Hynix Inc

Semiconductor device

A semiconductor device includes a buffer control circuit suitable for generating a buffer control signal in response to a power-down mode signal and a detection pulse, a first buffer circuit suitable for generating a first internal chip select signal by buffering a chip select signal depending on a select signal which is generated in response to the buffer control signal in a power-down mode, and a detection pulse generation circuit suitable for generating the detection pulse in response to the first internal chip select signal.. . ... Sk Hynix Inc

Memory system and operating method thereof

A memory system includes: a memory device; and a controller suitable for controlling the memory device to perform a serial read operation by providing a serial read command and a start physical address for the serial read command when an external read command includes a request for the serial read operation, the serial read command includes consecutive physical address numbers information, in response to the serial read command, the memory device sets a read bias, reads data stored therein with the set read bias according to the start physical address and the consecutive physical address numbers information, and then discharges the read bias.. . ... Sk Hynix Inc

Memory module including battery

A memory module may include a module substrate having first and second surfaces facing away from each other, a plurality of first memories mounted over one or more of the first and second surfaces, one or more second memories and a controller each mounted over one of the first and second surfaces of the module substrate, and a plurality of batteries mounted over one or more of the first and second surfaces of the module substrate.. . ... Sk Hynix Inc

Pcie virtual switches and an operating method thereof

A memory system and an operating method thereof include: at least a host; and at least pcie coupled with the host, wherein the at least pcie link includes at least a pcie switch and a plurality of pcie endpoints, wherein the plurality of pcie endpoints includes used pcie endpoints and unused pcie endpoints, the used pcie endpoints are mapped into a pcie enumeration tree, and the unused pcie endpoints are removed from the pcie enumeration tree, at virtual switch mode.. . ... Sk Hynix Inc

09/27/18 / #20180276158

System including interface circuit for high speed communication

A system includes a data transmission unit, a termination resistor and a data reception unit. The data transmission unit may drive a data transmission line based on data, and drive the data transmission line to a voltage level corresponding to a termination voltage during a specified operation period. ... Sk Hynix Inc

09/27/18 / #20180276136

Data storage device and operating method thereof

An operating method for a data storage device may include: reading data from a first memory region of a storage medium; storing the read data in a data buffer; and writing the data stored in the data buffer to a second memory region of the storage medium, based on a read count for the first memory region.. . ... Sk Hynix Inc

09/27/18 / #20180275920

Memory system and operating method thereof

A memory system may include: a memory device; and a controller suitable for: receiving a plurality of commands from a host; performing command operations corresponding to the commands to the memory device; providing operation results of the command operations to the host; and performing processing results including processing receptions of the commands, requests for performing the command operations and operation results for the command operations at a regular time duration interval.. . ... Sk Hynix Inc

09/27/18 / #20180275891

Memory system with latency distribution optimization and an operating method thereof

A memory system and an operating method thereof include: at least a cpu including multiple cpu cores, wherein the multiple cpu cores include reserved cpu cores and host cpu cores; at least a pcie link coupled with the cpu, wherein the pcie link includes at least a pcie switch and a plurality of memory devices; and the plurality of memory devices coupled with the host cpu cores through respective workload threads and interrupt handlers, wherein the workload threads and interrupt handlers of each of the host cpu cores are configured to be optimized, the host cpu cores are isolated for the optimized workloads threads and interrupt handlers, and the workload threads and interrupt handlers are executed at the host cpu cores coupled thereto.. . ... Sk Hynix Inc

09/27/18 / #20180275890

Memory system and method for operating the same

A memory system includes: two or more memory devices; and a controller suitable for: distributively storing input data in a primary memory device and in a secondary memory device when the input data requested to be stored in the primary device has a greater size than a transfer size for a single interleaving operation of the primary device; and collecting the input data stored in the secondary device into the primary device when the primary and secondary memory devices are in an idle state.. . ... Sk Hynix Inc

09/20/18 / #20180269905

State-based decoding of product codes

Techniques for reducing the latency for decoding product codewords with minimal hardware architecture changes are described. In an example, multiple decoding procedures are available a system. ... Sk Hynix Inc

09/20/18 / #20180269901

Semiconductor device

A semiconductor device may be provided. The semiconductor device may include an input and output (i/o) circuit configured to output transfer data generated from input data as internal data based on a write enablement signal and configured to output error information on the input data based on the write enablement signal. ... Sk Hynix Inc

09/20/18 / #20180269893

Successive approximation register analog-digital converter having a split-capacitor based digital-analog converter

A successive approximation register analog-digital converter including a split-capacitor based digital-analog converter includes a comparator, a split-capacitor based digital-analog converter including a positive capacitor array and a negative capacitor array, and a successive approximation register logic. The positive capacitor array and the negative capacitor array each includes a positive capacitor array of a first stage and a negative capacitor array of a first stage that generate input signals of the comparator corresponding to upper bits including an msb, respectively, a positive capacitor array of a second stage and a negative capacitor array of a second stage that generate input signals corresponding to intermediate bits, and a positive capacitor array of a third stage and a negative capacitor array of a third stage that generate input signals corresponding to lower bits of an lsb and a next to bit of the lsb.. ... Sk Hynix Inc

09/20/18 / #20180269858

Semiconductor device

A semiconductor device includes a first mode signal generation circuit suitable for generating a first mode signal in response to a command, the first mode signal being enabled in the case where a first period determined depending on a current characteristic of a first mos transistor is longer than a second period determined by a first passive element; and a second mode signal generation circuit suitable for generating a second mode signal in response to the command, the second mode signal being enabled in the case where a third period determined by a second passive element is longer than a fourth period determined depending on a current characteristic of a second mos transistor.. . ... Sk Hynix Inc

09/20/18 / #20180269238

Image sensor

An image sensor may include: a pixel array having a plurality of pixels arranged in a matrix structure; and an image array including a plurality of image dots which are arranged in a matrix structure, and implemented by output signals of the respective pixels. The position of a first pixel in the pixel array may not correspond to the position of an image dot corresponding to the first pixel in the image array, and the position of a second pixel adjacent to the first pixel in the pixel array may correspond to the position of an image dot corresponding to the second pixel in the image array.. ... Sk Hynix Inc

09/20/18 / #20180269216

Ferroelectric memory device and cross-point array apparatus including the same

A ferroelectric memory device includes a first electrode layer disposed on a substrate, a first tunnel barrier layer disposed on the first electrode layer, a second electrode layer disposed on the first tunnel barrier layer, a second tunnel barrier layer disposed on the second electrode layer, and a third electrode layer disposed on the second tunnel barrier layer. Any one of the first and second tunnel barrier layers includes a ferroelectric material.. ... Sk Hynix Inc

09/20/18 / #20180269211

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes: forming a bottom electrode of a high aspect ratio; forming an interface layer by sequentially performing a first plasma process and a second plasma process onto a surface of the bottom electrode; forming a dielectric layer over the interface layer; and forming a top electrode over the dielectric layer.. . ... Sk Hynix Inc

09/20/18 / #20180268919

Data storage device and operating method thereof

An operating method for a data storage device may include: determining a displacement value based on section memory cell numbers regarding a plurality of threshold voltage sections divided by a first read voltage and second read voltages; determining an adjustment direction based on the displacement value; adjusting at least one reliability value corresponding to at least one threshold voltage section among the threshold voltage sections, positioned in the adjustment direction from the first read voltage; and performing an error correction operation on data read from memory cells based on the first read voltage, using reliability values corresponding to the threshold voltage sections.. . ... Sk Hynix Inc

09/20/18 / #20180268917

Memory device and test method thereof

A test method for a memory device may include: performing a first write operation of writing test data to first regions of a normal cell region and a parity cell region, and storing a parity bit generated based on the test data in a temporary storage circuit; performing a second write operation of writing the parity bit stored in the temporary storage circuit to a second region of the parity cell region; performing a first read operation of reading the parity bit from the second region of the parity cell region, and storing the parity bit into the temporary storage circuit; and performing a second read operation of reading the test data from the first regions of the normal cell region and the parity cell region, correcting an error of the test data using the parity bit stored in the temporary storage circuit, and outputting error-corrected test data.. . ... Sk Hynix Inc

09/20/18 / #20180268892

Semiconductor memory device

A semiconductor memory device includes a memory cell array and a row decoder disposed in a first direction over a substrate and a plurality of coupling lines for electrically coupling the memory cell array and the row decoder. Each of the coupling lines includes a first conductive line disposed in the first direction; a second conductive line disposed parallel to the first conductive line; and a pad coupling the first conductive line and the second conductive line, and coupled to the memory cell array or the row decoder through a contact plug. ... Sk Hynix Inc

09/20/18 / #20180268884

Semiconductor devices

A semiconductor device may be provided. The semiconductor device may include a period code generation circuit configured to generate a period code having a logic level combination corresponding to a first command or a second command. ... Sk Hynix Inc

09/20/18 / #20180268880

Semiconductor memory device, flag generating circuit, and method of outputting data in a semiconductor device

A semiconductor memory device may include a memory circuit including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines, and configured to output data from the memory cell coupled to each of the bit lines through a global input/output line; a flag-generating circuit configured to generate a flag signal received with respect to the bit lines. The flag signal may include at least one of a duplicate data flag signal and a data bus inversion flag signal based on number of data having a specific logic level among the data in the memory cell for each of the bit lines that may be provided through the global input/output line in a read operation; and an output circuit configured to output the data based on at least one of the duplicate data flag signal and the data bus is inversion flag signal.. ... Sk Hynix Inc

09/20/18 / #20180268879

Semiconductor data multiplexer circuit

A semiconductor device includes a data output selection circuit suitable for outputting first pattern data as selection data in the case where a training operation is performed, outputting information data as the selection data in the case where a mode register read operation is performed, and outputting second pattern data in the case where the training operation is performed; and a data pad circuit including a first data pad and a second data pad, wherein the first data pad outputs the selection data and the second data pad outputs the second pattern data.. . ... Sk Hynix Inc

09/20/18 / #20180267903

Memory system and operating method thereof

A memory system includes: a controller suitable for generating a control signal for changing a data output status of a memory device to an abnormal status; and the memory device suitable for, when the data output status is the abnormal status, changing second data, which correspond to a read command from the controller among first data stored therein, into encrypted data, and outputting the encrypted data.. . ... Sk Hynix Inc

09/20/18 / #20180267897

Memory system and operating method thereof

A memory system includes: a memory device; and a controller including a cache which is coupled between a host and the memory device and includes a plurality of storing regions, for determining whether or not a storing region corresponding to address information which is requested by the host exists in the cache among the plurality of the storing regions based on bitmap information which hierarchically represents the plurality of the storing regions.. . ... Sk Hynix Inc

09/20/18 / #20180267895

Memory system

A memory system include: a plurality of first memory devices each coupled to a first channel and including a plurality of first memory blocks; a plurality of second memory devices each coupled to a second channel and including a plurality of second memory blocks; a first access controller suitable for controlling an access to the first memory blocks; a second access controller suitable for controlling an access to the second memory blocks; and a bad block controller suitable for: selecting one between the first and second access controllers by comparing bad physical addresses corresponding to bad blocks included in each of the first and second memory devices with first and second physical addresses respectively corresponding to the first and second memory blocks, and transferring one of the first and second physical addresses and substitute physical address that replace the bad physical addresses.. . ... Sk Hynix Inc

09/20/18 / #20180267877

Circuits relating to the calculation of power consumption of phase change memory devices, phase change memory systems including the same, and methods relating to the calculation of power consumption of phase change memory devices

A circuit for calculating power consumption of a phase change memory (pcm) device may be provided. The circuit may include a plurality of pipelines and an arithmetic logic circuit. ... Sk Hynix Inc

09/20/18 / #20180267852

Semiconductor devices

A semiconductor device includes an error count signal generation circuit and a row error control circuit. The error count signal generation circuit generates an error count signal which is enabled if the number of erroneous data of cells selected to perform an error scrub operation is equal to a predetermined number. ... Sk Hynix Inc

09/20/18 / #20180267743

Electronic device including semiconductor memory

An electronic device includes a semiconductor memory. The semiconductor memory includes a first variable resistance element, a first switching element coupled to the first variable resistance element via a first line, a second variable resistance element, and a second switching element coupled to the second variable resistance element via a second line, wherein a distance between the first switching element and the first variable resistance element is larger than a distance between the second switching element and the second variable resistance element, and wherein a second path from a first terminal of the second switching element to the second variable resistance element includes a resistance component, a resistance of the second path being greater than a resistance of a first path, the first path being from a first terminal of the first switching element to the first variable resistance element.. ... Sk Hynix Inc

09/20/18 / #20180267724

Data transfer training method and data storage device performing the same

A data transfer training method includes determining whether a program data transfer training command or a read data transfer training command is received from a host device; transferring normal program signals to non-training memory devices among a plurality of memory devices and performing a program data transfer training to a training memory device among a plurality of memory devices while performing normal program operations to the non-training memory devices in response to a received program data transfer training command; and transferring normal read signals to the non-training memory devices, and performing a read data transfer training to the training memory device while performing normal read operations to the non-training memory devices in response to a received read data transfer training command.. . ... Sk Hynix Inc

09/20/18 / #20180267708

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of pages in which data are stored, a plurality of memory blocks in which the pages are included, and a plurality of memory dies in which the memory blocks are included; and a controller suitable for performing command operations corresponding to a plurality of commands received from the host, predicting peak operation durations when performing the command operations, and scheduling the commands by minimizing overlaps between the peak operation durations.. . ... Sk Hynix Inc

09/06/18 / #20180255215

Image sensor

Disclosed is an image sensor device including a pixel array in which a plurality of pixel blocks are arranged. Each of the pixel blocks may include: a light receiver comprising a floating diffusion and a plurality of unit pixels and configured to receive incident light and generate photo charges in response to the received incident light, the plurality of unit pixels sharing the floating diffusion; a first driver located at a first side of the light receiver and comprising a driver transistor; a second driver located at a second side of the light receiver and comprising a reset transistor; and a conductive line having a first region coupling the driver transistor to the floating diffusion and a second region coupling the floating diffusion to the reset transistor, wherein the driver transistor and the reset transistor are respectively located the first side and the second side of the light receiver in a diagonal direction.. ... Sk Hynix Inc

09/06/18 / #20180254297

Image sensor with phase difference detection pixel

An image sensor includes a pixel array having a plurality of pixels arranged therein. At least any one of the plurality of pixels include: a photoelectric conversion unit including first and second photoelectric conversion elements; a first sub-lens formed over the first photoelectric conversion element, and having a vertex out of a central axis of the first photoelectric conversion element; a second sub-lens formed over the second photoelectric conversion element, and having a vertex out of a central axis of the second photoelectric conversion element; and a microlens formed over the photoelectric conversion element so as to overlap the first and second sub-lenses. ... Sk Hynix Inc

09/06/18 / #20180254285

Electronic device and method for manufacturing the same

A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.. . ... Sk Hynix Inc

09/06/18 / #20180254261

Semiconductor packages having asymmetric chip stack structure

A semiconductor package may include first chip stack including first chips which are stacked on a package substrate and offset to form a first reverse stepwise sidewall. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate and offset to form a second reverse stepwise sidewall. ... Sk Hynix Inc

09/06/18 / #20180254248

Electronic device and method for fabricating the same

An electronic device includes a semiconductor memory, wherein the semiconductor memory may include: a cell mat disposed over a substrate, the cell mat including a plurality of memory cells; an insulating layer disposed over the cell mat; a conductive pattern disposed over the insulating layer, the conductive pattern overlapping a first portion of the cell mat without overlapping a second portion of the cell mat; and a shielding layer disposed in the insulating layer, the shielding layer overlapping at least the second portion of the cell mat, the shielding layer being capable of blocking plasma. . ... Sk Hynix Inc

09/06/18 / #20180254080

Semiconductor devices

A semiconductor device may be provided. The semiconductor device may include an address input circuit and a target address generation circuit. ... Sk Hynix Inc

09/06/18 / #20180254078

Semiconductor device and method of driving the same

A semiconductor device according to an embodiment includes a plurality of memory regions suitable for performing a refresh operation based on a row address signal; an initialization circuit suitable for generating an initialization pulse signal for each refresh period during which a refresh pulse signal toggles as many times as the number of the memory regions; a control circuit suitable for activating a control pulse signal based on the refresh pulse signal and a plurality of memory address signals corresponding to the memory regions, and deactivating the control pulse signal based on the initialization pulse signal; and a row address generation circuit suitable for sequentially generating the row address signal based on the control pulse signal.. . ... Sk Hynix Inc

09/06/18 / #20180254072

Semiconductor apparatus including a sense amplifier control circuit

A semiconductor apparatus includes a sense amplifier configured to sense data transmitted through a data line and a sense amplifier control circuit configured to detect whether a level of an external voltage is equal to or larger than an reference voltage level and control a power voltage of the sense amplifier according to a detection result.. . ... Sk Hynix Inc

09/06/18 / #20180253394

Storage device, data processing system, and method for operating the storage device

A storage device may include: a protocol processing unit suitable for communicating with a host based on a predetermined protocol, and transferring a response signal to at least one status request signal that is received from the host; a power management unit suitable for supplying a power source voltage, and outputting a detection signal which represents a low voltage detection status where the power source voltage has a voltage level lower than a predetermined voltage level; and a core unit suitable for blocking a transfer of the response signal by the protocol processing unit in response to the detection signal, and processing at least one task request which is received from the host through the protocol processing unit after the blocking.. . ... Sk Hynix Inc

09/06/18 / #20180253345

Memory system and operating method thereof

A memory system comprising: a memory device including a plurality of memory dies each having a plurality of the memory blocks; and a controller suitable for performing a command operation to the memory dies, wherein the memory device comprises means for performing an error check operation to a first data provided from the controller to store the first data the memory device.. . ... Sk Hynix Inc

08/23/18 / #20180241542

Serializer, and semiconductor apparatus and system including the same

A serializer may be provided. The serializer may include a first data output circuit and a second data output circuit. ... Sk Hynix Inc

08/23/18 / #20180240973

Method for fabricating electronic device

A method for fabricating an electronic device including a semiconductor memory may include forming a buffer layer over a substrate, the buffer layer operable to aide in crystal growth of an under layer; forming the under layer over the buffer layer, the under layer operable to aide in crystal growth of a free layer; and forming a magnetic tunnel junction (mtj) structure including the free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer over the under layer.. . ... Sk Hynix Inc

08/23/18 / #20180240888

Method for manufacturing a transistor and method for manufacturing a ring oscillator using the same

In a method for manufacturing a transistor, a gate structure may be formed on a semiconductor substrate. A first material layer may be formed on the gate structure to expose an upper sidewall of the gate structure. ... Sk Hynix Inc

08/23/18 / #20180240846

Neuromorphic device including a synapse having carbon nano-tubes

A neuromorphic device is provided. The neuromorphic device may include a pre-synaptic neuron; a row line extending in a row direction from the pre-synaptic neuron; a post-synaptic neuron; a column line extending in a column direction from the post-synaptic neuron; and a synapse disposed at an intersection between the row line and the column line. ... Sk Hynix Inc

08/23/18 / #20180240826

Image sensor

An image sensor device includes a photoelectric conversion element configured to receive incident light and generate photocharges in response to the received incident light; a floating diffusion coupled to the photoelectric conversion element to store the photocharges generated by the photoelectric conversion element, the floating diffusion having a first capacitance value; a conductive pattern electrically coupled to the floating diffusion; and a variable electrode located apart from the conductive pattern by a gap, wherein the conductive pattern and the variable electrode form a variable capacitor coupled to the floating diffusion and having a second capacitance value and operable to change an effective capacitance of the floating diffusion in response to a control signal applied to the variable electrode.. . ... Sk Hynix Inc

08/23/18 / #20180240813

Semiconductor device

A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source layer; a plurality of conductive layers stacked substantially over the first source layer; channel layers that pass through the plurality of conductive layers and couple to the second source layer; and at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer.. . ... Sk Hynix Inc

08/23/18 / #20180240804

Ferroelectric memory device and method of manufacturing the same

In an embodiment, a ferroelectric memory device includes a substrate having a source region and a drain region. The ferroelectric memory device includes a ferroelectric superlattice structure disposed on the substrate and having at least two kinds of different dielectric layers alternately stacked. ... Sk Hynix Inc

08/23/18 / #20180240803

Ferroelectric memory device and method of manufacturing the same

In an embodiment, a ferroelectric memory device includes a substrate having a source region and a drain region, a ferroelectric structure disposed on the substrate, and a gate electrode layer disposed on the ferroelectric structure. The ferroelectric structure includes a ferroelectric material layer having a concentration gradient of a dopant.. ... Sk Hynix Inc

08/23/18 / #20180240528

Nonvolatile memory device, memory system including thereof and operating method thereof

A method for operating a memory system includes determining at least one erased memory cell among a plurality of erased memory cells as an unstable memory cell based on read data read from the at least one erased memory cell; determining the unstable memory cell as an unwritable memory cell based on write data to be written in the unstable memory cell; and prohibiting the plurality of erased memory cells from being used, depending on the number of erased memory cells as the unwritable memory cell among the plurality of erased memory cells.. . ... Sk Hynix Inc

08/23/18 / #20180240516

Memory system and operation method of the same

A memory system includes: a memory device; a cache memory suitable for caching a portion of a data stored in the memory device; and a read voltage controller suitable for controlling a level of a read voltage of the memory device by comparing a cache data in the cache memory with a data from the memory device corresponding to the cache data.. . ... Sk Hynix Inc

08/23/18 / #20180240506

Semiconductor memory device

A semiconductor memory device may include a memory cell array area, a peripheral area, and an interface area. The memory cell array area may include at least one memory plane. ... Sk Hynix Inc

08/23/18 / #20180240504

Semiconductor memory device having power mesh structure

A semiconductor memory device includes a peripheral circuit including a first unit circuit block and a second unit circuit block that are respectively disposed in a second region and a third region adjacent to each other in a first direction with a first region interposed therebetween, a first metal layer disposed over the peripheral circuit, a second metal layer disposed over the first metal layer, first power lines disposed in the first metal layer and suitable for transferring operating voltages to the first unit circuit block, second power lines disposed in the first metal layer and suitable for transferring the operating voltages to the second unit circuit block, and bridge power lines disposed in the second metal layer in the first region, and extending in a second direction intersecting with the first direction. The first power lines have lengths that extend from the second region to the first region, and the second power lines have lengths that extend from the third region to the first region. ... Sk Hynix Inc

08/23/18 / #20180240009

Neuromorphic device including a synapse having a variable resistor and a transistor connected in parallel with each other

A neuromorphic device may include a pre-synaptic neuron, a row line extending in a row direction from the pre-synaptic neuron, a post-synaptic neuron, a column line extending in a column direction from the post-synaptic neuron, and a synapse disposed at an intersection region between the row line and the column line. The synapse may include a first node electrically connected with the row line, a second node electrically connected with the column line, and a variable resistor and a first transistor electrically coupled between the first node and the second node. ... Sk Hynix Inc

08/23/18 / #20180239557

Nonvolatile memory device, data storage device including the same, and operating method of data storage device

A nonvolatile memory device includes a memory cell region including an external data area and an internal data area; and a control logic suitable for storing history data collected based on control signals received from an external device, in the internal data area, and controlling an operation for the external data area according to the control signals.. . ... Sk Hynix Inc

08/23/18 / #20180239548

Operating method of memory system

A method for operating a memory system includes updating, after accessing ail of one or more first memory regions included in a first list for a purpose of data storage, map data for the first memory regions; determining a list size based on a workload of the memory system, and generating a second list including one or more second memory regions depending on the list size; and accessing, after the updating of the map data, the second memory regions for a purpose of data storage.. . ... Sk Hynix Inc

08/16/18 / #20180233215

Semiconductor test device and semiconductor test method

A semiconductor test device and a semiconductor test method are disclosed. A semiconductor test device may include a dq signal receiver, a test mode register set signal processor, and a test mode command generator. ... Sk Hynix Inc

08/16/18 / #20180233214

Test apparatus and semiconductor chip

A test apparatus may be provided. The test apparatus may include a delay compensator configured to generate delayed read data by delaying read data according to a difference between an external turnaround delay value provided externally from the test apparatus and a turnaround delay detection value detected within the test apparatus. ... Sk Hynix Inc

08/16/18 / #20180233212

Semiconductor device

A semiconductor device may include a first pad configured to provide a first voltage. The semiconductor device may include a second pad. ... Sk Hynix Inc

08/16/18 / #20180233207

Memory device and method of operating the same

Provided herein are a memory device and a method of operating the memory device. The memory device comprises a plurality of memory cells stacked along a pillar vertical to a substrate, a peripheral circuit configured to program and verifying memory cells coupled to a selected word line, among the memory cells, and a control logic configured to control the peripheral circuit so that a pass voltage applied to unselected word lines is adjusted depending on a location of the selected word line when the memory cells are verified.. ... Sk Hynix Inc

08/16/18 / #20180233204

Semiconductor memory device and operating method thereof

The present disclosure relate a method of operating a semiconductor memory device including at least two memory blocks sharing one block word line. The method including applying an erase voltage to a source line commonly coupled to the memory blocks, one of which is a selected memory block and applying a first voltage to the block word line and a third voltage to a global word line of an unselected memory block of the memory blocks when the erase voltage is applied to the source line, wherein the first voltage is higher than a turn-on voltage to turn on a pass transistor coupled to the block word line, and wherein the third voltage floats a local word line included in the unselected memory block according to a level of the first voltage.. ... Sk Hynix Inc

08/16/18 / #20180233201

Memory device and method of operating the same

A memory device with a plurality of memory block may include a plurality of memory cells constituting a memory blocks, and two or more select transistors coupled to the plurality of memory cells constituting the memory block and configured to select the memory block, the two or more select transistors having different threshold voltages from one another.. . ... Sk Hynix Inc

08/16/18 / #20180233192

Semiconductor device

A semiconductor device is disclosed, which relates to a technology for a sense-amplifier (sense-amp) configured to compensate for mismatch of a sensing bit-line. The semiconductor device includes a sense-amplifier configured to selectively control connection between a pair of bit lines and a pair of sensing bit lines in response to a connection control signal in an offset compensation period, and precharge a pull-down power-supply line with a bit line precharge voltage level in the offset compensation period. ... Sk Hynix Inc

08/16/18 / #20180233187

Electronic devices and method for fabricating the same

An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer including a cofebal alloy and having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the cofebal alloy may have an al content less than 10 at %.. . ... Sk Hynix Inc

08/16/18 / #20180233184

Electronic device and method of operating the same

Provided herein may be a semiconductor memory device. The semiconductor memory device may include a memory unit configured to store the write data. ... Sk Hynix Inc

08/16/18 / #20180233179

Data output buffer

A data output buffer may be provided. The data output buffer may include a pull-up circuit configured to output a pull-up feedback signal by pull-up driving an output node. ... Sk Hynix Inc

08/16/18 / #20180233178

Sense amplifier for high speed sensing, memory apparatus and system including the same

A sense amplifier includes a current supply unit, an amplification unit, a pass transistor and a latch unit. The current supply unit may be configured to provide a sensing current to a sensing node. ... Sk Hynix Inc

08/16/18 / #20180232325

Memory system and method for operating the same

A memory system includes: a memory device for including a plurality of memory blocks each of which includes a plurality of pages, a plurality of planes each of which includes the memory blocks, and a plurality of memory dies each of which includes the planes; and a controller for grouping a plurality of read commands that are transferred from a host into one or more read command groups based on a policy that is designed in such a manner that a read operation is performed in an order from a relatively big physical area unit to a relatively small physical area unit based on a physical address value of each of the read commands, when the read commands are transferred from the host, and applying each of the read command groups to a read operation of the memory device.. . ... Sk Hynix Inc

08/16/18 / #20180232267

Memory device, memory controller and operation method thereof

An operation method of a memory controller may include: performing a preset number of write operations on a redundancy region of a memory device, reading data of the redundancy region of the memory device, and detecting error bits which occur in the data, and generating an identifier corresponding to the memory device based on the detected error bits.. . ... Sk Hynix Inc

08/16/18 / #20180232177

Memory system and operating method thereof

A memory system may include: a memory device having a plurality of blocks; and a controller suitable for performing a count operation on each of the blocks in response to a preset number of write requests, and performing a wear leveling operation based on the result of the count operation on each of the blocks.. . ... Sk Hynix Inc

08/09/18 / #20180227520

Image sensing device

An image sensing device includes pixel groups, each pixel group including two or more neighboring pixels and grouped into a same pattern; and a timing generator controlling the pixel groups based on one or more row units, wherein readout orders of first and second pixel groups arranged in different rows among the pixel groups are controlled differently, wherein the first pixel group reads out two or more pixel signals based on two or more first transmission control signals, wherein the second pixel group reads out two or more pixel signals based on two or more second transmission control signals, wherein the timing generator generates the first transmission control signals in a first order during one or more first row readout times, wherein the timing generator generates the second transmission control signals in a second order, which is different from the first order, during one or more second row readout times.. . ... Sk Hynix Inc

08/09/18 / #20180226965

Semiconductor device and system including the same

A semiconductor apparatus may be provided. The semiconductor apparatus may include a first buffer configured to generate a first preliminary clock and a first preliminary clock bar based on an external clock, an external clock bar, and a node voltage code. ... Sk Hynix Inc

08/09/18 / #20180226956

Internal clock generation circuits

An internal clock generation circuit includes an interpolation clock generation circuit and a locked clock generation circuit. The interpolation clock generation circuit generates an interpolation clock signal from a division clock signal in response to a switching control signal and a current control signal. ... Sk Hynix Inc

08/09/18 / #20180226568

Electronic devices having semiconductor magnetic memory units

A semiconductor device includes a resistance variable element including a free magnetic layer, a tunnel barrier layer and a pinned magnetic layer; and a magnetic correction layer disposed over the resistance variable element to be separated from the resistance variable element, and having a magnetization direction which is opposite to a magnetization direction of the pinned magnetic layer.. . ... Sk Hynix Inc

08/09/18 / #20180226567

Electronic device and method for fabricating the same

An electronic device may include a semiconductor memory, and the semiconductor memory may include a substrate; an interlayer dielectric layer formed over the substrate and patterned to include a contact hole; a lower contact structure formed over the substrate in the contact hole; and a variable resistance element formed over and electrically coupled to the lower contact structure, wherein the lower contact structure comprises: a spacer formed on sidewalls of the contact hole in the interlayer dielectric layer and including a material having a lower etch rate than that of silicon nitride (sin); a contact plug filling a portion of the contact hole; and a contact pad formed over the contact plug and filling a remaining portion of the contact hole.. . ... Sk Hynix Inc

08/09/18 / #20180226452

Electronic device and method for fabricating the same

An electronic device may include a semiconductor memory, and the semiconductor memory may include a variable resistance element. The variable resistance element may include a lower electrode; a spacer formed on a side surface of the lower electrode; and a variable resistance pattern disposed over the lower electrode, wherein a portion of the lower electrode covers a top surface of the spacer.. ... Sk Hynix Inc

08/09/18 / #20180226345

Fuse structure and method of manufacturing the same

A fuse structure may include an anode pattern, a cathode pattern and a connection member. The anode pattern may be formed on a semiconductor substrate. ... Sk Hynix Inc

08/09/18 / #20180226344

Fuse structure and method of manufacturing the same

A fuse structure may include an anode pattern, a cathode pattern and a connection member. The anode pattern may be formed on a semiconductor substrate. ... Sk Hynix Inc

08/09/18 / #20180226131

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device; a voltage detector suitable for detecting an operating voltage of the nonvolatile memory device; and a control unit suitable for making a first determination whether the operating voltage is dropped intentionally or unintentionally based on a first reference time and an elapsed time for which the operating voltage decreases from a first reference voltage to a second reference voltage.. . ... Sk Hynix Inc

08/09/18 / #20180226129

Method of programming semiconductor memory device

In a method of programming a semiconductor memory device, during a standby period, a standby voltage is applied to word lines coupled to a plurality of memory cells included in a selected memory cell string, and, during a first program period, a first pre-bias voltage is applied to a word line coupled to at least one of programmed memory cells of the selected memory cell string. The first pre-bias voltage is greater than the standby voltage.. ... Sk Hynix Inc

08/09/18 / #20180226119

Semiconductor device

A semiconductor device includes a period signal generation circuit and an interruption signal generation circuit. The period signal generation circuit generates a period signal in response to a refresh pulse and an end pulse. ... Sk Hynix Inc

08/09/18 / #20180226108

Electronic device and operating method thereof

According to an embodiment, a storage device may be provided. The storage device may include a semiconductor memory device, and a memory controller configured for controlling the semiconductor memory device. ... Sk Hynix Inc

08/09/18 / #20180225566

Neuromorphic device including a synapse having a plurality of synapse cells

A neuromorphic device is provided. The neuromorphic device may include a plurality of pre-synaptic neuron circuits, a plurality of post-synaptic neuron circuits, and a plurality of synapses. ... Sk Hynix Inc

08/09/18 / #20180225234

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device; a power management unit suitable for outputting first and second low voltage detection signals, each low voltage detection signal representing a voltage level of a source voltage equal to or lower than a predetermined reference voltage level; and a processor suitable for computing a detection interval between the first low voltage detection signal and the second low voltage detection signal before the first low voltage detection signal, comparing the computed detection interval and a predetermined threshold detection interval, and determining a subject to manage performing of a recovery operation according to low voltage generation based on a comparison result.. . ... Sk Hynix Inc

08/09/18 / #20180225220

Memory device and method of operating the same

A memory device and a method of operating the same. The memory device may include a memory block including a plurality of pages, and a control logic configured to include at least one register in which a plurality of program algorithms and a plurality of pieces of operation information are stored, select any one of the program algorithms in response to an address of a program target page, among the pages, and perform a program operation on the program target page based on the selected program algorithm and operation information corresponding to the selected program algorithm.. ... Sk Hynix Inc

08/09/18 / #20180225200

Operating method of data storage device

A method for operating a data storage device includes storing an erase count corresponding to a physical address, as a reference value, in response to a first event; comparing a current value of the erase count with the reference value in response to a second event; and selectively performing a purge operation for the physical address, depending on a result of the comparing.. . ... Sk Hynix Inc

08/09/18 / #20180225199

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device; and a controller suitable for setting a termination condition of a garbage collection operation based on an over-provisioning ratio of the nonvolatile memory device, performing the garbage collection operation, and terminating the garbage collection operation according to the termination condition.. . ... Sk Hynix Inc

08/09/18 / #20180225185

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device including a memory block having a plurality of memory regions; and a controller suitable for searching a first memory region for which error correction is passed, by scanning the plurality of memory regions in a reverse order of a write sequence for the memory block, determining a target memory region in the memory block based on data stored in the first memory region, and performing a recovery operation for the target memory region.. . ... Sk Hynix Inc

08/09/18 / #20180225173

Memory systems having extended product lifetime and methods of operating the same

A memory system includes a first memory device, a second memory device, and a controller. The second memory device has a write endurance which is higher than a write endurance of the first memory device. ... Sk Hynix Inc

08/09/18 / #20180225151

Data storage device and operating method thereof

A method for operating a data storage device includes determining a first weight based on the sum of data sizes for commands queued in a command queue; determining a second weight by summing weights by types of the commands; and controlling an urgent command selection threshold value for selecting an urgent command existing in the command queue, based on at least one of the first weight and the second weight.. . ... Sk Hynix Inc

08/09/18 / #20180225060

Memory system

A memory system includes a memory controller, a first memory module including first and second groups of first memory chips, a second memory module including first and second groups of second memory chips, and a channel including a first group of signal lines suitable for coupling the memory controller with the first memory module, and a second group of signal lines suitable for coupling the memory controller with the second memory module.. . ... Sk Hynix Inc

08/02/18 / #20180219572

Semiconductor device

A semiconductor device includes a plurality of chips, at least one line, and a controller. Each of the chips includes a chip input/output (i/o) pad, a transceiver configured to perform a transmission operation in response to a transmission enable signal or perform a reception operation in response to a reception enable signal, and a switch configured to couple the chip input/output (i/o) pad to the transceiver in response to a switch enable signal. ... Sk Hynix Inc

08/02/18 / #20180219537

Electronic device

An electronic device may include a ramp signal generator suitable for generating a ramp signal having a slope corresponding to an analog gain, and a slope correction circuit suitable for correcting the slope based on a correction code signal.. . ... Sk Hynix Inc

08/02/18 / #20180219023

Semiconductor memory device including a slit

A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block.. . ... Sk Hynix Inc

08/02/18 / #20180218945

Electronic device and method for fabricating the same

A semiconductor device may include: a plurality of first contacts arranged at a predetermined distance in a first direction and a second direction crossing the first direction; a plurality of second contacts alternately arranged between the first contacts and arranged at a predetermined distance in the first direction and the second direction; a plurality of dog bone-type conductive lines connected to the second contacts arranged in the second direction, respectively, among the plurality of second contacts, and having concave parts and convex parts; and a plurality of etching prevention patterns formed over the plurality of conductive lines so as to overlap the conductive lines, respectively.. . ... Sk Hynix Inc

08/02/18 / #20180218777

Memory apparatus relating to determination of a failed region and test method thereof, memory module and system using the same

A memory device may be provided. The memory device may include a test data output circuit configured to compare lower data output from a lower data storage region with upper data output from an upper data storage region and make a decision. ... Sk Hynix Inc

08/02/18 / #20180218776

Integrated circuits

An integrated circuit including semiconductor devices may be provided. The semiconductor device may be configured to compare phases of strobe signals which are generated according to internal delay times of the semiconductor devices and configured to control points of time that an internal command is inputted to the internal circuits of the semiconductor devices according to a comparison result of the phases of the strobe signals.. ... Sk Hynix Inc

08/02/18 / #20180217928

Data storage device and operating method thereof

A method for operating a data storage device includes determining an nth garbage collection throughput by multiplying a rate of a number of used pages of an open memory block to an amount of write data to be processed to a sum of the number of used empty memory blocks and an immediately previous garbage collection throughput average value; and performing a garbage collection operation based on the nth garbage collection throughput.. . ... Sk Hynix Inc

08/02/18 / #20180217895

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of memory blocks each having a plurality of sub memory blocks; and a controller suitable for performing an error correction operation to the memory blocks during a read operation to the memory blocks, updating a characteristic list for the memory blocks at each error correction operation to the memory blocks, classifying the memory blocks and the sub memory blocks according to the updated values in the characteristic list, and performing a program operation to the memory blocks according to the classification.. . ... Sk Hynix Inc

08/02/18 / #20180217894

Memory module, memory system including the same, and error correcting method thereof

An error correcting method of a memory system may include: reading read data and an error correction code from a plurality of memory chips; correcting an error of the read data using the error correction code; temporarily storing the read data and the error correction code in a buffer when the correcting of the error fails; writing a certain input test pattern in the plurality of memory chips, reading an output test pattern written in the plurality of memory chips, and detecting a fail chip in which a chipkill occurs; recorrecting, based on a location of the detected fall chip, the error of the read data stored in the buffer using the error correction code stored in the buffer; and rewriting error-corrected read data and the error correction code in the plurality of memory chips.. . ... Sk Hynix Inc

08/02/18 / #20180217785

Data storage device

A data storage device includes a nonvolatile memory device; and a controller suitable for controlling the nonvolatile memory device through a command, the controller comprising a memory controller including a queue which includes multiple slots, each of the multiple slots being mapped to one type among a plurality of types of the command, and suitable for processing a descriptor for the command enqueued to the queue to generate the command; and a processor suitable for requesting one slot of the multiple slots mapped to one type among the plurality of types of the command, to the memory controller, and enqueuing, when allocated with the one slot, the descriptor for the command, to the one slot.. . ... Sk Hynix Inc

08/02/18 / #20180217761

Data storage device and operating method thereof

A data storage device includes a storage medium including a plurality of logical units; and a controller suitable for accessing the storage medium by logical unit, the controller comprising: a first processor suitable for aligning tasks corresponding to at least one logical unit among the plurality of logical units, depending on a priority; and a second processor suitable for accessing other logical units among the plurality of logical units, wherein the first processor entrusts a task alignment operation for the other logical units, to the second processor, based on workloads of the first and second processors.. . ... Sk Hynix Inc

08/02/18 / #20180217754

Memory system and operating method thereof

A memory system may include: a plurality of memory dies; and a controller suitable for identifying a dependency between first and second commands and a priority order of the first and the second commands through a check engine, and control the memory dies to sequentially perform first and second command operations in response to the first and second commands according to the dependency and the priority order.. . ... Sk Hynix Inc

07/26/18 / #20180213168

Unit pixel apparatus with noise reduction function, operation method thereof, and cmos image sensor using the same

A unit pixel apparatus includes a unit pixel suitable for supporting initialization an output node and outputting a pixel signal corresponding to incident light through the output node; and a switching block suitable for initializing the output node and deciding an initial voltage of the output node.. . ... Sk Hynix Inc

07/26/18 / #20180212623

Controller and operating method thereof

A controller includes a processor suitable for determining whether to store further data corresponding to a command from a host into a first region in a main memory of the host when receiving the command from the host, requesting the host to store the further data corresponding to the command into the first region of the main memory when the first region is determined to store the further data corresponding to the command; and an error correction code unit suitable for encoding the further data stored in the first region in response to the storage request. The processor may control a memory device to store the encoded data.. ... Sk Hynix Inc

07/26/18 / #20180212621

Semiconductor device

Disclosed may be a repair information storage circuit. The repair information storage circuit may include a fuse set. ... Sk Hynix Inc

07/26/18 / #20180212597

Input buffer circuit

An input buffer circuit is disclosed, which relates to a technology for a receiver circuit including a plurality of input buffers having different characteristics. The input buffer circuit includes a first buffer configured to output a first input signal by buffering a command address received based on a flag signal, a second buffer configured to output a second input signal by buffering the command address based on the flag signal, a first delay matching circuit configured to output a first matching signal by delaying the first input signal by a first delay time, a second delay matching circuit configured to output a second matching signal by delaying the second input signal by a second delay time, and a selection circuit configured to select any one of the first matching signal and the second matching signal based on a selection signal.. ... Sk Hynix Inc

07/26/18 / #20180211994

Electronic device and method for fabricating the same

An electronic device including a semiconductor memory is provided. The semiconductor memory may include an mtj (magnetic tunnel junction) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer formed under the mtj structure, wherein the under layer may include metals and oxides of the metals.. ... Sk Hynix Inc

07/26/18 / #20180211913

Cross-point array device including conductive fuse material layer

A cross-point array device includes a pillar-shaped structure disposed in an intersection region where a first conductive line overlaps a second conductive line. The pillar-shaped structure includes a resistance change material layer disposed between the first conductive line and the second conductive line. ... Sk Hynix Inc

07/26/18 / #20180211696

Semiconductor systems performing double-write operations and methods of operating the same

A semiconductor system includes a controller. The controller is configured to have a write buffer that stores first write data outputted from a host before the first write data is written into a memory circuit. ... Sk Hynix Inc

07/26/18 / #20180211694

Memory module

A memory module includes a front side interface configured to serial-to-parallel convert a command, an address, and data, based on a host clock, and transfer the converted command, address, and data; a processing block configured to operate in synchronization with a division clock, process the command, address, and data transferred from the front side interface, and transfer the processed command, address, and data; a back side interface configured to include a pll for generating a media clock having a frequency different from the host clock, to parallel-to-serial convert the command, address, and data transferred from the processing block, based on the media clock, and to transfer the converted command, address, and data; and memory devices configured to operate in synchronization with the media clock, and to write the data transferred from the back side interface therein in response to the command and address transferred from the back side interface.. . ... Sk Hynix Inc

07/26/18 / #20180210826

Memory device, memory system, and operation method thereof

A memory device is provided. The memory device includes a plurality of normal memory blocks; and at least two or more bad memory blocks, wherein data having the same number of bits as data to be stored in a normal memory block and a parity code having the number of bits at least twice greater than that of a parity code to be stored in the normal memory block are stored in a first bad memory block and a second bad memory block among the bad memory blocks.. ... Sk Hynix Inc

07/26/18 / #20180210789

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of pages for storing data and a plurality of memory blocks including the pages; and a controller configured to read data, which corresponds to a read command received from a host, from the pages, perform bit flipping with respect to a plurality of constituent codes for the read data, and perform an error correction operation, the bit flipping is updated corresponding to a number of error correction bits in the constituent codes.. . ... Sk Hynix Inc

07/26/18 / #20180210786

Memory systems and electronic systems performing an adaptive error correction operation with pre-checked error rate, and methods of operating the memory systems

A memory system may include a test vector generator configured for generating a test vector to be written into a memory device, a data discrepancy checker configured for comparing read data outputted from the memory device with the test vector to generate an information signal corresponding to a comparison between the read data and the test vector, an error correction code (ecc) controller configured for performing an ecc encoding operation and an ecc decoding operation according to any one among a plurality of ecc levels based on a control signal, and a memory controller controlling the test vector generator, the data discrepancy checker and the ecc controller. The memory controller configured to transmit the control signal corresponding to an error rate of the memory device to the ecc controller, based on the information signal generated by the data discrepancy checker.. ... Sk Hynix Inc

07/26/18 / #20180210669

Memory system

A memory system includes: a non-volatile memory device for including a first storage region and a second storage region; and a controller for including first and second interfaces for inputting/outputting a data to/from a host, inputting/outputting a first data of the first storage region through the first interface, and inputting/outputting a second data of the second storage region through the second interface, wherein when the first data is programmed in the first storage region, the controller detects a value of the first data, selectively inverts the value of the first data based on the detection result, and program a resultant value, and when the second data is programmed in the second storage region, the controller detects a state of the second storage region where the second data is programmed, selectively inverts a value of the second data based on the state detection result, and program a resultant value.. . ... Sk Hynix Inc

07/26/18 / #20180210352

Methods of forming imprint patterns

A method of forming patterns is provided. The method may include forming a resist layer on a substrate and curing an extrusion confining pattern to define anchoring regions in the resist layer. ... Sk Hynix Inc

07/19/18 / #20180205377

Impedance calibration circuit and semiconductor apparatus including the same

An impedance calibration circuit includes a first detection unit configured to generate a first pull-up impedance detection signal according to a resistance value of an internal reference resistor, a second detection unit configured to generate a second pull-up impedance detection signal according to a resistance value of an external reference resistor coupled to an external reference resistor pad, a switching unit configured to select the first pull-up impedance detection signal or the second pull-up impedance detection signal according to the internal impedance calibration enable signal and output the selected pull-up impedance detection signal, and an impedance calibration signal generation unit configured to generate a plurality of impedance calibration signals according to an output of the switching unit.. . ... Sk Hynix Inc

07/19/18 / #20180204961

Image sensor having light refractive patterns

An image sensor is provided. The image sensor may include a photodiode formed in a substrate; a light refraction pattern formed on the photodiode; a color filter covering the light refraction pattern; and a micro-lens formed on the color filter.. ... Sk Hynix Inc

07/19/18 / #20180204850

Semiconductor device and manufacturing method of the same

A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.. . ... Sk Hynix Inc

07/19/18 / #20180204629

Input/output terminal characteristic calibration circuit and semiconductor apparatus including the same

An input/output terminal characteristic calibration circuit may include a plurality of input/output terminals a subset of which is configured to partially and selectively receive a characteristic calibration signal according to an external input, such that characteristics of the input/output terminals corresponding to the characteristic calibration signal are calibrated. The input/output terminal characteristic calibration circuit may also include a characteristic calibration signal generation circuit coupled to the plurality of input/output terminals in common through a test signal line, and configured to provide the characteristic calibration signal to the plurality of input/output terminals in common through the test signal line.. ... Sk Hynix Inc

07/19/18 / #20180204605

Semiconductor devices

A semiconductor device includes a latch signal generation circuit latching an external signal in synchronization with an internal clock signal to generate a latch signal, a test pulse generation circuit buffering the internal clock signal according to the latch signal to generate a test pulse signal, and a test period signal generation circuit generating a test period signal which is enabled, in response to a pulse of the test pulse signal, to execute a predetermined function.. . ... Sk Hynix Inc

07/19/18 / #20180203816

System including hot plug module and memory module

A system may include a host and a hot plug module. The hot plug module may include a training memory for performing a training operation with the host. ... Sk Hynix Inc

07/19/18 / #20180203775

Memory module, memory system including the same and operation method thereof

A memory module may include a first memory module comprising a plurality of first memory devices each having an extra memory region, a second memory module comprising a plurality of second memory devices each having an extra memory region, and a control logic suitable for writing/reading data to/from the first memory devices, wherein the control logic writes/reads target data to be transferred to/from a third memory device having an error among the first memory devices, to/from the extra memory regions of the second memory devices.. . ... Sk Hynix Inc

07/19/18 / #20180203760

Memory system and operation method thereof

A memory system may include: a nonvolatile memory device comprising a plurality of memory blocks; and a controller suitable for checking a read operation time, a read level class, an error occurrence, and an error occurrence class when performing the read operation on each of the memory blocks, classifying the memory blocks into various classes based on a result of the checking, and differently setting a durability parameter for each of the memory blocks based on a result of the classifying of the memory blocks.. . ... Sk Hynix Inc

07/19/18 / #20180203621

Semiconductor apparatus, memory module and operation method thereof

A memory module may be provided. The memory module may include a normal memory device, a spare memory device, and a row hammering determination circuit. ... Sk Hynix Inc

07/19/18 / #20180203616

Nonvolatile memory device and operating method thereof

A memory device may include a memory cell array having a plurality of memory cells, and a controller suitable for reading data of a memory cell corresponding to an address of write data, among the memory cells, and comparing the write data and the read data to check specific bits different from corresponding bits of the read data, among a plurality of bits of the write data, according to a write operation request. The controller may output a check result to outside after a preset time from the write operation request.. ... Sk Hynix Inc

07/12/18 / #20180198470

Operating method of memory system

An operating method of a memory system includes: reading a first data from a particular data group among a plurality of data groups included in a memory device; performing a first error correction code (ecc) decoding for the first data; when the first ecc decoding fails, reading a plurality of the remaining data other than the first data from the particular data group; performing a second ecc decoding for the plurality of the remaining data; when the second ecc decoding fails, identifying data, to which the second ecc decoding fails, among the plurality of the remaining data; obtaining first and second soft read values respectively corresponding to the first data, to which the first ecc decoding fails, and the second data, to which the second ecc decoding fails; determining reliability of the first and second data based on the first and second soft read values; and correcting the first data based on the reliability of the first and second data.. . ... Sk Hynix Inc

07/12/18 / #20180198468

Error correction code (ecc) decoders sharing logic operations, memory controllers including the error correction code decoders, and methods of decoding error correction codes

An error correction code (ecc) decoder includes a finite state machine (fsm) controller and a shared logic circuit. The fsm controller generates a first control signal and a second control signal each corresponding to a certain state. ... Sk Hynix Inc

07/12/18 / #20180197968

Nonvolatile storage circuit and semiconductor memory device including the same

A nonvolatile storage circuit may include a nonvolatile storage unit configured to include fuse set groups respectively including a plurality of fuse sets and a flag fuse; a rupture control unit configured to program an input address to the fuse sets in a first program mode, and to program a same input address to a specific fuse set among the plurality of fuse sets in a specific fuse set group among the fuse set groups and to program the flag fuse of the specific fuse set group in a second program mode; and a boot-up control unit configured to control the address programmed in the fuse sets to be outputted as fuse data, and to control the address programmed in the specific fuse set to be outputted as fuse data of remaining fuse sets among the plurality of fuse sets in the specific fuse set group.. . ... Sk Hynix Inc

07/12/18 / #20180197967

Nonvolatile memory device including multiple planes

A nonvolatile memory device includes bit lines arranged in a first direction over a substrate; a memory cell array disposed between the substrate and the bit lines, and including a plurality of planes which are arranged in a second direction perpendicular to the first direction; page buffer circuits disposed between the substrate and the memory cell array; contact pads disposed between the substrate and the memory cell array, the contact pads being suitable for electrically coupling the bit lines and the page buffer circuits; and routing lines disposed at the same layer as the contact pads, and extending in the second direction, wherein the contact pads are disposed to overlap with at least two lines which are arranged in the second direction, and the routing lines are formed in a bent pattern to pass between the contact pads which are disposed to overlap with different lines.. . ... Sk Hynix Inc

07/12/18 / #20180197880

Multi-level ferroelectric memory device and method of manufacturing the same

A ferroelectric memory device may include a semiconductor substrate, a plurality of ferroelectric layers, a source, a drain and a gate. The semiconductor substrate may have a recess. ... Sk Hynix Inc

07/12/18 / #20180197879

Multi-level ferroelectric memory device and method of manufacturing the same

A ferroelectric memory device may include a semiconductor substrate, a plurality of ferroelectric layers, a source, a drain and a gate. The semiconductor substrate may have a recess. ... Sk Hynix Inc

07/12/18 / #20180197866

Semiconductor device having buried gate structure and method for manufacturing the same, memory cell having the same and electronic device having the same

A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer.. . ... Sk Hynix Inc

07/12/18 / #20180197621

E-fuse circuit

An electrical fuse (e-fuse) circuit is disclosed, which relates to a technology for processing a failed part of the e-fuse circuit. The e-fuse circuit may be configured to detect failed data and or store a failed address.. ... Sk Hynix Inc

07/12/18 / #20180197597

Semiconductor devices

A semiconductor device may be provided. The semiconductor device may include an error scrub control circuit and or an active period signal generation circuit. ... Sk Hynix Inc

07/12/18 / #20180197590

Semiconductor device

Disclosed is a semiconductor device, including a memory cell array including a plurality of memory cells, a read circuit suitable for generating read data corresponding to a read current flowing in a first direction through a selected memory cell of the plurality of memory cells, a reverse read control circuit suitable for generating a reverse read control signal corresponding to the read data, and a reverse current generation circuit suitable for generating a reverse current flowing in a second direction through the selected memory cell in response to the reverse read control signal.. . ... Sk Hynix Inc

07/12/18 / #20180197587

Semiconductor device and operating method thereof

A semiconductor memory device may include a memory cell array. The semiconductor memory device may include a peripheral circuit coupled to the memory cell array through word lines. ... Sk Hynix Inc

07/12/18 / #20180196756

Address mapping method of memory system

Disclosed is an address mapping method of a memory system. The address mapping method may include grouping adjacent memory cells into multiple cubes, from a plurality of memory cells respectively located at intersections of a plurality of row lines and a plurality of column lines; allocating most significant bit (msb) n bits of a physical address for identifying the cubes; allocating least significant bit (lsb) m bits of the physical address for designating locations of memory cells included in each of the cubes, m and n being positive integers; storing information about a mapping between a logical address and the (m+n)-bit physical address in a mapping table; and when the logical address in response to an external request is received, translating the logical address to the physical address based on the mapping table.. ... Sk Hynix Inc

07/12/18 / #20180196749

Memory system and operating method of the same

An memory system includes a memory device that includes a first memory block and a super memory block including simultaneously controllable second memory blocks and a controller including a memory, and suitable for storing a data corresponding to a command in the memory, deciding a type of the command and a type of the data, and controlling the memory device to write the data in the first memory block or the super memory block based on the type of the command and the type of the data.. . ... Sk Hynix Inc

07/12/18 / #20180196713

Semiconductor device

A semiconductor device includes a write read control circuit for outputting a write enable signal which is enabled in response to a write command, and a test mode signal; and an error correction circuit suitable for performing a calculation operation of determining an error information of input data in response to the write enable signal and then outputting an internal parity signal including the error information, and outputting internal data by delaying the input data in response to the write enable signal.. . ... Sk Hynix Inc

07/12/18 / #20180196712

Apparatuses and methods for correcting errors and memory controllers including the apparatuses for correcting errors

An error correction apparatus may be provided. The error correction apparatus may be configured to perform a scrambling operation before an error correction code (ecc) operation is performed.. ... Sk Hynix Inc








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