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Sk Hynix Inc patents (2014 archive)


Recent patent applications related to Sk Hynix Inc. Sk Hynix Inc is listed as an Agent/Assignee. Note: Sk Hynix Inc may have other listings under different names/spellings. We're not affiliated with Sk Hynix Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Sk Hynix Inc-related inventors


12/25/14 / #20140380136

Semiconductor device, multichip package and semiconductor system using the same

A semiconductor device includes an error detection unit suitable for receiving data and a cyclic redundancy check (crc) code, and for outputting a detection signal by detecting a transmission error of the data, and a signal change unit suitable for generating error information based on the detection signal while changing a signal form of the error information based on a signal transmission environment of the data.. . ... Sk Hynix Inc

12/25/14 / #20140380110

Test apparatus and operating method thereof

A test apparatus includes a test apparatus may include a core suitable for accommodating a semiconductor device to be tested, a wrapper data register suitable for storing data used for testing the semiconductor device, and a bandwidth controller suitable for adaptively controlling a data bandwidth between the core and the wrapper data register according to the semiconductor device to be tested.. . ... Sk Hynix Inc

12/25/14 / #20140380109

Semiconductor memory device and method of operating the same

A semiconductor memory device and a method of operating the same are provided. The method of operating the semiconductor memory device includes detecting a first group of changed bits between first and second page data, by comparing the first and second page data, which are read out using first and second test voltages from the memory cells, respectively, detecting a second group of changed bits between the second page data and a third page data, by comparing the second page data with the third page data read out from the memory cells using a third test voltage, comparing the numbers of the first and second groups of changed bits, and determining one of the first to third test voltages as a read voltage according to the comparing of the numbers of the first and second groups of changed bits.. ... Sk Hynix Inc

12/25/14 / #20140380008

Memory system and operating method thereof

A memory system and an operating method thereof stably supplies power, so that it is possible to improve performance of a memory system by omitting an operation, which has been performed in order to prevent an error due to the blocking of a power supply, in a condition in which an error due to the blocking of the power supply may not be generated.. . ... Sk Hynix Inc

12/25/14 / #20140379995

Semiconductor device for controlling prefetch operation

A semiconductor device may include a pattern detector configured to select any one of a plurality of stride patterns as a detect pattern by referring to an input address, and the pattern detector may be configured to generate a prefetch address. The semiconductor device may also include a prefetch controller configured to generate a prefetch request according to the prefetch address generated by the pattern detector. ... Sk Hynix Inc

12/25/14 / #20140379982

Semiconductor memory device and memory system including the same

A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device, includes a memory cell array including a plurality of memory cells, a read and write circuit configured to store read data by sensing data stored in the plurality of memory cells and output the read data to input/output data lines in response to data read control signals, in a read operation, and an output controller configured to control the data read control signals so that activation intervals of the data read control signals generated in a cache read operation of the read operation are longer than those generated in a normal read operation of the read operation.. ... Sk Hynix Inc

12/25/14 / #20140376326

Semiconductor integrated circuit

A semiconductor integrated circuit includes a clock pulse generating circuit suitable for outputting a command enable clock pulse when a predetermined command is input during a predetermined command-masking period, a command interface circuit suitable for outputting an internal command signal based on the command enable clock pulse and the command, and a target operating circuit suitable for performing an operation corresponding to the command based on the internal command signal.. . ... Sk Hynix Inc

12/25/14 / #20140376315

Semiconductor device and method of operating the same

A semiconductor memory device includes a memory cell, a page buffer including a first and a second switching devices coupled in common to a sensing node coupled to the memory cell through a bit line and a first and a second sensing latch units coupled to the sensing node, respectively, through the first and the second switching devices, and a control logic suitable for transferring a first and a second sensing signals, respectively, to the first and the second switching devices when a threshold voltage of the memory cell is reflected on the sensing node through the bit line during a verification operation. The first and the second switching devices are turned on or off, respectively, in response to the first and the second sensing signals, and data are sensed by the first and the second sensing latch units.. ... Sk Hynix Inc

12/25/14 / #20140376314

Flash multiple-pass write with accurate first-pass write

An instruction to write to a location in the flash memory is received. It is determining if the flash memory exposes a level placement setting associated with defining what voltage range corresponds to what level. ... Sk Hynix Inc

12/25/14 / #20140376295

Memory device and system including the same

A memory device includes a plurality of first dies stacked on a substrate, and a second die configured to perform an error correction operation on data written in the first dies and data read out from the first dies.. . ... Sk Hynix Inc

12/25/14 / #20140376138

Semiconductor device

A semiconductor device includes an external voltage detection unit suitable for detecting a voltage level of an external voltage to output an external voltage detection signal based on the detected result, a reference voltage generation unit suitable for generating a reference voltage based on the external voltage, an internal voltage generation unit enabled in response to the external voltage detection signal, suitable for selectively generating a voltage corresponding to the reference voltage as an internal voltage, and an internal voltage control unit suitable for selectively providing a voltage having a target level corresponding to the internal voltage as the internal voltage in response to the external voltage detection signal.. . ... Sk Hynix Inc

12/25/14 / #20140375371

Semiconductor device for offset compensation of reference current

A semiconductor device includes a reference current generator suitable for generating a reference current, a current-voltage converter suitable for generating a first reference voltage and a second reference voltage in response to the reference current, and an analog-digital converter suitable for generating a digital code value based on a voltage difference between the first and second reference voltages, wherein the reference current generator includes a current control unit for controlling the reference current in response to the digital code value.. . ... Sk Hynix Inc

12/25/14 / #20140374923

Semiconductor apparatus and semiconductor system

Provided is a semiconductor apparatus including a plurality of semiconductor chips coupled through an electrical coupling unit. Each of the semiconductor chips includes: a chip id signal generation unit configured to generate a chip id signal; and a chip enable signal generation unit configured to receive a clock enable signal in response to the chip id signal, wherein one of the semiconductor chips shares the received clock enable signal as a transfer clock enable signal with the other semiconductor chips, and the chip enable signal generation unit detects whether or not an error occurs in the chip id signals of the plurality of semiconductor chips, selects any one of the transfer clock enable signal and the clock enable signal applied, and outputs the selected signal as a chip enable signal.. ... Sk Hynix Inc

12/25/14 / #20140374822

Semiconductor device and method for manufacturing the same

A semiconductor device and a method for manufacturing the same are disclosed, which include a gate electrode material in a recess or a buried gate cell structure, a polysilicon material doped with impurities over a sidewall of a recess located over the gate electrode material, and a junction formed by an annealing or a rapid thermal annealing (rta) process, thereby establishing a degree overlap between a gate electrode material of a buried gate and a junction.. . ... Sk Hynix Inc

12/25/14 / #20140374817

Non-volatile memory device

A non-volatile memory device includes: a semiconductor pillar stretched perpendicularly to a substrate; a plurality of memory cells stacked along the semiconductor pillar; a bit line coupled with a first end of the semiconductor pillar; a first source line coupled with one of the first end and a second end of the semiconductor pillar; a second source line disposed over the bit line and the first source line; a first switch having a first end coupled with the first source line and a second end coupled with a first voltage supplier, and controlling whether to supply a first voltage to the first source line; and a second switch having a first end coupled with the first source line and a second end coupled with the second source line, and controlling whether or not to supply a second voltage supplied from the second source line to the first source line.. . ... Sk Hynix Inc

12/25/14 / #20140374810

Semiconductor memory device

A semiconductor memory device includes: a plurality of first channel columns including a plurality of first channel layers that are arranged in a direction and offset by their centers; a plurality of second channel columns alternately arranged with the plurality of first channel columns and having a plurality of second channel layers that are arranged in the direction and offset by their centers; first insulating layers and first conductive layers alternately stacked to surround the first channel layers; second insulating layers and second conductive layers stacked to surround the second channel layers; and spacers placed between the first channel columns and the second channel columns and interposed between the first conductive layers and the second conductive layers.. . ... Sk Hynix Inc

12/25/14 / #20140374692

Semiconductor memory apparatus and fabrication method thereof

Semiconductor memory apparatus and a method of fabricating the same are provided. The semiconductor memory apparatus includes a semiconductor substrate in which a cell area and a peripheral area are defined, a plurality of pillars formed in the a cell area of the semiconductor substrate to a first depth, a stepped part formed in the peripheral area to a height corresponding to the first depth, a recessed part formed in the stepped part to a second depth, and a core switching device formed in the recessed part.. ... Sk Hynix Inc

12/25/14 / #20140374684

Variable resistance memory device and method of manufacturing the same

A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a multi-layered insulating layer formed on a semiconductor substrate on which a lower electrode is formed, and including a plurality of holes of which diameters are increased at a first height or higher, a variable resistance material layer formed on the lower electrode to a second height of each of the holes, and an upper electrode formed on the variable resistance material layer to be buried in each of the holes.. ... Sk Hynix Inc

12/25/14 / #20140374683

Variable resistance memory device and method of manufacturing the same

A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device may include a multi-layered insulating layer formed on a semiconductor substrate, on which a lower electrode is formed. ... Sk Hynix Inc

12/18/14 / #20140372839

Semiconductor device, semiconductor system and control method of semiconductor device

A semiconductor device includes a mode register set suitable for generating a first internal control signal and a second internal control signal, a per-dram addressability (pda) driving unit suitable for resetting the mode register set in response to the first internal control signal and an input value of data inputted through a data pad, and a cycle redundancy check (crc) driving unit suitable for performing a crc operation by checking whether or not data are correctly inputted through the data pad without an error in response to the first internal control signal and the second internal control signal.. . ... Sk Hynix Inc

12/18/14 / #20140372690

Memory system, semiconductor device and methods of operating the same

A memory system, a semiconductor memory device and methods of operating the same may perform a read operation on the basis of flag data stored in a flag register, without reading the flag data stored in a memory array, when performing the read operation, so that a time taken for the read operation may be reduced.. . ... Sk Hynix Inc

12/18/14 / #20140372664

Semiconductor memory device and memory system

A semiconductor memory device and a memory system are disclosed. The semiconductor memory device includes: a memory bank configured to include a first section and a second section, each of which is comprised of a plurality of memory cells; an lio line switching circuit configured to generate first and second selection signals on the basis of page-size information; and an input/output (i/o) circuit configured to access the first section, the second section, or the first and second sections on the basis of the first and second selection signals, wherein the page-size information includes first and second information. ... Sk Hynix Inc

12/18/14 / #20140370702

Semiconductor device and method for fabricating the same

A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment. ... Sk Hynix Inc

12/18/14 / #20140370679

Semiconductor device and method of manufacturing the same

A semiconductor device according an aspect of the present disclosure may include an isolation layer formed within a substrate and formed to define an active region, a junction formed in the active region, well regions formed under the isolation layer, and a plug embedded within the substrate between the junction and the well regions and formed extend to a greater depth than the well regions.. . ... Sk Hynix Inc

12/18/14 / #20140370676

Semiconductor device, memory system including the same, and method of manufacturing the same

The semiconductor device includes a vertical channel layer formed on a substrate; conductive layer patterns and insulating layer patterns alternately formed around a length of each of the vertical channel layer; and a charge storing layer pattern formed between each of the vertical channel layers and the conductive layer patterns, where each of the charge storing layer patterns is isolated by the insulating layer patterns.. . ... Sk Hynix Inc

12/18/14 / #20140370675

Semiconductor device

A semiconductor device includes a plurality of conductive layers and a plurality of insulating layers formed alternately with each other, at least one channel layer passing through the plurality of conductive layers and the plurality of insulating layers, and at least one first charge blocking layer surrounding the at least one channel layer, wherein a plurality of first regions, interposed between the at least one channel layer and the plurality of conductive layers, and a plurality of second regions, interposed between the at least one channel layer and the plurality of insulating layers, are alternately defined on the at least one first charge blocking layer, and each of the plurality of first regions has a greater thickness than each of the plurality of second regions.. . ... Sk Hynix Inc

12/18/14 / #20140369453

Receivers and semiconductor systems including the same

The receiver includes a first buffer configured to buffer a data to generate a first internal data, a first delay unit configured to retard the first internal clock signal by a first delay period to generate a first delayed internal clock signal, and a second buffer configured to buffer the first internal data to generate a first input data.. . ... Sk Hynix Inc

12/18/14 / #20140369153

Data strobe control device

A data strobe control device is disclosed, which relates to a technology for controlling a data write path of a semiconductor memory device. The data strobe control device includes: a plus-mode controller configured to output a first control signal for controlling a first mode and a plus on-the-fly signal upon receiving a plus-mode signal and an on-the-fly signal; an on-the-fly controller configured to output a second control signal for controlling a second mode according to the on-the-fly signal and an operation signal; a path controller configured to latch an address in response to the second control signal during the second mode, latch the address in response to the first control signal during the first mode, and accordingly output an address latch signal; and a strobe pulse generator configured to output a strobe control signal synchronized with a control clock signal in response to the address latch signal and a burst length signal.. ... Sk Hynix Inc

12/18/14 / #20140369150

Column decoders

Column decoders are provided. The column decoder includes a power supplier and a column selection signal generator. ... Sk Hynix Inc

12/18/14 / #20140369149

Word line drivers and semiconductor memory devices including the same

Word line drivers including a selection signal generator and a word line drive unit are provided. The selection signal generator generates a selection signal which is enabled according to a high-order address signal and a low-order address signal in an active mode. ... Sk Hynix Inc

12/18/14 / #20140369144

Chip tester and test method of semiconductor device

A chip tester includes a test unit suitable for performing a test on guarantee blocks and for detecting at least one second defective block from the guarantee blocks, a storage unit suitable for storing repair information, a determination unit suitable for comparing the number of available redundancy blocks, which are not allocated for first defective blocks, with the number of at least one second defective block, by referring to the repair information, and a guarantee block management unit suitable for updating the repair information to cancel allocation of at least one of a plurality of redundancy blocks based on a result of the comparison of the determination unit.. . ... Sk Hynix Inc

12/18/14 / #20140369140

Internal voltage generating circuit capable of controlling swing width of detection signal in semiconductor memory apparatus

An internal voltage generating circuit capable of controlling a swing width of a detection signal in a semiconductor memory apparatus is provided. The internal voltage generating circuit of a semiconductor memory apparatus includes an internal voltage level detecting unit configured to compare an internal voltage with a target voltage and then generate a detection signal, and an internal voltage level control unit configured to control the internal voltage based on a voltage level of the detection signal, wherein the internal voltage level detecting unit is configured to control a swing width of the detection signal based on a voltage difference between the internal voltage and the target voltage.. ... Sk Hynix Inc

12/18/14 / #20140369134

Semiconductor memory device and method of operating the same

A semiconductor memory device and a method of operating the same perform a program loop, including a program operation and a program verification operation based on a sub-verification voltage smaller than a target verification voltage and the target verification voltage, to the memory cells until a threshold voltage of the memory cells is greater than the target verification voltage. A positive voltage, supplied to the bit line of the memory cell of which the threshold voltage is higher than the sub-verification voltage, is increased whenever the program operation is performed, and thus a threshold voltage distribution of the memory cells may be improved.. ... Sk Hynix Inc

12/18/14 / #20140369133

Semiconductor memory device, memory system including the same, and operating method thereof

Disclosed are a semiconductor memory device, a memory system including the same, and an operation method thereof. The semiconductor memory device includes: a memory cell array including a plurality of memory cells; and a plurality of page buffers configured to supply currents to bit lines when a sensing operation is performed and sense currents of the bit lines to sense data of the plurality of memory cells and generate current paths between the bit lines and a ground according to program states of the plurality of memory cells.. ... Sk Hynix Inc

12/18/14 / #20140369131

Method of operating semiconductor device

A semiconductor device is operated by, inter alia: programming selected memory cells by applying a first program voltage which is increased by a first step voltage to a selected word line and by applying a first pass voltage having a constant level to unselected word lines, and when a voltage difference between the first program voltage and the first pass voltage reaches a predetermined voltage difference, programming the selected memory cells by applying a second program voltage which is increased by a second step voltage lower than the first step voltage to the selected word line and by applying a second pass voltage which is increased in proportion to the second program voltage to first unselected word lines adjacent to the selected word line among the unselected word lines.. . ... Sk Hynix Inc

12/18/14 / #20140369128

Semiconductor memory device and operation method thereof

A semiconductor memory device includes a memory cell suitable for having a predetermined cell state based on a data stored therein, a control signal generation unit suitable for generating a control signal for changing the cell state of the memory cell during a reading operation, an information storage unit suitable for storing a variation status information of the control signal to which a moment when the cell state of the memory cell changes is reflected, and an output unit suitable for outputting the variation status information of the control signal stored in the information storage unit as a signal corresponding to the data stored in the memory cell.. . ... Sk Hynix Inc

12/18/14 / #20140369121

Semiconductor device

Disclosed is a semiconductor device, including: an active region defined in a shape extended in at least four different directions in a semiconductor substrate; and gates of first to fourth transistors formed on extended portions of the active region, respectively, in which the first to fourth transistors share one junction area.. . ... Sk Hynix Inc

12/18/14 / #20140369109

Semiconductor memory device and memory system including the same

A semiconductor memory device includes a plurality of word lines each of which are connected to a plurality of memory cells, a row control unit suitable for sequentially activating and precharging a word line corresponding to a target address and a predetermined (n) number of adjacent word lines during a target activation mode, and a mode exit control unit suitable for counting the number of activation operations by the row control unit during the target activation mode to determine whether or not to exit from the target activation mode.. . ... Sk Hynix Inc

12/18/14 / #20140369106

Semiconductor device with fuse array and operating method thereof

A semiconductor device includes a fuse array for storing normal fuse data and pattern data through a programming operation, a boot-up control unit suitable for generating an enable signal for enabling an output of the pattern data, and a pattern detection unit suitable for detecting a pattern of the pattern data in response to the enable signal, and generating a detection signal. The fuse array outputs the normal fuse data in response to the detection signal.. ... Sk Hynix Inc

12/18/14 / #20140369095

Pumping circuit

A pumping circuit includes a charge pump configured to generate a pumping voltage based on a first voltage in response to an oscillation signal, and an oscillator configured to provide a period-controlled oscillation signal based on the first voltage and a second voltage.. . ... Sk Hynix Inc

12/18/14 / #20140368710

Pixel signal processing apparatus and cmos image sensor using the same

A cmos image sensor may include an active pixel sensor suitable for generating a pixel signal corresponding to incident light, a reference pixel array suitable for shielding incident light and generate a reference value, a readout circuit suitable for comparing the pixel signal and the reference value with a ramp signal and for removing a first noise of the pixel signal in a common mode, and a pixel signal processing circuit suitable for performing a linear operation on an output signal from the readout circuit and the reference value, and for removing a second noise of the pixel signal in the common mode.. . ... Sk Hynix Inc

12/18/14 / #20140368371

Amplifier using multi input differential pair, and comparator and analog-to-digital converting apparatus using the same

An amplifier includes a common load suitable for outputting an output signal, a coarse input differential stage, coupled to the common load, suitable for amplifying a difference between an input signal and a coarse ramping signal to output a coarse conversion signal as a first output signal, when the coarse ramping signal is lower than the input signal, and a fine input differential stage, coupled to the common load, suitable for amplifying a difference between a fine ramping signal and a bias signal and compensating the first output signal to output a fine conversion signal as the output signal, when a zero crossing occurs by the compensated first output signal.. . ... Sk Hynix Inc

12/18/14 / #20140368263

Voltage detection circuit and internal voltage generator using the same

A voltage detection circuit includes a voltage detection unit suitable for comparing a voltage level of a reference voltage terminal with a voltage level of an internal voltage terminal and for generating a detection signal based on a comparison result, a test reference voltage generating unit suitable for receiving an external reference voltage through a pad and for supplying the received external reference voltage to the reference voltage terminal as the reference voltage by using a first input resistance, during a test operation, and a normal reference voltage generating unit having a current mirror structure, wherein the normal reference voltage generating unit is suitable for generating an internal reference voltage, and for supplying the internal reference voltage to the reference voltage terminal as the reference voltage by using a second input resistance different from the first input resistance, during a normal operation.. . ... Sk Hynix Inc

12/18/14 / #20140368261

Semiconductor devices and semiconductor systems including the same

Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor device. ... Sk Hynix Inc

12/18/14 / #20140368256

Semiconductor systems

Semiconductor systems are provided. The semiconductor system includes a first semiconductor device and a second semiconductor device. ... Sk Hynix Inc

12/18/14 / #20140368252

Input and output device and system including the same

An i/o device comprises a driving unit coupled between a first voltage and a second voltage, and configured to receive a first signal so as to drive a second signal for swing with a second swing range narrower than a first swing range between the first voltage and the second voltage and supply the second signal to a transmission line. The driving unit includes a first stabilizer coupled between the first voltage and the transmission line and a second stabilizer coupled between the second voltage and the transmission line.. ... Sk Hynix Inc

12/18/14 / #20140368249

Delay control circuit

The present invention relates to a delay control circuit and technology in which the amount of delay can be regularly maintained although process, voltage, and temperature (pvt) conditions are changed. The delay control circuit of the present invention includes a zq calibration unit configured to generate an impedance code into which a change of pvt conditions has been incorporated, a voltage trimming unit configured to control a level of a trimming voltage at a calibration node, and a delay compensation unit configured to compensate for the amount of delay by controlling an effective capacitance value of a capacitor.. ... Sk Hynix Inc

12/18/14 / #20140368248

Flip-flop circuit and duty ratio correction circuit using the same

A flip-flop circuit includes a first unit configured to receive a reference clock signal and a reset signal, and a second unit configured to change an output node to a first level in response to the reference clock signal and change the output node to a second level by precharging the output node in response to a signal output from the first unit according to the reset signal.. . ... Sk Hynix Inc

12/18/14 / #20140368245

Duty rate detecter and semiconductor device using the same

A duty rate detection circuit includes a duty rate detection block suitable for outputting a duty rate detection signal by detecting a duty rate of a clock signal having a first logic duration and a second logic duration and an output control block suitable for comparing the number of the first logic duration and the number of the second logic duration for a detection period and controlling an output moment of the duty rate detection signal.. . ... Sk Hynix Inc

12/18/14 / #20140368243

Clock phase adjusting circuit and semiconductor device including the same

A semiconductor device includes a buffer suitable for receiving an input signal, a clock buffer suitable for receiving a clock, a delay locked loop (dll) suitable for delaying the clock to generate a delay locked clock, a code generation unit suitable for generating a digital code corresponding to 1/n of the clock cycle where n is an integer equal to or more than two, a delay unit suitable for delaying the clock corrected by the dll by a value corresponding to the digital code to output a delayed clock, and a strobing unit suitable for strobing the input signal using the delayed clock.. . ... Sk Hynix Inc

12/18/14 / #20140368241

Clock control device

A clock control device is disclosed, which relates to a technology for reducing the amount of current consumption when a semiconductor device operates at a high speed. The clock control device includes: a chip-select-signal control block configured to generate a chip-select-control signal by latching a chip select signal, and output a fast chip select signal according to the chip-select-control signal; and a clock control block configured to drive a clock signal in response to the fast chip select signal when a command clock enable signal is activated, thereby generating a clock control signal, wherein the chip-select-signal control block latches the chip-select-control signal, and controls the chip-select-control signal to be toggled after the command clock enable signal is transitioned.. ... Sk Hynix Inc

12/18/14 / #20140368238

Semiconductor device and semiconductor system including the same

A semiconductor device includes a normal code generation unit capable of generating a normal code, a test code output unit capable of storing a plurality of preliminary test codes to output a test code in response to a test control signal, and a reference voltage generation unit capable of generating a normal reference voltage in a normal operation mode and generating a test reference voltage in a test operation mode in response to the normal code and the test code.. . ... Sk Hynix Inc

12/18/14 / #20140368237

Driving device

A driving device is disclosed, which relates to a technology for reducing consumption of a leakage current unnecessary for a driver circuit. The driving device includes: a pre-driver configured to output a drive control signal upon receiving a power-supply voltage in response to an input signal, and change a voltage level of the drive control signal in response to a control signal so as to selectively provide the changed voltage level; an output driver configured to receive the power-supply voltage in response to the drive control signal, and output the received power-supply voltage to an output terminal; and a bulk-voltage controller configured to selectively control bulk-voltage levels of the pre-driver and the output driver in response to the control signal.. ... Sk Hynix Inc

12/18/14 / #20140368224

Test circuit and method for semiconductor device

A semiconductor device includes a first die, a second die coupled to the first die through a through-silicon-via (tsv), and a test circuit suitable for measuring a resistance of the tsv by controlling an amount of current flowing through the tsv.. . ... Sk Hynix Inc

12/18/14 / #20140368180

Reference voltage generator and voltage generating system having the same

A reference voltage generator includes a constant voltage generator suitable for using a high voltage as a first power supply voltage and for generating a constant voltage, and a first reference voltage generating unit suitable for using the constant voltage as a second power supply voltage and for generating a first reference voltage.. . ... Sk Hynix Inc

12/18/14 / #20140367851

Embedded packages, methods of fabricating the same, electronic systems including the same, and memory cards including the same

Embedded packages are provided. The embedded package includes a chip attached to a first surface of a core layer, a plurality of bumps on a surface of the chip opposite to the core layer, and a first insulation layer surrounding the core layer, the chip and the plurality of bumps. ... Sk Hynix Inc

12/18/14 / #20140367775

Semiconductor device and method for forming the same

A semiconductor device and a method for forming the same can block a moving path of electrons between neighbor buried gates. A semiconductor device includes a device isolation film formed to define an active region over a semiconductor substrate. ... Sk Hynix Inc

12/18/14 / #20140367769

Semiconductor device and method for manufacturing the same

A semiconductor device forms a salicide layer to surround an upper surface and a circumference of a lateral surface of a pillar. A contact area between the pillar and a lower electrode may be increased to reduce a contact resistance.. ... Sk Hynix Inc

12/18/14 / #20140367765

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source layer; a plurality of conductive layers stacked substantially over the first source layer; channel layers that pass through the plurality of conductive layers and couple to the second source layer; and at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer.. . ... Sk Hynix Inc

12/18/14 / #20140367761

Non-volatile memory device and method of fabricating the same

A non-volatile memory device may include a control plug formed over a substrate. A floating gate may be formed over the substrate, the floating gate surrounding the control plug and being separated from the control plug by a gap. ... Sk Hynix Inc

12/18/14 / #20140367756

Capacitor of nonvolatile memory device

The capacitor of a nonvolatile memory device includes first and second electrodes formed in the capacitor region of a semiconductor substrate to respectively have consecutive concave and convex shape of side surfaces formed along each other and a dielectric layer formed between the first and the second electrodes.. . ... Sk Hynix Inc

12/18/14 / #20140367551

Double data rate counter, and analog-digital converting appratus and cmos image sensor using the same

A double data rate (ddr) counter includes a clock selection unit suitable for selectively inverting a first counting clock based on a control signal and for outputting a second counting clock, a first latch stage suitable for latching the second counting clock based on a counting enable signal and for outputting the least significant bit (lsb) of the ddr counter, a determination unit suitable for generating the control signal based on the last bit state of the lsb in a reset counting period, and a second latch stage suitable for receiving the lsb as a clock input to generate a higher bit of the lsb at least in a main counting period.. . ... Sk Hynix Inc








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