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Sk Hynix Inc patents (2015 archive)


Recent patent applications related to Sk Hynix Inc. Sk Hynix Inc is listed as an Agent/Assignee. Note: Sk Hynix Inc may have other listings under different names/spellings. We're not affiliated with Sk Hynix Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Sk Hynix Inc-related inventors


12/31/15 / #20150381175

Semiconductor apparatus and reduced current and power consumption

A semiconductor apparatus may include a mode control circuit configured to output differential output signals which swing in a current mode logic (cml) area and a first control signal, in response to a power-down mode signal; a first circuit unit configured to be provided with the differential output signals, and operate in a power-down mode; and a second circuit unit configured to be provided with the differential output signals, and be interrupted in its operation in the power-down mode.. . ... Sk Hynix Inc

12/31/15 / #20150381155

Integrated circuit

An integrated circuit includes: a latch unit suitable for inverting a voltage level of a first node and driving a second node with the inverted voltage level of the first node, and inverting a voltage level of the second node and driving the first node with the inverted voltage level of the second node; and a sink unit coupled with one or more among the first and second nodes, and suitable for sinking a charge of the coupled node.. . ... Sk Hynix Inc

12/31/15 / #20150380429

Semiconductor device and method of manufacturing the same

A semiconductor device according to an embodiment of the invention includes a pipe channel layer including a first portion and a second portion protruding from the first portion, first channel pillars protruding from the second portion of the pipe channel layer, and second channel pillars protruding from the first portion of the pipe channel layer.. . ... Sk Hynix Inc

12/31/15 / #20150380426

Semiconductor device and method for manufacturing the same

A semiconductor device that includes a plurality of first conductive patterns stacked over a substrate, dummy patterns formed in the first conductive patterns, respectively, first barrier patterns each surrounding the respective first conductive patterns and partially interposed between the respective first conductive patterns and the respective dummy patterns, second barrier patterns each surrounding the respective first barrier patterns and the respective dummy patterns, a second conductive pattern located over or under the first conductive patterns, and a third barrier pattern surrounding the second conductive pattern, wherein the second conductive pattern has a greater thickness than the first conductive patterns.. . ... Sk Hynix Inc

12/31/15 / #20150380415

Semiconductor device and method for fabricating the same

A semiconductor device includes a bit line disposed over a semiconductor substrate, a supporting film being perpendicular to the bit line, a first storage node contact disposed at a lower part of a region disposed between the bit line and the supporting film, and a second storage node contact having a line shape, disposed over the first storage node contact and the bit line, isolated by the supporting film, and patterned in a diagonal direction across the bit line.. . ... Sk Hynix Inc

12/31/15 / #20150380407

Semiconductor device and method for fabricating the same

A method for fabricating a semiconductor device includes: forming a gate dielectric layer over a substrate; forming an etch stop layer over the gate dielectric layer; forming a first work function layer that covers a first portion of the etch stop layer and a sacrificial compound that covers a second portion of the etch stop layer; exposing the second portion of the etch stop layer by removing the sacrificial compound; and forming a second work function layer over the second portion of the etch stop layer and the first work function layer.. . ... Sk Hynix Inc

12/31/15 / #20150380402

Power integrated devices, electronic devices including the same and electronic systems including the same

A power integrated device includes a gate electrode on a substrate, a source region and a drain region disposed in the substrate at two opposite sides of the gate electrode, a drift region disposed in the substrate between the gate electrode and the drain region to be spaced apart from the source region, and a plurality of insulating stripes disposed in an upper region of the drift region to define at least one active stripe therebetween. Related electronic devices and related electronic systems are also provided.. ... Sk Hynix Inc

12/31/15 / #20150380366

Semiconductor package

A semiconductor package including a first metal layer configured for use as a bonding pad, a second metal layer formed over the first metal layer, and the second metal layer having a separation allowing for the second metal layer to be positioned above distal ends of the first metal layer. The semiconductor package also including a third metal layer formed over the second metal layer, and the third metal layer having a separation allowing for the third metal layer to be positioned above distal ends of the first metal layer, a trench defined by the separation of the third metal layer and second metal layer, and extending through the third metal layer and the second metal layer to expose the first metal layer, and a bonding ball located within the trench.. ... Sk Hynix Inc

12/31/15 / #20150380253

Method for fabricating semiconductor device

A method for fabricating a semiconductor device includes: preparing a substrate; performing a pre-treatment including a first hydrogen annealing on a surface of the substrate; forming a gate dielectric layer over the substrate; performing a post-treatment including a second hydrogen annealing on the substrate including the gate dielectric layer; and forming a gate electrode over the gate dielectric layer.. . ... Sk Hynix Inc

12/31/15 / #20150380105

Semiconductor devices and semiconductor systems including the same

The semiconductor system includes a controller and a semiconductor device. The controller outputs commands and receives an output datum to discriminate whether at least one of a plurality of fuse cells abnormally operates. ... Sk Hynix Inc

12/31/15 / #20150380104

Latch circuit and semiconductor device including the same

A latch circuit includes a write driving unit configured to output fuse data as boot-up data according to a fuse set select signal in a boot-up operation; and a latch set configured to latch the boot-up data when a latch select signal is activated in the boot-up operation, and output data latched as the latch select signal is activated as a repair column address in a normal operation.. . ... Sk Hynix Inc

12/31/15 / #20150380089

Three dimensional semiconductor memory device with line sharing scheme

A semiconductor memory device includes a memory array including memory blocks stacked in a plurality of layers over a substrate and an operation circuit suitable for performing a read operation and a program loop to memory cells included in the memory blocks, wherein word lines of the memory blocks are coupled to each other and a pair of the memory blocks are arranged vertically adjacent to each other and share bit lines.. . ... Sk Hynix Inc

12/31/15 / #20150380075

Semiconductor package

A semiconductor package may include a first die and a second die disposed adjacent to the first die. The semiconductor package may include a plurality of pads configured for receiving and outputting data mask addresses. ... Sk Hynix Inc

12/31/15 / #20150380074

Semiconductor devices and semiconductor systems including the same

The semiconductor memory device includes a power control signal generator and a sense amplifier circuit. The power control signal generator generates a first power control signal that is enabled in response to a temperature latch signal generated in response to latching a temperature signal in a predetermined mode. ... Sk Hynix Inc

12/31/15 / #20150380073

Memory device

A memory device includes a counter suitable for counting the number of times that a periodic wave is enabled and generating a code, one or more memory banks each including a plurality of word lines, and one or more measurement blocks corresponding to the memory banks, respectively, and suitable for measuring an active period of an activated word line in a corresponding memory bank among the memory banks, wherein each of the measurement blocks measures the active period of the activated word line based on a first value of the code at an activation starting point of the corresponding memory bank and a current value of the code.. . ... Sk Hynix Inc

12/31/15 / #20150380070

Latch circuit and input/output device including the same

A latch circuit includes an input block configured to latch first group input addresses and second group input addresses and output first group internal addresses, according to states of select signals; and a latch block configured to latch the first group internal addresses corresponding to a first active command when a first active control signal is activated, and output the first group internal addresses and second group internal addresses as row addresses corresponding to a second active command when a second active control signal is activated.. . ... Sk Hynix Inc

12/31/15 / #20150380068

Semiconductor memory device and method for operating the same

A semiconductor memory device includes: an enable signal generation portion suitable for generating a data output enable signal activated at a predetermined first moment corresponding to column address strobe (cas) latency based on a read command, a strobe signal generation portion suitable for generating a data strobe signal which has a preamble section until the data output enable signal is activated from a predetermined second moment ahead of the first moment based on the read command and toggles based on a source clock during an activated section of the data output enable signal, and a data output portion suitable for outputting internal data in synchronization with the data strobe signal during the activated section of the data output enable signal.. . ... Sk Hynix Inc

12/31/15 / #20150380066

Data storage device and operating method thereof

A data storage device includes a memory device suitable to perform an internal operation; a processor suitable to generate command generation information to command performance of the s internal operation; and a command set processing block suitable to generate a command set, which is provided to the memory device, based on the command generation information, wherein the command set processing block generates a final sequence which configures a pattern included in the command set.. . ... Sk Hynix Inc

12/31/15 / #20150380060

Semiconductor device

A semiconductor device includes a first cell array region disposed adjacent to a second cell array region; a dummy cell region disposed between the first cell array region and the second cell array region, and configured to distinguish the first cell array region from the second cell array region by dummy bit lines; first group segment input/output lines disposed to correspond to the first cell array region when viewed in terms of the dummy bit lines; and second group segment input/output lines disposed to correspond to the second cell to array region when viewed in terms of the dummy bit lines.. . ... Sk Hynix Inc

12/31/15 / #20150377966

Monitoring circuit of semiconductor device

The monitoring circuit of a semiconductor device includes: a boot-up controller configured to generate a boot-up enable signal in response to a power-up signal and a boot-up command signal; a read-period generator configured to output a read-period signal in response to a boot-up read signal; and a monitoring unit configured to output the read-period signal to an external output terminal during activation of the boot-up enable signal to allow the read-period signal to be monitored.. . ... Sk Hynix Inc

12/24/15 / #20150372135

Semiconductor device having vertical channel, resistive memory device including the same, and method of manufacturing the same

A semiconductor device includes a semiconductor substrate having a first conductivity type, a plurality of pillars extending to a direction perpendicular to a surface of the semiconductor substrate, a stress providing layer formed in the semiconductor substrate between pillars and forming a junction with the semiconductor substrate below each pillar to cause lattice deformation in the pillar, a source region having a second conductivity type opposite to the first conductivity type formed in the semiconductor substrate below the pillar, a drain region having the second conductivity type formed in an upper portion of the pillar, a gate insulating layer formed on a lateral surface of the pillar and a surface of the stress providing layer, and a gate electrode formed to surround the lateral surface of the pillar.. . ... Sk Hynix Inc

12/24/15 / #20150372117

Semiconductor device

A semiconductor device includes a plurality of epitaxial layers stacked over a supportive substrate, a first buried impurity region formed to share the supportive substrate with a lowermost epitaxial layer among the multiple epitaxial layers, one or more second buried impurity regions formed to be coupled with the first buried impurity region and share an nth epitaxial layer and an (n+1)th epitaxial layer among the multiple epitaxial layers, where n is a natural number, a body region formed in an uppermost epitaxial layer among the multiple epitaxial layers and a deep well formed in the uppermost epitaxial layer to surround the body region and to be coupled with the second buried impurity regions that share the uppermost epitaxial layer.. . ... Sk Hynix Inc

12/24/15 / #20150372061

Methods of manufacturing semiconductor devices including a cross point cell atrray

A method of fabricating a semiconductor device is provided. The method includes an intermediate pattern structure on a substrate. ... Sk Hynix Inc

12/24/15 / #20150372059

Semiconductor apparatus and method for fabricating the same

A semiconductor apparatus includes a variable resistor including a variable resistance layer, which is formed to surround on an inner surface of a resistive region, and an insert layer which is formed in the variable resistance layer and has a resistivity being different from that of the variable resistance layer.. . ... Sk Hynix Inc

12/24/15 / #20150372058

Method for fabricating semiconductor apparatus

A method for fabricating a semiconductor apparatus includes forming a diffusion barrier film on a semiconductor substrate, forming a first film on a semiconductor substrate including a common source region, forming a second film on the first film, forming a conductive film on the second film, patterning the conductive film and the second film, to form an active pattern, and patterning the first film and the semiconductor substrate using the active pattern as a mask, to form a pillar; and forming a gate electrode on an outer circumference of the pillar.. . ... Sk Hynix Inc

12/24/15 / #20150372057

Three dimensional semiconductor device having lateral channel

A 3d semiconductor device and a method of manufacturing the same are provided. The 3d semiconductor device includes a semiconductor substrate, an active line formed on the insulating layer, including a source region, a drain region and a channel region positioned between the source region and the drain region, a gate electrode located on a portion of the active line, corresponding to a region between the source region and the drain region, and extending to a direction substantially perpendicular to the active line, and a line-shaped common source node formed to be electrically coupled to the source region and extending substantially in parallel to the gate electrode in a space between gate electrodes. ... Sk Hynix Inc

12/24/15 / #20150372050

Image sensor having lens type color filter and method for fabricating the same

The image sensor includes lens-type color filters having a uniform shape for a plurality of pixels. The image sensor includes a plurality of pixels formed in a substrate, a plurality of color filter housings formed over outer boundaries of the respective pixels, and a plurality of color filters filled in spaces defined by the respective color filter housings, wherein the clock filter housings surround edges of the respective color filters with a given curvature.. ... Sk Hynix Inc

12/24/15 / #20150371993

Semiconductor device and method of manufacturing the same

A semiconductor device includes a stacked structure including conductive layers and insulating layers stacked alternately with each other, first semiconductor patterns passing through the stacked structure and arranged in a first direction, second semiconductor patterns passing through the stacked structure and arranged in the first direction, wherein the second semiconductor patterns are adjacent to the first semiconductor patterns in a second direction crossing the first direction, air gaps located between the first semiconductor patterns and the second semiconductor patterns and extending in the first direction, and at least one blocking pattern passing through the stacked structure and filling portions of the air gaps.. . ... Sk Hynix Inc

12/24/15 / #20150371988

Semiconductor device, resistor and manufacturing method of the same

A resistor includes a first conductive layer; a second conductive layer protruding from the first conductive layer; a third conductive layer located above and facing the first conductive layer to face the first conductive layer; and at least two contact plugs electrically coupled to the third conductive layer.. . ... Sk Hynix Inc

12/24/15 / #20150371944

Semiconductor device and method of manufacturing the same

A semiconductor device includes a plurality of transistors formed over a substrate, a support body including a horizontal portion and protrusions, wherein the horizontal portion covers at least one of the transistors, and the protrusions are formed over the horizontal portion and located between the transistors, and conductive layers and insulating layers alternately stacked over the support body and protruding upwardly along the sidewalls of the protrusions.. . ... Sk Hynix Inc

12/24/15 / #20150371891

Semiconductor device with air gap and method for fabricating the same

A method for fabricating a semiconductor device includes forming an insulation layer over a substrate; forming an open portion in the insulation layer; forming a sacrificial spacer over sidewalls of the open portion; forming, over the sacrificial spacer, a first conductive pattern in a lower section of the open portion; forming an ohmic contact layer over the first conductive pattern; forming an air gap by removing the sacrificial spacer; capping the air gap by forming a barrier layer over the ohmic contact layer; and forming a second conductive pattern over the barrier layer to fill an upper section of the open portion.. . ... Sk Hynix Inc

12/24/15 / #20150371717

Semiconductor memory device

A semiconductor memory device includes a voltage supply part suitable for providing a predetermined test detection voltages to a pair of bit lines respectively, during a test operation for detecting a failure between a word line and the pair of bit lines; a column connection section suitable for electrically coupling the pair of bit lines and a pair of segment lines to each other, respectively, in response to a column selection signal; and a precharge section suitable for precharging the pair of segment lines to a precharge voltage corresponding to one of the test detection voltages during a failure detection time section while performing the test operation.. . ... Sk Hynix Inc

12/24/15 / #20150371713

Semiconductor memory device and method of operating the same

A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array including memory blocks, a voltage generator configured to generate a precharge voltage; and a read and write circuit coupled to the memory blocks through bit lines, and configured to supply the precharge voltage to the bit lines when a selected memory block is accessed. ... Sk Hynix Inc

12/24/15 / #20150371700

Semiconductor memory device and operating method thereof

A semiconductor memory device includes an oscillating signal generation section suitable for generating an oscillation signal oscillating with a period, which is defined by a predetermined temperature-period function, a period control section suitable for controlling the period of the oscillation signal according to a combination of two or more predetermined temperature-period functions, which are different from one another, in response to a refresh characteristic information, and a memory cell array suitable for performing a refresh operation in response to the oscillation signal.. . ... Sk Hynix Inc

12/24/15 / #20150371699

Oscillator and memory device including the same

An oscillator includes a comparison means suitable for generating a comparison signal by comparing an internal voltage of an internal node with a reference voltage; an inverting unit suitable for inverting the comparison signal and transmitting the inverted comparison signal to an output node; a pull-up driving unit suitable for pull-up driving the internal node in response to the voltage of the output node; a discharge unit suitable for discharging the internal node; and a gate coupled between the internal node and the discharge unit, and turned on/off in response to the voltage of the output node, wherein at least part of a capacitive load included in the oscillator is electrically coupled to the internal node.. . ... Sk Hynix Inc

12/24/15 / #20150371692

Semiconductor device and method for operating the same

A semiconductor device may include a first pad suitable for inputting a dock, a plurality of second pads suitable for inputting data through a plurality of first data paths, a third pad suitable for inputting a first strobe signal through a first strobe signal path, a data latch unit suitable for latching the data inputted through the first data paths in response to the first strobe signal inputted through the first strobe signal path, and a calibration control unit suitable for calibrating delay values of the plurality of first data paths and the first strobe signal path in a first calibration mode such that a plurality of first test signals passing through the respective first data paths and a second test signal passing through the first strobe path are in phase with the clock inputted from the first pad.. . ... Sk Hynix Inc

12/24/15 / #20150371691

Semiconductor device and method for operating the same

A semiconductor device may include: a plurality of data pads; a plurality of data buffers each suitable for buffering a signal inputted through a first input node using a voltage inputted through a second input node, and outputting the buffered signal; and a calibration control unit suitable for generating a test signal in a calibration mode, adjusting the level of the test signal, receiving outputs of the plurality of data buffers while adjusting the level of the test signal, and adjusting offsets of the data buffers such that the logical values of the outputs of the data buffers transit when the test signal has a target level.. . ... Sk Hynix Inc

12/24/15 / #20150370731

Memory system and method for operating the same

A memory system includes a common data bus, a common control bus, memory devices suitable for sharing the common data bus and the common control bus, wherein the memory devices each have different latencies for recognizing control signals of the common control bus, and a controller suitable for controlling the memory devices through the common data bus and the common control bus.. . ... Sk Hynix Inc

12/24/15 / #20150370481

Semiconductor device

A semiconductor device may include a memory block including a plurality of memory cells, and an operation circuit configured to perform a first program loop, a second program loop, and a third program loop based on data stored in the memory cells. The first program loop may distribute threshold voltages of the memory cells into four levels. ... Sk Hynix Inc

12/17/15 / #20150365104

Semiconductor memory apparatus and training method using the same

A semiconductor memory apparatus may include a cyclic redundancy check (crc) circuit block electrically coupled with a first pad, and configured to generate internal crc information from data received from the first pad. The semiconductor memory apparatus may also include a comparison unit configured to compare external crc information received from outside the semiconductor memory apparatus with the internal crc information, and generate a read training result signal.. ... Sk Hynix Inc

12/17/15 / #20150365078

Semiconductor apparatus and regulation circuit thereof

A regulation circuit of a semiconductor apparatus includes a control block configured to generate control signals in response to a reference clock signal and a feedback clock signal; and a noise compensation block configured to compensate for a variation in a level of power in response to the control signals.. . ... Sk Hynix Inc

12/17/15 / #20150364447

Semiconductor device

A semiconductor device includes a package interface including n numbers of first group of data balls which are disposed on a first side thereof, n numbers of second group of data balls which are disposed on a second side thereof, and m numbers of command/address balls which are disposed between the first side and the second side; a first semiconductor chip which is stacked on the first side over the package interface, and includes 2n numbers of first group of data pads and m numbers of first command/address pads; and a second semiconductor chip which is stacked on the second side over the package interface, and includes 2n numbers of second group of data pads and m numbers of second command/address pads.. . ... Sk Hynix Inc

12/17/15 / #20150364381

Method of manufacturing 3d semiconductor integrated circuit device

A method of manufacturing a semiconductor integrated circuit device is provided. The method includes forming a plurality of pillars in a semiconductor substrate, forming an insulating layer between the plurality of pillars in such a manner that an upper region of each pillar protrudes, forming a silicide layer on an exposed surface of the pillar, and forming an insulating layer for planarization in a space between pillars.. ... Sk Hynix Inc

12/17/15 / #20150364219

Semiconductor apparatus with repair information control function

A semiconductor apparatus may include a global line configured to enable electrical coupling between a memory block and an input/output terminal, a fuse array configured to store and to transmit repair information through the global line, and a control unit configured to selectively enable or disable signal paths among the input/output terminal, the global line, and the fuse array according to an operation mode of the semiconductor apparatus.. . ... Sk Hynix Inc

12/17/15 / #20150364217

Semiconductor device and operation method thereof

A semiconductor device includes a latch circuit suitable for storing a test result; a non-volatile memory circuit suitable for staring information used for an operation of the semiconductor device; a decoding unit suitable for generating one or more internal program commands by using one or more control signals; and a control unit suitable for programming information in the non-volatile memory circuit in response to the test result stored in the latch circuit when the internal program commands are activated.. . ... Sk Hynix Inc

12/17/15 / #20150364210

Semiconductor device with fuse array and method for operating the same

A semiconductor device includes a fuse array including verification fuses and normal fuses, a determination block suitable for reading data programmed in the verification fuses based on a read reference voltage and during a boot-up preparation section, determining whether or not a read value is the same as a predetermined value, and a level control block suitable for adjusting a level of the read reference voltage based on a determined result during the boot-up preparation section.. . ... Sk Hynix Inc

12/17/15 / #20150364208

Semiconductor device

A semiconductor device includes a memory block including memory cells coupled to word lines, and an operation circuit suitable for performing a program operation and a verify operation on memory cells coupled to a selected word line, wherein, when performing the program operation, the operation circuit applies a first program allowance voltage to a bit line of a first program fail cell to keep a program fail status, and a second program allowance voltage having a voltage level different from the first program allowance voltage to a bit line of a second program fail cell to change a program pass status to a program fail status.. . ... Sk Hynix Inc

12/17/15 / #20150364197

Semiconductor memory device, memory system having the same and operating method thereof

An embodiment of the invention may provide a semiconductor memory device including a memory cell array including a plurality of memory cells, a peripheral circuit unit configured to perform a program operation with respect to a memory cell selected from the plurality of memory cells, wherein first to third program voltage applying operations and first to third verifying operations are alternatively performed, and a control logic configured to control the peripheral circuit unit to perform the first to third program voltage applying operations and the first to third verifying operations and to increase a second program voltage applied during the second program voltage applying operation more than a first program voltage applied during the first program applying operation by a first step voltage and a third program voltage applied during the third program voltage applying operation more than the second program voltage by a second step voltage.. . ... Sk Hynix Inc

12/17/15 / #20150364185

Semiconductor device and method of operating the same

A method of operating a semiconductor device includes performing a program operation on selected memory cells of a selected page, and selectively performing a soft erase operation on memory cells having threshold voltages greater than a reference voltage, among the selected memory cells, to reduce a width of a threshold voltage distribution of the selected memory cells.. . ... Sk Hynix Inc

12/17/15 / #20150364177

System including memories sharing calibration reference resistor and calibration method thereof

A semiconductor apparatus includes a first memory, a second memory, and a shared reference resistor. The first memory is electrically coupled to the shared reference resistor, and the second memory is also electrically coupled to the shared reference resistor. ... Sk Hynix Inc

12/17/15 / #20150364176

Electronic system generating multi-phase clocks and training method thereof

An electronic system includes a memory controller and a memory. The memory controller generates a plurality of controller clocks having different phases from one another based on a reference clock signal. ... Sk Hynix Inc

12/17/15 / #20150364174

Word line driver circuit and resistance variable memory apparatus having the same

A world line driver circuit according to an embodiment includes a driving unit configured to output a sub word line driving signal in response to a word line select signal and a main word line driving signal, a transmission unit configured to transmit the sub word line driving signal to a word line in response to a first enable signal, and a precharge unit configured to precharge a potential of the word line.. . ... Sk Hynix Inc

12/17/15 / #20150364172

Semiconductor apparatus configured to manage an operation timing margin

A semiconductor apparatus may include a read path configured to transmit data from the semiconductor apparatus in response to a read command and at least one read operation control signal, and an operation control circuit configured to receive a plurality of divided clock signals and the read command to identify the one of the plurality of divided clock signals that is relatively better matched to the received read command to manage timings associated with at least one of the read operation control signals.. . ... Sk Hynix Inc

12/17/15 / #20150364167

Integrated circuit and precharge/active flag generation circuit

An integrated circuit includes a first stage including first logic gates each of which performs a first logic operation on a corresponding signal among first to nth signals and a first bit of a binary code, and a second stage including second logic gates each of which performs a second logic operation on corresponding output signals of the first logic gates and is reset based on a second bit of the binary code.. . ... Sk Hynix Inc

12/17/15 / #20150364166

Semiconductor device

A semiconductor device includes: a sense amplification block suitable for sensing and amplifying a data loaded on a pair of data lines based on a pull-up driving voltage supplied through a pull-up power source line and a pull-down driving voltage supplied through a pull-down power source line; and a voltage supply block suitable for supplying a first high voltage as the pull-up driving voltage to the pull-up power source line and a first low voltage as the pull-down driving voltage to the pull-down power source line in a first mode, and supplying the first high voltage as the pull-up driving voltage to the pull-up power source line and a second low voltage having a voltage level lower than a voltage level of the first low voltage as the pull-down driving voltage to the pull-down power source line during an initial period of a second mode which is a subsequent mode of the first mode.. . ... Sk Hynix Inc

12/17/15 / #20150364165

Semiconductor apparatus

A semiconductor apparatus includes a first memory bank configured to store data transmitted through a first data line; and a precharge block configured to precharge the first data line to a level of a first voltage or a second voltage.. . ... Sk Hynix Inc

12/17/15 / #20150364164

Precharge circuit and semiconductor apparatus including the same

A semiconductor apparatus includes a memory region configured to store data transmitted through a first data line and a second data line; and a precharge block configured to precharge the second data line to a level of a first voltage and precharge the first data line to a level of a second voltage higher than the level of the first voltage, based on a write signal.. . ... Sk Hynix Inc

12/17/15 / #20150364163

Integrated circuits and semiconductor systems including the same

A integrated circuit may include an input buffer suitable for buffering a strobe signal in response to a buffer enablement signal to generate an internal strobe signal, an internal clock generator suitable for receiving the internal strobe signal to generate internal clock signals including different phases. The integrated circuit may include a strobe signal driver suitable for driving the strobe signal in response to a drive control signal. ... Sk Hynix Inc

12/17/15 / #20150364161

Electronic device and electronic system including the same

An electronic device includes a power-up signal generation circuit block suitable for generating a power-up signal during a power-up section of a source voltage, a delay circuit block suitable for generating a plurality of delay signals by sequentially delaying the power-up signal, and a plurality of internal circuit blocks sequentially initialized in response to a corresponding one of the power-up signal and the delay signals.. . ... Sk Hynix Inc

12/17/15 / #20150362945

Internal voltage generation circuit of semiconductor apparatus

An internal voltage generation circuit may include a first internal voltage generation block configured for receiving a first external voltage and for generating an internal voltage with a voltage level corresponding to a voltage level of a first reference voltage; and a second internal voltage generation block configured for receiving a second external voltage, generate the internal voltage with a voltage level corresponding to a voltage level of a second reference voltage, compare voltage levels of the second reference voltage and the internal voltage, and generate a comparison signal, wherein only one of the first and second internal voltage generation blocks is activated and the other is deactivated, in response to an enable signal, and the second internal voltage generation block disables the comparison signal to a voltage level of the first external voltage when the first internal voltage generation block is activated.. . ... Sk Hynix Inc

12/10/15 / #20150358010

Stacked semiconductor apparatus being electrically connected through through-via and monitoring method

A semiconductor apparatus includes a plurality of stacked chips. Each of the plurality of stacked chips includes a delay chain. ... Sk Hynix Inc

12/10/15 / #20150357377

Semiconductor integrated circuit device having reservoir capacitor and method of manufacturing the same

A semiconductor integrated circuit device having a reservoir capacitor and a method of manufacturing the same are provided. A first insulating layer is formed on a semiconductor substrate including a first region and a second region. ... Sk Hynix Inc

12/10/15 / #20150357364

Image sensor

An image sensor includes a plurality of pixels arranged in two dimensions, wherein at least one pixel includes: a photoelectric conversion layer formed in a substrate; a first color filter layer formed over the photoelectric conversion layer; and a second color filter layer formed over the first color filter layer and defining an opening that is eccentrically formed with respect to an optical axis of the photoelectric conversion layer.. . ... Sk Hynix Inc

12/10/15 / #20150357052

Semiconductor memory device

A semiconductor memory device includes: a memory cell array region having a plurality of normal cell lines and a plurality of repair cell lines; a plurality of normal cell line selection units suitable for selecting the plurality of normal cell lines, respectively, in response to a local address; a plurality of repair cell line selection units suitable for selecting the plurality of repair cell lines, respectively, in place of normal cell line selection units corresponding to fail information of the local address; a fuse driving unit comprising a fuse array in which the fail information is programmed, suitable for disabling the normal cell line selection units corresponding to the fail information, and enabling normal cell line selection units unrelated to the fail information; and an address determination unit suitable for controlling the plurality of repair cell line selection units based on the fail information.. . ... Sk Hynix Inc

12/10/15 / #20150357051

Semiconductor memory device

A semiconductor memory device includes: a memory cell array region having a plurality of normal cell lines and a plurality of repair cell lines; a plurality of normal cell line selection units suitable for selecting the plurality of normal cell lines, respectively, in response to a local address; a plurality of repair cell line selection units suitable for selecting the plurality of repair cell lines, respectively, in place of normal cell line selection units corresponding to fail information of the local address; a fuse driving unit comprising a fuse array in which the fail information is programmed, suitable for disabling the normal cell line selection units corresponding to the fail information, and enabling normal cell line selection units unrelated to the fail information; and an address determination unit suitable for controlling the plurality of repair cell line selection units based on the fail information.. . ... Sk Hynix Inc

12/10/15 / #20150357048

Semiconductor memory apparatus and test method thereof

A semiconductor memory apparatus may include a read/write circuit unit configured to receive an external voltage, to read data from a memory cell array, and to generate a pre-read signal, while an internal voltage is generated during a test mode, and a controller configured to selectively drive a write circuit unit in response to the pre-read signal.. . ... Sk Hynix Inc

12/10/15 / #20150357037

High voltage generating circuit for resistive memory apparatus

A high voltage generating circuit for a resistive memory apparatus is provided. The high voltage generating circuit includes a capacitor spaced from a semiconductor substrate and electrically insulated from the semiconductor substrate. ... Sk Hynix Inc

12/10/15 / #20150357004

Stack bank type semiconductor memory apparatus capable of improving alignment margin

A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks.. ... Sk Hynix Inc

12/10/15 / #20150357003

Stack bank type semiconductor memory apparatus capable of improving alignment margin

A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks.. ... Sk Hynix Inc

12/10/15 / #20150355854

Semiconductor memory device, memory system including the same, and operating method thereof

A semiconductor memory device may include a memory cell array, and a program and verify circuit configured to perform a write operation on the memory cell array by repeating a plurality of program and verify operations. When the write operation is stopped after a first program operation is performed according to a first program condition, the pnv circuit may perform a first verify operation corresponding to the first program operation according to a first target value, after the write operation has resumed.. ... Sk Hynix Inc

12/03/15 / #20150349109

Semiconductor device and method of manufacturing the same

A semiconductor device may include interlayer insulating layers stacked in a first direction and separated from each other, word lines formed between the interlayer insulating layers, and sacrificial insulating layers formed between the interlayer insulating layers so that the sacrificial insulating layers are arranged at layers where the word lines are formed. The semiconductor device may also include cell contact plugs each including a first pillar portion passing through at least one of the interlayer insulating layers and the sacrificial insulating layers in the first direction, and a first protruding portion protruding from a sidewall of the first pillar portion and contacting a sidewall of one of the word lines, wherein the cell contact plugs have different depths.. ... Sk Hynix Inc

12/03/15 / #20150349074

Electronic device comprising a semiconductor memory unit

Devices and methods based on disclosed technology include, among others, an electronic device capable of improving a signal transfer characteristic and a method for fabricating the same. Specifically, an electronic device in one implementation includes a plurality of buried gates formed in a substrate, open parts formed in the substrate on both sides of the buried gate, isolation layers each formed between a sidewall of the open part and a sidewall of the buried gate, source/drain regions formed in the substrate under the respective open parts, and contact plugs buried in the respective open parts.. ... Sk Hynix Inc

12/03/15 / #20150349073

Dual work function buried gate-type transistor, method for forming the same, and electronic device including the same

A transistor includes: a source region and a drain region that are formed in a substrate to be spaced apart from each other; a trench formed in the substrate between the source region and the drain region; and a buried gate electrode inside the trench, wherein the buried gate electrode includes: a lower buried portion which includes a high work-function barrier layer including an aluminum-containing titanium nitride, and a first low-resistivity layer disposed over the high work-function barrier layer; and an upper buried portion which includes a low work-function barrier layer disposed over the lower buried portion and overlapping with the source region and the drain region, and a second low-resistivity layer disposed over the low work-function barrier layer.. . ... Sk Hynix Inc

12/03/15 / #20150348992

Semiconductor device and method for fabricating the same

A semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel, a gate, and a memory layer is interposed between the channel and the gate. ... Sk Hynix Inc

12/03/15 / #20150348990

Nonvolatile memory device and method for fabricating the same

This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each connected with the pipe channel layer and extended in a direction substantially perpendicular to the substrate, a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, and metal silicide layers configured to be in contact with the pipe connection gate electrode. ... Sk Hynix Inc

12/03/15 / #20150348980

Semiconductor device and method of manufacturing the same

A semiconductor device includes a substrate including a plurality of active regions divided by a plurality of trenches, a plurality of tunnel insulating layer patterns formed over the active regions, a plurality of conductive film patterns formed over the tunnel insulating film patterns, a plurality of first isolation layers formed on sidewalls and bottom surfaces of the trenches, and a plurality of second isolation layers formed between the conductive film patterns.. . ... Sk Hynix Inc

12/03/15 / #20150348978

Semiconductor device including a reservoir capacitor

A semiconductor device includes: a through silicon via (tsv) region extending in a first direction and crossing a center portion of a semiconductor device; a plurality of cell regions disposed at both sides of the tsv region in a second direction crossing the first direction; a plurality of peripheral circuit regions each disposed between the tsv region and a corresponding cell region or between two neighboring cell regions in the first direction; a plurality of test pad regions each disposed at an edge portion of the semiconductor device and having a plurality of test pads, wherein the plurality of test pad regions encloses the cell regions, the peripheral circuit regions, and the tsv region; and a reservoir capacitor disposed below corresponding test pads in a test pad regions.. . ... Sk Hynix Inc

12/03/15 / #20150348942

Flexible stack packages having wing portions

A flexible stack package includes a first package and a second package. Each of the first and second packages includes a flexible layer, a chip embedded in the flexible layer, and a contact portion disposed on the chip to penetrate the flexible layer and exposed at a surface of the flexible layer. ... Sk Hynix Inc

12/03/15 / #20150348941

Stack package and reduction of standby current

The stack package includes: a plurality of chips each stacked with a plurality of layers; and a plurality of pads respectively formed on the plurality of chips. Each chip includes: a ground path unit configured to form a current path between a pad and a ground stage; a selection unit configured to selectively control a connection path electrically coupled to the pad according to a chip enable signal; and a controller configured to selectively control a connection between the selection unit and the ground path unit according to a control signal.. ... Sk Hynix Inc

12/03/15 / #20150348930

Flip chip packages having chip fixing structures, electronic systems including the same, and memory cards including the same

A flip chip package includes a chip having a surface, main bumps disposed on a first region of the surface of the chip, dummy bumps disposed on a second region of the surface of the chip, a substrate having a surface, dams disposed on the surface of the substrate, connection pads disposed on the surface of the substrate and electrically connected to respective ones of the main bumps, and adhesion patterns attaching the dummy bumps to respective ones of the dams.. . ... Sk Hynix Inc

12/03/15 / #20150348857

Semiconductor apparatus having tsv and testing method thereof

A test method of a semiconductor apparatus before a wafer is ground may include applying voltages to a bump electrically coupled to a through-silicon via (tsv) which is buried in the wafer and a first conductive layer formed to be electrically connected to a rear surface of the tsv, wherein the first conductive layer is withdrawn into an upper surface of the wafer. The method may include measuring a voltage between the bump and the first conductive layer. ... Sk Hynix Inc

12/03/15 / #20150348650

Semiconductor device and semiconductor system including the same

A semiconductor system includes: a memory controller; and a memory which determines whether to enable a control signal in response to block mode entry signals applied from the memory controller, enters a repair mode in response to a first address and a first command applied from the memory controller, and blocks an entry to the repair mode during an enabling section of the control signal.. . ... Sk Hynix Inc

12/03/15 / #20150348638

Semiconductor device and operating method thereof

A semiconductor device and a method of operating the same are provided. The semiconductor device includes a memory block including a plurality of pages having a plurality of first cells and a plurality of second cells, a circuit group configured to read first cells and second cells of a selected page of the pages, a strobe signal control circuit configured to store source bouncing information generated during a read operation of the first cells of the selected page and output a strobe signal based on stored information, and a control circuit configured to control the circuit group in response to the strobe signal during a read operation of the second cells of the selected page.. ... Sk Hynix Inc

12/03/15 / #20150348634

Semiconductor memory device, memory system including the same, and operating method thereof

A semiconductor memory device includes a plurality of memory cells coupled between a source line and a bit line, a voltage generation circuit suitable for applying an erase voltage to the source line during an erase operation, and a read and to circuit coupled to the bit line through a selection transistor and suitable for applying an operating voltage to a first node of the selection transistor during the erase operation.. . ... Sk Hynix Inc

12/03/15 / #20150348622

Resistive memory device, method of fabricating the same, and memory apparatus and data processing system having the same

A resistive memory device capable of implementing a multi-level cell, a method of fabricating the same, and a memory apparatus and data processing system including the same are provided. The resistive memory device includes a lower electrode, a first phase-change material layer formed over the lower electrode, a second phase-change material layer formed to surround an outer sidewall of the first phase-change material layer, and an upper electrode formed over the first phase-change material layer and the second phase-change material layer.. ... Sk Hynix Inc

12/03/15 / #20150348620

Semiconductor memory device and operation method thereof

A semiconductor memory device includes a memory cell suitable for having a predetermined cell state based on a data stored therein, a control signal generation unit suitable for generating a control signal for changing the cell state of the memory cell during a reading operation, an information storage unit suitable for storing a variation status information of the control signal to which a moment when the cell state of the memory cell changes is reflected, and an output unit suitable for outputting the variation status information of the control signal stored in the information storage unit as a signal corresponding to the data stored in the memory cell.. . ... Sk Hynix Inc

12/03/15 / #20150348611

Semiconductor devices and semiconductor systems including the same

A semiconductor memory device may include a power control signal generator and a sense amplifier circuit. The power control signal generator may generate a first power control signal, the first power control signal having an enablement period that may be controlled in response to a temperature signal having a cycle time. ... Sk Hynix Inc

12/03/15 / #20150348604

Semiconductor memory apparatus and semiconductor integrated circuit including the same

A semiconductor memory apparatus includes: a memory cell area including a plurality of banks each having a plurality of octet banks corresponding to a first group and a plurality of octet banks corresponding to a second group; and a control unit configured to generate a plurality of control signals to input a data signal to any one octet bank of the first group and any one octet bank of the second group with a predetermined margin.. . ... Sk Hynix Inc

12/03/15 / #20150347312

Controller for controlling non-volatile memory and semiconductor device including the same

A controller controlling a non-volatile memory includes a first memory area suitable for storing a first address table, a second memory area suitable for storing a second address table, an address conversion block suitable for converting a sector address received from a host into a physical address corresponding to the non-volatile memory with reference to the first and second address tables, and one or more function blocks suitable for sharing the second memory area with the address conversion block. The address conversion block exclusively uses the first memory area.. ... Sk Hynix Inc

12/03/15 / #20150347290

Semiconductor device

A semiconductor device may include a first memory cell array configured to store data according to a first address on a first basis, a second memory cell array configured to store data according to a second address on a second basis that is relatively smaller than the first basis, a memory selector configured to select one of the first memory cell array and the second memory cell array to store data during a write request, and an address map table configured to store mapping information between the first and second addresses for data stored in the second memory cell array.. . ... Sk Hynix Inc

12/03/15 / #20150346757

Active driver and semiconductor device having the same

An active driver includes a mirror circuit suitable for generating a drive voltage and a sink voltage using an external voltage, a first reset circuit suitable for outputting the drive voltage of a logic high level in a standby mode; a second reset circuit suitable for transitioning the drive voltage to a logic low level in response to the sink voltage when being changed from the standby mode to an active mode, and an output circuit suitable for outputting the external voltage as an internal voltage in response to the drive voltage when being changed from the standby mode to the active mode.. . ... Sk Hynix Inc

11/26/15 / #20150341019

Semiconductor device

A semiconductor device includes: a pre-emphasis control signal generation portion suitable for generating a pre-emphasis control signal for a pre-emphasis operation; and a plurality of output drivers, a portion of which performs the pre-emphasis operation based on the pre-emphasis control signal when an output operation is performed.. . ... Sk Hynix Inc

11/26/15 / #20150340998

Differential amplifier

A differential amplification circuit includes a first current control unit configured to control driving current in response to a voltage level difference between first input voltage and second input voltage, a second current control unit configured to control the driving current in response to a voltage level difference between the second input voltage independent from temperature and a temperature voltage depending on the temperature, and a signal output unit configured to generate a detection signal in response to the driving current.. . ... Sk Hynix Inc

11/26/15 / #20150340608

Semiconductor device and electronic device including the same

A semiconductor device includes a first conductive layer, a second conductive layer spaced from the first conductive layer, a variable resistance layer interposed between the first and second conductive layers, and an impurity-doped layer provided over a side surface of the variable resistance layer. The variable resistance layer has a smaller width than the first and the second conductive layers.. ... Sk Hynix Inc

11/26/15 / #20150340463

Three dimensional semiconductor device having lateral channel and method of manufacturing the same

A 3d semiconductor device and a method of manufacturing the same are provided. The 3d semiconductor device includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active line including a source region and a drain region formed on the insulating layer, a gate electrode located on a portion of the active line, corresponding to a region between the source region and the drain region, and extending to a direction substantially perpendicular to the active line, and a line-shaped common source node formed to be electrically coupled to the source region and extending substantially in parallel to the gate electrode in a space between gate electrodes.. ... Sk Hynix Inc

11/26/15 / #20150340407

Semiconductor device and fabrication method thereof

A semiconductor device and a fabrication method thereof are provided the semiconductor device includes a local silicon-on-insulator (soi) substrate in which a portion of a line-shaped active region is connected to a semiconductor substrate, and a remaining portion thereof is insulated from the semiconductor substrate, gate structures formed in a line shape to be substantially perpendicular to the active region on the active region insulated from the semiconductor substrate, and to surround a side and an upper surface of the active region, and having a stacking structure of a gate insulating layer, a liner conductive layer, a gate conductive layer, and a hard mask layer, a source region formed in the active region connected to the semiconductor substrate, and a drain region formed in the active region insulated from the semiconductor substrate between the gate structures.. . ... Sk Hynix Inc

11/26/15 / #20150340373

Semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device includes forming isolation layers in a first direction at trenches at isolation regions defined at a semiconductor substrate and forming gate lines in a second direction crossing the first direction over the isolation layers and active regions defined between the isolation layers, performing a dry-etch process to remove the isolation layers, and forming an insulating layer over the semiconductor substrate to form a first air gap extending in the first direction in the trenches and a second air gap extending in the second direction between the gate lines.. . ... Sk Hynix Inc

11/26/15 / #20150340370

Three-dimensional nonvolatile memory device, semiconductor system including the same, and method of manufacturing the same

A three-dimensional nonvolatile memory device includes a first vertical channel layer and a second vertical channel layer extending from a substrate, a plurality of memory cells, first selection transistors and second selection transistors spaced apart from each other along the first vertical channel layer and the second vertical channel layer, a pad, a contact plug and a bit line in a stacked configuration over the first vertical channel layer, and a common source line formed over the second vertical channel layer.. . ... Sk Hynix Inc

11/26/15 / #20150340303

Multi chip package and method for manufacturing the same

A multi chip package includes a protective layer having an upper surface that surrounds a first chip and a second chip, which are mounted over a first substrate, to expose an upper surface of the first chip and an upper surface of the second chip, a heat spreader disposed over the upper surfaces, and a thermal interface material disposed at an interface between the heat spreader and the upper surfaces.. . ... Sk Hynix Inc

11/26/15 / #20150340096

Semiconductor device, semiconductor system having the same and operating method thereof

A semiconductor device may include memory blocks having a plurality of strings including drain select transistors and memory cells electrically coupled in series between a bit line and a pipe transistor and source select transistors and memory cells electrically coupled in series between a common source line and the pipe transistor; a circuit group configured to float drain select lines electrically coupled to the drain select transistors included in unselected memory blocks and source select lines electrically coupled to the source select transistors included in the unselected memory blocks and to ground a pipe line electrically coupled to the pipe transistor when a program operation of a selected memory block among the memory blocks is performed; and a control circuit configured to control the circuit group.. . ... Sk Hynix Inc

11/26/15 / #20150340088

Semiconductor device and operating method thereof

A semiconductor device may include a candidate selector configured for generating a plurality of candidate threshold value sets from a plurality of digital values corresponding to a plurality of analog signals output from a memory cell array. The semiconductor device may include a threshold value selector configured for selecting one candidate threshold value set of the plurality of candidate threshold value sets as a threshold value set. ... Sk Hynix Inc

11/26/15 / #20150340079

Semiconductor memory apparatus

A semiconductor memory apparatus may include an active control portion configured to generate a preliminary bank active signal and a single bank refresh signal in response to a command, a refresh control signal, and a bank active signal. The semiconductor memory apparatus may also include a signal combination portion configured to enable the bank active signal when either the preliminary bank active signal or the single bank refresh signal is enabled.. ... Sk Hynix Inc

11/26/15 / #20150338456

Semiconductor apparatus

A semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode, a test output timing controller configured to generate a dll clock signal from an external clock signal, delay the applied external read command in synchronization with the dll clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode, and a multiplexer (mux) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.. . ... Sk Hynix Inc

11/19/15 / #20150333759

Semiconductor device, semiconductor system and method for operating semiconductor device

A semiconductor device includes a code generation block configured to generate an output clock by delaying a reference clock which is inputted from an exterior, control a delay value of the output clock based on a result of comparing phases of the reference clock and a feedback clock, and generate a first control code corresponding to the delay value of the output clock, a voltage generation block configured to generate an internal voltage with a voltage level corresponding to the first control code, a clock generation block configured to generate an internal clock with a frequency corresponding to the first control code, and a feedback delay block configured to generate the feedback clock by delaying the output clock by a delay value corresponding to a second control code.. . ... Sk Hynix Inc

11/19/15 / #20150333741

Semiconductor device with clock-based signal input circuit

A semiconductor device includes a signal input circuit suitable for synchronizing an input signal with a clock signal and receiving the clock signal as a power source when the input signal has a first phase, where the signal input circuit amplifies a swing width of the input signal based on a swing width of the clock.. . ... Sk Hynix Inc

11/19/15 / #20150333186

Semiconductor device and method of manufacturing the same

A semiconductor device includes a channel layer including a sidewall having protrusions and depressions alternating with each other in a direction in which the channel layer extends, a tunnel insulating layer surrounding the channel layer, first charge storage patterns surrounding the tunnel insulating layer formed in the depressions, blocking insulation patterns surrounding the first charge patterns formed in the depressions, wherein the blocking insulating patterns include connecting portions coupled to the tunnel insulating layer, and second charge storage patterns surrounding the tunnel insulating layer formed in the protrusions.. . ... Sk Hynix Inc

11/19/15 / #20150333069

Semiconductor device and manufacturing method thereof

A semiconductor device including a storage node contact that surrounds three sidewalls of an active region to increase the contact area between the storage node contact and the active region is provided.. . ... Sk Hynix Inc

11/19/15 / #20150332791

Electronic device and method for operating electronic device

An electronic device comprising a semiconductor memory unit that may include a plurality of data transfer lines; a plurality of columns including a plurality of memory cells; at least one redundancy column including a plurality of redundancy memory cells and configured to replace at least one column among the plurality of columns; a repair select information generation unit configured to store a column address of the at least one column to be replaced among the plurality of columns and generate a plurality of repair select information in response to the stored column address; and a plurality of repair selection units connected with data transfer lines corresponding to them among the plurality of data transfer lines, columns corresponding to them among the plurality of columns and the at least one redundancy column, and each configured to electrically connect a column selected among a column corresponding to it and the at least one redundancy column, to a data transfer line corresponding to it, in response to repair select information corresponding to it among the plurality of repair select information.. . ... Sk Hynix Inc

11/19/15 / #20150332790

Memory device

A memory device includes a first memory block, a second memory block, a reception circuit configured to receiving a repair address and compression information, and a nonvolatile memory circuit including a first region for repairing the first memory block and a second region for repairing the second memory block, and configured to program the repair address in both the first region and the second region when the compression information represents high compression and program the repair address in either the first region or the second region when the compression information represents low compression.. . ... Sk Hynix Inc

11/19/15 / #20150332789

Semiconductor memory device performing self-repair operation

A semiconductor memory device includes a memory cell array including a main cell array and a repair cell array, a command controller that controls an input/output operation of the memory cell array, an address generator that stores a repair address, and generates an internal address according to an external address requested to be read or written, an ecc that performs a parity operation for data input/output to the memory cell array, an address table that associates an address, at which a fail has occurred when the fail has occurred in the ecc, with a number of times of occurrence of the fail, and a repair controller that selects a repair address according to the number of times of the occurrence of the fail stored in the address table, and controls the address generator to allow information of the selected repair address to be stored.. . ... Sk Hynix Inc

11/19/15 / #20150332788

Read disturb detection

It is determined that a read count has reached one of a set of read count thresholds. An initial test page which corresponds to the read count threshold that has been reached is selected from a set of initial test pages. ... Sk Hynix Inc

11/19/15 / #20150332787

Semiconductor memory apparatus

A semiconductor memory apparatus includes a plurality of data storage regions; a first internal circuit configured to input a plurality of control signals to the plurality of data storage regions; and a second internal circuit configured to control input timing of a test control signal, and input the test control signal to the plurality of data storage regions according to the controlled input timing in response to a test mode signal.. . ... Sk Hynix Inc

11/19/15 / #20150332786

Semiconductor memory device and method for operating the same

A semiconductor memory device includes a first address input block which receives first information applied from an exterior as a corresponding normal address in a normal mode and receives the first information as a test clock in a test mode, a second address input block which receives second information applied from an exterior as the corresponding normal address in the normal mode and receives the second information as a test code in the test mode, and a test signal generation block which synchronizes the test code with the test clock in the test mode and generates a test command, a test address and a test data in response to a synchronized test code.. . ... Sk Hynix Inc

11/19/15 / #20150332783

Method of operating semiconductor device

A method of operating a semiconductor device includes programming a first cell, verifying a second cell adjacent to the first cell, and repeating the programming of the first cell and the verifying of the second cell until the verifying of the second cell passes.. . ... Sk Hynix Inc

11/19/15 / #20150332766

Electronic device

An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction crossing the first direction, and a plurality of memory cells provided between the first lines and the second lines at intersections of the first lines and the second lines. ... Sk Hynix Inc

11/19/15 / #20150332744

Semiconductor devices and semiconductor systems including the same

Semiconductor systems are provided. The semiconductor system may include a controller and a semiconductor device. ... Sk Hynix Inc

11/19/15 / #20150332743

Semiconductor memory device

A semiconductor memory device includes a first page buffer block and a second page buffer block corresponding to a first memory bank and a second memory bank, respectively, an input/output control circuit suitable for transferring input data to data lines, a first column decoder and a second column decoder suitable for latching the input data transferred through the data lines to the first page buffer block and the second page buffer block, respectively, based on a column address transferred through address lines that are shared by the first and second column decoders, and a control signal generation circuit suitable for generating a plurality of page buffer selection signals to control the first and second column decoders to selectively perform data latch operations on the first and second page buffer blocks.. . ... Sk Hynix Inc

11/19/15 / #20150332742

Semiconductor memory apparatus

A semiconductor memory apparatus may include a data conversion control block configured to control the number of pipe input control signals and the number of pipe output control signals which are enabled, in response to a training control signal. The semiconductor memory apparatus may also include a data conversion block configured to receive parallel data and output serial data, in response to the pipe input control signals and the pipe output control signals.. ... Sk Hynix Inc

11/19/15 / #20150332738

Semiconductor memory device, semiconductor device including the same, and method for operating the semiconductor device

A semiconductor device includes: a plurality of internal circuits which receive commands through a plurality of independent command lines in a first operation mode and receive a common command through a common command line in a second operation mode; and an operation control block which duplicates a command applied through a representative independent command line, which is selected among the plurality of independent command lines, in the second operation mode and transmits the duplicated command as the common command to the common command line.. . ... Sk Hynix Inc

11/19/15 / #20150331769

Memory module and operation method thereof

A memory module includes an emergency power supply block, a volatile memory, a nonvolatile memory, and a control block configured to control data of the volatile memory to be backed up in the nonvolatile memory, by using a power supplied from the emergency power supply block, upon a power failure, and control the data of the volatile memory to be recovered, by using data backed up in the nonvolatile memory, upon a power recovery, wherein the control block controls the data of the volatile memory not to be backed up while controlling the data of the volatile memory to be recovered, even upon the power failure.. . ... Sk Hynix Inc

11/19/15 / #20150331670

Noise generator, integrated circuit including the same, and operation method thereof

A noise generator includes a selection unit suitable for outputting first elements corresponding to first seeds based on a first function, and outputting second elements corresponding to second seeds based on a second function, a first permuter suitable for generating first pair elements based on a first correspondence relationship in which the respective first elements and the respective second elements correspond to each other, and a first calculation unit suitable for generating a first noise based on the first pair elements, wherein a product of the first function and the second function is a gaussian random variable.. . ... Sk Hynix Inc

11/12/15 / #20150326836

Image sensing device

An image sensing device includes: a pixel array including a plurality of pixels arranged in row and column directions; a row control portion suitable for controlling a part of a plurality of rows included in the pixel array by an unit of two or more sequential rows so that pixel signals are simultaneously outputted from the pixel array through the sequential rows; a first readout circuit portion suitable for sequentially reading out a part of the pixel signals in row sequence order; a second readout circuit portion suitable for sequentially reading out the rest of the pixel signals in row sequence order; and a storage portion suitable for storing on row by row basis the read out signals sequentially read out in row sequence order from the first and second readout circuit portions.. . ... Sk Hynix Inc

11/12/15 / #20150326804

Bias sampling device and cmos image sensor including the same

A bias sampling device includes a reference current generation unit suitable for generating a reference current; a plurality of multi-staged current mirror circuits suitable for receiving the reference current generated from the reference current generation unit and outputting a bias voltage; and a bias sampling unit suitable for performing sampling on a first bias voltage of a first current mirror circuit of the plurality of multi-staged current mirror circuits, wherein the first bias voltage of the first current mirror circuit, which is located prior to a final-staged current mirror circuit of the plurality of multi-staged current mirror circuits, is preset.. . ... Sk Hynix Inc

11/12/15 / #20150326242

Counter, analogue to digital converter including the counter and image sensing device including the analogue to digital converter

A counter includes a sampling unit suitable for sampling a logic state of a least significant bit (lsb) during a counting hold section, the counting hold section is present between first and second ramp sections; and a toggling control unit suitable for, in response to a clock and a sampling signal outputted from the sampling unit, generating the lsb according to a first voltage level of a counting target signal during a second part of the first ramp section and generating the lsb according to a second voltage level of the counting target signal during a first part of the second ramp section.. . ... Sk Hynix Inc

11/12/15 / #20150326218

Power-up circuit of semiconductor apparatus

A power-up circuit of a semiconductor apparatus using a plurality of external power voltages is configured to determine a stableness of the plurality of external power voltages through relative comparison of the plurality of external power voltages, and to activate a power-up signal.. . ... Sk Hynix Inc

11/12/15 / #20150326189

Amplification circuit adjusting duty cycle of output signal

An amplification circuit includes an input portion, a first load portion, a second load portion, and a duty cycle adjustment portion. The input portion changes a voltage level of an output node, which outputs a voltage level thereof as an output signal, in response to an input signal. ... Sk Hynix Inc

11/12/15 / #20150325789

Variable resistance memory device and method of fabricating the same

Disclosed herein are a variable resistance memory device and a method of fabricating the same. The variable resistance memory device may include a first electrode; a second electrode; and a variable resistance layer configured to be interposed between the first electrode and the second electrode, wherein the variable resistance layer includes a si-added metal oxide.. ... Sk Hynix Inc

11/12/15 / #20150325695

Semiconductor apparatus, method for fabricating the same, and variable resistive memory device

A semiconductor apparatus that includes a semiconductor substrate and a plurality of pillars formed in the semiconductor substrate. Each of the plurality of pillars includes a first pillar, and a second pillar formed on the first pillar, wherein the second pillar has a smaller linewidth than the first pillar.. ... Sk Hynix Inc

11/12/15 / #20150325582

Semiconductor memory device

A semiconductor memory device includes: a plurality of first channel columns including a plurality of first channel layers that are arranged in a direction and offset by their centers; a plurality of second channel columns alternately arranged with the plurality of first channel columns and having a plurality of second channel layers that are arranged in the direction and offset by their centers; first insulating layers and first conductive layers alternately stacked to surround the first channel layers; second insulating layers and second conductive layers stacked to surround the second channel layers; and spacers placed between the first channel columns and the second channel columns and interposed between the first conductive layers and the second conductive layers.. . ... Sk Hynix Inc

11/12/15 / #20150325306

Semiconductor memory device and a reading method thereof

A semiconductor memory device may include a common source line controller configured to provide a channel current to a cell string via a common source line during a read operation and a page buffer configured to detect data stored in a selected memory cell by detecting a current of the bit line when the channel current is provided. The page buffer may selectively bias the bit line to maintain a voltage of the bit line to be the same as or higher than a reference voltage.. ... Sk Hynix Inc

11/12/15 / #20150325284

Semiconductor apparatus capable of preventing refresh error and memory system using the same

A semiconductor apparatus includes a plurality of memory banks configured to perform a refresh operation in response to an address count value and row active signals; a refresh control block configured to update refresh bank informations which define a bank designated to perform the refresh operation in response to a refresh command and bank addresses, and activate a count control signal in response to the refresh bank informations; and a counter configured to change the address count value in response to activation of the count control signal.. . ... Sk Hynix Inc

11/12/15 / #20150324243

Semiconductor device including a plurality of processors and a method of operating the same

A semiconductor device may include a first processor transferring a plurality of command data sets, a mailbox receiving and storing the plurality of command data sets, and a second processor receiving command data sets of the mailbox, wherein the first processor may transfer at least one abort slot number to the mailbox, and wherein the mailbox may search and abort a command data set having a slot number which is identical to an abort slot number among the plurality of command data sets.. . ... Sk Hynix Inc

11/12/15 / #20150323579

Duty cycle detector and semiconductor integrated circuit apparatus including the same

A duty cycle detector may include a rising clock detection unit enabled in response to a first control signal; a falling clock detection unit enabled in response to a second control signal with a different activation timing from the first control signal; and a comparison unit configured to compare an output signal of the rising clock detection unit to an output signal of the falling clock detection unit in response to a comparison enable signal, and output a duty cycle detection signal.. . ... Sk Hynix Inc

11/05/15 / #20150318330

Semiconductor device and method of fabricating the same

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate in which a word line region is formed, and a barrier metal layer arranged on the word line region and causing a schottky junction. ... Sk Hynix Inc

11/05/15 / #20150318329

Semiconductor device and method of fabricating the same

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate in which a word line region is formed, and a barrier metal layer arranged on the word line region and causing a schottky junction. ... Sk Hynix Inc

11/05/15 / #20150318039

Nonvolatile memory apparatus

A nonvolatile memory apparatus includes a sensing voltage generation unit, a memory cell, a current copy unit and a data sensing unit. The sensing voltage generation unit provides a sensing voltage with a constant level, to a sensing node. ... Sk Hynix Inc

10/29/15 / #20150311885

Power-up signal generation circuit and semiconductor device including the same

A power-up signal generation circuit including a pre-power-up signal generation block operates by using a first power supply voltage, and generates a pre-power-up signal when the first power supply voltage becomes higher than a first level, and a second power supply voltage becomes higher than a second level; a level shifting block suitable for pull-down driving a first node when the pre-power-up signal is not in an activated state, and pull-up driving the first node with the second power supply voltage when the pre-power-up signal is in the activated state; a driving block suitable for pull-down driving the first node when the second power supply voltage is lower than the second level; and a power-up signal driving block operates by using the second power supply voltage, and generates a power-up signal through a second node by driving the second node based on a voltage level of the first node.. . ... Sk Hynix Inc

10/29/15 / #20150311316

Variable resistive memory device including vertical channel pmos transistor and method of manufacturing the same

A semiconductor device having a vertical channel, a variable resistive memory device including the same, and a method of manufacturing the same are provided. The semiconductor device having a vertical channel includes a vertical pillar formed on a semiconductor substrate and including an inner portion and an outer portion surrounding the inner portion, junction regions formed in the outer portion of the vertical pillar, and a gate formed to surround the vertical pillar. ... Sk Hynix Inc

10/29/15 / #20150311255

Variable resistive memory device including vertical channel pmos transistor and method of manufacturing the same

A semiconductor device having a vertical channel, a variable resistive memory device including the same, and a method of manufacturing the same are provided. The semiconductor device having a vertical channel includes a vertical pillar formed on a semiconductor substrate and including an inner portion and an outer portion surrounding the inner portion, junction regions formed in the outer portion of the vertical pillar, and a gate formed to surround the vertical pillar. ... Sk Hynix Inc

10/29/15 / #20150311211

Semiconductor device and method for manufacturing the same

In a semiconductor device and a method for manufacturing the same, a pillar pattern is formed in an alternating pattern and a one side contact (osc) is formed without using a tilted ion implantation process or a mask, resulting in formation of a vertical gate. The semiconductor device includes an alternating or zigzag-type pillar pattern formed over a semiconductor substrate, a first hole formed between pillars of the pillar pattern, a passivation layer formed over a sidewall of the first hole, a second hole formed by partially etching a lower part of the first hole, a bit line formed in the second hole, and a contact formed at a lower part of the pillar pattern.. ... Sk Hynix Inc

10/29/15 / #20150311209

3-d non-volatile memory device and method of manufacturing the same

A three-dimensional (3-d) non-volatile memory device includes a plurality of word line structures extended in parallel and including a plurality of interlayer dielectric layers and a plurality of word lines that are alternately stacked over a substrate, a plurality of channels protruding from the substrate configured to penetrate the plurality of interlayer dielectric layers and the plurality of word lines, and an air gap formed between the plurality of word line structures.. . ... Sk Hynix Inc

10/29/15 / #20150311182

Semiconductor package and method for manufacturing the same

A semiconductor package may include an interposer; a first semiconductor chip disposed on a first surface of the interposer and at least one second semiconductor chip disposed at a predefined distance from the first semiconductor chip, a molding part filling spaces between the first semiconductor chip and the at least one second semiconductor chip and having a trench hole formed therein, and a thermal expansion buffer pattern filling the trench hole.. . ... Sk Hynix Inc

10/29/15 / #20150310939

Semiconductor device, semiconductor repair system including the same, and method for operating the semiconductor device

A semiconductor device includes: a plurality of fuse arrays each including a plurality of fuses; a selection block which selects one fuse array among the fuse arrays in response to values of a group of bits of a repair code; a code alignment block which aligns disposition of bits other than the group of bits of the repair code, wherein the alignment disposition is changed based on the fuse array selected in the selection block; and an operation block which controls an operation of the fuse array selected in the selection block in response to a repair command and an output code of the code alignment block.. . ... Sk Hynix Inc

10/29/15 / #20150310936

Monitoring device of integrated circuit

A semiconductor memory device includes a plurality of data input/output pads configured to transmit and receive data to and from memory cells, an alert pad configured to output data error information while the data is transmitted and received, and a monitoring device configured to output the data error information to the alert pad in a first mode and to output monitoring information to the alert pad in a second mode.. . ... Sk Hynix Inc

10/29/15 / #20150310935

Monitoring device of integrated circuit

A semiconductor memory device includes a plurality of data input/output pads configured to transmit and receive data to and from memory cells, an alert pad configured to output data error information while the data is transmitted and received, and a monitoring device configured to output the data error information to the alert pad in a first mode and to output monitoring information to the alert pad in a second mode.. . ... Sk Hynix Inc

10/29/15 / #20150310931

Memory device, memory system, and method for operating memory device

A memory device includes a first memory block suitable for transmitting and receiving signals through a first channel, a second memory block suitable for transmitting and receiving signals through a second channel, and a test control unit suitable for applying a first command signal among a plurality of command signals to the first and second channels at different values, while applying the plurality of command signals from an exterior of the memory device to the first and second channels in a test operation, wherein the first command signal distinguishes write and read operations of the first and second memory blocks, wherein, when the first memory block performs a read operation in the test operation, the second memory block performs a write operation, and data outputted from the first memory block is inputted to the second memory block.. . ... Sk Hynix Inc

10/29/15 / #20150310925

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a fuse array block including a plurality of fuses programmed with state information, an operation direction control block suitable for controlling a program operation direction and a boot-up operation direction of the fuse array block, and a fuse information loading block suitable for loading the state information which is programmed in the plurality of fuses of the fuse array block through the boot-up operation.. . ... Sk Hynix Inc

10/29/15 / #20150310918

Eprom cell array, method of operating the same, and memory device including the same

An eprom cell array includes a cell array including multiple unit cells, each of which includes a mosfet having a floating gate, and which are disposed in an array with a plurality of rows and a plurality of columns; multiple first selection lines each coupled with drains of unit cells, which are disposed on the same row among the multiple unit cells; and multiple second selection lines each coupled with sources of unit cells, which are disposed on the same column among the unit cells, wherein a selected unit cell to be programmed or read is selected by one of the multiple first selection lines, and one of the multiple second selection lines. . ... Sk Hynix Inc

10/29/15 / #20150310914

Electronic device

Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory unit including one or more column, a data line, and a data line bar connected with a column selected among the one or more columns. Each of the one or more columns may include a plurality of storage cells each configured to store 1-bit data, each storage cell including a first and a second variable resistance elements; a bit line connected to one end of the first variable resistance element; a bit line bar connected to one end of the second variable resistance element; a source line connected to the other ends of the first and second variable resistance elements; and a driving block configured to latch data of the data line and the data line bar.. ... Sk Hynix Inc

10/29/15 / #20150310913

Electronic device

Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory unit comprising one or more columns and a date line and a data line bar connected with a column selected among the one or more columns. Each of the one or more columns includes a plurality of storage cells each configured to store 1-bit data, each storage cell including a first and second variable resistance elements; a bit line and a source line connected to the first variable resistance element; connected to the other end of the first variable resistance element; a bit line bar and a source line bar connected to the second variable resistance element; and a driving block configured to latch data of the data line and the data line bar.. ... Sk Hynix Inc

10/29/15 / #20150310912

Electronic device

An electronic device includes semiconductor memory, which includes a memory cell block including first and second cell arrays and a column control block. The first cell array includes a word line, a first bit line, and a first variable resistance layer disposed between the word line and the first bit line. ... Sk Hynix Inc

10/29/15 / #20150309943

Memory control unit and data storage device including the same

A data storage device includes a storage memory device, a control unit suitable for generating a descriptor, which describes a work for controlling the storage memory device, and storing the descriptor in a working memory, and a memory control unit suitable for generating control signals for the storage memory device by fetching an instruction set from an instruction memory based on the descriptor.. . ... Sk Hynix Inc

10/29/15 / #20150309865

Memory control unit and data storage device including the same

A data storage device includes a storage memory device; a signal generation block suitable for generating control signals to be provided to the storage memory device; and an error correction code (ecc) block suitable for ecc-encoding data to be stored in the storage memory device, wherein the ecc block operates before the signal generation block.. . ... Sk Hynix Inc

10/29/15 / #20150309864

Data storage device and method for operating the same

A method for operating a data storage device that includes reading data and storage parity data, generating transformation parity data through a masking operation on the storage parity data, and performing an error correcting operation on the data, based on the transformation parity data.. . ... Sk Hynix Inc

10/22/15 / #20150303922

High voltage switch circuit and nonvolatile memory including the same

A high voltage switch circuit includes a high voltage switch suitable for transferring a voltage of an input terminal to an output terminal in response to a voltage of a control node; a first transistor suitable for electrically connecting a first node and the control node in response to an inverted activation signal; a second transistor suitable for supplying a first high voltage to the first node in response to an activation signal; a third transistor connected in parallel to the second transistor, and operable in response to the control node; a discharge transistor suitable for discharging the control node; and a first level shifter suitable for changing a swing level of a preliminary activation signal, and generating the activation signal and the inverted activation signal.. . ... Sk Hynix Inc

10/22/15 / #20150303269

Transistor and semiconductor device including the same

Provided is a semiconductor device including a pillar, a gate electrode having a first conductive pattern surrounding the pillar and a plurality of second conductive patterns which protrude from the first conductive pattern and are arranged to be spaced apart from each other, and an insulating pattern interposed between the pillar and the first conductive pattern.. . ... Sk Hynix Inc

10/22/15 / #20150303211

Semiconductor device having three-dimensional structure and method of manufacturing the same

A semiconductor device includes a semiconductor pattern; conductive layers each including a first portion through which the semiconductor pattern passes and a second portion having a thickness greater than the first portion, wherein the first portion of each conductive layer includes a first barrier pattern surrounding the semiconductor pattern and a material pattern, which is formed in the first barrier pattern and has an etch selectivity with respect to the first barrier pattern, and the second portion of each conductive layer includes a conductive pattern; and contact plugs connected to the second portion of each of the conductive layers.. . ... Sk Hynix Inc

10/22/15 / #20150303208

Nonvolatile memory device

A nonvolatile memory device includes a first active region and a second active region separated from each other; a floating gate crossing the first active region, and disposed such that an end thereof overlaps with the second active region; a selection gate crossing the first active region, and disposed side by side with and coupled to the floating gate; a dielectric layer disposed between the floating gate and the selection gate, wherein a stack of the dielectric layer, the floating gate and the selection gate forms a first capacitor in a horizontal structure; a well region disposed in the second active region and coupled to the floating gate, wherein a stack of the well region and the floating gate forms a second capacitor in a vertical structure; and a contact commonly coupled to the well region and the selection gate.. . ... Sk Hynix Inc

10/22/15 / #20150303204

Nonvolatile memory devices having charge trapping layers and methods of fabricating the same

A nonvolatile memory device includes a substrate having a first charge trap region, a second charge trap region, and a selection region between the first and second charge trap regions. A well region is disposed in the substrate. ... Sk Hynix Inc

10/22/15 / #20150303203

Nonvolatile memory device having single-layer gate, method of operating the same, and memory cell array thereof

A nonvolatile memory device includes a single-layer gate, a first area, and a second area. The first area includes a first well region, a first contact region arranged in the first well region, and source and drain regions arranged at both sides of the single-layer gate in the first well region. ... Sk Hynix Inc

10/22/15 / #20150303181

Semiconductor package and method for manufacturing the same

A semiconductor package includes an interposer, first and second semiconductor chips horizontally arranged over a first surface of the interposer, the second semiconductor chip being adjacent to the first semiconductor chip, and a thermal expansion reinforcing pattern disposed over a second surface of the interposer.. . ... Sk Hynix Inc

10/22/15 / #20150303175

Semiconductor package and method for fabricating the same

A semiconductor package includes a package substrate on which a substrate pad is disposed, a structure disposed over the package substrate, a semiconductor chip disposed over the structure using an adhesive member having a magnetic material layer disposed therein, a chip pad disposed on a top surface of the semiconductor chip, and a bonding wire coupling the substrate pad and the chip pad.. . ... Sk Hynix Inc

10/22/15 / #20150303109

Semiconductor device and method for fabricating the same

A semiconductor device includes a semiconductor substrate configured to include a circuit pattern at one surface, an insulation film formed over a back surface of the semiconductor substrate, a through silicon via (tsv) configured to pass through the semiconductor substrate and the insulation film, and an oxide film formed at a sidewall of the tsv and protruded from the back surface of the semiconductor substrate in a manner that the oxide film partially contacts the insulation film.. . ... Sk Hynix Inc

10/22/15 / #20150303107

Semiconductor device, resistor and manufacturing method of the same

A resistor includes a first conductive layer; a second conductive layer protruding from the first conductive layer; a third conductive layer located above and facing the first conductive layer to face the first conductive layer; and at least two contact plugs electrically coupled to the third conductive layer.. . ... Sk Hynix Inc

10/22/15 / #20150302915

Semiconductor memory device

A semiconductor memory device includes: a master chip suitable for generating a plurality of first control signals and a second control signal based on a read command; and a plurality of slave chips each suitable for latching data read from a plurality of memory cells included in a corresponding slave chip and transmitting the latched data to the master chip based on a correspond control signal of the first control signals, wherein the master chip latches the data transmitted from the slave chips based on the first control signals and outputs the data latched in the master chip based on the second control signal.. . ... Sk Hynix Inc

10/22/15 / #20150302909

Semiconductor memory apparatus and operating method of the same

A semiconductor memory apparatus includes a delay control portion configured to generate a plurality of control signals by performing subtraction operation on a cl information and an al information; and a delay portion configured to decide a delay amount, delay an input signal by the delay amount, and output the delayed input signal as a delay signal in response to the plurality of control signals.. . ... Sk Hynix Inc

10/22/15 / #20150302900

Semiconductor stacked package

A semiconductor stacked package may include a substrate formed with a plurality of coupling pads, a plurality of semiconductor chips stacked on the substrate. The semiconductor stacked package may also include first circuit units disposed on each of the semiconductor chips, and electrically connected with the coupling pads by the medium of bonding pads. ... Sk Hynix Inc

10/22/15 / #20150302899

Semiconductor memory device

A semiconductor memory device includes: a first memory region including a plurality of first memory cells, two or more of which are simultaneously selected by a single address, and stores a first single datum; and a second memory region including a plurality of second memory cells, each of which is selected by the single address, and stores a second single datum.. . ... Sk Hynix Inc

10/01/15 / #20150281603

Analog-to-digital converter and cmos image sensor including the same

A cmos image sensor includes an active pixel array suitable for generating an active pixel signal, a dummy pixel array suitable for generating a dummy pixel signal, a row driver suitable for controlling the active pixel array and the dummy pixel array to simultaneously operate at a same column, and a correlated double sampling (cds) array suitable for generating an active sampling signal and a dummy sampling signal, which are sampled from the active pixel signal and the dummy pixel signal by using a correlated double sampling, respectively, based on a first ramp signal and a second ramp signal, and comparing the active sampling signal with the dummy sampling signal.. . ... Sk Hynix Inc

10/01/15 / #20150280745

Data processing block and data storage device including the same

A data processing block that includes a syndrome computation unit suitable for generating odd syndrome values in response to a received codeword, an elp solver suitable for generating even syndrome values, based on the odd syndrome values in a first mode, and generating an error location polynomial, based on the odd syndrome values and the even syndrome values in a second mode, and a chien search unit suitable for generating solutions of the error location polynomial.. . ... Sk Hynix Inc

10/01/15 / #20150280721

Clock delay detecting circuit and semiconductor apparatus using the same

Provided is a clock delay detecting circuit and semiconductor apparatus using the same that is capable of generating a period signal whose period is a delay time of a clock, dividing the period signal, and counting the divided period signal. The clock delay detection circuit comprises a period signal generating unit configured to generate a counting control signal, a period signal dividing unit configured to generate a counting enable signal by dividing the counting control signal, and a counting unit configured to generate a delay information signal by counting the counting enable signal with a clock, wherein the counting control signal has a period with a predetermined time.. ... Sk Hynix Inc

10/01/15 / #20150280720

Output control circuit for semiconductor apparatus and output driving circuit including the same

An output control circuit may include a period setting signal generation unit configured to output a setup signal enabled during a designated period, in response to a delayed locked loop (dll) locking signal and an output enable reset signal. The output control circuit may also include a clock division unit configured to divide an internal clock at a preset division ratio in response to the setup signal, and output a divided clock. ... Sk Hynix Inc

10/01/15 / #20150280713

Data output circuit of semiconductor apparatus

A data output circuit of a semiconductor apparatus includes a pull-up driver electrically coupled between a power supply terminal and an output terminal, and configured to drive the output terminal in response to pull-up control signals. The data output circuit may also include a pull-down driver electrically coupled between the output terminal and a ground terminal, and configured to drive the output terminal in response to pull-down control signals. ... Sk Hynix Inc

10/01/15 / #20150280712

Data output circuit of semiconductor apparatus

A data output circuit of a semiconductor apparatus includes a pull-up driver electrically coupled between a power supply terminal and an output terminal, and configured to drive the output terminal in response to pull-up control signals. The data output circuit may also include a pull-down driver electrically coupled between the output terminal and a ground terminal, and configured to drive the output terminal in response to pull-down control signals. ... Sk Hynix Inc

10/01/15 / #20150280709

Semiconductor device

The semiconductor device includes: a first die configured to include a first input pad and a first output pad; and a second die configured to include a second input pad and a second output pad. The second die corrects a level of an output voltage in response to a feedback reference voltage applied from the first output pad to the second input pad.. ... Sk Hynix Inc

10/01/15 / #20150280693

Data output circuit of a semiconductor apparatus

A data output circuit of a semiconductor apparatus includes a pull-up driver including a plurality of leg units configured to be controlled in respective resistance values in response to code signals, be controlled in an entire resistance value as one or more of the plurality of leg units are selectively activated in response to selection signals, and configured to apply an output voltage with an output voltage level selected according to a control of the entire resistance value among a plurality of output voltage levels, to a data output pad; a control block configured to generate the selection signals in response to mode register signals; and a code generator configured to generate the code signals according to an external resistor.. . ... Sk Hynix Inc

10/01/15 / #20150280692

Data output circuit of a semiconductor apparatus

A data output circuit of a semiconductor apparatus includes a pull-up driver including a plurality of leg units configured to be controlled in respective resistance values in response to code signals, be controlled in an entire resistance value as one or more of the plurality of leg units are selectively activated in response to selection signals, and configured to apply an output voltage with an output voltage level selected according to a control of the entire resistance value among a plurality of output voltage levels, to a data output pad; a control block configured to generate the selection signals in response to mode register signals; and a code generator configured to generate the code signals according to an external resistor.. . ... Sk Hynix Inc

10/01/15 / #20150279998

Semiconductor device having fin channel and method for forming the same

A semiconductor device includes an active region with a first gate trench formed when a gate region is etched to a first depth, a device isolation film defining the active region and including a second gate-trench formed when a gate region is etched to a second depth, a gate buried below the first gate trench and the second gate trench, and a source plug and a drain plug formed when a conductive material is deposited in a source region and a drain region of the active region.. . ... Sk Hynix Inc

10/01/15 / #20150279952

Three dimensional semiconductor integrated circuit having gate pick-up line and method of manufacturing the same

A 3d semiconductor integrated circuit having a gate pick-up line and a method of manufacturing the same, wherein the semiconductor integrated circuit includes a plurality of active pillars formed in a gate pick-up region, buffer layers formed on the respective active pillars in the gate pick-up region, gates each surrounding an outer circumference of the corresponding active pillar and the corresponding buffer layer, and a gate pick-up line electrically coupled to the gates.. . ... Sk Hynix Inc

10/01/15 / #20150279950

Semiconductor device and method for forming the same

A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an active region, a device isolation film, a first liner nitride film disposed over a lower portion of a sidewall of the active region, and a second liner nitride film disposed over an upper portion of the sidewall of the active region and having a higher density of nitrogen than a density of nitrogen in the first liner nitride film.. ... Sk Hynix Inc

10/01/15 / #20150279938

Semiconductor device and method of manufacturing the same

A semiconductor device includes first conductive layers and first interlayer insulating layers stacked alternately with each other, at least one second conductive layer and at least one second interlayer insulating layer formed on the first conductive layers and the first interlayer insulating layers and stacked alternately with each other, a first semiconductor layer passing through the first conductive layers and the first interlayer insulating layers and including polysilicon, and a second semiconductor layer coupled to the first semiconductor layer and passing through the at least one second conductive layer the at least one second interlayer insulating layer, wherein the second semiconductor layer includes silicon germanium.. . ... Sk Hynix Inc

10/01/15 / #20150279856

Semiconductor device and method of manufacturing the same

A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.. . ... Sk Hynix Inc

10/01/15 / #20150279819

Thin stack packages

The stack package includes a substrate body layer having a top surface and a bottom surface, first circuit patterns disposed on the bottom surface of the substrate body layer, second circuit patterns disposed on the top surface of the substrate body layer, a first semiconductor chip including first bumps, and a second semiconductor chip including second bumps. The first bumps extend through the substrate body layer to be electrically coupled to the first circuit patterns, and the second bumps extend past sidewalls of the first semiconductor chip to be electrically coupled to the second circuit patterns. ... Sk Hynix Inc

10/01/15 / #20150279798

Semiconductor devices having through electrodes, methods of manufacturing the same, and semiconductor packages including the same

A semiconductor device includes a semiconductor layer having a first surface and a second surface, a through electrode penetrating the semiconductor layer and having a protruding portion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed on the first surface of the semiconductor layer and electrically coupled to the through electrode, a passivation pattern including a first insulation pattern that surrounds a sidewall of the protruding portion of the through electrode and extends onto the second surface of the semiconductor layer and a second insulation pattern that covers the first insulation pattern and has an etch selectivity with respect to the first insulation pattern, and a back-side bump covering an end surface of the protruding portion of the through electrode and extending onto the passivation pattern.. . ... Sk Hynix Inc

10/01/15 / #20150279758

Semiconductor package on which semiconductor chip is mounted on substrate with window

The semiconductor package includes: a substrate having a window and first and second bond fingers arranged over a first surface along a periphery of the window; a first semiconductor chip disposed within the window and having a plurality of first bonding pads arranged over edges of an upper surface; a plurality of first connection members electrically coupling the first bonding pads with the first bonding fingers; a second semiconductor chip disposed over the first semiconductor chip and the first surface of the substrate and a plurality of second bonding pads in the edges of the lower surface; a plurality of second connection members electrically coupling the second bonding pads with the second bonding fingers of the substrate adjacent to the second bonding pads; and an encapsulation member formed over the first surface of the substrate to cover side surfaces of the second semiconductor chip.. . ... Sk Hynix Inc

10/01/15 / #20150279661

Fine pattern structures having block co-polymer materials

A fine pattern structure includes a layer having or including alternating protrusion portions and recess portions, polymer patterns disposed in recess regions formed by the recess portions, brush patterns disposed on top surfaces of the protrusion portions, and a block co-polymer layer including first polymer block patterns formed on the brush patterns and second polymer block patterns formed on the polymer patterns.. . ... Sk Hynix Inc

10/01/15 / #20150279477

Fuse array

A fuse array may include: an e-fuse including a plurality of active regions having a floating node and a contact node, and a plurality of gates overlapping the respective active regions and separated from each other between the floating node and the contact node; and a plurality of fuse sets each including two or more e-fuses and sharing the floating node or the contact node.. . ... Sk Hynix Inc

10/01/15 / #20150279471

Semiconductor device

A semiconductor device includes a plurality of memory blocks, wherein each of the plurality of memory blocks includes a first select transistor electrically coupled to a common source line, a second select transistor electrically coupled to a bit line, and a plurality of memory cells electrically coupled between the first and second select transistors, and an operation circuit suitable for applying operation voltages for a program operation, a read operation, and an erase operation to a selected memory block selected from the plurality of memory blocks, and applying a first positive voltage to gates of the first select transistors in unselected memory blocks of the plurality of memory blocks when an erase voltage is applied to the common source line during the erase operation.. . ... Sk Hynix Inc

10/01/15 / #20150279469

Nonvolatile memory device, program method thereof, and data processing system including the same

A program method of a nonvolatile memory device includes a pre-program verify step for verifying a threshold voltage of a selected memory cell; a step of setting a bit line voltage of the selected memory cell according to the threshold voltage of the selected memory cell which is determined through the pre-program verify step; a step of applying a program voltage to the selected memory cell set with the bit line voltage; and a post-program verify step for verifying a programmed state of the selected memory cell applied with the program voltage.. . ... Sk Hynix Inc

10/01/15 / #20150279443

Semiconductor memory and method for operating the same

A semiconductor memory may include: a bank control signal generation unit suitable for sequentially generating a plurality of bank control signals for controlling a memory bank based on an active command, a signal detection unit suitable for detecting a firstly activated signal and a lastly activated signal among the bank control signals, and a bank enable control unit suitable for controlling an active period of the memory bank in response to the detected signals.. . ... Sk Hynix Inc

10/01/15 / #20150279442

Semiconductor memory device and semiconductor memory system including the same

A semiconductor memory device includes a plurality of normal word lines and a plurality of redundancy word lines which are disposed adjacent to the normal word lines, a detection block suitable for detecting a first word line whose active history satisfies a predetermined condition and a second word line adjacent to the first word line as a target word line and a target neighboring word line, among the normal word lines and the redundancy word lines, and a control block suitable for sequentially refreshing the normal word lines and the redundancy word lines whenever a refresh command is applied, and additionally refreshing the target word line, the target neighboring word line and a normal word line adjacent to the redundancy word lines among the normal word lines.. . ... Sk Hynix Inc

10/01/15 / #20150278128

Resistive memory apparatus having hierarchical bit line structure

A resistive memory apparatus includes a plurality of bit lines, a plurality of local bit lines, and a plurality of global bit lines. The plurality of bit lines is electrically coupled to a plurality of memory cells. ... Sk Hynix Inc

10/01/15 / #20150277392

Semiconductor device

A semiconductor device, wherein the semiconductor device includes a high-voltage supply circuit suitable for supplying a high voltage; a discharge circuit suitable for discharging the high voltage; and an auxiliary-voltage supply circuit suitable for supplying a first auxiliary voltage, which varies according to an operation state of the high-voltage supply circuit, to a reference node of the discharge circuit.. . ... Sk Hynix Inc

10/01/15 / #20150276841

Noise detection circuit and semiconductor system using the same

A noise detection circuit may include a divider configured to receive a clock signal and a clock bar signal, divide the clock signal and the clock bar signal, and generate a first divided signal and a second divided signal. The noise detection circuit may also include a noise detection reference block configured to reflect a power supply voltage level variation on the first divided signal and the second divided signal, and generate a first reference signal and a second reference signal, and a duty sensing unit configured to generate first duty information and second duty information of the clock signal in response to the first reference signal and the second reference signal. ... Sk Hynix Inc

10/01/15 / #20150273790

Fine pattern structures having block co-polymer materials

A fine pattern structure includes a lower hard mask layer on a pattern formation layer having a first region and a second region, first upper hard mask patterns disposed on the lower hard mask layer in the first region to expose portions of the lower hard mask layer, a second upper hard mask pattern covering the lower hard mask layer in the second region, guide patterns on the first and second upper hard mask patterns, neutralization patterns on the exposed portions of the lower hard mask layer in the first region, a first block co-polymer layer covering the guide patterns in the first region and the neutralization patterns, and a second block co-polymer layer covering the guide pattern in the second region.. . ... Sk Hynix Inc

09/24/15 / #20150270995

Receiver of semiconductor apparatus and semiconductor system including the same

A receiver of a semiconductor apparatus includes a first buffer unit configured to buffer a first positive input signal and a first negative input signal having a phase opposite the phase of the first positive input signal and to output the buffered first positive input signal as a first positive transmission signal and to output the buffered first negative input signal as a first negative transmission signal in response to a first enable signal, a second buffer unit configured to buffer a second positive input signal and a second negative input signal having a phase opposite the phase of the second positive input signal and to output the buffered second positive input signal as a second positive transmission signal and to output the buffered second negative input signal as a second negative transmission signal in response to a second enable signal, is and an output unit configured to invert one of the first and second positive transmission signals and to output the inverted one of the first and second positive transmission signals as a positive output signal, and to invert one of the first and second negative transmission signals and to output the inverted one of the first and second negative transmission signals as a negative output signal.. . ... Sk Hynix Inc

09/24/15 / #20150270834

Method for reducing noise using layout scheme and comparing device

A comparing device includes a first stage comparator and a second stage comparator serially coupled to the first stage comparator, wherein output lines of the second stage comparator are disposed to be overlapped with respective input lines of the second stage comparator.. . ... Sk Hynix Inc

09/24/15 / #20150270482

Electronic device and method for fabricating the same

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an interlayer dielectric layer formed over a substrate including first and second areas; a first contact plug contacted with the substrate through the interlayer dielectric layer of the second area; an anti-peeling layer formed over the interlayer dielectric layer including the first contact plug; a second contact plug contacted with the substrate through the anti-peeling layer and the interlayer dielectric layer in the first area; and a variable resistance pattern contacted with the second contact plug.. ... Sk Hynix Inc

09/24/15 / #20150270362

Semiconductor device and method of fabricating the same

A semiconductor device and a method for manufacturing the same are capable of improving gidl in a buried gate, and preventing degradation of device characteristics and reliability due to reduction in gate resistance. The semiconductor device may include: junction regions formed at both sidewalls of a trench formed in a semiconductor substrate; a first gate electrode formed in a lower portion of the trench; a second gate electrode formed on at least one inner sidewall of the trench which overlaps one of the junction regions on the first gate electrode; and a third gate electrode formed on one side of the second gate electrode on the first gate electrode.. ... Sk Hynix Inc

09/24/15 / #20150270360

Nonvolatile memory devices having single-layered floating gates

A nonvolatile memory device includes a plurality of twin cells arrayed on a substrate. Each of the plurality of twin cells includes a drain mesa protruding from a surface of a substrate. ... Sk Hynix Inc

09/24/15 / #20150270283

Nonvolatile memory device, method for operating the same, and method for fabricating the same

A nonvolatile memory device includes a substrate including a plurality of active regions which are constituted by a p-type semiconductor; first and second vertical strings disposed over each active region, wherein each of the first and second strings includes a channel vertically extending from the substrate, a plurality of memory cells, and a select transistor, wherein the plurality of memory cells and the select transistor are located along the channel; and a bottom gate being interposed between a lowermost memory cell and the substrate, contacting the channel with a first gate dielectric layer interposed therebetween, and controlling connection of the first vertical string with the second vertical string.. . ... Sk Hynix Inc

09/24/15 / #20150270281

Semiconductor memory device and method of fabricating the same

A semiconductor memory device includes insulating patterns and conductive patterns stacked alternately with each other, penetrating structures passing through the insulating patterns and the conductive patterns, and deposition suppressing layers formed on one end portions of respective interfaces between the insulating patterns and the conductive patterns.. . ... Sk Hynix Inc

09/24/15 / #20150270252

Stack package and method for manufacturing the same

A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.. . ... Sk Hynix Inc

09/24/15 / #20150270248

Semiconductor package and guard units

A semiconductor package may include: a plurality of slave chips stacked over a master chip through a through silicon via (tsv); a first guard unit disposed around each of the slave chips; and a second guard unit formed at a first distance from the first guard unit and disposed at the master chip.. . ... Sk Hynix Inc

09/24/15 / #20150270229

Semiconductor chip and semiconductor package having the same

A semiconductor chip includes a semiconductor substrate having a front surface, a circuit unit formed within the semiconductor substrate and extending from the front surface into the semiconductor substrate, and a rear surface opposite the front surface, and a girder beam disposed outside of the circuit unit and within the semiconductor substrate.. . ... Sk Hynix Inc

09/24/15 / #20150270220

Semiconductor devices having through electrodes and methods of manufacturing the same

Semiconductor devices are provided. The semiconductor device includes a semiconductor layer having a first surface and a second surface that are opposite each other, a through electrode penetrating the semiconductor layer and having a protrusion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed over the first surface of the semiconductor layer and electrically coupled to the through electrode, a polymer pattern disposed over the second surface of the semiconductor layer to enclose a part of the protrusion of the through electrode, and a back-side bump covering an upper surface and a sidewall of a remaining part of the protrusion of the through electrode and extending over a portion of the polymer pattern.. ... Sk Hynix Inc

09/24/15 / #20150270165

Semiconductor device and method of fabricating the same

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes conductive patterns and interlayer insulating patterns having a stair structure and being alternately stacked, pad patterns connected to end portions of upper surfaces of the conductive patterns exposed through the stair structure, and a channel film penetrating the conductive patterns and the interlayer insulating patterns.. ... Sk Hynix Inc

09/24/15 / #20150270138

Method for forming fine patterns of semiconductor device

A method for forming fine patterns includes: forming a sacrificial layer over an etch target layer; forming a plurality of sacrificial patterns each of which has at least one tapered point at each end of each sacrificial pattern by selectively etching the sacrificial layer; forming spacers at sides of each of the sacrificial patterns; removing the sacrificial layer; and forming the fine patterns by using the spacers as etch barriers and etching the etch target layer.. . ... Sk Hynix Inc

09/24/15 / #20150270009

Semiconductor memory device and method of operating the same

The semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit unit configured to perform a program voltage applying operation, a first verifying operation, and a detrap voltage applying operation with respect to the plurality of memory cells, and a control logic unit configured to issue at least one command to the peripheral circuit unit to determine whether to perform the detrap voltage applying operation based on a result of the first verifying operation performed following the performance of the program voltage applying operation.. . ... Sk Hynix Inc

09/24/15 / #20150270003

Non-volatile memory and method for programming the same

A method for programming a non-volatile memory includes applying a first program pulse to a program cell one or more times until a threshold voltage of the program cell reaches a preliminary target voltage, which is lower than a target voltage, while supplying a first voltage to a bit line corresponding to the program cell, and applying a second program pulse to the program cell a predetermined number of times while supplying a second voltage, which is higher to than the first voltage, to the bit line after the threshold voltage of the program cell reaches the preliminary target voltage.. . ... Sk Hynix Inc

09/24/15 / #20150269980

Semiconductor memory device

A semiconductor memory device includes first and second memory regions configured to store data in a mirrored fashion with respect to each other during a high speed operation period; and a read operation block configured to repeatedly and alternately select the first and second memory regions and read data from a selected memory region, in the case where the first or second memory region is repeatedly selected in read operations of at least two times during the high speed operation period.. . ... Sk Hynix Inc

09/24/15 / #20150269979

Semiconductor apparatus and data bit inversion

A semiconductor apparatus may include a first semiconductor chip; and a second semiconductor chip configured to transmit/receive signals to/from the first semiconductor chip. Further, a serializer/deserializer (serdes) configured to serialize/deserialize input/output signals and a data bit inversion (dbi) logic electrically coupled to the serdes and configured to perform a data inversion function on input/output data of the serdes may be arranged in a preset region of any one of the first and second semiconductor chips.. ... Sk Hynix Inc

09/24/15 / #20150269021

Data storage device and operating method thereof

An operating method of a data storage device includes performing an error correcting operation for first data and verifying the error correcting operation to determine whether one or more error decision bits determined as an error through the error correcting operation are actual error bits or normal bits, when a result of the error correcting operation is a pre-correction success.. . ... Sk Hynix Inc

09/17/15 / #20150264284

Ramp signal generator and cmos image sensor having the same

A ramp signal generator may include a ramp signal generation unit suitable for generating a ramp signal and a gain amplification control signal, an overlap voltage generation unit suitable for generating an overlap voltage to be overlapped with the ramp signal, and a voltage overlapping unit suitable for controlling a voltage gain by amplifying the ramp signal according to the gain amplification control signal, and overlapping the overlap voltage with the ramp signal.. . ... Sk Hynix Inc

09/17/15 / #20150264281

Replica noise generator using pixel modeling and ramp signal generator including the same

A replica noise generator includes a control logic unit suitable for outputting a capacitance adjusting signal; a replica noise generation unit suitable for generating a replica noise through a coupling of a power voltage used in a pixel array by adjusting a capacitance value in response to the capacitance adjusting signal; and a source follower suitable for inputting the generated replica noise.. . ... Sk Hynix Inc

09/17/15 / #20150263739

Latency control circuit and semiconductor apparatus using the same

A latency control circuit may include a first latency control section configured to control a latency of a delay-locked termination signal according to a first divided clock signal, and generate a first preliminary signal, and a second latency control section configured to control the latency of the delay-locked termination signal according to a first divided clock bar signal which is generated by inverting the first divided clock signal, and generate a second preliminary signal. The latency control circuit may also include a signal combination unit configured to shift the first preliminary signal and the second preliminary signal by latency values set differently from each other, according to the first divided clock signal, and generate a first combined signal and a second combined signal, and a signal generation unit configured to generate a latency-controlled termination signal in response to the first combined signal and the second combined signal.. ... Sk Hynix Inc

09/17/15 / #20150263714

Ramp signal generator with noise canceling function

A ramp signal generator includes a reset control block suitable for generating a switch control signal according to a reset control signal from a control unit; a ramp signal generation block suitable for generating differential ramp signals, which include a power noise or a ground noise as well as a ramp noise; and a common noise canceling unit suitable for being initialized according to the switch control signal, and suitable for canceling common noise through a differential operation between the differential ramp signals.. . ... Sk Hynix Inc

09/17/15 / #20150263711

Buffer circuit and operation method thereof

A buffer circuit includes an amplifying unit suitable for comparing an input voltage of an input terminal with an output voltage of an output terminal, a current sinking unit suitable for controlling a sinking current of the amplifying unit when the input voltage is varied, and a current compensation unit suitable for uniformly maintaining a sinking current amount of the current sinking unit.. . ... Sk Hynix Inc

09/17/15 / #20150263704

Data driving circuit

A data driving circuit includes: an equalizer which transmits an input data as an output signal while a dock is at a first level and equalizes the output signal while the clock is at a second level; a driver which drives an output data in response to the input data; and a compensator which drives the output data in response to the output signal.. . ... Sk Hynix Inc

09/17/15 / #20150263703

Semiconductor devices and semiconductor systems for conducting a training operation

The semiconductor device includes a flag signal generator, a reference voltage generator and a first buffer. The flag signal generator generates a flag signal in response to an internal command and an information code. ... Sk Hynix Inc

09/17/15 / #20150263283

Method of fabricating semiconductor integrated circuit having phase-change layer

A method of fabricating a semiconductor integrated circuit that includes forming a lower electrode in a semiconductor substrate, forming an interlayer insulating layer including a phase-change region exposing the lower electrode on the semiconductor substrate, forming a first phase-change layer having a crystalline state along surfaces of the interlayer insulating layer and an exposed lower electrode, and growing a second phase-change layer on the first phase-change layer based on the crystallinity of the first phase-change layer to be filled in the phase-change region.. . ... Sk Hynix Inc

09/17/15 / #20150263282

Method for fabricating semiconductor apparatus

A method for fabricating a semiconductor apparatus includes setting a semiconductor substrate in a process chamber, increasing an internal temperature of the process chamber to a predetermined temperature for pyrolyzing a source gas, supplying the source gas to the inside of the process chamber and pyrolyzing ions of the source gas to remain on the semiconductor substrate, and forming the ohmic contact layer by supplying a reaction gas to the inside of the process chamber, wherein the reaction gas is reacted with non-metal ions pyrolyzed from source gas.. . ... Sk Hynix Inc

09/17/15 / #20150263119

Semiconductor device with metal gate electrode and high-k dielectric material and method for fabricating the same

A semiconductor device includes a gate stacked structure including a gate dielectric layer over a semiconductor substrate, a metal layer formed over the gate dielectric layer, and a capping layer formed over the metal layer, where the capping layer includes a chemical element with a higher concentration at an interface between the capping layer and the metal layer than another region of the capping layer and the chemical element is operable to control an effective work function (ewf) of the gate stacked structure.. . ... Sk Hynix Inc

09/17/15 / #20150263111

Semiconductor device and method for forming the same

A semiconductor device includes a semiconductor substrate including a trench, a gate insulation film located over a bottom and sidewall of the trench, a first gate formed over the gate insulation film and in a lower portion of the trench, a second gate formed over the first gate and in an upper portion of the trench, a multi-layered structure provided between the gate insulation film and the second gate.. . ... Sk Hynix Inc

09/17/15 / #20150263071

Electronic device and method for fabricating the same

Provided is an electronic device including a semiconductor memory which includes a first region in which a first variable resistance element for storing data is disposed; and a second region in which a reference resistance element for sensing data stored in the first variable resistance element is disposed, and wherein the reference resistance element comprising: a plurality of second variable resistance elements formed of the same material at the same level as the first variable resistance element; a plurality of contacts coupled to each of the second variable resistance elements; and a first pad coupled to part of the contacts which are coupled to one of two adjacent second variable resistance elements and part of the contacts which are coupled to the other of the two adjacent second variable resistance elements for coupling the two adjacent second variable resistance elements with each other.. . ... Sk Hynix Inc

09/17/15 / #20150263070

Electronic device and method for fabricating the same

An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of first pillar electrodes spaced apart from each other, a plurality of second pillar electrodes spaced apart from each other, each second pillar electrode being spaced apart from adjacent first pillar electrodes, and a plurality of variable resistance layers enclosing sidewalls of corresponding second pillar electrodes, respectively, wherein a group of adjacent first pillar electrodes is in contact with one variable resistance layer, and a group of adjacent variable resistance layers is in contact with one first pillar electrode.. ... Sk Hynix Inc

09/17/15 / #20150263016

Semiconductor device

A semiconductor device includes a common source region formed in a semiconductor substrate, a bit line formed over the semiconductor substrate, first and second vertical channel layers coupled between the bit line and the common source region, wherein the first and second vertical channel layers are alternately arranged on the semiconductor substrate, first conductive layers stacked over the semiconductor substrate to surround one side of the first vertical channel layer, second conductive layers stacked over the semiconductor substrate to surround one side of the second vertical channel layer, and a charge storage layer formed between the first vertical channel layer and the first conductive layers and between the second vertical channel layer and the second conductive layers.. . ... Sk Hynix Inc

09/17/15 / #20150263011

Semiconductor device and method for manufacturing the same

A semiconductor device and a method of manufacturing the same, wherein the semiconductor device includes a memory string; a first metal pattern for a source line formed under the memory string; a second metal pattern for a peripheral circuit interconnection horizontally spaced apart from the first metal pattern; and peripheral circuit transistors connected to the second metal pattern.. . ... Sk Hynix Inc

09/17/15 / #20150263009

Semiconductor device having buried gate, method of fabricating the same, and module and system having the same

A semiconductor device includes junction regions formed in upper portions of both sidewalls of a trench formed in a semiconductor substrate, a first gate electrode buried in the trench and having a stepped upper surface, and a second gate electrode formed on the first gate electrode to overlap a junction region.. . ... Sk Hynix Inc

09/17/15 / #20150262946

Semiconductor device and method for forming the same

A semiconductor device includes a first pad region including a plurality of first storage nodes, a second pad region neighboring the first pad region and including a plurality of second storage nodes, a coupling portion disposed between the first pad region and the second pad region, and a plate electrode disposed over the plurality of first storage nodes of the first pad region and the plurality of second storage nodes of the second pad region, and disposed in the coupling portion to interconnect the first pad region and the second pad region.. . ... Sk Hynix Inc

09/17/15 / #20150262678

Semiconductor device and programming method thereof

A semiconductor device includes a plurality of electrically coupled memory cells in a generally vertical configuration extending in a generally perpendicular direction from a semiconductor substrate, a peripheral circuit configured to program the memory cells, and a control circuit configured to program a memory cell selected from the plurality of memory cells to trap charge in the selected memory cell, and to issue at least one command to the peripheral circuit to manage a dispersion of at least a portion of the trapped charge between memory cells adjacent to the selected memory cell.. . ... Sk Hynix Inc

09/17/15 / #20150262651

Gapless pattern detection circuit and semiconductor device including the same

A semiconductor device that includes: a detection circuit suitable for detecting a gapless pattern section of a detection target signal; and an internal circuit suitable for performing a normal operation during a normal section and additionally performing the normal operation during a compensating section corresponding to the gapless pattern section in response to a detection result signal outputted from the detection circuit.. . ... Sk Hynix Inc

09/17/15 / #20150262646

Semiconductor device

A semiconductor device may include a write control block configured to generate a plurality of write enable signals for controlling a write operation, and a write delay block configured to apply delay times to a plurality of write data which are transmitted through a write global input/output line. The semiconductor device may also include a plurality of banks configured to operate in response to the plurality of write enable signals and receive the plurality of write data, wherein the plurality of write data have different delay times according to physical positions of the plurality of banks.. ... Sk Hynix Inc

09/17/15 / #20150262637

Electronic device and method for fabricating the same

This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a contact plug which is disposed over a substrate and extends in a vertical direction; a variable resistance element which is coupled to the contact plug and includes a first magnetic layer having a variable magnetization direction, a second magnetic layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the first magnetic layer and the second magnetic layer; and a third magnetic layer which surrounds a sidewall of the contact plug and has a same magnetization direction as the second magnetic layer.. ... Sk Hynix Inc

09/17/15 / #20150262635

Latch circuit and semiconductor device including the same

A latch circuit includes: first to nth storage nodes, where n is an even number equal to or greater than 4; first to nth pairs of transistors, each of which includes a pmos transistor and an nmos transistor coupled in series with each other through a corresponding storage node among the first to nth storage nodes, wherein each of the first to nth storage nodes is coupled with a gate of the nmos transistor included in a previous one of the pairs of transistors and a gate of the pmos transistor included in a next one of the pairs of transistors; and an initialization block suitable for initializing voltages of two or more nodes among the first to nth storage nodes to a first level in response to an initialization signal.. . ... Sk Hynix Inc

09/17/15 / #20150261437

Electronic device

An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of planes vertically stacked over a substrate. ... Sk Hynix Inc

09/10/15 / #20150256184

Semiconductor apparatus and semiconductor system including the same, and method of operating the same

A semiconductor apparatus includes a clock division block suitable for generating a first internal dock and a second internal clock having a first phase difference at which active sections of the first internal clock and the second internal clock overlap with each other by dividing a phase of a source clock at a predetermined rate, and a phase detection block suitable for outputting detection result information generated by combining a result obtained by detecting a phase of the first internal clock at a predetermined edge of a strobe signal and a result obtained by detecting a phase of the second internal clock at the predetermined edge of the strobe signal.. . ... Sk Hynix Inc

09/10/15 / #20150256183

Semiconductor device and semiconductor system including the same

A semiconductor device includes a dock division block suitable for dividing a frequency of a source clock and generating first and second internal clocks; a strobe division block suitable for dividing a frequency of a strobe signal, and generating first and second internal strobe signals; and a phase difference detection block suitable for generating and alternately outputting first and second detection information as a detection result information.. . ... Sk Hynix Inc

09/10/15 / #20150256153

Semiconductor devices and semiconductor systems including the same

A semiconductor system includes a controller and a semiconductor device. The controller receives a temperature code signal and responsively generates a mode set signal operable to adjust a level variation and a voltage variation rate of a temperature voltage signal, wherein the temperature voltage signal level varies according to temperature when a logic level combination of the temperature code signal is different from a predefined logic level combination. ... Sk Hynix Inc

09/10/15 / #20150255717

Variable resistive memory device and method of fabricating the same and method of driving the same

Provided are a variable resistive memory device, and methods of fabricating and driving the same. The variable resistive memory device includes a plurality of memory cells arranged in a first direction and in a second direction different from the first direction, each of the plurality of memory cells comprising a variable resistor and a selection device serially connected w the variable resistor. ... Sk Hynix Inc

09/10/15 / #20150255472

Nonvolatile memory device and method for fabricating the same

A nonvolatile memory device includes a floating gate formed over a substrate; a contact plug formed on a first side of the floating gate and disposed parallel to the floating gate with a gap defined therebetween; and a spacer formed on a sidewall of the floating gate and filling the gap, wherein the contact plug and the floating gate have a sufficiently large overlapping area to enable the contact plug to operate as a control gate for the floating gate.. . ... Sk Hynix Inc

09/10/15 / #20150255466

Semiconductor device with line-type air gaps and method for fabricating the same

A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.. . ... Sk Hynix Inc

09/10/15 / #20150255464

Semiconductor device having buried gate and manufacturing method thereof

A dummy active region is formed in a region in which a gate contact for supplying operation power to the buried gate is formed, and a pn junction diode connected to the gate contact in a reverse bias direction is formed in the dummy active region. Current leakage, in which current flows out toward a substrate, is prevented even when misalignment of the gate contact occurs.. ... Sk Hynix Inc

09/10/15 / #20150255427

Chip stack embedded packages

A chip stack embedded package includes a first dielectric layer having a multistep cavity therein, a first plurality of semiconductor chips disposed in a first level of the multistep cavity, a second plurality of semiconductor chips disposed in a second level of the multistep cavity, and a second dielectric layer filling the multistep cavity to cover the first and second pluralities of semiconductor chips.. . ... Sk Hynix Inc

09/10/15 / #20150255385

Semiconductor device and method of fabricating the same

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes insulating layers stacked in the shape of stairs, and conductive layers alternately stacked with the insulating layers, wherein the conductive layers each include a first region interposed between upper and lower insulating layers thereof, among the insulating layers, and a second region which extends from the first region and protrudes between the upper and lower insulating layers, and wherein a protruding part formed on a sidewall or an upper surface of the second region.. ... Sk Hynix Inc

09/10/15 / #20150255291

Semiconductor device and method for fabricating the same

A method for fabricating a semiconductor device includes: implanting a first species into a substrate at a cold temperature to form a first region; and implanting a second species into the substrate at a hot temperature to form a second region that is adjacent to the first region.. . ... Sk Hynix Inc

09/10/15 / #20150255168

Semiconductor memory device and memory system including the same

A semiconductor memory device includes a command buffering unit suitable for receiving and buffering a command signal based on an enable control signal, a fuse array suitable for programming data based on the command signal, and an enable control unit suitable for generating the enable control signal, wherein an activation operation on the command buffering unit by the enable control signal is controlled during a programming operation period of the fuse array.. . ... Sk Hynix Inc

09/10/15 / #20150255140

Semiconductor memory device and refresh control system

A semiconductor memory device includes an address latch unit suitable for consecutively latching first refresh addresses, which correspond to successively-activated word lines, from consecutively received addresses for word lines to be activated in response to word line hit signals identifying the successively-activated word lines; an address comparison unit suitable for generating a comparison result signal by comparing the previously latched first address with the currently latched first address; a refresh control unit suitable for selecting a first refresh operation corresponding to the currently latched first address, and a second refresh operation corresponding to a second address in response to the comparison result signal, and a refresh command signal; and a refresh operation unit suitable for performing the first and second refresh operations on memory cells therein according to the selection of the refresh control unit.. . ... Sk Hynix Inc

09/10/15 / #20150255132

Semiconductor system and method of operating the same

A semiconductor system includes multiple semiconductor devices operating commonly in response to a command signal, wherein each of the multiple semiconductor devices is independently activated according to each of multiple data strobe signals respectively corresponding to the multiple semiconductor devices; and a controller suitable for providing the command signal and the multiple data strobe signals.. . ... Sk Hynix Inc

09/10/15 / #20150255131

Stacked semiconductor apparatus and semiconductor system capable of inputting signals through various paths

A semiconductor apparatus includes a control signal reception portion. The control signal reception portion may set information related to operation of a memory chip by receiving a command signal and an address signal from one among a stack chip test portion, a control signal interface portion and a test setting portion.. ... Sk Hynix Inc

09/10/15 / #20150255128

Amplifying circit and semiconductor memory device inclding the same

An amplifying circuit includes a first sense amplifying unit suitable for sensing and amplifying data on input/output lines, a second sense amplifying unit suitable for sensing and amplifying the data on the input/output lines or an output signal of the first sense amplifying unit, and a control unit suitable for activating the first sense amplifying unit during an initial operation period of an active operation and inactivating the first sense amplifying unit after the initial operation period, wherein the second sense amplifying unit performs a sensing and amplifying operation, based on the output signal of the first sense amplifying unit during the initial operation period, and based on the data on the input/output lines after the initial operation period.. . ... Sk Hynix Inc

09/10/15 / #20150254006

Semiconductor device and method of operating the same

A semiconductor device includes a plurality of memory blocks each including a plurality of memory cells, a circuit group performing a program operation, a read operation and an erase operation on a selected memory block, among the plurality of memory blocks, and a control circuit controlling the circuit group to program the memory cells of the selected memory block in a healing pattern, before the program operation is performed on the selected memory block, wherein the memory cells of the healing pattern include erased memory cells and programmed memory cells arranged alternately.. . ... Sk Hynix Inc

09/03/15 / #20150249443

Data output circuit of semiconductor apparatus

A data output circuit of a semiconductor apparatus may include a first driver coupled to an output terminal via a first node, a second driver coupled to the output terminal via a second node and a controller coupled to the first and second drivers and configured to adjust a slew rate of a data signal output via the output terminal.. . ... Sk Hynix Inc

09/03/15 / #20150249206

Electronic device and method for fabricating the same

This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes an interlayer dielectric layer formed over a substrate and having a contact hole; a lower contact filled in a part of the contact hole; and a variable resistance element which is disposed over and coupled to the lower contact, and has a first part filled in the contact hole and a second part disposed over the first part and protruding over the interlayer dielectric layer, wherein the first part includes a first metal which has a higher electron affinity than a component included in the second part, and an oxide of the first metal is an insulating material.. ... Sk Hynix Inc

09/03/15 / #20150249204

Electronic device and method for fabricating the same

An electronic device comprising a semiconductor memory unit includes: variable resistance patterns formed over a substrate; a protective layer formed over the substrate including the variable resistance patterns and including a leakage current blocking layer that is spaced apart from the variable resistance patterns; and contact plugs formed adjacent to the variable resistance patterns over the substrate and penetrating through the protective layer to be coupled with the substrate.. . ... Sk Hynix Inc

09/03/15 / #20150249154

Electronic device and method for fabricating the same

This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes a transistor comprising a gate where at least a portion of the gate is filled in a semiconductor substrate including an active region defined by an isolation layer; a junction which is disposed over the active region at both side of the gate and includes a metal-containing layer and a first semiconductor layer doped with an impurity and interposed between the active region and the metal-containing layer; and a material layer which is interposed between the junction and the active region to prevent diffusion of the impurity from the first semiconductor layer and defines an opening for coupling the junction to the active region.. ... Sk Hynix Inc

09/03/15 / #20150249111

Electronic device

An electronic device is provided to comprise a semiconductor memory unit that comprises: a substrate including active regions, which are extended in a second direction and disposed from each other in a first direction; a plurality of gates extended in the first direction and across with the active regions; a lower contact disposed in both sides of gates and coupling the active regions in the first direction; an upper contact of the lower contact overlapping with the active region out of the active regions in a side of each gate, and overlapping with the active regions in the other side of each gate; and first and second interconnection lines coupled to the upper contact, extended in the second direction, and being alternately disposed from each other in the first direction, wherein the upper contact of a side of the gates has a zigzag shape in a first oblique direction.. . ... Sk Hynix Inc

09/03/15 / #20150249110

Electronic device and method for fabricating the same

An electronic device includes a semiconductor memory that includes: an inter-layer dielectric layer which is formed over a substrate; a contact plug which is coupled with the substrate by passing through the inter-layer dielectric layer and has a protruding portion over the inter-layer dielectric layer; a first variable resistance pattern which is formed over the contact plug; and a protective layer which covers the first variable resistance pattern and a portion of sidewalls of the contact plug in such a manner that the sidewalls of the contact plug are exposed.. . ... Sk Hynix Inc

09/03/15 / #20150249095

Nonvolatile memory device and method of fabricating the same

This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate, a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, and etch stop layers including metal silicide and formed over the pipe connection gate electrode.. ... Sk Hynix Inc

09/03/15 / #20150249075

Semiconductor chips having a dual-layered structure, packages having the same, and methods of fabricating the semiconductor chips and the packages

Dual-layered structural semiconductor chips are provided. The semiconductor chip includes a first semiconductor chip and a second semiconductor chip bonded to the first semiconductor chip. ... Sk Hynix Inc

09/03/15 / #20150248938

Data storage device

A data storage device that includes a nonvolatile memory device, a controller suitable for controlling the nonvolatile memory device and for reading and writing data to the nonvolatile memory device, and a power management unit suitable for supplying power to the nonvolatile memory device. The controller may control the power management unit to adjust the power supplied to the nonvolatile memory device.. ... Sk Hynix Inc

09/03/15 / #20150248932

Electronic device

Provided is an electronic device including a semiconductor memory unit. The semiconductor memory unit may include: a storage cell comprising a variable resistance element; a first selecting element coupled to one end of the storage cell and having a threshold voltage set to a first voltage; and a second selecting element coupled to the other end of the storage cell and having a threshold voltage set to a second voltage higher than the first voltage.. ... Sk Hynix Inc

08/27/15 / #20150244954

Driver and image sensing device including the same

A driver includes a first level shifting unit generating a second signal swinging in a second threshold range in response to a first signal swinging in a first threshold range, a second level shifting unit generating a third signal swinging in a third threshold range in response to the second signal, a first pull-up driving unit driving an output terminal with a first high-voltage in response to the second signal, a first pull-down driving unit driving the output terminal with a first low voltage in response to the third signal, a second pull-down driving unit driving the output terminal with a second low voltage higher than the first low voltage in response to the fourth signal, and a first path coupling unit coupling the second pull-down driving unit with the output terminal in response to the second signal.. . ... Sk Hynix Inc

08/27/15 / #20150244391

Ramp signal generator using programmable gain amplifier

According to an embodiment of the inventive concept disclosed in this application, a ramp signal generator may include a ramp signal generation unit suitable for generating a ramp signal, a gain amplification control unit suitable for outputting a gain amplification control signal for controlling a voltage gain in response to a control signal from a control unit; and a programmable gain amplifier (pga) suitable for controlling the voltage gain by amplifying the ramp signal provided from the ramp signal generation unit in response to the gain amplification control signal from the gain amplification control unit.. . ... Sk Hynix Inc

08/27/15 / #20150244379

Semiconductor device and operating method thereof

A semiconductor device includes first and second circuits disposed separately from each other. The first circuit may include: a counting unit suitable for generating count codes, each bit of which is cyclically changing, wherein the count codes include a number of toggles of a sampling signal toggling with a preset frequency representing a distance of single round trip of the sampling signal between the first and second circuits; and a pulse generation unit suitable for generating a measurement pulse according to the count codes representing the distance, wherein the pulse generation unit determines a pulse width of the measurement pulse according to the distance.. ... Sk Hynix Inc

08/27/15 / #20150244356

Power-up signal generation circuit

A power-up signal generation circuit includes a control signal generation unit suitable for generating first and second control voltages based on a power-up signal, a level tracing voltage generation unit suitable for generating a level tracing voltage whose voltage level varies based on the first and second control voltages, and a power-up signal generation unit suitable for generating the power-up signal based on the level tracing voltage, and providing a feedback on the power-up signal to the control signal generation unit.. . ... Sk Hynix Inc

08/27/15 / #20150243707

Tunneling transistor having a vertical channel, variable resistive memory device including the same, and method for manufacturing the same

A tunneling transistor including a semiconductor substrate on which a source is formed in an upper region and having a first semiconductor material layer, a pillar formed on the semiconductor substrate and having a structure in which a channel layer and a drain are sequentially stacked, a gate formed to surround a circumference of the pillar, and a second semiconductor material layer constituting a portion of the source, formed between the source and the channel layer, having the same conductivity type as the source, and having a band gap smaller than the first semiconductor material layer. Wherein, the source and the drain have opposite conductivity types.. ... Sk Hynix Inc

08/27/15 / #20150243673

Semiconductor device

Provided are a semiconductor device. The semiconductor device includes a memory block including a drain select line, word lines, and a source select line, which are spaced apart from one another and stacked in a direction perpendicular to a semiconductor substrate; and a peripheral circuit including a switching device connected to a bit line, which is disposed under a vertical channel layer vertically passing through the drain select line, the word lines, and the source select line.. ... Sk Hynix Inc

08/27/15 / #20150243672

Semiconductor device and method of manufacturing the same

The semiconductor device includes a stacked structure having alternately stacked conductive patterns and interlayer insulating patterns, a through-hole passing through the stacked structure, a channel pattern formed in the through-hole and protruding from an inside of the through hole over the through-hole, and a capping conductive pattern formed to be in contact with the protruded channel pattern and have a width greater than the through-hole.. . ... Sk Hynix Inc

08/27/15 / #20150243634

Semiconductor device

A semiconductor device includes an operation circuit formed on a top surface of a semiconductor substrate, a memory array formed over the operation circuit, an inner pad group formed on an intermediate layer between the operation circuit and the memory array and coupled to the operation circuit, a first outer pad group formed on a bottom surface of the semiconductor substrate, and a wiring structure passing through the semiconductor substrate, and coupling the inner pad group to the first outer pad group.. . ... Sk Hynix Inc

08/27/15 / #20150243619

Conductive bump, semiconductor chip and stacked semiconductor package using the same

A conductive bump includes a step member formed to form a step on a portion of a connection pad; and a conductive member formed on the connection pad and the step member and having an inclined surface which is inclined with respect to the connection pad.. . ... Sk Hynix Inc

08/27/15 / #20150243596

Package substrates, packages including the same, methods of fabricating the packages with the package substrates, electronic systems including the packages, and memory cards including the packages

A package substrate includes a substrate body and a plurality of patterns disposed on the substrate body. The substrate body has a first region including a chip attachment region and a second region adjacent to the first region. ... Sk Hynix Inc

08/27/15 / #20150243375

Semiconductor memory device and operation method thereof

A semiconductor memory device includes a memory cell array including a plurality of memory cells and a plurality of redundancy memory cells, a fuse array to be programmed with information of a defective memory cell among the memory cells of the memory cell array, and a control unit suitable for setting up a program operation section for programming the fuse array in response to an external command, wherein when the control unit sets up the program operation section, the control unit sets up a refresh operation section for refreshing the memory cell array, which is terminated before the program operation section ends without overlapping with the program operation section.. . ... Sk Hynix Inc

08/27/15 / #20150241509

Semiconductor device and operating method thereof

A semiconductor device may include: a fuse array including a plurality of fuses; a voltage generation unit suitable for generating a first measurement voltage having a preset level; and a measurement unit suitable for supplying the first measurement voltage to a sourcing node of the fuse array and a second measurement voltage, which is provided from an external through a first pad, to a sinking node of the fuse array, and outputting a current, which is caused by voltage difference between the first and second measurement voltages and passes through one or more of the multiple fuses, through the first pad.. . ... Sk Hynix Inc

08/20/15 / #20150236706

Delay locked loop and semiconductor apparatus

A delay locked loop includes: a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a delay locked loop clock signal; a delay model unit configured to delay the delay locked loop clock signal by a modeled delay value and output delayed delay locked loop clock signal as a feedback clock signal; a calculation code generation unit configured to convert a phase of the reference clock signal and a phase of the feedback clock signal into a first code and a second code, respectively, and perform a calculation on the first and second codes so as to generate a calculation code; and a delay code generation unit configured to control the delay code in response to the calculation code.. . ... Sk Hynix Inc

08/20/15 / #20150236680

Internal voltage generation circuits

Internal voltage generation circuits are provided. The internal voltage generation circuit includes a code signal generator and an internal voltage generator. ... Sk Hynix Inc

08/20/15 / #20150236675

Semiconductor apparatus and operating method thereof

A sense amplifier control circuit of a semiconductor apparatus includes a driving unit configured to apply a first voltage to a sense amplifier in response to a first driving signal. The driving unit may also be configured to apply a second voltage to the sense amplifier in response to a second driving signal. ... Sk Hynix Inc

08/20/15 / #20150236579

Current generation circuits and semiconductor devices including the same

Semiconductor devices are provided. The semiconductor device may include a current generation circuit and an internal circuit. ... Sk Hynix Inc

08/20/15 / #20150236154

Anti-fuse and method for forming the same

An anti-fuse includes a first gate structure disposed in a semiconductor substrate and a second gate structure that is spaced apart from the first gate structure by a distance and disposed in the semiconductor substrate. The first and second gate structures have different depths from each other in the semiconductor substrate.. ... Sk Hynix Inc

08/20/15 / #20150236126

Semiconductor device having vertical channel, resistive memory device including the same, and method of manufacturing the same

A semiconductor device, a resistive memory device including the same, and a method of manufacturing the same are provided. The semiconductor device includes a pillar extending substantially perpendicular from a semiconductor substrate, the pillar including an inner portion and an outer portion surrounding the inner portion. ... Sk Hynix Inc

08/20/15 / #20150236112

Transistor, semiconductor device and method of manufacturing the same

A semiconductor device including a central region, side regions located in both sides of the central region, and conductive layers including a first barrier pattern formed in the central region, a material pattern formed in the first barrier pattern and having an etch selectivity with respect to the first barrier pattern, and a second barrier pattern formed in the material pattern; and insulating layers alternately stacked with the conductive layers.. . ... Sk Hynix Inc

08/20/15 / #20150236039

Nonvolatile memory device and method of fabricating the same

This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a bottom buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled to the pipe channel layer and extended in a direction substantially perpendicular to the substrate, and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, wherein the pipe connection gate electrode includes a metal silicide layer formed within the groove. ... Sk Hynix Inc

08/20/15 / #20150236037

Nonvolatile memory device and method for fabricating the same

A non-volatile memory device in accordance with one embodiment of the present invention includes a substrate including a p-type impurity-doped region, a channel structure comprising a plurality of interlayer insulating layers that are alternately stacked with a plurality of channel layers on the substrate, a p-type semiconductor pattern that contacts sidewalls of the plurality of channel layers, wherein a lower end of the p-type semiconductor pattern contacts the p-type impurity-doped region, and source lines that are disposed at both sides of the p-type semiconductor pattern and contact the sidewalls of the plurality of channel layers.. . ... Sk Hynix Inc

08/20/15 / #20150236036

Semiconductor device and methods of manufacturing and operating the same

A semiconductor device includes a memory cell array including a vertical channel layer, two or more selection transistors, and a plurality of memory cells formed along the vertical channel; a peripheral circuit suitable for programming the two or more selection transistors and the memory cells; and a control circuit suitable for controlling the peripheral circuit to decrease a pass voltage applied to one word line adjacent to two or more selection lines coupled to the respective selection transistors, during a program operation in which the peripheral circuit applies a program voltage to the two or more selection lines and applies the pass voltage to a plurality of word lines connected to the memory cells.. . ... Sk Hynix Inc

08/20/15 / #20150235950

Semiconductor device and manufacturing method thereof

A semiconductor device includes a spacer having a nitride/oxide/nitride (non) structure. The spacer is disposed between a sidewall of a bit line and a bit line contact and a sidewall of a storage node contact plug to reduce coupling capacitance between the bit line and a storage node contact plug and between the bit line contact and the storage node contact plug.. ... Sk Hynix Inc

08/20/15 / #20150235942

Semiconductor device and method for manufacturing the same

A semiconductor device and a method for manufacturing the same are disclosed. In the semiconductor device, an upper part of a storage node contact plug is increased in size, and an area of overlap between a storage node formed in a subsequent process and a storage node contact plug is increased, such that resistance of the storage node contact plug is increased and device characteristics are improved. ... Sk Hynix Inc

08/20/15 / #20150235715

Stacked semiconductor memory apparatus and test circuit therefor

A stacked semiconductor memory apparatus includes a memory module including a plurality of memory chips; and a logic circuit block with the memory module stacked thereon, configured to be electrically coupled with an interface substrate through a first terminal group and a second terminal group and to communicate with a controller, and to include a test circuit that receives a first test signal through the first terminal group from the controller and outputs the first test signal through the second terminal group in a test mode.. . ... Sk Hynix Inc

08/20/15 / #20150235714

Semiconductor device for parallel bit test and test method thereof

A semiconductor device includes a plurality of memory chips and a plurality of signal selection units respectively corresponding to the plurality of memory chips, and suitable for commonly transferring test data signals from an external to a corresponding one of the plurality of memory chips during a common test mode, wherein one or more of the plurality of signal selection units may transfer the test data signals from the external to corresponding ones of the plurality of memory chips during an individual test mode, and wherein the semiconductor device may be set to the common test mode when a common test signal is enabled, and set to the individual test mode when both the common test signal and a test control signal are enabled.. . ... Sk Hynix Inc

08/20/15 / #20150235708

Non-volatile memory devices and methods of manufacturing the same

This technology relates to nonvolatile memory devices and methods of manufacturing the same. A nonvolatile memory device can include a memory cell array configured to include a plurality of strings, a page buffer unit connected to the plurality of strings, respectively, and configured to sense data, and a switching unit disposed between the memory cell array and the page buffer unit and configured to comprise a variable resistor.. ... Sk Hynix Inc

08/20/15 / #20150235707

Flash multiple-pass write with accurate first-pass write

An instruction to write to a location in the flash memory is received. It is determining if the flash memory exposes a level placement setting associated with defining what voltage range corresponds to what level. ... Sk Hynix Inc

08/20/15 / #20150235702

Semiconductor device and operating method thereof

The semiconductor device includes a cam block including a plurality of vertical strings having a perpendicular configuration with respect to a semiconductor substrate, wherein each of the plurality of vertical strings is electrically coupled to a plurality of word lines and each of the plurality of word lines is electrically coupled to a plurality of cam cells, a peripheral circuit configured to program cam cells selected from the plurality of cam cells, and a control circuit configured to issue at least one command to the peripheral circuit to simultaneously apply a program voltage to an nth word line, an n−1th word line and an n+1th word line to simultaneously program cam cells electrically coupled to the n−1th word line, the nth word line and the n+1th word line, wherein the n−1th word line and an n+1th word line are adjacent to the nth word line and the selected cam cells are electrically coupled to the nth word line.. . ... Sk Hynix Inc

08/20/15 / #20150235697

Nonvolatile memory apparatus and operating method thereof

A method operates a nonvolatile memory apparatus. The method includes performing a first write operation to store first data in first to third memory cells; and performing a second write operation to store second data in the first to third memory cells in which the first data has been stored, wherein, as a result of the first write operation and the second write operation, each of the first to third memory cells has one of first to third states.. ... Sk Hynix Inc

08/20/15 / #20150235694

Semiconductor memory device

A semiconductor memory device includes a control signal generator suitable for generating a control signal corresponding to temperature information, a refresh controller suitable for enabling a refresh signal for a smart refresh operation at a predetermined moment in response to a refresh command signal and enabling the refresh signal for a normal refresh operation at a moment corresponding to the control signal in response to the refresh command signal, and a data storage suitable for storing a data and performing the smart refresh operation and the normal refresh operation in response to the refresh signal of the refresh controller.. . ... Sk Hynix Inc

08/20/15 / #20150235693

Memory system including semiconductor memory device and refresh operation method thereof

A memory system includes a memory module including a plurality of memories and a memory controller suitable for controlling an operation timing of each of the memories, wherein the memories enter a refresh operation mode simultaneously in response to a refresh operation command of the memory controller and individually perform a refresh operation according to the operation timing.. . ... Sk Hynix Inc

08/20/15 / #20150235687

Semiconductor apparatus and testing method thereof

A semiconductor apparatus includes a plurality of memory blocks divided into an even mat group and an odd mat group; and an active control block configured to activate any one group of the even mat group and the odd mat group at a first timing in response to a plurality of test signals, and activate the other group at a second timing.. . ... Sk Hynix Inc

08/20/15 / #20150235685

Semiconductor device

A semiconductor device includes a driving signal generation unit configured to selectively drive a sub word line driving signal in response to a sub word line select signal. The semiconductor device also includes a sub word line driving unit configured to drive a sub word line in response to a main word line select signal and the sub word line driving signal. ... Sk Hynix Inc

08/20/15 / #20150235684

Semiconductor apparatus

A semiconductor apparatus includes: a command control unit configured to decode external signals and generate a read strobe signal or a write strobe signal; a clock enable signal generation unit configured to activate one of a read clock enable signal and a write clock enable signal in response to the read strobe signal or the write strobe signal; and a clock control unit configured to generate a first control clock signal and a second clock control signal in response to an internal clock signal, the read clock enable signal, and the write to clock enable signal.. . ... Sk Hynix Inc

08/20/15 / #20150235683

Semiconductor devices

A semiconductor device including a data aligner that aligns input data in response to internal strobe signals obtained by dividing a data strobe signal to generate a first alignment data and a second alignment data. The semiconductor device may also include a phase sensor that generates a control clock signal in response to a clock signal and senses phases of the internal strobe signals with the control clock signal to generate a selection signal, and a data selector that selectively outputs the first and second alignment data as a first selection alignment data and a second selection alignment data in response to the selection signal.. ... Sk Hynix Inc

08/20/15 / #20150234010

Test circuit and semiconductor apparatus including the same

A test circuit of a semiconductor apparatus includes a plurality of pads, a pattern generator configured to generate at least one internal test pattern in response to at least one pattern select signal, and a plurality of test units configured to transmit the at least one internal test pattern through the plurality of pads in response to a self test mode signal, and to compare the at least one test pattern received via the plurality of pads with the at least one generated internal test pattern and generate at least one test determination value based on the comparison.. . ... Sk Hynix Inc

08/20/15 / #20150234002

Semiconductor device

A semiconductor device includes a normal pad and a first monitoring unit suitable for monitoring whether a bunker is formed in the normal pad based on an inherent resistance component of the normal pad during a probe test.. . ... Sk Hynix Inc

08/13/15 / #20150229300

Receiver circuit

A receiver circuit includes a first amplification unit, a second amplification unit, a first equalizing unit, and a second equalizing unit. The first amplification unit is configured to differentially amplify an input signal and a reference signal and generate a positive intermediate output signal and a negative intermediate output signal. ... Sk Hynix Inc

08/13/15 / #20150229299

Semiconductor device and operation method thereof

A semiconductor device includes a driving unit suitable for driving a plurality of signal lines, which are directly coupled to a plurality of bump pads, to a preset voltage level in a level determination period, and adjusting the preset voltage level in a predetermined order when the level determination period is repeated, a signal input circuit suitable for receiving voltage levels that are inputted through the signal lines and determining logic values for the inputted voltage levels of the signal lines, and an operation unit suitable for receiving voltage levels of the signal lines from the signal input circuit in a parallel manner in the level determination period, latching the logic values of the voltage levels, and serially outputting the logic values through a probe pad.. . ... Sk Hynix Inc

08/13/15 / #20150229296

Semiconductor devices with periodic signal generation circuits and semiconductor systems including the same

A semiconductor system includes a controller and a semiconductor device. The controller receives a temperature signal including information on temperature variation to generate an auto-refresh signal. ... Sk Hynix Inc

08/13/15 / #20150229208

Dc-to-dc converter and method for fabricating the same

A dc-to-dc converter includes: a substrate having a switching element region defined by an isolation layer; a transistor formed over the switching element region; a landing plate formed over the isolation layer; a capacitor formed over the landing plate and includes a bottom plate, a dielectric layer and a top plate; multi-layer metal lines disposed in an upper portion of the transistor and coupled with the transistor; and an interconnection portion coupled with the multi-layer metal lines to electrically connect the transistor with the capacitor.. . ... Sk Hynix Inc

08/13/15 / #20150228896

Semiconductor device and method of fabricating the same

A semiconductor device includes a first conductive layer extending in a first direction, a second conductive layer extending in a second direction and disposed over the first conductive layer, the first and second directions being substantially perpendicular to each other, and a variable resistance layer disposed over the first conductive layer, the variable resistance layer extending in the second direction. An upper portion of the variable resistance layer is disposed between lower portions of two neighboring second conductive layers including the second conductive layer.. ... Sk Hynix Inc

08/13/15 / #20150228890

Resistive memory device

A resistive memory device includes: a resistive layer which includes a first magnetic layer, a second magnetic layer, and a tunnel insulating layer interposed between the first magnetic layer and the second magnetic layer, and is switched between different resistance states; and a strained film formed over a sidewall of the resistive layer and applying a strain to the resistive layer, wherein the strained film includes a semiconductor material containing ions implanted therein. . ... Sk Hynix Inc

08/13/15 / #20150228767

Semiconductor memory device and method of manufacturing the same

A semiconductor memory device and a method of manufacturing the same are provided. The device includes a semiconductor substrate in which active regions and isolation regions are alternately defined, and a support region is defined in a direction crossing the active regions and the isolation regions, first trenches formed in the isolation regions, second trenches formed under the first trenches in the active regions and the isolation regions; and a support layer formed under the first trenches in the support region.. ... Sk Hynix Inc

08/13/15 / #20150228754

Semiconductor device with air gap and method for fabricating the same

A method for fabricating a semiconductor device includes forming a gate structure over a substrate, forming a multi-layer sidewall spacer including a first sacrificial spacer which covers sidewalls of the gate structure and a second sacrificial spacer which is disposed on a sidewall of the first sacrificial spacer and recessed lower than an upper surface of the gate structure, forming an air gap having a narrower width top portion than a middle and a bottom portions, by removing the first and second sacrificial spacers, and forming a capping layer which caps the top portion of the air gap.. . ... Sk Hynix Inc

08/13/15 / #20150228751

Semiconductor device and method for manufacturing the same

A semiconductor device forms a salicide layer to surround an upper surface and a circumference of a lateral surface of a pillar. A contact area between the pillar and a lower electrode may be increased to reduce a contact resistance.. ... Sk Hynix Inc

08/13/15 / #20150228750

Semiconductor device and method for manufacturing the same

A semiconductor device forms a salicide layer to surround an upper surface and a circumference of a lateral surface of a pillar. A contact area between the pillar and a lower electrode may be increased to reduce a contact resistance.. ... Sk Hynix Inc

08/13/15 / #20150228709

Semiconductor device and method of manufacturing the same

Disclosed is a semiconductor device having a substrate including first and second regions. First interlayer insulation layers and conductive patterns alternately are stacked on a first region of the substrate. ... Sk Hynix Inc

08/13/15 / #20150228657

Semiconductor device, module and system each including the same, and method for manufacturing the semiconductor device

A barrier for preventing a bridge between adjacent storage node contacts is formed below a bit line located between the bit line contacts, so that a contact region between each storage node contact and an active region is increased in size. The semiconductor device includes a device isolation film defining an active region, a bit line contact coupling the active region to a bit line, and a barrier formed below the bit line located between the bit line contacts.. ... Sk Hynix Inc

08/13/15 / #20150228643

Diode-connected bipolar junction transistors and electronic circuits including the same

A diode-connected bipolar junction transistor includes a common collector region of a first conductivity, a common base region of a second conductivity disposed over the common collector region, and a plurality of emitter regions of the first conductivity disposed over the common base region, arranged to be spaced apart from each other, and arranged to have island shapes.. . ... Sk Hynix Inc

08/13/15 / #20150228491

Transistor having tungsten-based buried gate structure, method for fabricating the same

A method for fabricating a transistor that includes forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a first fluorine-free tungsten layer as an interface stabilization layer over the gate dielectric layer, forming a second fluorine-free tungsten layer as a barrier layer over the first fluorine-free tungsten layer, forming a bulk tungsten layer as a gate electrode over the second tungsten layer to fill the trench, and selectively recessing the third tungsten layer, the second tungsten layer and the first tungsten layer to form a buried gate structure.. . ... Sk Hynix Inc

08/13/15 / #20150228475

Methods of fabricating a pattern using the block co-polymer materials

A method of fabricating a pattern comprising sequentially forming a pattern formation layer and a neutral layer on over a substrate having in a first regions and a second regions, forming guide patterns on first portions of over the neutral layer in the second regions, forming a first block copolymer layers on over second portions of the neutral layer in the first regions, phase-separating the tint block copolymer layers such that each of the first block copolymer layers includes to form first polymer blocks having a first phase and first polymer blocks having a second phase, removing the guide patterns to form openings that expose the first portions of the neutral layer in the second region, forming a second block copolymer layer on over the phase-separated first block copolymer layers and in the openings, phase-separating the second block copolymer layer into to form second polymer blocks having the first phase and second polymer blocks having the second phase removing the second polymer blocks having the second phase and the first polymer blocks having the second phase, and etching, the neutral layer and the pattern formation layer using the first polymer blocks having the first phase and the second polymer blocks having the first phase as an etch masks,. . ... Sk Hynix Inc

08/13/15 / #20150228356

Semiconductor integrated circuit device and multi chip package including the same

A semiconductor integrated circuit device includes a first circuit block configured to receive data from a plurality of data i/o (input/output) lines and output test data in a test mode, and a second circuit block configured to connect the plurality of data i/o lines and the first circuit block, output the data of the plurality of data i/o lines in a normal mode and output the test data provided from the first circuit block in the test mode.. . ... Sk Hynix Inc

08/13/15 / #20150228352

Semiconductor memory device and memory system including the same

The semiconductor memory device includes a memory cell array including a first plurality of normal memory cells and a second plurality of dummy memory cells in a stacked configuration over a substrate, a first plurality of normal word lines electrically coupled to the first plurality of normal memory cells, and a second plurality of dummy word lines electrically coupled to the second plurality of dummy memory cells, wherein the first plurality of normal memory cells includes at least one bad memory cell and each of the at least one bad memory cells are is replaced with a dummy memory cell from among the second plurality of dummy memory cells.. . ... Sk Hynix Inc

08/13/15 / #20150228349

Semiconductor device

A semiconductor device includes a memory block including memory cells for storing program data and one or more flag cells for storing erase state information, an operation circuit suitable for performing a program operation, an erase operation, and a read operation on the memory cells and the flag cell, and a data conversion circuit suitable for encoding read data read from the memory cells based on the erase state information.. . ... Sk Hynix Inc

08/13/15 / #20150228348

Semiconductor device and operating method thereof

An operating method of a semiconductor device includes repeating an erase loop operable to lower threshold voltages of memory cells in a selected memory block by applying an erase voltage to the selected memory block and performing an erase verification to determine whether the threshold voltages of the memory cells in the selected memory block are less than or equal to a target level, wherein an erase voltage is increased by a voltage difference wherein the voltage difference is increased between successive applications of two or more of the erase loops, and repeating a program loop including applying a program voltage to a selected word line to increase threshold voltages of memory cells electrically coupled to the selected word line and performing a program verification to determine whether the threshold voltages are greater than or equal to a target level, wherein a program voltage is increased by a voltage difference wherein the voltage difference is increased between successive applications of two or more program voltages.. . ... Sk Hynix Inc

08/13/15 / #20150228343

Non-volatile memory device

A non-volatile memory device includes: a floating gate having a plurality of fingers; a first coupling unit including an active control gate which overlaps with the floating gate in a vertical direction; a second coupling unit including a plurality of control plugs which overlap with the floating gate in a horizontal direction; and a control unit which electrically connects the active control gate to the control plugs and controls a bias to be applied to the active control gate.. . ... Sk Hynix Inc

08/13/15 / #20150228336

Resistive memory apparatus and operation method thereof

A resistive memory apparatus includes a memory region including a plurality of resistive memory cells, and a controller suitable for storing a threshold number of write operations according to a data storage material of the resistive memory cells, counting numbers of write operations for the respective resistive memory cells as a write operation is performed for the memory region, and performing interrupt control when a memory cell that reaches the threshold number of write operations is detected.. . ... Sk Hynix Inc

08/13/15 / #20150228329

Semiconductor devices and semiconductor systems including the same

The semiconductor device includes a mode signal generator and a refresh controller. The mode signal generator generates a mode signal. ... Sk Hynix Inc

08/13/15 / #20150228326

Internal voltage generation circuit, semiconductor memory device and semiconductor memory system

An internal voltage generation circuit includes a charging unit suitable for charging electrical charges for a time corresponding to a control signal; a charge control unit suitable for generating the control signal, which is activated for a time corresponding to temperature information, and controlling a charging operation of the charging unit; and an output unit suitable for generating an internal voltage based on charge amount by the charging operation.. . ... Sk Hynix Inc

08/13/15 / #20150228319

Internal address generation circuits

Internal address generation circuits are provided. The internal address generation circuit includes an aging detector and an address decoder. ... Sk Hynix Inc

08/13/15 / #20150228316

Driver and semiconductor memory device including the same

A driver includes a driving block suitable for driving a data transferred through a first signal line to a second signal line, a first precharge unit suitable for precharging the second signal line with a first driving power during a first precharge operation; and a second precharge unit suitable for precharging the second signal line with a second driving power which is different from the first driving power during a second precharge operation performed subsequent to the first precharge operation.. . ... Sk Hynix Inc

08/13/15 / #20150228313

Semiconductor memory device

A semiconductor memory device includes: a burst start signal generation unit configured to generate a first burst start signal by delaying a write pulse by a first period, generate a second burst start signal by delaying the write pulse by a second period, and selectively transmit the first or second burst start signal as a select burst start signal in response to a test signal; an input control signal generation unit configured to generate an input control signal in response to the first burst start signal; and a write command generation unit configured to generate a write driver enable signal in response to the select burst start signal.. . ... Sk Hynix Inc

08/13/15 / #20150228311

Semiconductor memory apparatus, and reference voltage control circuit and internal voltage generation circuit therefor

An internal voltage control circuit according to an embodiment may include a source power supply selection unit configured to receive a first internal power supply voltage and a second internal power supply voltage and selecting the first internal power supply voltage and the second internal power supply voltage as a source voltage in response to a test mode enable signal, a first reference voltage generation unit configured to receive the source voltage from the source power supply selection unit, and configured to generate a to first low reference voltage and a first high reference voltage. The reference voltage control circuit may also include a second reference voltage generation unit configured to receive the first internal power supply voltage and configured to generate a second low reference voltage and a second high reference voltage.. ... Sk Hynix Inc

08/13/15 / #20150227417

Semiconductor memory apparatus and operating method thereof

A semiconductor memory apparatus may include an error check and correction circuit block configured to receive a plurality of cell data, and output error-checked data and error data discrimination signals after receiving an error check enable signal; and a data bus inversion circuit block configured to receive the plurality of cell data, and output the plurality of cell data by inverting or non-inverting the cell data after receiving a read data bus inversion enable signal, the error check enable signal and the error data discrimination signals.. . ... Sk Hynix Inc

08/13/15 / #20150227040

Photomask blank and photomask for suppressing heat absorption

A photomask blank and/or photomask includes a light transmitting substrate, a highly reflective material layer disposed on the light transmitting substrate, and a transfer pattern layer disposed on the highly reflective material layer. The highly reflective material layer reflects light to be transmitted through the light transmitting substrate, with a predetermined reflectivity.. ... Sk Hynix Inc

08/13/15 / #20150226786

Semiconductor system and operating method thereof

A semiconductor system includes a semiconductor device suitable for generating measuring data, and a controller suitable for comparing the measuring data with a given expected value and controlling a voltage level, which is supplied to the semiconductor device, based on the comparison result.. . ... Sk Hynix Inc

08/06/15 / #20150222364

Semiconductor packages with optical transceivers

A semiconductor package includes a package substrate, a first semiconductor substrate and a second semiconductor substrate stacked on the package substrate, and an optical transceiver that generates and receives an optical signal travelling between the package substrate and the second semiconductor substrate using an infrared (ir) ray that passes through the first semiconductor substrate.. . ... Sk Hynix Inc

08/06/15 / #20150221738

Semiconductor device and method of operating the same

A semiconductor device including a channel layer, a gate insulating layer formed on a surface of the channel layer, a cell gate pattern formed along the gate insulating layer, and an electro migration (em) pattern formed in the cell gate pattern, and movable by an electric field formed between the cell gate pattern and the channel layer.. . ... Sk Hynix Inc

08/06/15 / #20150221700

Electronic device

An electronic device comprising a semiconductor memory unit that includes a first vertical electrode; a first variable resistance layer surrounding the first vertical electrode; a second vertical electrode surrounding the first variable resistance; a second variable resistance layer surrounding the second vertical electrode; and a plurality of horizontal electrodes contacted with an outer side of the second variable resistance layer, wherein the plurality of horizontal electrodes are spaced apart from each other in a vertical direction.. . ... Sk Hynix Inc

08/06/15 / #20150221559

Semiconductor device with transistor and method of fabricating the same

A method of fabricating a semiconductor device that includes forming a gate stack layer including a metal-containing layer on a semiconductor substrate having an nmos region and a pmos region, introducing arsenic to the gate stack layer in the nmos region, introducing aluminum to the gate stack layer in the pmos region, and etching the gate stack layers, where the arsenic and the aluminum are introduced, to form a first gate structure and a second gate structure in the nmos region and the pmos region, respectively.. . ... Sk Hynix Inc

08/06/15 / #20150221548

Semiconductor devices having bit line contact plugs and methods of manufacturing the same

A semiconductor device including active regions defined in a semiconductor substrate to be non-parallel with a first direction and a second direction which are perpendicular to each other, word lines intersecting active regions and extending in first directions to be spaced apart from each other in the second direction, bit lines crossing over word lines and extending in second directions to be spaced apart from each other in the first direction, first impurity regions disposed in respective ones of central portions of active regions to non-overlap with the word lines, second impurity regions disposed in both ends of each of the active regions to non-overlap with the word lines, and bit line contact plugs disposed between the first impurity regions and the bit lines. The bit line contact plugs having longish shapes including major axes substantially parallel with the second direction and minor axes substantially parallel with the first direction.. ... Sk Hynix Inc

08/06/15 / #20150221397

Semiconductor devices

A semiconductor device includes a normal test signal generator and a termination signal generator. The normal test signal generator is suitable for generating a first enablement signal and a first pulse signal in response to an external command signal when a first code signal and a second code signal have a predetermined logic combination. ... Sk Hynix Inc

08/06/15 / #20150221395

Semiconductor devices and semiconductor systems including the same

The semiconductor device includes a latch pulse generator and a data latch unit. The latch pulse generator generates a test section signal in response to a test pulse signal. ... Sk Hynix Inc

08/06/15 / #20150221394

Semiconductor devices and semiconductor systems including the same

A semiconductor device including a first latch unit suitable for storing a first address of a first memory cell tested in a first cell array block, a second latch unit suitable for storing a second address of a second memory cell tested in a second cell array block, a first selector suitable for receiving a first selection signal or a second selection signal to output any one of the first address and the second address as a selected address, and a program controller suitable for determining whether the selected address has to be stored in a fuse array and to control an operation for programming the fuse array.. . ... Sk Hynix Inc

08/06/15 / #20150221393

Semiconductor device including fuse array

The semiconductor device includes a control signal driver, a control signal latch unit, an internal driver and a buffer. The control signal driver drives a control signal in response to a fuse reset signal, a fuse set signal and a fuse data. ... Sk Hynix Inc

08/06/15 / #20150221392

Semiconductor devices including e-fuse arrays

Semiconductor systems are provided. The semiconductor system includes a boot-up operation circuit and a timing sensor. ... Sk Hynix Inc

08/06/15 / #20150221389

Semiconductor memory device and operating method thereof

Provided are a semiconductor memory device and an operating method thereof. The semiconductor memory device may include a memory cell array having a plurality of strings each including a drain select transistor, a plurality of drain side memory cells, a pipe transistor, a plurality of source side memory cells, and a source select transistor. ... Sk Hynix Inc

08/06/15 / #20150221385

Semiconductor memory device and system including the same

A semiconductor memory device includes a plurality of normal memory cells stacked over a substrate and coupled in series with each other, a plurality of selection transistors coupled in series, and one or more dummy memory cells coupled between the plurality of normal memory cells and the plurality of selection transistors, wherein the plurality of selection transistors includes first and second selection transistors, and the first selection transistor is adjacent to the dummy memory cells, and has a lower threshold voltage than the second selection transistor.. . ... Sk Hynix Inc

08/06/15 / #20150221380

Semiconductor device

A semiconductor device includes a memory block including memory cells coupled between bit lines and a common source line and operated by voltages applied to word lines, and an operation control block suitable for performing an erase operation and a pre-program operation on the memory block, wherein the operation control block performs an erase level control operation after the erase operation is completed so that threshold voltages of the memory cells relatively close to the bit lines and threshold voltages of the memory cells relatively close to the common source line are distributed at different erase levels.. . ... Sk Hynix Inc

08/06/15 / #20150221379

Semiconductor system and method of operating the same

A semiconductor system includes a data storage unit including memory blocks, a circuit group and a control circuit, wherein the memory blocks store data therein and are arranged in a longitudinal direction and a vertical direction. The circuit group is suitable for performing a program, read or erase operation on the memory blocks, and the control circuit controls the circuit group. ... Sk Hynix Inc

08/06/15 / #20150221374

Semiconductor device

A semiconductor device includes memory cells electrically coupled to word lines. In addition, the semiconductor device includes an operation circuit performing a program loop on memory cells electrically coupled to a selected word line. ... Sk Hynix Inc

08/06/15 / #20150221370

Memory system

The memory system includes at least one volatile memory configured to store data. The memory system also includes a non-volatile memory controller configured to provide a control signal to allow the data to be stored in a non-volatile memory during a power interruption mode. ... Sk Hynix Inc

08/06/15 / #20150221360

Semiconductor memory device

A semiconductor memory device includes a memory cell array configured to include a plurality of word lines, a dock enable buffer configured to receive a clock enable signal, a plurality of command buffers configured to receive a plurality of commands, a refresh control unit configured to sequentially activate the plurality of word lines in a self-refresh mode, a command decoder configured to decode the clock enable signal and the plurality of commands, and to allow the refresh control unit to enter the self-refresh mode or exit from the self-refresh mode, and a buffer control unit configured to disable the plurality of command buffers when the clock enable signal is deactivated, and to enable the plurality of command buffers when the refresh control unit exits from the self-refresh mode.. . ... Sk Hynix Inc

08/06/15 / #20150221359

Semiconductor devices

A semiconductor device includes a section signal generator and a decoder. The section signal generator generates a section signal by retarding a pre-section signal including a pulse created during a read operation or a write operation by a delay time that is set according to a level combination of first and second test mode signals. ... Sk Hynix Inc

08/06/15 / #20150221353

Data sensing circuit and semiconductor apparatus using the same

A data sensing circuit may include a pair of first signal lines, and a pair of second signal lines precharged with a first power supply voltage. The data sensing circuit may also include a line level control block configured for applying a second power supply voltage to any one signal line of the pair of second signal lines in response to a read command.. ... Sk Hynix Inc

08/06/15 / #20150221352

Semiconductor devices including e-fuse arrays

Semiconductor devices are provided. The semiconductor device includes a voltage generation control circuit, a read voltage generator, and a control data storage unit. ... Sk Hynix Inc

08/06/15 / #20150220102

Level detection circuits and semiconductor devices including the same

Level detection circuit includes a reference voltage generator, a level signal generator, and a comparator. The reference voltage generator includes a temperature dependent element and generates a reference voltage signal whose level varies according to a temperature characteristic of the temperature dependent element. ... Sk Hynix Inc

08/06/15 / #20150220092

Internal voltage generation circuits

Internal voltage generation circuits are provided. The internal voltage generation circuit includes a drive controller and an initialization unit. ... Sk Hynix Inc

07/30/15 / #20150214362

Dual work function buried gate type transistor and method for fabricating the same

A transistor may include a source region and a drain region separately formed in a substrate, a trench defined in the substrate between the source region and the drain region, and a buried gate electrode formed. The buried gate electrode includes a high work function liner layer having a bottom portion which is positioned over a bottom of the trench and sidewall portions which are positioned on lower sidewalls of the trench; a low work function liner layer positioned on upper sidewalls of the trench, and overlapping with the source region and the drain region; and a low resistance layer contacting the high work function liner layer and the low work function liner layer, and partially filling the trench.. ... Sk Hynix Inc

07/30/15 / #20150214360

Semiconductor device

The present invention provides a semiconductor device that ensures both the breakdown voltage characteristic and specific on-resistance characteristic required for a high-voltage semiconductor device and that includes a gate over a substrate, a source region formed at one side of the gate, a drain region formed at the other side of the gate, and a plurality of device isolation films formed between the source region and the drain region, below the gate.. . ... Sk Hynix Inc

07/30/15 / #20150214314

Dual work function buried gate type transistor and method for fabricating the same

A transistor includes a substrate having an active region defined by an isolation layer; a first trench defined in the active region and a second trench defined in the isolation layer; a fin region formed under the first trench; and a buried gate electrode covering sidewalls of the fin region and filling the first and second trenches. The buried gate electrode includes a first work function layer formed on the sidewalls of the fin region; a second work function layer formed on sidewalls of the first trench and the second trench; a third work function layer positioned over the fin region and contacting the second work function layer; and a low resistance layer contacting the third work function layer and partially filling the first and second trenches.. ... Sk Hynix Inc

07/30/15 / #20150214313

Transistor having dual work function buried gate electrode and method for fabricating the same

A transistor having a source region and a drain region which are separately formed in a substrate, a trench which is defined in the substrate between the source region and the drain region, and a gate electrode which is formed in the trench. The gate electrode includes a first electrode buried over a bottom of the trench; a second electrode formed over the first electrode; and a liner electrode having an interface part which is positioned between the first electrode and the second electrode and a side part, which is positioned on sidewalls of the second electrode and overlaps with the source region and the drain region.. ... Sk Hynix Inc

07/30/15 / #20150214310

Semiconductor device and method for forming the same

A semiconductor device in which a gettering layer is formed in a semiconductor substrate, and a method for forming the same are disclosed, resulting in increased reliability of the semiconductor substrate including the gettering layer. The semiconductor device includes a semiconductor substrate; a gettering layer formed of a first-type impurity and a second-type impurity in the semiconductor substrate so as to perform gettering of metal ion; and a deep-well region formed over the gettering layer in the semiconductor substrate.. ... Sk Hynix Inc

07/30/15 / #20150214268

Image sensor and method for fabricating the same

An image sensor includes a substrate including two or more photoelectric conversion regions corresponding to two or more pixels respectively, two or more color filters formed on the substrate corresponding to the photoelectric conversion regions, an interlayer insulation layer including an interconnection line and formed on the substrate, two or more condensing patterns each having a plurality of high refractive index regions and a plurality of low refractive index i regions, which are alternately disposed, wherein line widths of the high and low refractive index regions are different in the respective condensing patterns depending on the pixels.. . ... Sk Hynix Inc

07/30/15 / #20150214262

Image sensor and method for fabricating the same

An image sensor includes a substrate including a photoelectric conversion region, an interlayer insulation layer including an interconnection line and formed on the substrate, a condensing pattern having a first refractive index and including a first region upwardly protruding from the interlayer insulation layer and a second region buried in the interlayer insulation layer, and a color filter formed on the condensing pattern to bury the condensing pattern.. . ... Sk Hynix Inc

07/30/15 / #20150214240

Nonvolatile memory device and method for fabricating the same

A nonvolatile memory device includes: a channel layer protruding perpendicular to a surface of a substrate; a tunnel insulation layer formed on a surface of the channel layer; a stack structure, in which a plurality of floating gate electrodes and a plurality of control gate electrodes are alternately formed along the channel layer; and a charge blocking layer interposed between each floating gate electrode, of the plurality of floating gate electrodes, and each control gate electrode of the plurality of control gate electrodes, wherein the floating gate electrode includes a first floating gate electrode between two control gate electrodes and a second floating gate electrode positioned in the lowermost and uppermost parts of the stack structure and having a smaller width in a direction parallel to the substrate than the first floating gate electrode.. . ... Sk Hynix Inc

07/30/15 / #20150214234

Semiconductor device and method for fabricating the same

A semiconductor device is formed by depositing a nitride material having a lower etch rate than an oxide material over or between buried gates when forming a metal contact at an end portion of a cell region, to prevent a lower substrate from being etched during an etching process forming a metal contact hole. The semiconductor device includes at least one buried gate formed in a device isolation film of a semiconductor substrate, an etch stop film formed over and between the buried gates, and a metal contact formed perpendicular to the buried gate in the etch stop film.. ... Sk Hynix Inc

07/30/15 / #20150214153

Semiconductor apparatus

A semiconductor apparatus has one or more semiconductor chips. The semiconductor apparatus may include a power supply pad; power lines disposed on one side of the power supply pad, and including a first power line and a second power line; and connection lines connecting the power supply pad and the power lines. ... Sk Hynix Inc

07/30/15 / #20150214147

Semiconductor device and method for manufacturing the same

A semiconductor device and a method for manufacturing the same are disclosed. A semiconductor device includes a contact hole formed over a semiconductor substrate so as to open an active region, a contact plug coupled to the active region in the contact hole and having a height lower than that of the contact hole, and a bit line that is coupled to the contact plug and has the same width as the contact plug. ... Sk Hynix Inc

07/30/15 / #20150214108

Semiconductor device and method of fabricating the same

A semiconductor device having a dummy active region for metal ion gathering, which is capable of preventing device failure due to metal ion contamination, and a method of fabricating the same are provided. The semiconductor device includes active regions defined by an isolation layer in a semiconductor substrate and ion-implanted with an impurity, and a dummy active region ion-implanted with an impurity having a concentration higher than that of the impurity in the active region and configured to gather metal ions.. ... Sk Hynix Inc

07/30/15 / #20150213907

Semiconductor test device

A semiconductor test device performs a test using a high-speed internal clock. The semiconductor test device includes a clock generator suitable for generating an internal clock in response to a test mode signal during a test mode, a data generator suitable for generating internal data in response to the internal clock, and a data latch circuit suitable for latching the internal data in response to the internal clock, and outputting the latched data to an internal logic circuit.. ... Sk Hynix Inc

07/30/15 / #20150213906

Integrated circuit with programmable storage cell array and boot-up operation method thereof

An integrated circuit may include a first programmable storage cell group suitable for storing program validity information, second to n-th programmable storage cell groups suitable for storing a plurality of data, wherein n is an integer equal to or more than 3, and a validity determination unit suitable for determining whether the program validity information read from the first programmable storage cell group is valid or not so that read operations for the second to n-th programmable storage cell groups is performed or skipped based on the determined result.. . ... Sk Hynix Inc

07/30/15 / #20150213902

Semiconductor memory device and method of operating the same

A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array configured to include memory cells, a peripheral circuit configured to perform an erase operation and a soft program operation and a control circuit configured to control the peripheral circuit so that the memory cells are programmed though a hot carrier injection hci method when the soft program operation is performed.. ... Sk Hynix Inc

07/30/15 / #20150213861

Semiconductor devices

The semiconductor device includes a first data aligner, an input strobe signal generator and a second data aligner. The first data aligner aligns input data in synchronization with an internal strobe signal to generate alignment data. ... Sk Hynix Inc

07/30/15 / #20150213859

Burst length control circuit

A burst length control circuit includes a burst length input circuit that outputs a mode register burst length signal and a burst length on-the-fly signal, a burst length generator circuit that outputs a burst length signal, and a burst length adjuster that delays the burst length signal by a write latency time to produce a write burst length control signal. A selection circuit selects any one of the burst length signal and the write burst length control signal according to a write read command signal and an on-the-fly signal received from the burst length input circuit, and outputs a burst length control signal. ... Sk Hynix Inc

07/30/15 / #20150213856

Precharge circuit and semiconductor memory apparatus using the same

A precharge circuit may include a precharge control unit, a first precharge unit, and a second precharge unit. The precharge control unit may generate a read precharge signal and a write precharge signal in response to a read signal, a write signal, and a precharge signal. ... Sk Hynix Inc

07/30/15 / #20150213845

System using minimum operation power and power supply voltage setting method of memory device

A system includes a memory device, a controller, and a power supply. The controller stores a write data in the memory device, and generates a voltage control signal by comparing a read data outputted from the memory device with the write data. ... Sk Hynix Inc

07/30/15 / #20150212879

Semiconductor device performing error correction operation

A semiconductor device may include a memory core including a data cell region and a parity cell region, a parity calculation logic configured for generating a parity from data received by the parity calculation logic, and an error correcting logic configured for outputting error-corrected data by using data that is output from the data cell region and a parity that is output from the parity cell region.. . ... Sk Hynix Inc

07/30/15 / #20150211939

Temperature sensors

The temperature sensor includes a voltage generator and a temperature code generator. The voltage generator includes a first temperature element having a first resistance value and a second temperature element having a second resistance value and utilizes the first and second temperature elements to generate a temperature voltage signal having a voltage level that varies according to a variation in temperature. ... Sk Hynix Inc

07/23/15 / #20150207506

Level shifter and serializer having the same

A level shifter includes a level shifting unit suitable for changing a swing voltage level of an input signal from a first swing voltage level to a second swing voltage level based on a clock signal, a precharging unit suitable for precharging an output node of the level shifting unit based on the clock signal, and an output unit suitable for latching a signal of the output node having the second swing voltage level to output as an output signal.. . ... Sk Hynix Inc

07/23/15 / #20150207073

Semiconductor memory apparatus and fabrication method thereof

Semiconductor memory apparatus and a method of fabricating the same are provided. The semiconductor memory apparatus includes a semiconductor substrate in which a cell area and a peripheral area are defined, a plurality of pillars formed in the a cell area of the semiconductor substrate to a first depth, a stepped part formed in the peripheral area to a height corresponding to the first depth, a recessed part formed in the stepped part to a second depth, and a core switching device formed in the recessed part.. ... Sk Hynix Inc

07/23/15 / #20150207069

Nonvolatile memory devices

A nonvolatile memory device includes an inserted electrode line disposed between a first and a second electrode lines and extending in parallel with the second electrode line. The inserted electrode line is coupled to the second electrode line. ... Sk Hynix Inc

07/23/15 / #20150207068

Resistive memory device and fabrication method thereof

A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a bottom structure including a heating electrode, data storage materials, each of the data storage materials formed on the bottom structure in a confined structure perpendicular to the bottom structure, and having a lower diameter smaller than an upper diameter, an upper electrode formed on each of the data storage materials, and an insulation unit formed between adjacent data storage materials.. ... Sk Hynix Inc

07/23/15 / #20150206895

Semiconductor device and method of manufacturing the same

A semiconductor device may include interlayer insulating patterns and local word lines which are alternately stacked to form a stepped structure, and a first insulating layer formed on a surface of the stepped structure. The semiconductor device may also include a word line selection gate formed along a surface of the first insulating layer, and active patterns passing through the word line selection gate and the first insulating layer, and connected to the local word lines, respectively.. ... Sk Hynix Inc

07/23/15 / #20150206867

Semiconductor apparatus having pad and bump

A semiconductor apparatus may include a semiconductor chip, and the semiconductor chip may include a first pad, a second pad, and a bump. The first pad may be configured to receive a signal from an external device, and the second pad may include first and second metal layers electrically isolated from each other. ... Sk Hynix Inc

07/23/15 / #20150206825

Semiconductor device having through-silicon via

A semiconductor device includes a through electrode vertically passing through the semiconductor device; a metal pad electrically coupling the through electrode and an exterior; a data input block suitable for transferring a data signal to the metal pad in response to a write command; a through electrode storage block suitable for storing the data signal transferred through the metal pad; and a data output block suitable for outputting the data signal, which is stored in the through electrode storage block, to the exterior in response to a read command.. . ... Sk Hynix Inc

07/23/15 / #20150206805

Semiconductor device with metal gate and high-k materials and method for fabricating the same

A semiconductor device includes a substrate including first and second regions. A first gate stack structure containing a first effective work function adjust species is formed over the first region and a second gate stack structure containing a second effective work function adjust species is formed over the second region. ... Sk Hynix Inc

07/23/15 / #20150206800

Semiconductor device with air gap and method for fabricating the same

A semiconductor device includes a dielectric structure which has an opening exposing a surface of a substrate; and a conductive structure which is formed in the opening, wherein the conductive structure comprises: a first conductive pattern recessed in the opening; a second conductive pattern covering a top surface and sidewalls of the first conductive pattern; an air gap defined between sidewalls of the opening and the second conductive pattern; and a third conductive pattern capping the second conductive pattern and the air gap.. . ... Sk Hynix Inc

07/23/15 / #20150206601

Semiconductor memory device, test control system, and method of operating test control system

A semiconductor memory device includes a plurality of memory cells electrically coupled to a plurality of word lines and a word line failure detection unit suitable for supplying a test voltage to a test target word line selected from among the plurality of word lines, and for detecting the test voltage transferred from at least one of the plurality of word lines, wherein the at least one of the plurality of word lines does not include the test target word line.. . ... Sk Hynix Inc

07/23/15 / #20150206595

Antifuse array architecture

An anti-fuse including a program transistor which can be short-circuited depending on whether the program transistor is programmed, and also including a read transistor which is coupled with the program transistor and a bit line, and outputs information to the bit line based on whether the program transistor is short-circuited, comprising: an active region formed in a first direction in a semiconductor substrate; a bit line contact formed over the active region and coupled with the bit line; a program gate electrode the entire or part of which is buried in the active region over the program transistor; and a read gate electrode disposed over the read transistor and formed between the program gate electrode and the bit line contact.. . ... Sk Hynix Inc

07/23/15 / #20150206591

Nonvolatile memory device and operating method thereof

A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with p-type impurities.. . ... Sk Hynix Inc

07/23/15 / #20150206585

Electronic device and method for fabricating the same

An electronic device including a semiconductor memory is provided. The semiconductor memory includes a first electrode, a second electrode crossing the first electrode, and a variable resistance pattern positioned in an intersection region of the first electrode and the second electrode and buried in the first electrode.. ... Sk Hynix Inc

07/23/15 / #20150206572

Memory and memory system including the same

A memory includes a plurality of word lines, a measurement block suitable for measuring an active duration of an activated word line among the multiple word lines, and a refresh circuit suitable for controlling a refresh operation to refresh one or more of the multiple word lines adjacent to the activated word line when the active duration exceeds a predetermined threshold.. . ... Sk Hynix Inc

07/23/15 / #20150206571

Semiconductor device

A semiconductor device including an operation initiation block suitable for sequentially generating a plurality of operation initiation signals at a predetermined time interval in response to an operation initiation source signal, a clock-based signal generation block suitable for generating an operation termination source signal in response to one of the multiple operation initiation signals and a clock, an operation termination block suitable for sequentially generating a plurality of operation termination signals at the predetermined time interval in response to the operation termination source signal, and an operation control block suitable for sequentially generating a plurality of first operation control signals in response to the multiple operation initiation signals and the multiple operation termination signals.. . ... Sk Hynix Inc

07/23/15 / #20150206563

Semiconductor system

A semiconductor system includes a first clock channel and a second clock channel. The first clock channel transmits a first clock signal from a controller to a memory. ... Sk Hynix Inc

07/23/15 / #20150205312

Calibration circuit and semiconductor device including the same

A calibration circuit includes a pad suitable for receiving calibration data that toggles, a calibration reference voltage generation unit suitable for generating a calibration reference voltage from a median value of the calibration data, a comparison unit suitable for outputting a comparison signal by comparing the calibration reference voltage and a reference voltage with each other, and a reference voltage generation unit suitable for generating the reference voltage which is calibrated based on the comparison signal.. . ... Sk Hynix Inc

07/23/15 / #20150204938

Clock controller and semiconductor device including the same

A dock controller may include a dock period detector suitable for delaying a first dock signal through a plurality of unit delay circuits, and outputting a detection signal by detecting a period of the first dock signal as the number of unit delay circuits used for unit delay of the first clock signal among the unit delay circuits; and a clock generator suitable for generating a delay clock signal delayed by a half period of the first dock signal in response to the detection signal outputted from the clock period detector, and generating a second clock signal having a period corresponding to edges of the first clock signal and the delay clock signal.. . ... Sk Hynix Inc

07/16/15 / #20150200656

Duty cycle correction circuit and operation method thereof

A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.. . ... Sk Hynix Inc

07/16/15 / #20150200655

Duty cycle correction circuit and operation method thereof

A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.. . ... Sk Hynix Inc

07/16/15 / #20150200368

Semiconductor integrated circuit device having phase-change structure and method of manufacturing the same

A semiconductor integrated circuit device including a phase-change structure and a method of manufacturing the same are provided. The method includes providing a semiconductor substrate including a lower electrode, sequentially stacking a plurality of phase-change material layers on the semiconductor substrate, and patterning the stacked plurality of phase-change material layers in a stepwise manner to form a phase-change structure.. ... Sk Hynix Inc

07/16/15 / #20150200358

Semiconductor integrated circuit device having variable resistive layer and method of manufacturing the same

A semiconductor integrated circuit device includes a semiconductor substrate, a lower electrode disposed on the semiconductor substrate wherein an upper surface of the lower electrode has a recess, an interlayer insulating layer disposed on the semiconductor substrate and the lower electrode, the interlayer insulating layer including a variable resistive region exposing the upper surface of the lower electrode, and a variable resistive layer filled in the variable resistive region that contacts the recess of the lower electrode. The variable resistive layer is formed to have an increased width toward a top and a bottom thereof.. ... Sk Hynix Inc

07/16/15 / #20150200263

Semiconductor device and method for manufacturing the same

A semiconductor device and a method for manufacturing the same are disclosed, which can form a gate electrode material only in a recess of a buried gate cell structure, improve a gate induced drain leakage (gidl) of a gate electrode material and a junction (i.e., drain region), prevent the gate electrode material from overlapping with the junction (i.e., drain region), and adjust the depth of junction, thereby improving channel resistance. The method for manufacturing a semiconductor device includes forming a device isolation region defining an active region over a semiconductor substrate, burying a gate electrode material in the semiconductor substrate, forming a gate electrode pattern by etching the gate electrode material, wherein the gate electrode pattern is formed at sidewalls of the active region including a source region, and forming a capping layer in the exposed active region.. ... Sk Hynix Inc

07/16/15 / #20150200088

Access device, fabrication method thereof, and semiconductor memory device having the same

An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. ... Sk Hynix Inc

07/16/15 / #20150200015

Semiconductor memory device and method of operating the same

A semiconductor memory device includes a memory cell unit including a plurality of memory banks each including a pair of a first memory bank and a second memory bank, a sense amplifier group including a plurality of sense amplifier units each including a first sense amplifier and a second sense amplifier coupled to the first memory bank and the second memory bank, respectively, and a control logic block generating a first column selection signal to transfer data of the first memory bank to the first sense amplifier and a second column selection signal to transfer data of the second memory bank to the second sense amplifier, wherein an active section of the first column selection signal overlaps an active section of the second column selection signal.. . ... Sk Hynix Inc

07/16/15 / #20150199998

Semiconductor device

A semiconductor device includes a first set of stacked structures including alternately stacked insulating layers and conductive layers disposed on a substrate, and arranged in a generally parallel configuration with respect to each other, a second set of stacked structures including alternately stacked insulating layers and conductive layers disposed on the substrate between the first stacked structures, and arranged in a generally parallel configuration with respect to each other, a first wiring structure configured to electrically couple conductive layers located on the same layer in different stacked structures of the first set of stacked structures, a second wiring structure configured to electrically couple conductive layers located on the same layer in different stacked structures of the second set of stacked structures, and a third wiring structure configured to electrically couple the first wiring structure and the second wiring structure with an operation circuit.. . ... Sk Hynix Inc

07/16/15 / #20150198970

Apparatus and method for generating timing signals based on processor, and cmos image sensor using the same

A timing signal generation apparatus includes a timing signal generation module suitable for generating a timing signal based on a timing pattern, a timing pattern generation and control module suitable for generating the timing pattern and controlling the timing signal generation module, and an interface module suitable for signal interface with a neighboring device.. . ... Sk Hynix Inc

07/16/15 / #20150198968

Semiconductor devices and semiconductor systems including the same

The semiconductor device includes a command generator, an information signal storage unit, a termination signal generator and a code generator. The command generator generates a mode register write command signal, a start command signal and a termination command signal from external command signals. ... Sk Hynix Inc

07/16/15 / #20150198653

Semiconductor device and semiconductor system including the same

A semiconductor system includes a semiconductor chip; a penetrating electrode, which is formed to penetrate the semiconductor chip; two or more metals, which are formed in the upper portion of the penetrating electrode; a bump, which is formed to contact the upper portions of the metals and supplies a data signal inputted from outside to the metals; a detection block suitable for detecting whether or not the bump is coupled with the metals by comparing voltage levels of the metals with each other and generating a decision signal; and a signal output block suitable for outputting the decision signal externally.. . ... Sk Hynix Inc

07/09/15 / #20150194410

Chip stack packages, methods of fabricating the same, electronic systems including the same and memory cards including the same

A chip stack package includes a first chip disposed over a substrate, a second chip disposed over the first chip and having an overhang, and a first supporter attached to a bottom surface of the overhang of the second chip and a sidewall of the first chip. The overhang of the second chip protrudes from the sidewall of the first chip.. ... Sk Hynix Inc

07/09/15 / #20150194221

Semiconductor device having fuse array and method of operating the same

A semiconductor device that includes a fuse array including a plurality of fuses, and suitable for operating using a fuse operation voltage in a fuse operation period, a first voltage generation block suitable for generating an internal voltage based on a first target level, a second voltage generation block suitable for generating the fuse operation voltage based on a second target level in the fuse operation period, and generating the fuse operation voltage based on the first target level outside the fuse operation period, and a connection control block suitable for disconnecting a line of the internal voltage and a line of the fuse operation voltage in the fuse operation period, and connecting the line of the internal voltage and the line of the fuse operation voltage outside the fuse operation period.. . ... Sk Hynix Inc

07/09/15 / #20150194220

Semiconductor device and memory system including the same

A semiconductor device having a memory block which includes a plurality of pages and an operation circuit suitable for performing a program operation on memory cells included in an erase page when the erase page is detected among the plurality of pages through an erase page check operation, and performing an erase loop on the memory block after the program operation.. . ... Sk Hynix Inc

07/09/15 / #20150194199

Semiconductor devices and semiconductor systems including the same

The semiconductor device may include a first internal command generator suitable generating first internal command signals after decoding the external command signals in response to the external control signal, a column control signal generator suitable for generating a column control signal after decoding the external command signals in response to the external control signal, and a second internal command generator suitable for generating second internal command signals from the first internal command signals in response to the column control signal. Related systems are also provided.. ... Sk Hynix Inc

07/02/15 / #20150188566

Apparatus and method for processing data

A data processing device includes a compression circuit and a padding circuit. The compression circuit is configured to compare pairs of two contiguous bits within data composed of 2n bits (where n is a natural number), and compress the data based on a result of the comparison. ... Sk Hynix Inc

07/02/15 / #20150188544

Semiconductor apparatus cross-references to related application

A semiconductor apparatus including an inverter chain including a plurality of inverters, wherein the plurality of inverters are electrically coupled in series, and at least one of the plurality of inverters includes at least two output nodes.. . ... Sk Hynix Inc

07/02/15 / #20150188542

Data transmission circuit

A data transmission circuit may include a first driving block configured to drive an output terminal for a first time in response to a data driving signal and a level of the output terminal, and a second driving block configured to drive the output terminal for a second time after the first time, in response to the data driving signal.. . ... Sk Hynix Inc

07/02/15 / #20150188529

Semiconductor device

A semiconductor device including a common delay circuit configured to delay an input signal in response to a delay control code to output a first delayed input signal and a second delayed input signal; a first delay circuit configured to delay the first delayed input signal in response to the delay control code and to output a first output signal; and a second delay circuit configured to delay the second delayed input signal in response to the delay control code and to output a second output signal.. . ... Sk Hynix Inc

07/02/15 / #20150188526

Semiconductor apparatus

A delay circuit of a semiconductor apparatus includes a control signal generation block configured to output a control signal having an analog voltage level in response to an input signal, and an input/output block configured to delay the input signal by a delay amount based on the analog voltage level of the control signal, and output a resultant signal.. . ... Sk Hynix Inc

07/02/15 / #20150188518

Semicondutor apparatus for controlling back bias

A semiconductor apparatus includes a back bias control block, a first back bias switching block and second back bias switching block. The back bias control block is configured to generate a first p channel control signal and a second n channel control signal. ... Sk Hynix Inc

07/02/15 / #20150188418

Pumping circuit

A pumping circuit includes a cross-coupled charge pump circuit including first and second capacitors configured to pump an input voltage in response to a first clock signal and to an inverted first clock signal and a plurality of transistors configured to one of transfer the input voltage to the first and second capacitors and to transfer a pumping voltage to an output node, and a switching voltage supply circuit configured to supply switching voltages to gates of the plurality of transistors to enable the transfer of the input voltage and the pumping voltage.. . ... Sk Hynix Inc

07/02/15 / #20150187911

Semiconductor device and fabrication method thereof

A semiconductor device includes a gate electrode formed on a sidewall of a structure extending from a semiconductor substrate. A junction region is form in the structure to a first depth from a top of the structure and formed to overlap the gate electrode. ... Sk Hynix Inc

07/02/15 / #20150187899

Semiconductor device and method for forming the same

A semiconductor device includes a junction region on both sides of a trench in a semiconductor substrate, a first gate electrode with a first workfunction buried in the trench, and a second gate electrode formed of a polycide layer having a second workfunction overlapping with the junction region at an upper part of the first gate electrode.. . ... Sk Hynix Inc

07/02/15 / #20150187842

Nonvolatile memory devices

A nonvolatile memory device includes a plurality of first electrode lines including upper portions that have convex top surfaces. A plurality of second electrode lines are disposed over the plurality of first electrode lines to cross the plurality of first electrode lines, and a plurality of memory patterns are disposed between the plurality of first electrode lines and the plurality of second electrode lines.. ... Sk Hynix Inc

07/02/15 / #20150187835

Transistor, image sensor including the same and method for fabricating the same

A transistor includes a substrate and a gate insulation layer formed on the substrate having a negative charge storage layer with a fixed negative charge to induce a buried channel in the substrate. A gate electrode is formed on the gate insulation layer.. ... Sk Hynix Inc

07/02/15 / #20150187789

Semiconductor device and method for manufacturing the same

A semiconductor device that includes a plurality of first conductive patterns stacked over a substrate, dummy patterns formed in the first conductive patterns, respectively, first barrier patterns each surrounding the respective first conductive patterns and partially interposed between the respective first conductive patterns and the respective dummy patterns, second barrier patterns each surrounding the respective first barrier patterns and the respective dummy patterns, a second conductive pattern located over or under the first conductive patterns, and a third barrier pattern surrounding the second conductive pattern, wherein the second conductive pattern has a greater thickness than the first conductive patterns.. . ... Sk Hynix Inc

07/02/15 / #20150187744

3d semiconductor apparatus for initializing channels

A semiconductor apparatus includes a plurality of stack dies which are formed with a predetermined number of channels. The semiconductor apparatus also includes a base die configured to initialize a channel not electrically coupled with the stack dies.. ... Sk Hynix Inc

07/02/15 / #20150187705

Semiconductor package having emi shielding and method of fabricating the same

A semiconductor package includes a dielectric layer in which a chip is embedded, interconnection parts disposed on a first surface of the dielectric layer, through connectors each of which penetrates a portion of the dielectric layer over the chip to electrically couple the chip to a corresponding one of the interconnection parts, a shielding plate covering a second surface of the dielectric layer that is opposite to the first surface, and a shielding encapsulation part connected to one of the interconnection parts and covering sidewalls of the dielectric layer. The shielding encapsulation part includes a portion contacting the shielding plate.. ... Sk Hynix Inc

07/02/15 / #20150187698

Semiconductor apparatus and an improved structure for power lines

A semiconductor apparatus includes a first power supply pad configured to supply a first power; a second power supply pad configured to supply a second power; a first power line configured to be directly electrically coupled to the first power supply pad; and a second power line configured to be directly electrically coupled to the second power supply pad.. . ... Sk Hynix Inc

07/02/15 / #20150187680

Semiconductor apparatus, manufacturing method thereof and testing method thereof

A semiconductor apparatus includes one or more semiconductor chips. Each semiconductor chip includes a semiconductor substrate formed with a through-silicon via, and a bottom wiring layer with a first dielectric layer formed on a bottom of the semiconductor substrate. ... Sk Hynix Inc

07/02/15 / #20150187648

Semiconductor device and method for fabricating the same

A semiconductor device and a method for fabricating the same are disclosed, which can prevent migration of copper (cu) ion when forming a through silicon via (tsv). The semiconductor device includes a through silicon via (tsv) formed to pass through a semiconductor substrate; an oxide film located at a lower sidewall of the tsv; and a first prevention film formed to cover an upper portion of the tsv, an upper sidewall of the tsv, and an upper surface of the oxide film.. ... Sk Hynix Inc

07/02/15 / #20150187644

Semiconductor device with air gap and method of fabricating the same

A method of fabricating a semiconductor device and a semiconductor device formed by the method. The method includes form a stack conductive structure by stacking a first conductive pattern and an insulation pattern over a substrate; forming a sacrificial pattern over sidewalls of the stack conductive structure; forming a second conductive pattern having a recessed surface lower than a top surface of the stack conductive structure; forming a sacrificial spacer to expose sidewalls of the insulation pattern by removing an upper portion of the sacrificial pattern; reducing a width of the exposed portion of the insulation patters; forming a capping spacer to cap the sidewalls of the insulation pattern having the reduced width over the sacrificial spacer; and forming an air gap between the first conductive pattern and the second conductive pattern by converting the sacrificial spacer to volatile byproducts. ... Sk Hynix Inc

07/02/15 / #20150187438

Semiconductor memory apparatus and test method using the same

A semiconductor memory apparatus includes first data outputted from a first data storage region; second data outputted from a second data storage region; a data comparison block configured to perform a comparison to determine whether the first data and the second data are the same, and generate a comparison result signal; a timing control block configured to latch the comparison result signal in response to a clock and a latency signal, and output a comparison signal; and a data output block configured to receive a test signal and invert the first data in response to the comparison signal and output data.. . ... Sk Hynix Inc

07/02/15 / #20150187434

Test circuit of semiconductor apparatus

A test circuit of a semiconductor apparatus includes a plurality of memory blocks, and a comparison block configured to compare data of two memory blocks, wherein the two of the plurality of memory blocks do not share word lines.. . ... Sk Hynix Inc

07/02/15 / #20150187426

Memory system and method for operating the same

A memory system and a method for operating the same are provided. The memory system includes a semiconductor memory device suitable for performing an erase operation in response to a control signal, and if an erase command is input from a host, a controller suitable for temporarily storing erase block information according the erase command, and when a program command is input after the erase command is input, transmitting the control signal according to the erase command to the semiconductor memory device.. ... Sk Hynix Inc

07/02/15 / #20150187422

Semiconductor device

A semiconductor device includes first memory strings coupled between a first common source line formed on a substrate and bit lines formed over the first common source line, and second memory strings coupled between the bit lines and a second common source line formed over the bit lines, wherein each of the bit lines includes a stacked structure of a conductive layer and a silicon layer formed on the conductive layer.. . ... Sk Hynix Inc

07/02/15 / #20150187420

Semiconductor memory device, memory system including the same, and operating method thereof

The memory system includes a semiconductor memory device including a cam data block for storing cam data, and a controller configured to control an operation of the semiconductor memory device in response to a cam data program command received from a host, wherein the semiconductor memory device is configured to perform a pre-program operation and an erase operation of the cam data block prior to the performance of a cam data program operation associated with the cam data block.. . ... Sk Hynix Inc

07/02/15 / #20150187415

Electronic device and method for fabricating the same

An electronic device comprising a semiconductor memory unit that includes a cell structure having two memory cells, which share one selector, wherein the cell structure includes first electrodes, variable resistance patterns and second electrodes which are symmetrically disposed on both sides of the selector.. . ... Sk Hynix Inc

07/02/15 / #20150187408

Circuit for small swing data line and method of operating the same

A circuit includes a first buffer configured to provide data on a signal line. The first buffer may be powered by a first power supply voltage. ... Sk Hynix Inc

07/02/15 / #20150187407

Power supply scheme for small swing data line and method of operating the same

A circuit includes a plurality of buffers configured to provide data on a corresponding signal line. Each of the plurality of buffers may be coupled to a power supply voltage through a corresponding diode. ... Sk Hynix Inc

07/02/15 / #20150187406

Active control device, semiconductor device and system including the same

Disclosed herein are an active control device, a semiconductor device and system including the same. The active control device may include a refresh control unit configured for outputting a refresh signal by controlling a delay time for a refresh start time when a refresh operation is performed and a precharge signal generation unit configured for generating a bank precharge signal for precharging a bank in response to the refresh signal. ... Sk Hynix Inc

07/02/15 / #20150187405

Stacked semiconductor apparatus for generating refresh signal

A stacked semiconductor apparatus includes a plurality of chips which are stacked one upon the other. One chip of the plurality of chips may be configured to generate a plurality of refresh period signals for performing refresh operations within the plurality of chips, and may be configured to transmit the plurality of refresh period signals to the plurality of chips excluding the one chip. ... Sk Hynix Inc

07/02/15 / #20150187403

Memory device and memory system including the same

A memory device may include a plurality of memory banks, a row control signal input unit suitable for receiving a plurality of row control signals, a column control signal input unit suitable for receiving a plurality of column control signals, a row control unit suitable for selecting a memory bank and a row in response to the row control signals, and controlling a row operation for the selected row, and a column control unit suitable for selecting a memory bank and column in response to the column control signals, and controlling a column operation for the selected column.. . ... Sk Hynix Inc

07/02/15 / #20150187401

Semiconductor memory apparatus

A semiconductor memory apparatus may include a clock buffer configured to receive an external clock signal, buffer the external clock signal in response to an activation control signal, and the clock buffer configured to output an internal clock signal in response to an activation control signal. The semiconductor memory apparatus may also include a delay-locked loop block configured to receive the internal clock signal outputted from the clock buffer and compare phases of the internal clock signal and a feedback clock signal, and responsively generate a delay-locked clock signal. ... Sk Hynix Inc

07/02/15 / #20150187400

Data sensing circuit of semiconductor apparatus

A data sensing circuit of a semiconductor apparatus includes a sensing unit configured to drive a pair of output lines based on a voltage level difference between a pair of input/output lines in response to a pair of enable signals, a timing control unit configured to perform an equalizing operation between the pair of output lines while the pair of enable signals are in a deactivated state in response to a control signal, and to interrupt the equalizing operation between the pair of output lines when a predetermined period of time has passed following the activation of the pair of enable signals, and a control signal generation unit configured to generate the control signal in response to the enable signal.. . ... Sk Hynix Inc

07/02/15 / #20150187396

Buffer control circuit of semiconductor memory apparatus

A buffer control circuit of a semiconductor memory apparatus includes a delay unit configured to determine delay amounts for a command in response to a plurality of command latency signals, delay the command according to a clock, and generate a plurality of delayed signals; and a buffer control signal generation unit configured to receive the plurality of command latency signals and the plurality of delayed signals, and generate a buffer control signal.. . ... Sk Hynix Inc

07/02/15 / #20150186309

Apparatus and method for processing data

A data processing device includes a controller. The controller includes a compression circuit configured to compare a plurality of data groups, each of which has a first burst length and is transmitted in units of an input/output width, with a predetermined pattern, and perform data compression on the data groups based on a result of comparison. ... Sk Hynix Inc

07/02/15 / #20150185796

Semiconductor apparatus

A power-up circuit of a semiconductor apparatus includes a detection block configured to detect a first target level of an external voltage and activate a power-up signal; and a bias block configured to divide the external voltage according to a division ratio that is variable in response to the power-up signal, and output a bias voltage.. . ... Sk Hynix Inc

07/02/15 / #20150185758

Receiver circuit for correcting skew, semiconductor apparatus and system including the same

A receiver circuit includes a deserialization unit, a sampling clock control unit and a sampling clock generation unit. The deserialization unit is configured to receive sampling clock signals, sample a plurality of input data signals, and generate a plurality of internal data signals. ... Sk Hynix Inc

07/02/15 / #20150185745

Semiconductor apparatus

A voltage generation circuit of a semiconductor apparatus includes a first detection block configured to detect an output voltage and output a first detection signal; a second detection block configured to detect the output voltage and output a second detection signal; a signal generation block configured to generate a control signal in response to the first detection signal and the second detection signal; and a voltage generation block configured to generate the output voltage in response to the control signal, wherein responding speeds of the first detection block and the second detection block with respect to a variation in the output voltage are different.. . ... Sk Hynix Inc

06/25/15 / #20150181143

Image sensing device

An image sensing device includes a first read unit suitable for generating a first read signal by reading a first pixel signal, a first input line suitable for transmitting the first pixel signal, a first feedback line suitable for feeding back the first read signal, a second read unit disposed adjacent to the first read unit in a same row and suitable for generating a second read signal by reading a second pixel signal, a second input line suitable for transmitting the second pixel signal, and a second feedback line suitable for feeding back the second read signal wherein the first input line and the first feedback line are disposed symmetrically to the second input line and the second feedback line.. . ... Sk Hynix Inc

06/25/15 / #20150180704

Semiconductor chip and transmission/reception system including the same

A transmission/reception system includes first to nth channels, where n is an integer equal to or greater than 3; a transmission chip suitable for transmitting first to (n−1)th signals through the first to (n−1)th channels and transmitting a correction signal generated by using the first to (n−1)th signals to the nth channel; and a reception chip suitable for receiving signals of the first to nth channels and generating restored signals of the first to nth channels by using the first to nth channels.. . ... Sk Hynix Inc

06/25/15 / #20150179929

Phase-change memory device and fabrication method thereof

A phase-change memory device and a method of fabricating the same are provided. The phase-change memory device includes a semiconductor substrate in which a word line is arranged, a diode line disposed over the word line and extending parallel to the word line, a phase-change line pattern disposed over the diode line, and a projection disposed between the diode line and the phase-change line pattern and protruding from the diode line. ... Sk Hynix Inc

06/25/15 / #20150179618

Package-on-package modules, electronic systems including the same, and memory cards including the same

Package-on-package (pop) modules are provided. The pop module includes a lower package and an upper package disposed over the lower package. ... Sk Hynix Inc

06/25/15 / #20150179608

Embedded packages having a connection joint group

An embedded package includes a first semiconductor chip embedded in a package substrate, a second semiconductor chip disposed over a first surface of the package substrate, and a group of external connection joints disposed on the first surface of the package substrate and between a sidewall of the second semiconductor chip and an edge of the embedded package. Related memory cards and related electronic systems are also provided.. ... Sk Hynix Inc

06/25/15 / #20150179588

Semiconductor packages having emi shielding layers, methods of fabricating the same, electronic systems including the same, and memory cards including the same

Semiconductor packages are provided. In some embodiments, the semiconductor package includes a substrate, a first ground line including a first internal ground line disposed along edges of the substrate and a plurality of first extended ground lines between the first internal ground line and sidewalls of the substrate, a chip on the substrate, a molding member disposed on the substrate to cover the chip, and an electromagnetic interference (emi) shielding layer covering the molding member, the emi shielding layer extending along the sidewalls of the substrate and contacting the end portions of the plurality of first extended ground lines. ... Sk Hynix Inc

06/25/15 / #20150179564

Semiconductor device and method of manufacturing the same

A semiconductor device includes a stacked structure having first conductive layers stacked stepwise and first insulating layers interposed between the first conductive layers, wherein undercuts are formed under the first conductive layers and each of the first conductive layers includes a first region covered by the first conductive layer and a second region extending from the first region, contact pads coupled to the second regions of the respective first conductive layers, and a liner layer formed on the contact pads and filling the undercuts.. . ... Sk Hynix Inc

06/25/15 / #20150179545

Semiconductor devices and methods of manufacturing the same

A semiconductor device includes a through electrode penetrating a substrate such that a first end portion of the through electrode protrudes from a first surface of the substrate, a passivation layer covering the first surface of the substrate and a sidewall of the first end portion of the through electrode, a bump having a lower portion penetrating the passivation layer and coupled to the first end portion of the through electrode, and a lower metal layer disposed between the bump and the first end portion of the through electrode. The lower metal layer extends onto a sidewall of the bump and has a concave shape.. ... Sk Hynix Inc

06/25/15 / #20150179526

Anti-fuse array of semiconductor device and method for forming the same

An anti-fuse array of a semiconductor device and a method for forming the same are disclosed. The anti-fuse array for a semiconductor device includes a first-type semiconductor substrate formed to define an active region by a device isolation region, a second-type impurity implantation region formed in the active region, a first-type channel region isolated from the semiconductor substrate by the second-type impurity implantation region, a gate electrode formed over the channel region, and a first metal contact formed over the second-type impurity implantation region.. ... Sk Hynix Inc

06/25/15 / #20150179519

Interconnection structures in a semiconductor device and methods of manufacturing the same

Methods of fabricating interconnection structures of a semiconductor device are provided. The method includes, inter alia: forming a first insulation layer on a semiconductor substrate, forming a mold layer having trenches on the first insulation layer, forming a sidewall protection layer including a first metal silicide layer on sidewalls of the trenches, forming second metal lines that fill the trenches, forming upper protection layers on the second metal lines, removing the mold layer after formation of the upper protection layers to provide gaps between second metal lines, and forming a second insulation layer in the gaps and on the upper protection layers. ... Sk Hynix Inc

06/25/15 / #20150179498

Nonvolatile memory device and method for fabricating the same

A nonvolatile memory device includes gate structures formed over a substrate, each gate structure including a tunnel insulating layer, a floating gate, an inter-gate dielectric layer, and a control gate that are sequentially stacked, a protective layer formed on sidewalls of the floating gate, and a second insulating layer covering the gate structures and having an air gap formed between the gate structures, wherein an adhesive strength between the second insulating layer and the protective layer is smaller than an adhesive strength between the second insulating layer and the gate structure.. . ... Sk Hynix Inc

06/25/15 / #20150179434

Nano-scale structures

A nanoscale structure includes an array of pillars over an underlying layer, a separation wall layer including first separation walls formed over sidewalls of the pillars, and a block co-polymer (bcp) layer formed over the separation wall layer and filling gaps between the pillars. The bcp layer is phase-separated to include first domains that provide second separation walls formed over the first separation walls and second domains that are separated from each other by the first domains.. ... Sk Hynix Inc

06/25/15 / #20150179283

Semiconductor devices and semiconductor systems including the same

Semiconductor device includes a first data input/output (i/o) portion suitable for storing data inputted thereto through a first pad in a first cell block in synchronization with a test data strobe signal or a first data strobe signal and suitable for outputting the data stored in the first cell block to the first pad, a second data i/o portion suitable for storing data inputted thereto through a second pad in a second cell block in synchronization with the test data strobe signal or a second data strobe signal and suitable for outputting the data stored in the second cell block to the second pad, and a connection portion suitable for electrically connecting the first and second pads to each other in a test mode. Related semiconductor systems are also provided.. ... Sk Hynix Inc

06/25/15 / #20150179266

Semiconductor memory device and operating method thereof

A semiconductor memory device and an operating method thereof are set forth. The semiconductor memory device includes a memory cell array with a string. ... Sk Hynix Inc

06/25/15 / #20150179259

Electronic device and method for fabricating the same

An electronic device including a semiconductor memory is provided, wherein the semiconductor memory comprises: a substrate in which first to third regions are provided; first to third trenches formed in the first to third regions, respectively, and having a different line width from each other; and first to third device isolation layers formed in the first to third trenches, respectively, wherein the first device isolation layer includes a stack structure of a first insulation layer and a second insulation layer, the second device isolation layer includes the first insulation layer formed over a part of a bottom and one sidewall of the second trench, the second insulation layer having a stepped type and a third insulation layer which is formed over the second insulation layer, and the third device isolation layer includes a stack structure of the first to third insulation layers.. . ... Sk Hynix Inc

06/25/15 / #20150179249

Semiconductor devices and integrated circuits including the same

A first semiconductor device equalizes levels of a bit line and a complementary bit line of a high-order bit line pair in a first memory block using a first drive voltage signal whose level is controlled when a power-down mode or a self-refresh mode is activated according to a level combination of high-order command/address signals. A second semiconductor device equalizes levels of a bit line and a complementary bit line of a low-order bit line pair in a second memory block using a second drive voltage signal whose level is controlled when the power-down mode or the self-refresh mode is activated according to a level combination of low-order command/address signals.. ... Sk Hynix Inc

06/25/15 / #20150179243

Word line driving circuit

The word line driving circuit includes a plurality of first pull-down transistors connected in series and suitable for pull-down driving a control node in response to a plurality of address information signals, a driving signal output unit suitable for activating a word line driving signal when the control node is activated and deactivating the word line driving signal when a word line off signal is activated, a first pull-up transistor suitable for pull-up driving the control node when the word line driving signal is deactivated, and a clamping unit suitable for limiting the amount of current flowing to the first pull-up transistor.. . ... Sk Hynix Inc

06/25/15 / #20150179242

Address detection circuit and memory device including the same

An address detection circuit may include one or more address storage units, an initialization unit suitable for deleting an address stored in an address storage unit having a value greater than n, wherein the value is obtained by dividing a respective total input number that addresses have been inputted after the corresponding address is stored by a respective input number corresponding to the stored address, a detection unit suitable for detecting an address having an input number that is a reference number or more from the addresses stored in the one or more address storage units, and a selection unit suitable for selecting an address storage unit in which an address is not stored and storing an input address in the selected address storage unit.. . ... Sk Hynix Inc

06/25/15 / #20150179241

Semiconductor device

A semiconductor device may include a nonvolatile storage unit, a select signal generation unit suitable for generating a plurality of select signals using a clock, a plurality of storage units suitable for storing data transmitted from the nonvolatile storage unit in response to the plurality of select signals, respectively, and a clock blocking unit suitable for blocking the clock inputted to the select signal generation unit when the data transmitted from the nonvolatile storage unit is the same as the data stored in the plurality of storage units.. . ... Sk Hynix Inc

06/25/15 / #20150179239

Semiconductor device

A semiconductor device includes a plurality of memory cell region regions with each memory cell region region having a plurality of normal memory cell regions, a dummy memory cell region disposed at one side of the plurality of normal memory cell regions, and another dummy memory cell region disposed at another side of the plurality of normal memory cell regions. The semiconductor device further includes a plurality of circuit regions, each including a control circuit to control a portion of the plurality of normal memory cell regions, the dummy memory cell region, and the other dummy memory cell region. ... Sk Hynix Inc

06/25/15 / #20150179237

Integrated circuit and memory device

An integrated circuit may include a nonvolatile memory circuit, a data bus suitable for transferring data outputted from the nonvolatile memory circuit, a shift register suitable for sequentially activating first to nth selection signals whenever a clock is activated, and first to nth latch circuits corresponding to the first to nth selection signals, respectively, and suitable for storing data of the data bus in response to activation of one or more of the first to nth selection signals.. . ... Sk Hynix Inc

06/25/15 / #20150179231

Semiconductor memory apparatus

A semiconductor memory apparatus may include a program voltage generation block configured to generate a program voltage in response to program codes; a precharge voltage generation block configured to generate a precharge voltage in response to the program codes and addresses; and a main bit line configured to be applied with the program voltage and the precharge voltage.. . ... Sk Hynix Inc

06/25/15 / #20150178192

Nonvolatile memory device and data storage device including the same

A data storage device including a first nonvolatile memory device having a first state information transmission block, a second nonvolatile memory device having a second state information transmission block, which shares a state information line with the first state information transmission block, and a controller having a state information reception block which is suitable for transmitting a control signal for controlling the first state information transmission block and the second state information transmission block to transmit a state information frame, and sequentially receiving a first state information frame transmitted from the first state information transmission block and a second state information frame transmitted from the second state information transmission block, through the state information line.. . ... Sk Hynix Inc

06/25/15 / #20150178156

Memory system

A memory system is provided. The memory system includes a memory device suitable for reading out data from memory cells by a plurality of read voltages having various levels, and a controller suitable for updating probabilistic information based on the read out data when the read out data is input to the controller, and performing an error correction operation by the updated probabilistic information, wherein the controller updates the probabilistic information a predetermined number of times that the memory device reads out the data.. ... Sk Hynix Inc

06/25/15 / #20150178153

Memory system

Provided is a memory system having a memory device. The memory system includes a memory device suitable for performing an even read operation of even memory cells connected to a word line and an odd read operation of odd memory cells connected to the word line, and a controller suitable for performing an error correction operation on even data read out from the even memory cells according to even probability information and odd data read out from the odd memory cells according to odd probability information, and the controller is configured to correct the even probability information or the odd probability information according to characteristics of the even memory cells and the odd memory cells.. ... Sk Hynix Inc

06/25/15 / #20150178009

Data storage device and data processing system including the same

A data processing system includes a host device including a first volatile memory device, and a data storage device including a second volatile memory device and a nonvolatile memory device, and suitable for storing data to be accessed by the host device. The data storage device uploads data stored in the second volatile memory device to the first volatile memory device before the data storage device in a normal mode enters a power-save mode.. ... Sk Hynix Inc

06/25/15 / #20150177777

Pulse generation circuit, burst order control circuit, and data output circuit

A pulse generation circuit includes a control unit configured to activate one or more of control clocks among a plurality of control clocks, and to activate one or more of select signals among a plurality of select signals, in response to one or more of sequence signals; a plurality of shifting units each configured to generate one or more of output signals, and to sequentially activate the one or more of output signal's by shifting an input pulse when a corresponding control clock among the plurality of control clocks is activated; and a signal transfer unit configured to transfer one or more of output signals of a shifting unit corresponding to an activated select signal among the plurality of shifting units, as one or more of pulses.. . ... Sk Hynix Inc

06/25/15 / #20150177769

Voltage generation circuits and semiconductor devices including the same

Voltage generation circuits are provided. The voltage generation circuit includes a reference voltage generator suitable for generating a reference voltage signal having a constant level without a correspondence to a temperature variation. ... Sk Hynix Inc

06/25/15 / #20150177763

Initialization signal generation circuits and semiconductor devices including the same

The initialization signal generation circuit includes a first driver and a second driver. The first driver includes at least one passive element and drives an initialization signal while a level of an external voltage signal reaches an initial level. ... Sk Hynix Inc

06/25/15 / #20150177320

Semiconductor chip, stack chip including the same, and testing method thereof

A semiconductor chip includes an input pad and an output pad formed on the semiconductor chip; at least one bump formed on the semiconductor chip; and a test scan chain configured to output data applied from the input pad, to a node which is electrically coupled with the bump, store data corresponding to capacitance of the node by floating the node for a predetermined time, and output data corresponding to the stored capacitance, to the output pad.. . ... Sk Hynix Inc

06/18/15 / #20150171996

Transmitter/receiver for supporting differential signaling and semiconductor transmitter/receiver system including the same

A transmitter includes first to third power supply terminals, a first buffer that is electrically coupled between the first power supply terminal and the second power supply terminal and buffers and outputs a first input signal, and a second buffer that is electrically coupled between the second power supply terminal and the third power supply terminal and buffers and outputs a second input signal that is in a differential relation to the first input signal.. . ... Sk Hynix Inc

06/18/15 / #20150171875

Clock generation circuit

A clock generation circuit includes a counting unit configured to generate a counting code during a preset time section of an input clock; a control code generation unit configured to generate a decoding code by varying the counting code; and a variable period oscillation unit configured to generate an output clock having a frequency corresponding to the decoding code.. . ... Sk Hynix Inc

06/18/15 / #20150171871

Double data rate counter, and analog-to-digital converter and cmos sensor including the same

A double data rate (ddr) counter includes a first control block suitable for toggling a counter clock according to a count mode signal and a previous state value of a sampling block; a second control block suitable for determining whether to toggle a clock signal inputted to a counting block corresponding to an (lsb+1) bit or higher; a third control block suitable for determining an enable period of the counting block; the sampling block suitable for sampling a state of the clock signal and outputting an lsb value, when an input signal transits; and the counting block suitable for performing counting according to output signals of the second and third control blocks and outputting a counter output signal having the (lsb+1) bit or higher.. . ... Sk Hynix Inc

06/18/15 / #20150171867

Semiconductor device

A semiconductor device includes: a first level shifter suitable for shifting a level of a region identification signal identifying first and second regions to a preset voltage; a plurality of second level shifters suitable for shifting levels of a plurality of internal control signals to the preset voltage; and a plurality of logic operators suitable for generating a plurality of first internal assignment signals assigned to the first region and a plurality of second internal assignment signals assigned to the second region in response to a common shifting signal output from the first level shifter and a plurality of individual shifting signals output from the plurality of second level shifters.. . ... Sk Hynix Inc

06/18/15 / #20150171836

Duty cycle correction circuit

A duty cycle correction circuit may include an error booster suitable for amplifying an input clock duty error, a driver suitable for driving an output clock based on the input clock, and a duty corrector suitable for correcting the output clock duty based on the duty error amplified by the error booster.. . ... Sk Hynix Inc

06/18/15 / #20150171831

Period signal generation circuits

A period signal generation circuit including a control voltage generator and a period controller. The control voltage generator selecting one of temperature-dependent voltages to output the selected temperature-dependent voltage as a control voltage. ... Sk Hynix Inc

06/18/15 / #20150171809

Mos transistors having low offset values, electronic devices including the same, and methods of fabricating the same

A mos transistor includes a gate electrode disposed over an active region without overlapping with an isolation region, the active region including a channel region, the isolation region defining the active region, a source region and a drain region disposed in first and second portions of the active region, respectively, the first and second portions being disposed at first and second sides of the gate electrode, respectively, the first side opposing the second side, a first blocking region disposed in a third portion of the active region between a third side of the gate electrode and the isolation region and between the source and the drain region, and a second blocking region disposed in a fourth portion of the active region between a fourth side of the gate electrode and the isolation region and between the source and the drain region, the fourth side opposing the third side.. . ... Sk Hynix Inc

06/18/15 / #20150171143

Transistor, resistance variable memory device including the same, and manufacturing method thereof

A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (ldd) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the ldd region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first work function.. . ... Sk Hynix Inc

06/18/15 / #20150171133

Image sensor and method for fabricating the same

An age sensor including a transfer gate formed on a substrate, a photoelectric conversion region formed on a side of the transfer gate, a floating diffusion region with a trench formed on another side of the transfer gate, a barrier layer which covers a bottom of the trench and a conducting layer, which is gap-filled in the trench.. . ... Sk Hynix Inc

06/18/15 / #20150171106

Semiconductor memory device and method of manufacturing the same

Provided are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device may include insulating patterns and conductive patterns, which are alternately stacked, a channel layer configured to pass through the insulating patterns and the conductive patterns, and a tunnel insulating layer configured to cover sidewalls of the channel layer, and the channel layer is formed of a sige layer in which a ge concentration of a portion in contact with the tunnel insulating layer is greater than that of a center portion.. ... Sk Hynix Inc

06/18/15 / #20150171014

Semiconductor device with air gap

A method of fabricating a semiconductor device may include forming isolation structures that include openings, over a substrate; forming sacrificial spacers on sidewalls of the openings; forming, on the sacrificial spacers, first conductive patterns that are recessed in the openings; removing the sacrificial spacers, and defining air gaps; forming a liner layer that caps the first conductive patterns and the air gaps; forming second conductive patterns through silicidation of the liner layer; and forming third conductive patterns over the second conductive patterns.. . ... Sk Hynix Inc

06/18/15 / #20150170919

Semiconductor device and fabrication method

A semiconductor device using a small-sized metal contact as a program gate of an antifuse, and a method of fabricating the same are described. The semiconductor device includes a metal contact structure formed on a semiconductor substrate of a peripheral circuit area, and includes a first gate insulating layer to be ruptured. ... Sk Hynix Inc

06/18/15 / #20150170765

Apparatus and method for decoding data

A data decoding apparatus includes a first decision unit suitable for determining whether or not an error is present in a read data based on a first decoding method and identifying an error occurrence position, wherein the read data is read by a first read voltage, a second decision unit suitable for determining a low reliability position that belongs to the error occurrence position by checking reliability of the error occurrence position based on a second read voltage changed from the first read voltage within a set range, and an error correction unit suitable for generating an error correction data by correcting an error of the low reliability position.. . ... Sk Hynix Inc

06/18/15 / #20150170761

Semiconductor memory device and method for operating the same

A semiconductor memory device includes an operation control block suitable for controlling an entrance/escape to/from a test public mode and a test application mode in response to a first preset command and an address signal that is inputted through an address pad, a test normal input block suitable for receiving the address signal as a test operation signal in response to the first preset command in the test application mode, a test public input block suitable for receiving a data signal, which is inputted through a data pad as the test operation signal in response to a second preset command in the test public mode, and an internal circuit suitable for performing a preset test operation in response to the test operation signal in the test application mode.. . ... Sk Hynix Inc

06/18/15 / #20150170733

Memory and memory system including the same

A memory may include a plurality of word lines, a target address generation unit suitable for generating one or more target addresses by using a stored address, a refresh control section suitable for activating a refresh signal in response to a refresh command that is periodically inputted and periodically activating the refresh signal in a self-refresh mode, a target refresh control section suitable for activating a target refresh signal when the refresh signal is activated m times, wherein the m is a natural number, and deactivating the target refresh signal in the self-refresh mode and a row control section suitable for sequentially refreshing the plurality of word lines in response to the refresh signal and refreshing a word line corresponding to the target address in response to the refresh signal when the target refresh signal is activated.. . ... Sk Hynix Inc

06/18/15 / #20150170728

Memory and memory system including the same

A memory may include a plurality of word lines, one or more redundancy word lines for replacing one or more word lines among the plurality of word lines, a target address generation unit suitable for generating one or more target addresses using a stored address, and a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command which is periodically inputted, refreshing a word line selected based on the target address when the refresh command is inputted m times, and refreshing the one or more redundancy word lines whenever the refresh command is inputted n times, wherein the m and n are natural numbers.. . ... Sk Hynix Inc

06/18/15 / #20150170723

Semiconductor devices and reduction of operation times

The semiconductor device includes a command decoder and a voltage generation circuit. The command decoder may be suitable for decoding external command signals to generate a preparation signal and a voltage control signal. ... Sk Hynix Inc

06/18/15 / #20150170722

Semiconductor memory device and method for operating the same

A semiconductor memory device includes a first pre-charge control block suitable for generating a first control signal by counting a number of toggles of an operation clock in response to a first active pulse in a self-refresh operation exit mode, a second pre-charge control block suitable for generating a second control signal in response to an active command for an active operation in a self-refresh operation mode, and an operation control block suitable for disabling the first pre-charge control block in the self-refresh operation mode, and disabling the second pre-charge control block in a self-refresh operation exit mode, wherein a pre-charge operation starts in response to the first and second control signals after the active operation. The semiconductor memory device may then be secured in a minimal time for stably performing an active operation during a self-refresh operation.. ... Sk Hynix Inc

06/18/15 / #20150170715

Semiconductor device with power distribution network

A semiconductor device that includes first to fourth banks spaced apart from each other in first and second directions, column control regions extending in the second direction between the first bank and the second bank and between the third bank and the fourth bank, and suitable for controlling column operations of the first to fourth banks, at least one power supply/ground voltage line extending in the second direction at one side edge of the first to fourth banks adjacent to the column control regions, and at least one power supply/ground voltage pad adjacent to and coupled with the at least one power supply/ground voltage line between the first bank and the third bank and between the second bank and the fourth bank, and suitable for receiving an external power supply voltage and a ground voltage.. . ... Sk Hynix Inc

06/18/15 / #20150169235

Data storage device and operating method thereof

A data storage device includes a memory device and a controller suitable for controlling an operation of the memory device according to a memory interface mode between the memory device and the controller. The controller performs a memory interface matching operation when there is a mismatch between the memory interface modes of the memory device and the controller.. ... Sk Hynix Inc

06/18/15 / #20150168966

Semiconductor apparatus and retaining voltage levels

A semiconductor apparatus includes a reference voltage generation unit configured to generate a reference voltage. The semiconductor apparatus also includes an internal voltage generation unit configured to generate an internal voltage which corresponds to a voltage level of the reference voltage. ... Sk Hynix Inc

06/11/15 / #20150162911

Operation mode setting circuit of semiconductor apparatus and data processing system using the same

An operation mode setting circuit of a semiconductor apparatus includes a mode register set configured to update an operation mode information generated internally at the semiconductor apparatus based on preliminary information data in response to a preliminary information setting signal and a preliminary information providing block configured to provide the preliminary information data selected from a plurality of pre-stored preliminary information data to the mode register setting response to the preliminary information setting signal, the selected preliminary information data corresponding to a detected operation parameter detected in response to the preliminary information setting signal.. . ... Sk Hynix Inc

06/11/15 / #20150162529

Electronic device and method for fabricating the same

An electronic device includes a switch element. The switch element includes a first electrode including a first metal nitride which is conductive, a second electrode, a switching layer interposed between the first electrode and the second electrode, and a first barrier layer which is interposed between the first electrode and the switching layer and includes a second metal nitride which is insulative, wherein a metal in the first metal nitride is the same as a metal in the second metal nitride, and a metal-to-nitrogen bonding ratio of the first metal nitride is different from a metal-to-nitrogen bonding ratio of the second metal nitride.. ... Sk Hynix Inc

06/11/15 / #20150162526

Electronic device and method for fabricating the same

An electronic device including a semiconductor memory is provided. The semiconductor memory includes an interlayer dielectric layer disposed over a substrate, and having a recess which exposes a portion of the substrate; a bottom contact partially filling the recess; and a resistance variable element including a bottom layer which fills at least a remaining space of the recess over the bottom contact, and a remaining layer which is disposed over the bottom layer and protrudes out of the interlayer dielectric layer.. ... Sk Hynix Inc

06/11/15 / #20150162345

Semiconductor memory device including a slit

A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block.. . ... Sk Hynix Inc

06/11/15 / #20150162342

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first semiconductor patterns passing through the first stacked structure, a coupling pattern coupled to the first semiconductor patterns, and a slit passing through the first stacked structure and the coupling pattern.. . ... Sk Hynix Inc

06/11/15 / #20150162341

Non-volatile memory device having increased memory capacity

A non-volatile memory device according to an embodiment of the present invention includes a first memory layer including a plurality of memory cells stacked between a first conductive line and a second conductive line over a semiconductor substrate. In addition, a second memory layer including the plurality of memory cells stacked between the second conductive line and a third conductive line. ... Sk Hynix Inc

06/11/15 / #20150162268

Electronic device and method for fabricating the same

An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes a plurality of conductive pillars stretching in a direction perpendicular to a substrate, the plurality of conductive pillars arranged in a first direction and a second direction intersecting the first direction, conductive patterns disposed between the conductive pillars, variable resistance layers each of which is disposed between a corresponding one of the conductive pillars and a corresponding one of the conductive patterns, said each of the variable resistance layers contacting the corresponding conductive pattern and the corresponding conductive pillar, first lines disposed between the conductive pillars in the second direction and stretch in the first direction, the first lines contacting the conductive patterns under the conductive patterns, and second lines disposed between the conductive pillars in the first direction and stretch in the second direction, the second lines contacting the conductive patterns over the conductive patterns.. ... Sk Hynix Inc

06/11/15 / #20150162263

Semiconductor device and method of manufacturing the same

The semiconductor device includes first interlayer insulating layers and first conductive patterns which are alternately stacked; a second interlayer insulating layer formed on the first interlayer insulating layers and the first conductive patterns; and a slit passing through the second interlayer insulating layer, the first interlayer insulating layers and the first conductive patterns to divide the first interlayer insulating layers and the first conductive patterns into stack structures.. . ... Sk Hynix Inc

06/11/15 / #20150162237

Semiconductor device and method for fabricating the same

A semiconductor device includes a first isolation layer formed in a trench in a substrate. The isolation layer includes a first oxide layer formed in the trench and a second oxide layer formed over the first oxide layer, wherein the first oxide layer and the second oxide layer have a same composition.. ... Sk Hynix Inc

06/11/15 / #20150162094

Semiconductor device and method for driving the same

A semiconductor device includes at least one first row selection line, at least one column selection line that intersects with the first row selection line, and a first fuse circuit including a first fuse array, and suitable for outputting a first fuse signal programmed in the first fuse array by using an external voltage as a source voltage in a power-up mode, wherein the first fuse array includes at least one first fuse cell coupled with the first row selection line and the column selection line.. . ... Sk Hynix Inc

06/11/15 / #20150162073

Semiconductor devices

The semiconductor device includes a pre-internal refresh signal generator and an internal refresh signal generator. The pre-internal refresh signal generator receives a first periodic signal during a refresh operation to generate a pre-internal refresh signal including pulses which are periodically created. ... Sk Hynix Inc

06/11/15 / #20150162071

Address storage circuit and memory and memory system including the same

A memory including a plurality of word lines to which one or more memory cells are coupled, an address storage unit suitable for storing an input address corresponding to a first external signal that is inputted at a random time, and a control unit suitable for activating a word line corresponding to the input address of the plurality of word lines in response to an active command and refreshing one or more target word lines selected using an address stored in the address storage unit when performing a refresh operation.. . ... Sk Hynix Inc

06/11/15 / #20150162067

Memory and memory system including the same

A memory may include a plurality of word lines coupled to one or more memory cells; a target address generation unit suitable for generating one or more target addresses using a stored address; and a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command which is periodically inputted, and refreshing a word line corresponding to the target address in response to the refresh command at a random time.. . ... Sk Hynix Inc

06/11/15 / #20150162066

Address storage circuit and memory and memory system including the same

A memory including a plurality of word lines to which one or more memory cells are coupled, an address storage unit suitable for storing an input address corresponding to a first external signal that is inputted at a random time, and a control unit suitable for activating a word line corresponding to the input address of the plurality of word lines in response to an active command and refreshing one or more target word lines selected using an address stored in the address storage unit when performing a refresh operation.. . ... Sk Hynix Inc

06/11/15 / #20150162064

Refresh control circuit of semiconductor apparatus and refresh method using the same

A refresh control circuit of a semiconductor apparatus includes a repair address processing unit configured to compare refresh addresses and repair information, activate a redundant enable signal, and convert the semiconductor apparatus into the same operation state as an initialization state of the repair information in response to activation of a repair initialization signal; a refresh counter configured to count the refresh addresses extended to a signal bit in response to activation of a redundant count enable signal; and a refresh control unit configured to activate the repair initialization signal and the redundant count enable signal when an additional refresh mode is set in response to a refresh command.. . ... Sk Hynix Inc

06/11/15 / #20150160665

Period signal generation circuits

A period signal generation circuit including a control voltage generator and a period controller. The control voltage generator selecting one of temperature-dependent voltages to output the selected temperature-dependent voltage as a control voltage. ... Sk Hynix Inc

06/04/15 / #20150155869

Semiconductor apparatus and reduced current and power consumption

A semiconductor apparatus may include a mode control circuit configured to output differential output signals which swing in a current mode logic (cml) area and a first control signal, in response to a power-down mode signal; a first circuit unit configured to be provided with the differential output signals, and operate in a power-down mode; and a second circuit unit configured to be provided with the differential output signals, and be interrupted in its operation in the power-down mode.. . ... Sk Hynix Inc

06/04/15 / #20150155861

Semiconductor device and semiconductor system including the same

A semiconductor device includes a first pad suitable for receiving a first clock that is inputted from an exterior, a second pad suitable for receiving a second clock that is inputted from the exterior, a differential clock recognition unit suitable for recognizing between the first clock and the second clock as a positive clock of differential clocks and recognizing the other as a negative clock of the differential clocks in response to a mirror function signal which represents whether a mirror function is enabled or not, an output unit suitable for outputting an internal signal as an output signal in response to the differential clocks and controlling an output moment of the output signal in response to the mirror function signal and an output moment control signal, and a third pad suitable for supplying the output signal to the exterior.. . ... Sk Hynix Inc

06/04/15 / #20150155857

Flip-flop circuit and semiconductor apparatus using the same

A flip-flop circuit may include: a latch unit configured to latch an input signal in response to a clock signal; and a timing control unit configured to delay a signal provided from the latch unit by a predetermined time regardless of the clock signal.. . ... Sk Hynix Inc

06/04/15 / #20150155482

Electronic device and method for fabricating the same

An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of first planes and a plurality of second planes which are disposed over a substrate and alternately stacked in a vertical direction over the substrate, where each of the first planes includes a plurality of first lines which extends in a first direction parallel to the substrate and each of the second planes includes a plurality of second lines which extends in a second direction parallel to the substrate and intersecting with the first direction, a plurality of variable resistance patterns which is interposed between each of the first planes and each of the second planes, each of the variable resistance patterns being disposed at a cross point between a first line and a corresponding second lines, and an air-gap which is disposed between neighboring variable resistance patterns.. ... Sk Hynix Inc

06/04/15 / #20150155371

3-dimensional non-volatile memory device and method of manufacturing the same

A non-volatile memory device comprising a plurality of strings each including a drain select transistor, drain-side memory cells, a pipe transistor, source-side memory cells, and a source select transistor coupled in series, wherein the plurality of strings are arranged in a first direction and a second direction, and the strings arranged in the second direction form each of string columns; a plurality of bit lines extended in the second direction and coupled to the drain select transistors of the strings included in each string column; and a plurality of source lines extended in the first direction and in common coupled to the source select transistors of strings adjacent to each other in the second direction, wherein strings included in one of the string columns are staggered in the first direction and each of the string columns are coupled to at least two of the bit lines.. . ... Sk Hynix Inc

06/04/15 / #20150155360

Non-volatile memory device and method for fabricating the same

A non-volatile memory device may include a first well of a first conductive type formed over a substrate, a second well of a second conductive type formed over the substrate to contact the first well, a trench formed over the substrate on a border formed by the contact of the first well and the second well, and a memory gate having a memory layer formed over a surface of the trench, and a gate electrode formed to fill the trench over the memory layer.. . ... Sk Hynix Inc

06/04/15 / #20150155335

Variable resistance memory device and method of manufacturing the same

A variable resistance memory device includes a semiconductor substrate having a vertical transistor with a shunt gate that increases an area of a gate of the vertical transistor.. . ... Sk Hynix Inc

06/04/15 / #20150155296

Semiconductor device and method of manufacturing the same

Provided is a semiconductor device including a first stacked structure in which first conductive patterns and first interlayer insulating layers are alternately stacked, a second stacked structure formed on the first stacked structure and including second conductive patterns and second interlayer insulating layers, which are alternately stacked, an interfacial pattern formed between the first stacked structure and the second stacked structure, first through-areas passing through the first stacked structure and the interfacial pattern, and including first protrusions protruding toward a sidewall of the interfacial pattern, second through-areas passing through the second stacked structure and connected to the first through-areas, and through-structures formed along sidewalls of the first through-areas and the second through-areas.. . ... Sk Hynix Inc

06/04/15 / #20150155295

Semiconductor device and method of manufacturing the same

A semiconductor device includes first semiconductor patterns with protrusions formed on the sidewalls thereof, and second semiconductor patterns respectively coupled to the first semiconductor patterns and increasing in width away from joining surfaces where the first semiconductor patterns and the second semiconductor patterns are coupled.. . ... Sk Hynix Inc

06/04/15 / #20150155278

Semiconductor apparatus

A semiconductor apparatus includes a reservoir capacitor, and the reservoir capacitor includes a plurality of mos capacitors serially coupled to one another. The plurality of mos capacitors are arranged in one well.. ... Sk Hynix Inc

06/04/15 / #20150155274

Semiconductor apparatus including dummy patterns

A semiconductor apparatus and system including a semiconductor apparatus may include: a main pattern block having a plurality of main patterns formed to be coupled to a power source and one or more dummy pattern blocks formed around the main pattern block. Any one of the one or more dummy pattern blocks may include a protection part formed to protect the main pattern block.. ... Sk Hynix Inc

06/04/15 / #20150155262

Semiconductor packages including a multi-layered dielectric layer and methods of manufacturing the same

The embedded package includes a semiconductor chip having contact portions disposed on a top surface thereof, a first dielectric layer substantially surrounding sidewalls of the semiconductor chip and including first fillers dispersed therein, a second dielectric layer substantially covering the top surface of the semiconductor chip and including second fillers dispersed therein, and first external interconnection portions disposed on the second dielectric layer and electrically connected to the contact portions, wherein an average size of the first fillers is different from that of the second fillers.. . ... Sk Hynix Inc

06/04/15 / #20150155235

Anti-fuse of semiconductor device, semiconductor module and system each including the semiconductor device, and method for forming the anti-fuse

An anti-fuse based on a field nitride trap (fnt) is disclosed. The anti-fuse includes a first active pillar including a first junction, a second active pillar including a second junction, a selection line buried between the first active pillar and the second active pillar, and a trap layer for electrically coupling the first junction to the second junction by trapping minority carriers according to individual voltages applied to the first junction, the second junction and the selection line. ... Sk Hynix Inc

06/04/15 / #20150155207

Cmos circuit and method for fabricating the same

A semiconductor device includes a semiconductor substrate and a gate insulation layer formed over the semiconductor substrate. A gate electrode is formed over the gate insulation layer. ... Sk Hynix Inc

06/04/15 / #20150155180

Fine pattern structures having block co-polymer materials

Various embodiments are directed to fine pattern structures, such as fine pattern structures having block co-polymer materials, methods of forming fine pattern structures with block co-polymer materials, and methods of fabricating semiconductor devices including fine pattern structures with block co-polymer materials. According to some embodiments, a method of fabricating a fine pattern structure includes providing a layer of alternating protrusion portions and recess portions, forming polymer patterns in recess regions formed in the recess portions, forming brush patterns on top surfaces of the protrusion portions, forming first polymer block patterns on the brush patterns and second polymer block patterns on the polymer patterns, and removing the second polymer block patterns and the polymer patterns.. ... Sk Hynix Inc

06/04/15 / #20150155057

Error detection circuit and semiconductor integrated circuit using the same

The technology may include: a first error detection operation unit configured to perform a serial error detection operation on a data signal which is inputted in sequence through each of multiple input/output pads, and to generate multiple pieces of preliminary information; and a second error detection operation unit configured to perform a parallel error detection operation on the multiple pieces of preliminary information, and to generate an error detection code.. . ... Sk Hynix Inc

06/04/15 / #20150155054

Semiconductor memory device and method of wafer burn-in test for the same

A semiconductor memory device comprising a memory cell array with a plurality of word lines, first and second dummy word lines, and a dummy word line driver suitable for separately driving the first and second dummy word lines for a wafer burn-in test where the word lines are driven by group.. . ... Sk Hynix Inc

06/04/15 / #20150155051

Semiconductor device having fuse circuit

A semiconductor device includes a fuse array with a plurality of fuses, a common signal generation unit suitable for receiving a power-up signal and generating an inverted power-up signal and a reset signal, a plurality of fuse registers suitable for latching a plurality of fuse data for the plurality of fuses and commonly receiving the inverted power-up signal and the reset signal from the common signal generation unit by grouped fuse registers, and an output selection unit suitable for outputting the plurality of fuse data stored on the plurality of fuse registers according to a predetermined sequence.. . ... Sk Hynix Inc

06/04/15 / #20150155047

Semiconductor memory device and erasing method thereof

Provided is a semiconductor memory device and a method of erasing the same. The semiconductor memory device includes a memory cell array including a plurality of memory cells; and a peripheral circuit unit configured to apply a pre-erase voltage, an erase voltage, and an erase operation voltage to the memory cell array so as to erase data stored in the plurality of memory cells when an erase operation is performed. ... Sk Hynix Inc

06/04/15 / #20150155041

Semiconductor memory device, memory system including the same and operating method thereof

A semiconductor memory device, a memory system including the same and an operating method thereof are set forth. The semiconductor memory device includes a memory cell array having a plurality of memory cells, peripheral circuits configured to perform a program operation using an incremental step pulse programming (ispp) method on selected memory cells from among the plurality of memory cells. ... Sk Hynix Inc

06/04/15 / #20150155040

Semiconductor memory device and operating method thereof

Provided are a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell array including a plurality of strings, wherein each of the plurality of strings includes a first memory cell group, and a second memory cell group and peripheral circuits configured to generate a first precharge voltage applied to the first memory cell group and a second precharge voltage applied to the second memory cell group when a channel precharge operation is performed during a program operation, and generate a program voltage to apply the program voltage to the memory cell array when a program voltage application is performed.. ... Sk Hynix Inc

06/04/15 / #20150155030

Semiconductor memory device

A semiconductor memory device includes a first bank, a second bank disposed separately from the first bank along a first direction, a third bank disposed separately from the first bank along a second direction substantially perpendicular to the first direction, a fourth bank disposed separately from the second bank along the second direction and from the third bank along the first direction, a first row control region, which is disposed between the first bank and the second bank, suitable for controlling a row decoding operation of the first bank and the second bank, a second row control region, which is disposed between the third bank and the fourth bank, suitable for controlling a row decoding operation of the third bank and the fourth bank, and a refresh control unit suitable for controlling a refresh operation of the first to fourth banks.. . ... Sk Hynix Inc

06/04/15 / #20150155028

Memory, memory system including the memory and method for operating the memory system

A memory system includes a memory controller suitable for applying a refresh command and a refresh operation times information that represents the number of times that refresh operations are to be performed to a memory device, and the memory device suitable for performing a refresh operation as many times as the refresh operation times information represents in response to the refresh command.. . ... Sk Hynix Inc

06/04/15 / #20150155026

Semiconductor device and method for driving the same

A semiconductor device includes a voltage supply unit suitable for providing a first voltage as a source voltage during a standby mode, and a second voltage as the source voltage during an active mode, and a precharge unit suitable for precharging a pair of input/output lines with the source voltage during the standby mode and the active mode.. . ... Sk Hynix Inc

06/04/15 / #20150155025

Semiconductor memory device, refresh control system, and refresh control method

A semiconductor memory device includes a normal command generation unit suitable for generating a normal refresh command in response to a refresh command; a smart command generation unit suitable for performing a counting operation on the refresh command to generate a plurality of smart refresh commands which are activated at a predetermined period; and a refresh operation unit suitable for performing a refresh operation in response to the normal refresh command and the plurality of smart refresh commands, wherein the smart command generation unit resets the counting operation when entering into the refresh operation.. . ... Sk Hynix Inc

06/04/15 / #20150155023

Semiconductor memory device

A semiconductor memory device includes a clock signal generation unit suitable for dividing an external clock signal to generate a first internal clock signal corresponding to odd number periods of the external clock signal and a second internal clock corresponding to even number periods, a first input unit suitable for receiving an external command signal and an external address signal in response to the first internal clock signal, a second input unit suitable for receiving the external command signal and the external address signal in response to the second internal clock signal, and an operation control unit suitable for enabling one of the first input unit and the second input unit and disabling the other of the first input unit and the second input unit, during a gear-down mode.. . ... Sk Hynix Inc

06/04/15 / #20150155022

Data processing apparatus and method

A data processing apparatus includes a controller configured to provide, using a unified connector, group data processing information for a processing operation of a data group processed based on the same data processing information. The data group comprises a plurality data transmitted or received through a plurality of connectors. ... Sk Hynix Inc

06/04/15 / #20150155020

Semiconductor apparatus

A semiconductor apparatus includes a logic memory chip including a transmission block which outputs input signals and a strobe signal; and a plurality of memory chips stacked with the logic memory chip. At least one of the plurality of memory chips includes a plurality of reception blocks. ... Sk Hynix Inc

06/04/15 / #20150155019

Semiconductor integrated circuit

A semiconductor integrated circuit includes a data latch unit configured to latch arranged data according to a domain crossing control signal, and to output the arranged data as write data; and a domain crossing controller configured to generate the domain crossing control signal with respect to the timing of a data strobe signal.. . ... Sk Hynix Inc

06/04/15 / #20150155018

Control circuit for bit-line sense amplifier and semiconductor memory apparatus having the same, and operating method thereof

A control circuit for a bit-line sense amplifier may include: a bank active signal generator configured to generate an internal active signal and a bank active signal; and a sense amplifier enable signal generator configured to determine a skew in response to the internal active signal, and set an output time of a sense amplifier enable signal by delaying the bank active signal according to the determined skew.. . ... Sk Hynix Inc

06/04/15 / #20150155016

Semiconductor memory device and semiconductor memory system

A semiconductor memory device includes a unit memory bank having a plurality of memory cell mats, which shares a local data line, and divided by a row address; and at least one dummy cell mat disposed between the plurality of memory cell mat.. . ... Sk Hynix Inc

06/04/15 / #20150155013

Semiconductor memory apparatus

A semiconductor memory apparatus includes a latch section including a plurality of latches configured to store test data, a control signal generation part configured to generate a mode selection signal in response to a latch address signal and a first mode signal, and an output circuit configured to operate in accordance with a training enable signal, and generate at least a subset of test data output by each of the plurality of latches in response to a latch selection signal, the mode selection signal, and a second mode signal.. . ... Sk Hynix Inc

06/04/15 / #20150155012

Buffer circuit of semiconductor apparatus

A buffer circuit of a semiconductor apparatus includes a sensing circuit configured to sense input signals according to a data strobe signal, generate latch control signals, provide the latch control signals at nodes, and remove parasitic components of the nodes in response to a clock signal; and a latch circuit configured to generate and latch output data in response to the latch control signals.. . ... Sk Hynix Inc

06/04/15 / #20150154135

Semiconductor memory device and i/o control circuit therefor

An i/o control circuit, includes a mode setting unit configured to generate a first mode signal, a second mode signal, a third mode signal, and a fourth mode signal in accordance with one of a plurality of i/o option modes, a first control signal generation unit configured to generate a first mode determination signal and a first control signal enable signal in response to the first i/o option signal and the first mode signal, and a second control signal generation unit configured to generate a second control signal enable signal, a third control signal enable signal, and a fourth control signal enable signal in response to a second i/o option signal, the first mode determination signal, the second mode signal, the third mode signal, and the fourth mode signal.. . ... Sk Hynix Inc

06/04/15 / #20150154095

Built-in self-test circuit and semiconductor device including the same

A built-in self-test circuit includes a command storage unit that stores commands inputted from an external device, an input/output control unit that controls the command storage unit to sequentially store the commands and sequentially output stored commands as internal commands in a test operation, and a command decoder unit that decodes the internal commands outputted from the command storage unit and outputs a test command.. . ... Sk Hynix Inc

06/04/15 / #20150154089

Error recovery for flash memory

An indication of a page type which failed error correction decoding is received. A threshold to adjust is selected from a plurality of thresholds based at least in part on the page type. ... Sk Hynix Inc

06/04/15 / #20150154067

Memory system including randomizer and derandomizer

Provided is a memory system including a semiconductor memory device including a buffer memory block suitable for storing page data, and including a main memory block, and a controller suitable for generating a combination seed by performing a logical operation on a randomizing seed, a derandomizing seed, and error information, and for providing the generated combination seed to the semiconductor memory device.. . ... Sk Hynix Inc

06/04/15 / #20150153794

System including memory controller for managing power of memory

A system includes a power supply, a memory controller and a memory device. The memory controller is configured to receive power from the power supply, generate a memory power supply voltage for use by the memory device based on the power received from the power supply and provide the memory power supply voltage to the memory device.. ... Sk Hynix Inc

06/04/15 / #20150153750

Semiconductor system for tuning skew of semiconductor chip

A semiconductor system includes a master chip and a plurality of slave chips. The master chip controls internal voltage levels of the respective slave chips based on signals outputted from the plurality of slave chips such that, by referring to any one slave chip of the plurality of slave chips, internal voltage levels of remaining slave chips are controlled.. ... Sk Hynix Inc

06/04/15 / #20150153649

Fine pattern structures having block co-polymer materials and methods of fabricating the same

A method for fine pattern structures includes forming a pattern formation layer over a first region and a second region of a substrate, forming a first block co-polymer layer in the first region, forming a second block co-polymer layer in the second region, etching the first and second block co-polymer layers, and forming the fine pattern structure in the pattern formation layer in the first region without forming a pattern in the pattern formation layer in the second region.. . ... Sk Hynix Inc

05/28/15 / #20150149820

Memory and memory module including the same

A memory unit including a first data transferring/receiving unit suitable for transferring/receiving data through a first data bus for communication with a host, a second data transferring/receiving unit suitable for transferring/receiving data through a second data bus for a data backup, and a control unit suitable for controlling the first data transferring/receiving unit and the second data transferring/receiving unit to be activated or inactivated according to whether a power failure occurs in the host.. . ... Sk Hynix Inc

05/28/15 / #20150149740

Data storage device and data processing system including the same

A data processing system includes a data storage device including memory cells, which are erased to an erasure state and programmed to program states to store data, and a host device suitable for accessing the data, wherein the data storage device programs a first memory cell to a first state other than the erasure state to delete data of the first memory cell in response to a request of the host device.. . ... Sk Hynix Inc

05/28/15 / #20150149728

Semiconductor device and operating method thereof

A semiconductor device may include a first address cache configured to store a physical address of a semiconductor memory device and a write count associated with the physical address, an address monitor configured to update the physical address and the write count in the first address cache based on a received write request, and an arbiter configured to store a write address and write data associated with the write request in a write cache in response to a command from the address monitor, wherein the command generated by the address monitor is based on whether an update is made to the physical address and the write count in first address cache.. . ... Sk Hynix Inc

05/28/15 / #20150149674

Embedded storage device

An embedded storage device for use with a computer device is provided. The embedded storage device includes a microprocessor, a master storage unit, a slave storage unit, and a relay bus. ... Sk Hynix Inc

05/28/15 / #20150147878

Semiconductor device and method for manufacturing the same

A semiconductor device includes a semiconductor substrate having two surfaces. First side faces second side and includes recesses, and a plurality of through silicon vias (tsv), which penetrate through the semiconductor substrate, are exposed by the recesses. ... Sk Hynix Inc

05/28/15 / #20150147859

Antifuse of semiconductor device and method of fabricating the same

An antifuse of a semiconductor device and a method of fabricating the same capable of causing an antifuse to stably operate by rupturing the antifuse at a specific point and stabilizing a current level when rupturing the antifuse are provided. The antifuse may include: a device isolation layer defining a first active region in a semiconductor substrate; a first and second junction regions provided in the first active region; a second active region formed over the first junction region; a gate insulating layer formed over the first active region and the second active region; and a gate electrode formed over the gate insulating layer.. ... Sk Hynix Inc

05/28/15 / #20150147844

Method for fabricating semiconductor device

A method for fabricating a semiconductor device includes supplying a first source gas including a germanium (ge) precursor onto a semiconductor substrate for a first time period, and periodically interrupting the supplying of the first source gas for the first time period to form ge elements on the semiconductor substrate.. . ... Sk Hynix Inc

05/28/15 / #20150146492

Semiconductor devices

The semiconductor device includes an input clock generator and a data input unit. The input clock generator generates an input clock signal including a first pulse and a second pulse, wherein the first pulse is generated in response to a write signal and a write latency signal and the second pulse is generated in response to an external command signal and a burst length signal. ... Sk Hynix Inc

05/28/15 / #20150146488

Semiconductor device and program fail cells

A semiconductor device includes a memory block including even memory cells configured to form an even page and odd memory cells configured to form an odd page. The semiconductor device may also include an operation circuit configured to perform a program operation on the even memory cells and the odd memory cells. ... Sk Hynix Inc

05/28/15 / #20150146487

Non-volatile memory device and method for erasing the same

Provided are a non-volatile memory device and a method for erasing the non-volatile memory device having vertical channel layers formed with different widths varying by height and a plurality of memory cells stacked along the vertical channel layers, the method including increasing potentials of the vertical channel layers, and when potentials of word lines connected to the memory cells are increased, erasing the memory cells while lowering the potentials of the word lines beginning from a word line positioned in an area in which a width of the vertical channel layer is wide to a word line positioned in an area in which the width of the vertical channel layer is narrow.. . ... Sk Hynix Inc

05/28/15 / #20150146471

Anti-fuse array of semiconductor device and method for operating the same

An anti-fuse array includes: a plurality of first transistors having a matrix structure over a semiconductor substrate; a plurality of second transistors respectively disposed adjacent to first ends of the plurality of first transistors along a first direction of the matrix structure; and a plurality of third transistors respectively disposed at second ends of the plurality of first transistors along a second direction.. . ... Sk Hynix Inc

05/28/15 / #20150145573

Pulse signal generation circuit and operating method thereof

The present invention relates to a pulse signal generation circuit for changing a pulse width of an input pulse signal and outputting an output pulse signal having the changed pulse width. In an aspect, the pulse signal generation circuit may include a control signal generator configured to generate at least one control signal according to a pulse width of a input pulse signal and a pulse signal generator configured to control a pulse width of an input pulse signal in response to a control signal and to generate an output pulse signal with the controlled pulse width. ... Sk Hynix Inc

05/28/15 / #20150145131

Substrates having ball lands, semiconductor packages including the same, and methods of fabricating semiconductor packages including the same

A package substrate includes a core layer having a first surface and a second surface which are opposite to each other, a ball land pad disposed on the first surface of the core layer, an opening that penetrates the core layer to expose the ball land pad, and a dummy ball land disposed on the second surface of the core layer to surround the opening. The dummy ball land includes at least one sub-pattern and at least one vent hole. ... Sk Hynix Inc

05/28/15 / #20150145121

Thin embedded packages, methods of fabricating the same, electronic systems including the same, and memory cards including the same

An embedded package includes a core layer having a cavity, a first semiconductor chip disposed in the cavity, and bumps disposed on a top surface of the first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and the core layer, pads disposed on a top surface of the second semiconductor chip, and a first insulation layer disposed on the core layer and the first and second semiconductor chips. The first insulation layer has first openings that expose the bumps and second openings that expose the pads, and the first and second openings have a similar depth.. ... Sk Hynix Inc

05/28/15 / #20150145120

Semiconductor device having a through electrode

A semiconductor device includes a through electrode, a pad, and a bump. The through electrode penetrates a device body of the semiconductor device. ... Sk Hynix Inc

05/28/15 / #20150145085

Image sensor and method for fabricating the same

An image sensor includes a substrate including a pixel array region and a logic region where a surface of the pixel array region is higher than a surface of the logic region, and a light shielding pattern formed over the substrate of the logic region and having a surface on substantially the same plane as a surface of the substrate.. . ... Sk Hynix Inc

05/28/15 / #20150145031

Vertical-type semiconductor apparatus and fabrication method thereof

A semiconductor apparatus includes a semiconductor substrate including first and second regions, an inactive region formed in the semiconductor substrate of the second region and from a surface thereof, one or more first pillars vertically extending from the semiconductor substrate of the first region, one or more second pillars vertically extending from the inactive region, a gate conductive layer formed on the semiconductor substrate and surrounding the first and second pillars, and a gate contact formed on at least one of the second pillars to be coupled to the gate conductive layer, wherein the at least one of the second pillars has a height lower than the gate conductive layer.. . ... Sk Hynix Inc

05/28/15 / #20150145019

Nonvolatile memory device

A nonvolatile memory device may include: an isolation layer formed in a substrate and defining an active region; a control plug formed over the isolation layer; a floating gate formed over the substrate and including a plurality of fingers adjacent to the control plug with a gap provided therebetween; and a charge blocking layer formed on sidewalls of the floating gate so as to fill the gap. The control plug may include: a first control plug formed between the plurality of fingers and having sidewalls facing inner walls of the fingers; and a second control plug formed outside the floating gate and having sidewalls facing outer walls of the fingers.. ... Sk Hynix Inc

05/28/15 / #20150145013

Semiconductor device and method for forming the same

A semiconductor device includes an active region tilted at an angle with respect to a buried bit line. The buried bit line includes a metal silicide pattern and a metal pattern. ... Sk Hynix Inc

05/21/15 / #20150143203

Semiconductor device and method of operating the same

A semiconductor device includes a memory device suitable for outputting health monitoring data including information on a threshold voltage distribution, and outputting read data read from memory cells included in the memory device, and a controller suitable for receiving a predetermined quantity of the read data from the memory device based on the health monitoring data, and performing a decoding operation for an error correction by using the received read data.. . ... Sk Hynix Inc

05/21/15 / #20150143155

Data storage apparatus

A data storage apparatus includes a controller including a controller input/output unit suitable for receiving a ready/busy delay signal and generating a ready/busy output signal in response to a first control signal, and a memory chip including a memory input/output unit suitable for receiving a chip enable delay signal and generating a chip enable output signal in response to a second control signal. The ready/busy delay signal and the chip enable delay signal are transmitted through a substantially same transmission line.. ... Sk Hynix Inc

05/21/15 / #20150143028

Data storage apparatus and operating method thereof

A data storage apparatus includes a translation section suitable for performing a translation operation for translating first address mapping data to second address mapping data, and an operation memory device suitable for storing the second address mapping data.. . ... Sk Hynix Inc

05/21/15 / #20150140808

Semiconductor device having buried bit lines and method for fabricating the same

A semiconductor device includes body lines, formed substantially perpendicular to a substrate, and having recessed sidewalls, buried bit lines, buried in the recessed sidewalls, and including a metal silicide, and a barrier layer interposed between each of the buried bit lines and the body lines corresponding thereto, and containing germanium.. . ... Sk Hynix Inc

05/21/15 / #20150140804

Semiconductor device and method for manufacturing the same

A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes adjacent storage node contact plugs having different heights, and lower-electrode bowing profiles having different heights, such that a spatial margin between the lower electrodes is assured and a bridge fail is prevented, resulting in improved device operation characteristics. ... Sk Hynix Inc

05/21/15 / #20150140775

Resistive memory device, method of fabricating the same, and memory apparatus and data processing system having the same

A resistive memory device capable of implementing a multi-level cell, a method of fabricating the same, and a memory apparatus and data processing system including the same are provided. The resistive memory device includes a lower electrode, a first phase-change material layer formed over the lower electrode, a second phase-change material layer formed to surround an outer sidewall of the first phase-change material layer, and an upper electrode formed over the first phase-change material layer and the second phase-change material layer.. ... Sk Hynix Inc

05/21/15 / #20150139364

Method for detecting phase and phase detecting system

A phase detection method includes providing by a controller a second control signal having two or more neighboring pulses when the time during which a state of a second control signal is retained is a predetermined time or more, receiving by the controller phase detection results of a phase of a first control signal different from the second control signal in response to the second control signal, and determining by the controller a phase detection result based on a first pulse of the two neighboring pulses of the second control signal, of the phase detection results.. . ... Sk Hynix Inc

05/21/15 / #20150138900

Data storage device and operating method thereof

An operating method of a data storage device includes performing a read operation on a nonvolatile memory device based on a read request and a logical address from a host device, determining whether one or more physical addresses, which correspond to one or more logical addresses continuous to the logical address, are continuous to a physical address corresponding to the logical address, and prefetching data stored in a region of the nonvolatile memory device, corresponding to the one or more physical addresses, when the one or more physical addresses are determined to be continuous.. . ... Sk Hynix Inc

05/21/15 / #20150138899

Data storage device and operating method thereof

An operating method of a data storage device may include performing a first write operation on a first memory region, and performing a second write operation on a second memory region to store position information on the first write operation.. . ... Sk Hynix Inc

05/21/15 / #20150138894

Finding optimal read thresholds and related voltages for solid state memory

A read is performed using a first iteration of a read threshold voltage that is set to a default voltage to obtain a first characteristic. A second iteration of the read threshold voltage is generated using the default voltage and an offset. ... Sk Hynix Inc

05/21/15 / #20150138872

Electronic device including a memory and method for fabricating the same

An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes first lines extending along a first direction; second lines extending along a second direction that intersects with the first direction; a silicon-added metal oxide layer disposed in each intersection region of the first lines and the second lines; a metal oxide layer that is disposed alternately with the silicon-added metal oxide layer in the first direction and that is disposed in a region between two adjacent second lines and over a corresponding one of the first lines over which the silicon-added metal oxide layer is disposed; and a silicon oxide layer that is disposed alternately with the silicon-added metal oxide layer in the second direction and that is disposed in a region between two first lines and under a corresponding one of the second lines under which the silicon-added metal oxide layer is disposed.. ... Sk Hynix Inc

05/21/15 / #20150137257

Semiconductor device with dual work function gate stacks and method for fabricating the same

A method for fabricating a semiconductor device includes forming a gate dielectric layer over a substrate; forming a metal containing layer, containing an effective work function adjust species, over the gate dielectric layer; forming an anti-reaction layer over the metal containing layer; increasing an amount of the effective work function adjust species contained in the metal containing layer; and forming, on the substrate, a gate stack by etching the anti-reaction layer, the metal containing layer, and the gate dielectric layer.. . ... Sk Hynix Inc

05/21/15 / #20150137209

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first channel layer, a second channel layer protruding from the first channel layer, a pipe gate including a silicide area surrounding the first channel layer, a tunnel insulating layer surrounding the second channel layer, a data storage layer surrounding the second channel layer with the tunnel insulating layer interposed therebetween, and interlayer insulating layers and conductive patterns which are alternately stacked while surrounding the second channel layer with the data storage layer and the tunnel insulating layer interposed therebetween.. . ... Sk Hynix Inc

05/21/15 / #20150137066

Electronic device

An electronic device includes a memory. The memory includes a first cell array including a plurality of flash memory cells, a first peripheral circuit suitable for controlling the first cell array, a second cell array including a plurality of variable resistance memory cells, and a second peripheral circuit suitable for controlling the second cell array. ... Sk Hynix Inc

05/07/15 / #20150127914

Semiconductor memory device, memory system and method of operating the same

A memory system including a plurality of memory chips is provided. The memory system includes a first memory chip and a second memory chip that share a data bus and become active by a chip enable signal, and a controller transmitting multi chip select commands to the first and second memory chips. ... Sk Hynix Inc

05/07/15 / #20150127887

Data storage system and operating method thereof

An operating method of a data storage system may include detecting a sudden power-off during a program operation on pages in a memory block, identifying a dummy program target page in the memory block when power is on after the sudden power-off, and performing the program operation on the dummy program target page using dummy data, and performing the program operation on pages in the memory block subsequent to the dummy program target page using normal data.. . ... Sk Hynix Inc

05/07/15 / #20150127884

Memory device and system including the same

A memory device include a memory array, a transmitter suitable for outputting data to the outside of the memory device, and a data bus suitable for transmitting data of a selected memory cell in the memory array to the transmitter during a read operation. When successive read commands for the same memory cell are applied, data transmission from the memory array to the data bus is blocked, and data previously loaded in the data bus is outputted through the transmitter.. ... Sk Hynix Inc

05/07/15 / #20150127873

Semiconductor device and memory system including the same

A semiconductor device and a memory system including the same are disclosed, which relate to a technology for reducing a toggle current of a global input output (gio) of a semiconductor device configured to use a data bus inversion (dbi) scheme. The semiconductor device includes:a local input/output (lio) line driver configured to perform inversion or non-inversion of data of a global input/output (gio) line according to a control signal, and to output the inversion or non-inversion result to the lio line; and an inversion processor configured to combine an inversion control signal and mat information, and output the control signal for controlling inversion or non-inversion of data to the lio line driver.. ... Sk Hynix Inc

05/07/15 / #20150127870

Semiconductor memory device

A semiconductor memory device includes a first global line suitable for inputting/outputting data from/to a first bank, a second global line suitable for inputting/outputting data from/to a second bank, a multi-purpose register (mpr) suitable for loading data having a predetermined value on the first global line in a training mode, a first data input/output (i/o) unit suitable for inputting/outputting data between one of the first and second global lines and a first data pad and selectively transferring data loaded on the first global line to the second global line in response to a bandwidth option in the training mode, and a second data i/o unit enabled in response to the bandwidth option, suitable for inputting/outputting data between the second global line and a second data pad.. . ... Sk Hynix Inc

05/07/15 / #20150126013

Semiconductor device including air gaps and method for fabricating the same

Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. ... Sk Hynix Inc

05/07/15 / #20150124549

Semiconductor devices

The semiconductor device includes a pulse width comparator suitable for generating an internal pulse signal having the same pulse width as an output pulse signal whose pulse width is controlled by first and second control signals during a predetermined period and suitable for generating first and second digital signals and a comparison pulse signal from the internal pulse signal according to a delay time which is set by the first and second control signals, an output pulse signal generator suitable for retarding the comparison pulse signal by the delay time determined by first and second control signals to generate the output pulse signal, and a control signal generator suitable for generating the first and second control signals which are sequentially enabled in response to pulses of the output pulse signal.. . ... Sk Hynix Inc

05/07/15 / #20150124546

Voltage regulator and apparatus for controlling bias current

A voltage regulator includes: a comparator configured to compare a feedback voltage with a reference voltage to output an enable signal and operate based on a bias current; a pass transistor turned on according to the enable signal and configured to output an external power voltage as an output voltage; a voltage distribution circuit configured to distribute and output the output voltage to an input terminal of the comparator; and a bias current control unit configured to control an amount of the bias current supplied to the comparator based on the output voltage.. . ... Sk Hynix Inc

05/07/15 / #20150124545

Semiconductor device and method for driving the same

A semiconductor device includes a periodic signal generating circuit for generating a periodic signal having a set period regardless of changes in temperature in response to a first trimming signal as a default value and controlling the set period of the periodic signal based on the temperature in response to a second trimming signal, and an internal circuit to perform a set operation in response to the periodic signal.. . ... Sk Hynix Inc

05/07/15 / #20150124544

Semiconductor devices and semiconductor systems including the same

A semiconductor system includes a controller and a semiconductor device. The controller outputs offset signals whose level combination is controlled according to temperature code signals including information on an internal temperature. ... Sk Hynix Inc

05/07/15 / #20150124543

Semiconductor devices

Semiconductor devices are provided. The semiconductor device includes a first pre-charge element and a second pre-charge element. ... Sk Hynix Inc

05/07/15 / #20150124542

Semiconductor memory device, semiconductor memory module and operation methods thereof

An operation method of a semiconductor memory device including a fuse array for storing one or more repair addresses includes latching additionally a repair address having an address value, which is not stored in the fuse array in response to an active command signal during a repair operation mode, receiving a repair entry control code from an external device in response to a first column command signal during the repair operation mode, performing a rupture operation of the repair address, which is latched, in response to a second column command signal, wherein the rupture operation is determined based on a value of a repair entry control code, and performing exit of the repair operation mode in response to a precharge command signal, which is provided after the second column command signal.. . ... Sk Hynix Inc

05/07/15 / #20150124540

Semiconductor integrated circuit

A system including a circuit integrated with a semiconductor is provided. The system includes a first data line, a second data line, and a first sense amp configured to sense and amplify data of the first data line. ... Sk Hynix Inc

05/07/15 / #20150124538

Semiconductor memory device

A semiconductor memory device includes a plurality of banks; a plurality of word lines; an advanced refresh operation mode where two or more word lines are selected in parallel in each bank; a pulse generation unit suitable for generating a single bank refresh pulse that toggles for a given time in response to a single bank refresh command of a single bank refresh operation mode; and an address generation unit suitable for generating an advanced single bank address for selecting at least two word lines in one of the banks in response to the single bank refresh pulse and an input address in an entry section of the advanced refresh operation mode.. . ... Sk Hynix Inc

05/07/15 / #20150124536

Semiconductor devices

The semiconductor device includes a comparator and a data output unit. The comparator compares a phase of a first pulse signal generated in a first memory region with a phase of a second pulse signal generated in a second memory region and responsively generates a detection signal. ... Sk Hynix Inc

05/07/15 / #20150124535

Semiconductor integrated circuit

A semiconductor integrated circuit may include: a memory block partitioned into a first region and a second region; a data latch unit configured to latch data outputted from the memory block in response to a control signal; and a control circuit configured to generate a source signal separated into an odd order and an even order in response to a column access signal consecutively inputted to access the first region or the second region, and to generate the control signal in response to the source signal.. . ... Sk Hynix Inc

05/07/15 / #20150124530

Memory string and semiconductor device including the same

A memory string includes a pass transistor, first memory cells connected in series to a drain terminal of the pass transistor, and first to kth memory cell groups connected in parallel to a source terminal of the pass transistor and each including a plurality of second memory cells connected in series. Here, ‘k’ denotes an integer that is equal to or greater than ‘2’.. ... Sk Hynix Inc

05/07/15 / #20150124529

Semiconductor device, method for operating the same, and semiconductor system including the same

A semiconductor device includes a page buffer configured to read data out of a memory cell array in response to a bias enable signal, and a control logic configured to generate the bias enable signal and a bias precharge signal that are used to control the memory cell array. The control logic activates the bias enable signal and the precharge signal before a ready/busy signal activating a read operation of the memory cell array is enabled.. ... Sk Hynix Inc

05/07/15 / #20150124525

Semiconductor device and method for operating the same

A semiconductor device comprises a memory cell array comprising memory cells coupled to word lines and bit lines, a voltage generator suitable for generating a drive voltage to be applied to a selected word line, and a control logic suitable for detecting the number of pulses of a program voltage received from the memory cell array in a program operation, storing bias information corresponding to the detected number of pulses in a register, and controlling a level of the program voltage for a subsequent program operation based on the bias information.. . ... Sk Hynix Inc

05/07/15 / #20150123832

Comparator and analog-to-digital converter using the same

A comparator includes a first amplification unit suitable for differentially amplifying a pixel signal and a ramp signal, a second amplification unit suitable for amplifying a signal outputted from the first amplification unit and outputting a comparison result, a current control unit suitable for controlling a current flow in response to the comparison result and a current compensation and noise removal unit suitable for compensating for current and removing noise under control of the current control unit.. . ... Sk Hynix Inc

05/07/15 / #20150123826

Serializers

Serializers are provided. The serializer includes a first drive control signal generator and a second drive control signal generator. ... Sk Hynix Inc

05/07/15 / #20150123698

Test circuit and method of semiconductor integrated circuit

A test circuit of a semiconductor integrated circuit includes a through via, a voltage driving unit, and a determination unit. The through via is charged by receiving an input voltage. ... Sk Hynix Inc

05/07/15 / #20150123288

Semiconductor package and method for manufacturing the same

The semiconductor package includes semiconductor chips, each chip having one or more bonding pads. The semiconductor chips are stacked in a stepped configuration over the surface of the substrate without covering one or more bonding pads. ... Sk Hynix Inc

05/07/15 / #20150123283

Semiconductor package and method for manufacturing the same

A method of manufacturing a semiconductor package includes: forming a strip substrate including a plurality of unit substrates, each being provided with a first connection pad and a second connection pad on a first surface of the unit substrate and each unit substrate being electrically and physically isolated from each other with the intervention of saw lines, first ground connection pads formed on the respective unit substrates, each of the first ground connection pads being electrically coupled with the first connection pad over the respective unit substrates, second ground connection pads formed on the saw line on the first surface side of the unit substrates and electrically isolated from the unit substrates, and test wiring formed on the saw line, the test wiring being electrically isolated from the unit substrates and electrically coupled with the second ground connection pads; and attaching semiconductor chips onto the respective unit substrates.. . ... Sk Hynix Inc

05/07/15 / #20150123278

Semiconductor devices, methods of manufacturing the same, memory cards including the same and electronic systems including the same

Semiconductor devices are provided. The semiconductor device includes a through electrode penetrating a substrate such that an end portion of the through electrode protrudes from a surface of the substrate, a passivation layer covering the surface of the substrate and defining a plug hole that exposes the end portion of the through electrode, and a barrier plug filling the plug hole. ... Sk Hynix Inc

05/07/15 / #20150123226

Image sensor and method for fabricating the same

An image sensor includes a photoelectric conversion region formed in a substrate, an interlayer insulation layer formed over a front side of the substrate, a carbon-containing layer doped with impurities and formed over a back side of the substrate, and a color filter and a micro-lens formed over the carbon-containing layer.. . ... Sk Hynix Inc

05/07/15 / #20150123182

Transistor and semiconductor device including the same

Provided is a semiconductor device including a pillar, a gate electrode having a first conductive pattern surrounding the pillar and a plurality of second conductive patterns which protrude from the first conductive pattern and are arranged to be spaced apart from each other, and an insulating pattern interposed between the pillar and the first conductive pattern.. . ... Sk Hynix Inc

05/07/15 / #20150123167

Method and gate structure for threshold voltage modulation in transistors

A method of fabricating a semiconductor device. A substrate (pmos/nmos regions) is prepared. ... Sk Hynix Inc

05/07/15 / #20150123133

Integrated circuit for detecting defects of through chip via

An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode.. ... Sk Hynix Inc

05/07/15 / #20150123132

Semiconductor system

A semiconductor system may include a first semiconductor device including a first pad, a second pad and a first test input pad, and suitable for storing data inputted in series through the first test input pad and outputting the stored data in parallel through the first pad and the second pad; a second semiconductor device including a third pad, a fourth pad and a second test output pad, and suitable for storing data inputted in parallel through the third pad and the fourth pad, a first through via connecting the first pad and the third pad so that the stored data outputted in parallel through the first pad is inputted in parallel through the third pad; and a second through via connecting the second pad and the fourth pad so that the stored data outputted in parallel through the second pad is inputted in parallel through the fourth pad.. . ... Sk Hynix Inc

05/07/15 / #20150123067

Electronic device and method for fabricating the same

An electronic device including a semiconductor memory includes a plurality of first electrodes and a plurality of second electrodes, which are disposed over a substrate and alternately arrayed in a first direction that is parallel to a plane of the substrate; and a plurality of resistance variable patterns, each of which is interposed between a corresponding one of the first electrodes and a corresponding one of the second electrodes, wherein the first and second electrodes and the resistance variable patterns extend upwards by a predetermined height from the substrate.. . ... Sk Hynix Inc

04/30/15 / #20150121168

Memory system including randomizer and de-randomizer

A memory system according to an embodiment of the present invention may include a semiconductor memory device including a plurality of memory areas, and a controller suitable for writing data to the semiconductor memory device and reading data from the semiconductor memory device. The controller provides a combined seed, which is used to copy data in a first memory area to a second memory area, to the semiconductor memory device, the combined seed being obtained by performing an operation on a de-randomizing seed corresponding to the first memory area and a randomizing seed corresponding to the second memory area.. ... Sk Hynix Inc

04/30/15 / #20150121026

Semiconductor system and operating method thereof

A semiconductor system includes a semiconductor memory device suitable for storing data, and a host suitable for controlling the semiconductor memory device in response to an external command signal, in which the semiconductor memory device includes a buffer block suitable for storing first data programmed under control of the host, and a main block suitable for storing the second data programmed under control of the host or a copy of the first data stored in the buffer block at a sudden power fail.. . ... Sk Hynix Inc

04/30/15 / #20150121018

Semiconductor memory system and voltage setting method

A semiconductor memory system includes a memory controller and memory apparatus. The memory controller provides a first data having a first level and a second data having a second level. ... Sk Hynix Inc

04/30/15 / #20150120999

Memory system and method for operating the same

A memory system may include a memory including a cell array having a plurality of word lines and an address storage unit that stores an address in response to a capture command, wherein the memory sequentially refreshes the word lines in response to a refresh command at a set cycle, and refreshes a word line corresponding to the stored address in response to the refresh command when the address is stored in the address storage unit; and a memory controller transmitting the refresh command to the memory at the set cycle when a word line satisfying one or more of conditions that the number of activation times is equal to or more than a reference number and an activation frequency is equal to or more than a reference frequency is detected, and transmitting the capture command and an address of the detected word line to the memory.. . ... Sk Hynix Inc

04/30/15 / #20150120991

Data processing system and operating method thereof

A data processing system includes a host device comprising an application and suitable for generating information on an attribute of the application and providing the information on the attribute of the application together with a request of the application and a data storage device suitable for writing data based on the information on the attribute of the application in response to the request of the application.. . ... Sk Hynix Inc

04/30/15 / #20150118808

Non-volatile memory device and method for fabricating the same

A method for fabricating a non-volatile memory device includes: providing a substrate which includes a cell region where a plurality of memory cells are to be formed and a peripheral circuit region where a plurality of peripheral circuit devices are to be formed; forming the memory cells that are stacked perpendicularly to the substrate of the cell region; and forming a first conductive layer for forming a gate electrode of a selection transistor over the memory cells while forming the first conductive layer in the peripheral circuit region simultaneously, wherein the first conductive layer of the peripheral circuit region functions as a resistor body of at least one peripheral circuit device of the peripheral circuit devices.. . ... Sk Hynix Inc

04/30/15 / #20150117133

Semiconductor memory device capable of preventing degradation of memory cells and method for erasing the same

A semiconductor memory device according to an embodiment of the present invention may include a memory cell array having a plurality of memory cells, a pass transistor group having normal pass transistors coupled between global word lines and local word lines to which the plurality of memory cells are coupled, and an address decoder coupled to the global word lines and a block word line to which gates of the normal pass transistors are coupled in common, wherein the address decoder gradually increases a voltage, obtained by subtracting a voltage of the global word lines from a voltage of the block word line, when an erase voltage is provided to a channel of the plurality of memory cells.. . ... Sk Hynix Inc

04/30/15 / #20150117132

Semiconductor memory device and data storage device including the same

A semiconductor memory device includes a memory cell array, a voltage generator suitable for generating voltages used for controlling the memory cell array in response to a power-saving signal, and a control logic suitable for providing a power-saving signal to the voltage generator, based on a chip select signal. The control logic includes a delay block suitable for delaying the chip select signal and generating the power-saving signal based on the delayed chip select signal.. ... Sk Hynix Inc

04/30/15 / #20150117129

Semiconductor memory device, memory system including the same and operating method thereof

A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit suitable for generating program and erase voltages and applying the program and erase voltages to the plurality of memory cells when program and erase operations are performed on the plurality of memory cells, and a control logic suitable for controlling the peripheral circuit unit during the program and erase operations and counting a pulse number of the program and erase voltages to store a resultant count number as status data.. . ... Sk Hynix Inc

04/30/15 / #20150117125

Semiconductor memory device, memory system including the same and operating method thereof

Provided are a semiconductor memory device, a memory system including the same, and an operating method thereof. The semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit suitable for reading least significant bit data and most significant bit data of neighboring memory cells adjacent to selected memory cells out of the plurality of memory cells, and generating pattern flag data using the least significant bit data and the most significant bit data and a control logic suitable for controlling the peripheral circuit to set a read voltage to be applied to the selected memory cells based on the pattern flag data.. ... Sk Hynix Inc

04/30/15 / #20150117123

Semiconductor memory device and method of operating the same

A semiconductor memory device includes a memory cell array having memory cells coupled to a plurality of word lines and a peripheral circuit group configured to supply a pass voltage to unselected word lines among the plurality of word lines, wherein the peripheral circuit group stepwise raises the pass voltage supplied to the unselected word lines to a target level.. . ... Sk Hynix Inc

04/30/15 / #20150117121

Semiconductor memory apparatus and data storage and power consumption

A semiconductor memory apparatus includes a write driver configured to transfer input data to a data storage region. The semiconductor memory apparatus may also include a sense amplifier configured to sense and amplify the data stored in the data storage region and output output data. ... Sk Hynix Inc

04/30/15 / #20150117115

Discharge circuit

A discharge circuit includes a first circuit connected between a high-voltage terminal and a connection node, wherein first circuit includes a depletion high voltage nmos transistor of which a drain connected to the high-voltage terminal, a source connected to the connection node, and a gate receiving a reference voltage, and a second circuit connected between a power supply voltage terminal and the connection node and suitable for discharging the connection node through the power supply voltage terminal when a power-off of a power supply voltage occurs. The discharge circuit may stably perform a discharge operation in the case of sudden power-off.. ... Sk Hynix Inc

04/30/15 / #20150117108

Semiconductor device and methods of manufacturing and operating the same

A semiconductor device includes a memory cell array including a vertical channel layer, two or more selection transistors, and a plurality of memory cells formed along the vertical channel; a peripheral circuit suitable for programming the two or more selection transistors and the memory cells; and a control circuit suitable for controlling the peripheral circuit to decrease a pass voltage applied to one word line adjacent to two or more selection lines coupled to the respective selection transistors, during a program operation in which the peripheral circuit applies a program voltage to the two or more selection lines and applies the pass voltage to a plurality of word lines connected to the memory cells.. . ... Sk Hynix Inc

04/30/15 / #20150117079

Sub word line driver and semiconductor integrated circuit device

A sub word line driver and a semiconductor integrated circuit device having the same are provided. The semiconductor integrated circuit device includes adjacent four sub word line drivers configured to drive four sub word lines in response to signals of four main word lines, wherein first and second sub word line drivers of adjacent sub word line drivers share one keeper transistor with each other, and third and fourth sub word line drivers of the adjacent sub word line drivers share one keeper transistor with each other.. ... Sk Hynix Inc

04/30/15 / #20150116003

Differential amplifier and dual mode comparator using the same

A differential amplifier includes an input common mode voltage generation unit suitable for generating an input common mode voltage, an input common mode voltage sampling unit suitable for performing an independent sampling operation on the input common mode voltage, and a differential amplifying unit suitable for performing a differential amplifying operation on an input voltage and the sampled input common mode voltage.. . ... Sk Hynix Inc

04/30/15 / #20150115435

Semiconductor apparatus including through via

A semiconductor apparatus with a through via includes a semiconductor chip and a through via formed by penetrating through the semiconductor chip. The system further includes a first metal layer connected to a portion of the through via at an end of the through via and a second metal layer connected to another portion of the through via at the end of the through via.. ... Sk Hynix Inc

04/30/15 / #20150115392

Semiconductor device and method for fabricating the same

A semiconductor device includes a bit line disposed over a semiconductor substrate, a supporting film being perpendicular to the bit line, a first storage node contact disposed at a lower part of a region disposed between the bit line and the supporting film, and a second storage node contact having a line shape, disposed over the first storage node contact and the bit line, isolated by the supporting film, and patterned in a diagonal direction across the bit line.. . ... Sk Hynix Inc

04/30/15 / #20150115379

Cobalt (co) and platinum (pt)-based multilayer thin film having inverted structure and method for manufacturing same

The present invention relates to a cobalt (co) and platinum (pt)-based multilayer thin film having a novel structure and perpendicular magnetic anisotropy, and to a fabrication method thereof. More specifically, the invention relates to a cobalt and platinum-based multilayer thin film having perpendicular magnetic anisotropy (pma), which includes thin cobalt layers and thin platinum layers alternately deposited over a substrate, and has an inverted structure in which a thickness of the thin cobalt layers is greater than that of the thin platinum layers, and to a fabrication method thereof. ... Sk Hynix Inc

04/30/15 / #20150115347

Semiconductor device and method for fabricating the same

A semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel, a gate, and a memory layer is interposed between the channel and the gate. ... Sk Hynix Inc

04/30/15 / #20150115268

Semiconductor apparatus and testing method thereof

A semiconductor apparatus having a through via to be electrically coupled with a chip includes a latch memory cell configured to be electrically coupled with the through via and receive a signal transmitted through the through via, and output a stored signal to the through via.. . ... Sk Hynix Inc

04/23/15 / #20150113355

Data storage device

A data storage device includes a nonvolatile memory device, an error correction code unit suitable for detecting and correcting a data error read from the nonvolatile memory device in response to an operation clock, and a clock unit suitable for selectively providing the operation clock to the error correction code unit depending on whether the data is read from the nonvolatile memory device or not.. . ... Sk Hynix Inc

04/23/15 / #20150113333

Data processing system and operating method thereof

An operating method of a data processing system includes calculating a test result by performing a test for measuring characteristics of each of lanes included in the data processing system, and selecting one or more operating lanes among the lanes based on the test result.. . ... Sk Hynix Inc

04/23/15 / #20150113322

Data storing system and operating method thereof

A data storing system includes a semiconductor device suitable for repeatedly performing a read operation by changing a level of a read voltage according to read voltages listed on a read retry table when a read operation on a selected page is passed, in response to a command and an address, and a controller suitable for controlling the read operation of the semiconductor device by generating the command and the address, wherein a read voltage to be used for performing the read operation is determined among the read voltages listed on the read retry table when the semiconductor device performs the read operation based on data read as a result of a predetermined number of read operations.. . ... Sk Hynix Inc

04/23/15 / #20150113305

Data storage device

A data storage device includes a nonvolatile memory device; and a controller suitable for controlling an operation of the nonvolatile memory device based on a request from a host device, wherein the controller includes a first core activated in a normal mode and a second core activated in a standby mode.. . ... Sk Hynix Inc

04/23/15 / #20150113237

Data storing system and operating method thereof

A method of operating a data storing system includes performing a first copy operation of copying data stored in memory cells of first to nth word lines (n>1, and n is an integer) of a first memory block to first to nth pages of a word line of a second memory block; if a power is turned off, searching for a first erase page, which is recognized to be in an erase state, among the pages of the second memory block when the power comes back on; performing a first map-update on copied pages of the second memory block except for a set number of pages copied right before the first erase page; and performing a second copy operation from the first erase page.. . ... Sk Hynix Inc

04/23/15 / #20150113213

Resistive memory device, operating method thereof, and system having the same

A resistive memory device includes a memory cell array including a plurality of resistive memory cells, an address decoder suitable for decoding an address signal and selecting the resistive memory cells, a read/write control circuit suitable for programming data to the memory cell array or reading data from the memory cell array, a voltage generator suitable for generating operation voltages and providing the operation voltages to the address decoder and a controller suitable for controlling the address decoder, the read/write control circuit, and the voltage generator to perform a write operation in response to a write command and a plurality of write data.. . ... Sk Hynix Inc

04/23/15 / #20150113207

Operating method of data storage device

A method for operating a data storage device includes grouping memory blocks of a nonvolatile memory device based on program counts or erase counts of the respective memory blocks, into a first group and a second group, which has program counts or erase counts larger than the first group, performing a reprogram operation for memory blocks included in the first group, and performing a read retry operation for a selected memory cell of a memory block included in the first group or the second group, based on a read retry voltage set for each of the first group and the second group, when an error of data read from the selected memory cell is not correctable.. . ... Sk Hynix Inc

04/23/15 / #20150111352

Semiconductor device and method of manufacturing the same

A semiconductor device includes word lines and interlayer insulating layers alternately stacked over a substrate, vertical channel layers protruding from the substrate and passing through the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding each of the vertical channel layers, a charge trap layer surrounding the tunnel insulating layer, wherein first regions of the charge trap layer between the tunnel insulating layer and the word lines have a thickness smaller than a thickness of second regions thereof between the tunnel insulating layer and the interlayer insulating layers, and first charge blocking layer patterns surrounding the first regions of the charge trap layer.. . ... Sk Hynix Inc

04/23/15 / #20150111309

Method for fabricating semiconductor device

In a method for fabricating a semiconductor device, a conductive layer is formed on a substrate, where the substrate has a bottom layer formed thereon. A magnetic tunnel junction layer is formed on the conductive layer. ... Sk Hynix Inc

04/23/15 / #20150109856

Semiconductor memory apparatus and temperature control method thereof

A semiconductor memory apparatus and a temperature control method thereof are provided. The semiconductor memory apparatus includes a temperature adjustment unit suitable for adjusting a temperature of a memory cell, and a temperature control unit suitable for sensing a temperature of the temperature adjustment unit, comparing a sensed temperature with a reference temperature range, and controlling the temperature adjustment unit to adjust the temperature thereof within the reference temperature range based on a comparison result.. ... Sk Hynix Inc

04/23/15 / #20150109841

Semiconductor device and method for operating the same

A semiconductor device comprises a memory block having a content addressable memory (cam) cell array storing data for internal operation conditions, and a memory cell array. The semiconductor device also comprises a page buffer to program data in the memory block or read the data programmed in the memory block; a control logic to activate a reset enable signal for initializing the page buffer during a reset operation and output the activated reset enable signal; and a power-supply controller to output a reset control signal for initializing the page buffer when the reset enable signal is activated, and provide a page buffer power-supply signal to the page buffer. ... Sk Hynix Inc

04/23/15 / #20150109840

Semiconductor device and method for operating the same

A semiconductor device employs a technology for improving data retention characteristics of a cell array storing data regarding conditions for controlling internal operations of the semiconductor device. The semiconductor device includes a content addressable memory (cam) cell array configured to store cam data regarding conditions for controlling the internal operations, a control logic configured to store the cam data read out of the cam cell array, and a microprocessor configured to perform a reprogramming operation on the cam cell array using the cam data stored in the control logic.. ... Sk Hynix Inc

04/23/15 / #20150109041

Method for reducing output data noise of semiconductor apparatus and semiconductor apparatus implementing the same

Provided is a semiconductor apparatus which includes a plurality of output buffers configured to connect a plurality of power sources, and a data noise measuring unit configured to fix an output data of a selected output buffer among the plurality of output buffers to have a specific level, measure a noise of the output data using a capacitance and control a slew rate of the plurality of output buffers based on the noise.. . ... Sk Hynix Inc

04/23/15 / #20150108601

Semiconductor device including a wall oxide film and method for forming the same

A semiconductor device includes an oxide film structure having different thicknesses depending on where the oxide film structure is formed. In the semiconductor device, a wall oxide film is formed to have different thicknesses depending on locations of sidewalls of an active region. ... Sk Hynix Inc

04/23/15 / #20150108574

Semiconductor device and method for forming the same

A semiconductor device has a semiconductor substrate including a cell region and a peripheral region and includes: a silicon-metal-silicon (sms)-structured wafer formed in the cell region, which includes a stacked structure of a first silicon substrate, a metal layer, and a second silicon substrate; and a silicon on insulator (soi)-structured wafer formed in the peripheral region, which includes a stacked structure of the first silicon substrate, a silicon insulation film, and the second silicon substrate.. . ... Sk Hynix Inc

04/16/15 / #20150106678

Semiconductor device and semiconductor system including the same

A semiconductor system includes a memory configured to output a parity bit during a read operation and receive a data mask (dm) signal during a write operation. The semiconductor system also includes a system on chip (soc) configured to detect errors by decoding the parity bit during the read operation, and output the dm signal to the memory during the write operation. ... Sk Hynix Inc

04/16/15 / #20150106573

Data processing system

A data processing system includes a host device including a first working memory and a data storage device suitable for responding to an access request from the host device. The data storage device includes a controller suitable for controlling an operation of the data storage device, a second working memory suitable for storing data used for driving of the controller, and an access controller suitable for accessing a shared memory region of the first working memory under the control of the controller.. ... Sk Hynix Inc

04/16/15 / #20150106551

Semiconductor device and operating method thereof

A semiconductor device remaps the relationship between logical addresses and physical addresses of a semiconductor memory device at each first interval. The semiconductor device may include a wear leveling controller configured to select a first physical address of the semiconductor memory device to remap a logical address corresponding to the first physical address of the semiconductor memory device to a second physical address of the semiconductor memory device, and to adjust the first interval.. ... Sk Hynix Inc

04/16/15 / #20150104934

Semiconductor device and method for fabricating the same

A semiconductor device includes a substrate including an active region, an insulation layer formed over the substrate, a plurality of openings formed in the insulation layer, a plurality of contact plugs filling the plurality of openings, a silicide layer formed over the substrate and between the substrate and each contact plug of the contact plugs in order to cover a bottom of each contact plug. The semiconductor device may decrease contact resistance by forming a silicide layer before the formation of openings regardless of the linewidth and aspect ratio of the openings. ... Sk Hynix Inc

04/16/15 / #20150104924

Nonvolatile memory device and method for fabricating the same

A nonvolatile memory device includes a substrate having active regions that are defined by an isolation layer and that have first sidewalls extending upward from the isolation layer, floating gates adjoining the first sidewalls of the active regions with a tunnel dielectric layer interposed between the active regions and the floating gates and extending upward from the substrate, an intergate dielectric layer disposed over the floating gates, and control gates disposed over the intergate dielectric layer.. . ... Sk Hynix Inc

04/16/15 / #20150104919

Three-dimensional semiconductor device, variable resistive memory device including the same, and method of manufacturing the same

A three-dimensional semiconductor device, a resistive variable memory device including the same, and a method of manufacturing the same are provided. The method may include forming a source on a semiconductor substrate, sequentially forming a first semiconductor layer formed of a first material, a second semiconductor layer formed of a second material having a higher oxidation rate than that of the first material, and a third semiconductor layer formed of the first material on the source; patterning the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; forming a lightly doped drain (ldd) region in the second semiconductor layer and a drain in the third semiconductor layer; oxidizing outer circumferences of the first semiconductor layer, the ldd region and the drain region to form a gate insulating layer; forming a gate on an outer circumference of the gate insulating layer to overlap the first semiconductor layer and a portion of the ldd region; foaming a heating electrode on the drain; and forming a variable resistance layer on the heating electrode.. ... Sk Hynix Inc

04/16/15 / #20150104884

Semiconductor memory device and manufacturing method thereof

A method for manufacturing a semiconductor memory device includes forming a magnetic tunnel junction layer on a lower electrode, forming a spacer having an annular shape on the magnetic tunnel junction layer, forming upper electrodes on both sidewall surfaces of the annular shaped spacer, removing the spacer, and etching the magnetic tunnel junction layer by using the upper electrodes as an etch mask.. . ... Sk Hynix Inc

04/16/15 / #20150103609

Semiconductor devices

A semiconductor device including a control signal generator and an internal refresh signal generator is provided. The control signal generator generates first and second control signals, one of which is selectively enabled in response to temperature code signals and mode set signals after a pulse of an internal refresh signal is outputted by the internal refresh signal generator. ... Sk Hynix Inc

04/16/15 / #20150103606

Semiconductor device

A semiconductor device includes a data output circuit suitable for transferring an output data to an external data line during a data output operation, and a controller suitable for generating control signals for controlling the data output circuit during the data output operation, wherein the data output circuit senses a variation and transfers the output data to the external data line based on the sensing result.. . ... Sk Hynix Inc

04/16/15 / #20150103589

Resistive memory apparatus, operation method thereof, and system having the same

A resistive memory apparatus includes a memory cell array including a plurality of resistive memory cells, an address decoder suitable for decoding an address signal, and accessing the memory cell array, a read/write control circuit suitable for programming data in the memory cell array or reading out data from the memory cell array, a voltage generation unit suitable for generating a program voltage and a first read voltage for a program operation and a second read voltage for a read operation and providing the voltages to the address decoder, and a controller suitable for controlling the voltage generation unit to generate the first read voltage for verification of the program operation in response to a program command, and the second read voltage higher than the first voltage in response to a read command.. . ... Sk Hynix Inc

04/16/15 / #20150103588

Variable resistance memory apparatus, manufacturing method thereof

A variable resistance memory apparatus and a method of manufacturing the same are provided. The variable resistance memory apparatus includes a plurality of memory cells. ... Sk Hynix Inc

04/16/15 / #20150103587

Electronic device and method for driving the same

In an electronic device including a semiconductor memory, the semiconductor memory may include a unit storage cell including a variable resistor having a resistance value that is changed according to current flowing through both terminals of the variable resistor and a selection element that is electrically coupled to one terminal of the variable resistor, a unit current generation section that generates the current flowing through both terminals by using predetermined voltage according to a polarity of current data as compared with existing data, and a pad that receives the predetermined voltage from an exterior and allows the current flowing through both terminals to be measured from an exterior.. . ... Sk Hynix Inc

04/16/15 / #20150102857

Voltage generator, integrated circuit, and voltage generating method

A voltage generator includes: a first pump configured to generate and output a first voltage to a first node in response to a first clock signal; a second pump configured to generate and output a second voltage to a second node in response to the first clock signal; a third pump configured to generate and output a third voltage to the first and second nodes in response to the first clock signal; a first switch configured to deliver the third voltage to the first node in response to a first control signal; and a second switch configured to deliver the third voltage to the second node in response to a second control signal, in which the first pump has a first drivability, the second pump has a second drivability, and the third pump has a third drivability greater than the first and second drivabilities.. . ... Sk Hynix Inc

04/16/15 / #20150102840

Cascoded comparator with dynamic biasing for column parallel single slope adcs

Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. ... Sk Hynix Inc

04/16/15 / #20150102838

Semiconductor device and method for detecting state of input signal of semiconductor device

A semiconductor device includes a signal detection unit suitable for detecting a state of an input signal and generating a detection signal based on a detected result, and a signal transmission unit suitable for selectively transmitting the input signal in response to the detection signal, wherein the signal detection unit includes a state signal generation unit suitable for detecting a level shifting time of the input signal, and generating a state signal at a detected level shifting time, and a state determination unit suitable for comparing a voltage level of the input signal with a voltage level of a reference voltage in response to the state signal, and outputting the detection signal.. . ... Sk Hynix Inc

04/16/15 / #20150102837

Semiconductor device including an arbiter cell

A semiconductor device is implemented with a technology for removing a command bubbling generated when performing a rank-to-rank switching on chips that are stacked and interconnected through a through silicon via (tsv). The semiconductor device includes a first memory, a second memory stacked over the first memory to input/output data through a tsv, and an arbiter configured to adjust first data received from the first memory and second data received from the second memory through the tsv and provide the adjusted data to an input/output (i/o) pad.. ... Sk Hynix Inc

04/16/15 / #20150102415

Semiconductor device

A semiconductor device includes a first and a second active regions having a first conductive type and a second conductive type, respectively, being arranged in a first direction; a gate extending in the first direction; a first and a second channel regions defined under the gate in the first and the active regions, respectively; a first low-concentration doped region, having the second conductive type, formed at sides of the gate in the first active region and a first high-concentration doped region, having the second conductive type, formed at sides of the first low-concentration doped region in the first active region; and a second low-concentration doped region, having the first conductive type, formed at sides of the gate in the second active region and a second high-concentration doped region, having the first conductive type, formed at sides of the second low-concentration doped region in the second active region.. . ... Sk Hynix Inc

04/16/15 / #20150102280

Variable resistive memory device and method of fabricating the same

Provided are a variable resistive memory device and a method of fabricating the same. The variable resistive memory device includes an interlayer insulating film having an opening therein, the opening exposing a surface of a first electrode which is disposed at a bottom of the opening. ... Sk Hynix Inc

04/09/15 / #20150100850

Semiconductor device, memory device, and system including the same

A memory device includes a memory array suitable for storing write data of the memory device and providing the stored data as read data of the memory device, a programmable storage unit suitable for storing information for the memory device, a command decoder suitable for storing decoding one or more command signals, and generating a write command for writing the write data, a read command for outputting the read data, and an information read command for outputting information stored in the programmable storage unit, a control unit suitable for controlling the information stored in the programmable storage unit to be sequentially read in response to activation of the information read command, and an output unit suitable for outputting the read information to an outside of the memory device in response to the information read command.. . ... Sk Hynix Inc

04/09/15 / #20150100849

Memory system and operating method thereof

A memory system and an operating method thereof are provided. The memory system includes a semiconductor memory device configured to perform a read operation and a controller configured to control the read operation of the semiconductor memory device, and the controller, by determining programmed states of memory cells located nearby selected memory cells, divides the selected memory cells into a plurality of groups depending on an amount of interference, and corrects data of one of the groups having a great amount of interference.. ... Sk Hynix Inc

04/09/15 / #20150100837

Semiconductor memory device and semiconductor system including the same

A semiconductor memory device includes a memory cell array including a normal region for storing a plurality of data, an error information region for storing a plurality of error information data corresponding to the plurality of normal data, respectively, and a redundancy region for replacing the normal region, an error detection unit suitable for detecting an error on the plurality of data in response to the plurality of error information data, and storing an error location information, which indicates a storage region of a data having an error in the normal and redundancy regions, based on an error detection result, and a repair operation unit suitable for replacing the storage region, which is indicated by the error location information, by the redundancy region during a repair operation period.. . ... Sk Hynix Inc

04/09/15 / #20150100814

Semiconductor device and semiconductor systems including the same

A semiconductor device includes an information detection unit suitable for receive an input signal and detecting a clock and data from the input signal by using reference voltages corresponding to voltage levels of the clock and data, and a synchronization unit suitable for outputting internal data by synchronizing the data with the dock detected by the information detection unit.. . ... Sk Hynix Inc

04/09/15 / #20150099354

Semiconductor device

A semiconductor device includes vertical channel layers, control gates and interlayer insulating layers stacked alternately with each other on the substrate and surrounding the vertical channel layers, floating gates interposed between the vertical channel layers and the control gates and separated from each other by the interlayer insulating layers, and charge blocking layers interposed between the floating gates and the control gates.. . ... Sk Hynix Inc

04/09/15 / #20150099343

Semiconductor memory device

A semiconductor memory device includes a plurality of auxiliary patterns formed over a semiconductor substrate, a plurality of gate line patterns disposed in parallel with one another over the semiconductor substrate between the plurality of auxiliary patterns, and an air gap formed between the plurality of gate line patterns and between each of the plurality of gate line patterns and each of the auxiliary patterns.. . ... Sk Hynix Inc

04/09/15 / #20150099339

Non-volatile memory device and method for fabricating the same

A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.. ... Sk Hynix Inc

04/09/15 / #20150099338

Non-volatile memory device and method of manufacturing the same

A non-volatile memory device includes first and second vertical channel layers generally protruding upwardly from a semiconductor substrate substantially in parallel; a first gate group configured to include a plurality of memory cell gates which are stacked substantially along the first vertical channel layer and are isolated from each other with an interlayer insulating layer interposed substantially between the memory cell gates; a second gate group configured to include a plurality of memory cell gates which are stacked substantially along the second vertical channel layer and are isolated from each other with the interlayer insulating layer interposed substantially between the memory cell gates; a pipe channel layer configured to couple the first and the second vertical channel layers; and a channel layer extension part generally extended from the pipe channel layer to the semiconductor substrate and configured to couple the pipe channel layer and the semiconductor substrate.. . ... Sk Hynix Inc

04/09/15 / #20150099337

Nonvolatile memory device and method for fabricating the same

A nonvolatile memory device includes a substrate; a channel layer projecting from a surface of the substrate, in a direction perpendicular to the surface; a tunnel dielectric layer surrounding the channel layer; a plurality of interlayer dielectric layers and a plurality of control gate electrodes alternately formed along the channel layer; floating gate electrodes interposed between the tunnel dielectric layer and the plurality of control gate electrodes, the floating gate electrodes comprising a metal-semiconductor compound; and a charge blocking layer interposed between each of the plurality of control gate electrodes and each of the plurality of floating gate electrodes.. . ... Sk Hynix Inc

04/09/15 / #20150098296

Semiconductor device and semiconductor system with the same

A semiconductor device includes a first internal clock generation unit suitable for generating a first internal clock for synchronizing a first signal in response to a first external clock; a second internal clock generation unit suitable for generating a second internal clock for synchronizing a second signal in response to a second external clock; and a delay amount information provision unit suitable for providing delay amount information corresponding to a phase difference between the first internal clock and the second internal clock to an external device.. . ... Sk Hynix Inc

04/09/15 / #20150098294

Counter circuit and semiconductor device including the same

A counter circuit includes a lower count signal generation unit suitable for generating a lower bit, an upper count signal generation unit suitable for generating an upper bit, and a control unit suitable for determining a counting route in response to a control signal and controlling the lower and upper count signal generation units based on a determined route, wherein in a first route, the upper bit is generated in response to the lower bit, and in a second route, the lower bit is generated in response to the upper bit.. . ... Sk Hynix Inc

04/09/15 / #20150098293

Semiconductor integrated circuit

A semiconductor integrated circuit includes a plurality of semiconductor chips. Each of the plurality of semiconductor chips includes a chip selection unit suitable for generating an internal chip selection signal in response to one or more selective chip selection signals and transferring the selective chip selection signals to an adjacent semiconductor chip of the plurality of semiconductor chips, a selective setting unit suitable for generating a selective internal signal, selectively activated in each semiconductor chip, in response to the internal chip selection signal and an external setting signal, and a common setting unit suitable for generating a common internal signal, activated in common in the plurality of semiconductor chips, in response to the setting signal and an external common chip selection signal.. ... Sk Hynix Inc

04/09/15 / #20150098288

Electronic device including semiconductor memory and operation method of the same

An electronic device includes a semiconductor memory. The semiconductor memory includes a cell array including first to nth word lines, where the n is an integer equal to or larger than 2, first to nth memory sets respectively corresponding to the first to nth word lines, and an activation number updating block configured to, when a kth word line of the word lines is activated, initialize a value stored in a kth memory set and increase values stored in memory sets corresponding to adjacent word lines of the kth word line, among the memory sets, wherein the k is an integer equal to or larger than 1 and equal to or smaller than n.. ... Sk Hynix Inc

04/09/15 / #20150098287

Memory device and operation method of memory device and memory system

An operation method of a memory device includes entering a repair mode, changing an input path of setting data from a set path to a repair path in response to the entering of the repair mode, receiving the setting data together with a setting command, ending the repair mode after the receiving is repeated a set number of times, changing the input path of the setting data from the repair path to the set path in response to the ending of the repair mode, and programming a repair address for a defective memory cell of the memory device to a nonvolatile memory using the setting data.. . ... Sk Hynix Inc

04/09/15 / #20150098286

Semiconductor memory device

A semiconductor memory device includes: a memory cell array region having a plurality of normal cell lines and a plurality of repair cell lines; a plurality of normal cell line selection units suitable for selecting the plurality of normal cell lines, respectively, in response to a local address; a plurality of repair cell line selection units suitable for selecting the plurality of repair cell lines, respectively, in place of normal cell line selection units corresponding to fail information of the local address; a fuse driving unit comprising a fuse array in which the fail information is programmed, suitable for disabling the normal cell line selection units corresponding to the fail information, and enabling normal cell line selection units unrelated to the fail information; and an address determination unit suitable for controlling the plurality of repair cell line selection units based on the fail information.. . ... Sk Hynix Inc

04/09/15 / #20150098284

Semiconductor memory device and memory system including the same

A semiconductor memory device may include: a memory cell array; a first address controller configured to receive a first command and a first address and generate a first control signal in response to the first command; and a second address controller configured to receive a second address and a second command inputted at the same time as the first command, and generate a second control signal in response to the second command.. . ... Sk Hynix Inc

04/09/15 / #20150098283

Semiconductor device and semiconductor system including the same

A semiconductor device includes a pipe latch suitable for sequentially latching data in response to a pipe input control signal and sequentially outputting data in response to a pipe output control signal, a pipe latch control unit suitable for generating the pipe input/output control signals in response to a command signal and latency information, and resetting the pipe input/output control signals in response to a pipe reset signal, and an error detection unit suitable for receiving the pipe input control signal and the pipe output control signal, detecting a latency error, and generating the pipe reset signal. . ... Sk Hynix Inc

04/09/15 / #20150098282

Semiconductor memory device and semiconductor system including the same

Disclosed herein is a semiconductor memory device using a pre-fetch method and a semiconductor system including the same. The semiconductor memory device may include a memory bank having an odd-numbered array region suitable for inputting/outputting data through n first local lines in response to an odd-numbered column address, and an even-numbered array region suitable for inputting/outputting data through n second local lines in response to an even-numbered column address, n being a positive integer, a column address generation unit suitable for consecutively generating the odd-numbered column address and the even-numbered column address whose generation sequence is controlled depending on whether an external column address has an even-numbered value or an odd-numbered value, and n global lines coupled in common to the n first local lines and the n second local lines, suitable for inputting/outputting data.. ... Sk Hynix Inc

04/09/15 / #20150098281

Semiconductor chip and semiconductor integrated circuit including the same

A semiconductor chip includes an internal voltage generation circuit suitable for generating an internal voltage having a predetermined level, a target internal circuit suitable for performing a predetermined operation using the internal voltage, and a control circuit suitable for checking operating speed of the target internal circuit based on an operation result signal generated from the target internal circuit, and generating the control signal based on the checked operating speed, wherein a voltage level of the internal voltage for target internal circuit is controlled based on the control signal.. . ... Sk Hynix Inc

04/09/15 / #20150098264

Resistive memory apparatus, operating method thereof, and system having the same

A resistive memory apparatus includes a memory unit including a resistive memory cell array, a voltage generation unit suitable for receiving a radio frequency (rf) signal, and converting the rf signal into a direct current (dc) voltage, and a control unit suitable for controlling a refresh operation to be performed on the resistive memory cell array, wherein the boosted dc voltage is used as an operation voltage for the refresh operation.. . ... Sk Hynix Inc

04/09/15 / #20150098262

Semiconductor memory device having ray detector, and electronic device including the same, and operating method thereof

A semiconductor memory device includes a first memory region, a second memory region suitable for storing the same data as the first memory region, and a ray detection circuit suitable for detecting an incident ray to the first memory region, wherein a data stored in the second memory region is copied into the first memory region when the incident ray is detected.. . ... Sk Hynix Inc

04/09/15 / #20150097605

Duty correction circuit and method

A duty correction circuit includes a duty ratio control unit suitable for generating an output clock by adjusting the duty ratio of an input clock, a code generation unit suitable for detecting a duty of the output clock and generating a first duty ratio control code based on the detection result, and a code filter unit suitable for providing the duty ratio control unit with a second duty ratio control code corresponding to a target value when a value of the first duty ratio control code is within a predetermined critical range adjacent to the target value.. . ... Sk Hynix Inc

04/09/15 / #20150097596

Cascoded comparator with dynamic biasing for column parallel single slope adcs

Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. ... Sk Hynix Inc

04/09/15 / #20150097229

3-d nonvolatile memory device and method of manufacturing the same

A three-dimensional (3-d) nonvolatile memory device includes channel layers protruding perpendicular to a surface of a substrate, interlayer insulating layers and conductive layer patterns alternately formed to surround each of the channel layers, a slit formed between the channel layers, the slit penetrating the interlayer insulating layers and the conductive layer patterns, and an etch-stop layer formed on the surface of the substrate at the bottom of the slit.. . ... Sk Hynix Inc

04/09/15 / #20150097185

Semiconductor device having test unit, electronic apparatus having the same, and method for testing the semiconductor device

A semiconductor device can detect a defective or faulty part caused by copper (cu) ions migrated from a through silicon via (tsv), resulting in improvement of device characteristics and reliability. The semiconductor device includes: a semiconductor substrate including an active region defined by a device isolation region; a through silicon via (tsv) formed to pass through the semiconductor substrate; and a test unit formed in the vicinity of the tsv so as to determine the presence or absence of metal pollution caused by the tsv.. ... Sk Hynix Inc

04/02/15 / #20150095668

Internal voltage generation circuits

An internal voltage generation circuit includes a bulk voltage generator and an internal voltage driver. The a bulk voltage generator is configured to output any one of a power supply voltage signal and a core voltage signal as a first bulk voltage signal and any one of a ground voltage signal and a low voltage signal as a second bulk voltage signal. ... Sk Hynix Inc

04/02/15 / #20150095522

Semiconductor memory

A semiconductor memory in accordance with an embodiment includes: a control unit configured to generate a plurality of second control signals in response to a page size signal and a plurality of first control signals; a plurality of input/output switches configured to be coupled to each of a plurality of unit memory blocks and activated in response to the plurality of second control signals; and a plurality of page change switches configured to couple data lines of the plurality of unit memory blocks in response to the page size signal.. . ... Sk Hynix Inc

04/02/15 / #20150095520

Semiconductor memory apparatus and data input and output method thereof

A semiconductor memory apparatus includes an input data bus inversion unit, a data input line, a termination unit, a data recovery unit and a memory bank. The input data bus inversion unit determines whether or not to invert a plurality of input data based on an operation mode signal and the plurality of input data and generates a plurality of conversion data. ... Sk Hynix Inc

04/02/15 / #20150093875

Semiconductor device and method of manufacturing the same

The semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein, semiconductor memory elements formed over the semiconductor substrate in the cell region, an interlayer insulating layer formed over the semiconductor substrate in the peripheral circuit region, first conductive layers substantially vertically passing through the interlayer insulating layer, and arranged in a matrix, and second conductive layers coupling the first conductive layers in rows or columns, each pair of the second conductive layers and the first conductive layers coupled to the each pair of the second conductive layers, respectively, forming electrodes of a capacitor.. . ... Sk Hynix Inc

04/02/15 / #20150093866

Nonvolatile memory device and method for fabricating the same

A nonvolatile memory device includes a pipe insulation layer having a pipe channel hole, a pipe gate disposed over the pipe insulation layer, a pair of cell strings each having a columnar cell channel, and a pipe channel coupling the columnar cell channels and surrounding inner sidewalls and a bottom of the pipe channel hole.. . ... Sk Hynix Inc

04/02/15 / #20150092509

Semiconductor apparatus and chip id generation method thereof

Provided is a semiconductor apparatus including a plurality of memory chips which are sequentially stacked. Each of the memory chips includes: a temperature sensor configured to sense the temperature of the memory chip; and a chip id output unit configured to generate a chip id for the memory chip based on an output of the temperature sensor.. ... Sk Hynix Inc

04/02/15 / #20150092504

Semiconductor devices

Semiconductor devices are provided. The semiconductor device includes a charge controller, a delay unit and a discharger. ... Sk Hynix Inc

04/02/15 / #20150092500

Semiconductor memory apparatus

A semiconductor memory apparatus includes a first data storage region configured to be supplied with a driving voltage via a first voltage line, a second data storage region configured to be supplied with a driving voltage via a second voltage line and a switch configured to one of electrically couple the first voltage line with the second voltage line and decouple the first voltage line from the second voltage line in response to a switching control signal.. . ... Sk Hynix Inc

04/02/15 / #20150092495

Semiconductor memory device and method of operating the same

A semiconductor memory device includes a memory cell array configured to store data; peripheral circuits configured to perform program verifying operation, read operation, and erase verifying operation on the memory cell array; and a control circuit configured to control the peripheral circuits, wherein the control circuit is configured to control the peripheral circuits to set a bit line voltage in the program verifying operation to have a higher level than a bit line voltage in the read operation, and a bit line voltage in the erase verifying operation to have a lower level than the bit line voltage in the read operation.. . ... Sk Hynix Inc

04/02/15 / #20150092484

Semiconductor integrated circuit

A plurality of memory blocks; and a control block configured to independently operate a part of the plurality of memory banks as a first sub-channel and a remainder of the plurality of memory banks as a second sub-channel according to whether a sub-channel is set.. . ... Sk Hynix Inc

04/02/15 / #20150092482

Electronic device and method of fabricating the same

An electronic device includes a semiconductor memory, wherein the semiconductor memory includes a variable resistance element formed over a substrate, and a multi-layer passivation layer positioned over sidewalls of the variable resistance element and having two or more insulating layers formed over the sidewalls of the variable resistance element.. . ... Sk Hynix Inc

04/02/15 / #20150092481

Electronic device and method for fabricating the same

An electronic device includes a semiconductor memory, wherein the semiconductor memory includes: a variable resistance element having a stacked structure of a first magnetic layer, a tunnel barrier layer, and a second magnetic layer; and a protection layer including a pillar-shaped magnetic compensation layer and a non-magnetic layer, which are formed on the sidewall of the variable resistance element.. . ... Sk Hynix Inc

04/02/15 / #20150092480

Electronic device and method of fabricating the same

An electronic device includes a semiconductor memory, wherein the semiconductor memory includes: a seed layer including conductive hafnium silicate; a first magnetic layer formed over the seed layer; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer.. . ... Sk Hynix Inc

04/02/15 / #20150092474

Resistive memory device, method of fabricating the same, and memory apparatus and data processing system having the same

A resistive memory device capable of implementing a multi-level cell, a method of fabricating the same, and a memory apparatus and data processing system including the same are provided. The resistive memory device includes a lower electrode, a first phase-change material layer formed over the lower electrode, a second phase-change material layer formed to surround an outer sidewall of the first phase-change material layer, and an upper electrode formed over the first phase-change material layer and the second phase-change material layer.. ... Sk Hynix Inc

04/02/15 / #20150092472

Electronic devices having semiconductor memories

Provided is an electronic device including a semiconductor memory which includes a cell array region having a first variable resistance element and a peripheral circuit region having a decoupling capacitor, the decoupling capacitor including a bottom electrode, a dielectric layer pattern, and a top electrode. The cell array region may include: a first gate; a first contact over the first gate; a second contact over an active region at one side of the first gate; and the first variable resistance element over the second contact, and the peripheral circuit region may include: a second gate formed of the same material at the same level as the first gate; the bottom electrode disposed over the second gate and formed at the same level as the first contact; and the dielectric layer pattern and the top electrode disposed over the bottom electrode.. ... Sk Hynix Inc

04/02/15 / #20150091639

Semiconductor device

A semiconductor device includes conducting lines of a first group and a second group arranged in parallel, a plurality of first internal elements respectively coupled to the conducting lines of the first group and the second group and a plurality of first contact pads arranged between and along the conducting lines of the first group and the second groups, wherein at least a part of the plurality of first contact pads are respectively coupled to control terminals of the plurality of first internal elements, and the part of the plurality of first internal elements receive a plurality of first control signals through corresponding control terminals, respectively.. . ... Sk Hynix Inc

04/02/15 / #20150091619

Semiconductor apparatus

A semiconductor apparatus include a signal level switching decision unit and a transmitter unit. The signal level switching decision unit generates a switching control signal according to off-current of transistors included therein. ... Sk Hynix Inc

04/02/15 / #20150091612

Noise elimination circuit of semiconductor apparatus

A semiconductor apparatus includes a pulse generation unit configured to detect a transition of an input signal and generate a preliminary pulse signal, and an error elimination unit configured to determine error of the preliminary pulse signal and output a signal as a pulse signal.. . ... Sk Hynix Inc

04/02/15 / #20150091611

Impedance calibration circuits

Impedance calibration circuits are provided. The impedance calibration circuit includes an operation control signal generator and an impedance calibrator. ... Sk Hynix Inc

04/02/15 / #20150091541

Internal voltage generation circuit

An internal voltage generation circuit includes a comparison unit suitable for comparing a voltage level of a feedback voltage with that of a reference voltage, and generating a comparison signal and an acceleration voltage, a pull-up driving unit suitable for driving an internal voltage terminal to be pulled up in response to the comparison signal, a discharging unit suitable for discharging the internal voltage terminal in response to the acceleration voltage, and a voltage division unit suitable for dividing a voltage level of the internal voltage terminal, and generating the feedback voltage.. . ... Sk Hynix Inc

04/02/15 / #20150091186

Interconnection structure, semiconductor device, and method of manufacturing the same

A semiconductor device includes a first insulating layer, a second insulating layer formed on the first insulating layer, a plurality of interconnection lines formed in the second insulating layer, and a first air gap disposed between the first insulating layer and the second insulating layer to surround a lower part of the interconnection lines.. . ... Sk Hynix Inc

04/02/15 / #20150091185

Semiconductor device and method for forming the same

A semiconductor device includes: a second conductive layer formed over a first conductive layer; and a dummy conductive layer formed between the first and second conductive layers with through-holes formed therein. The first and second conductive layers include signal lines electrically coupled to each other through signal metal contacts passing through the through-holes, and the second conductive layer includes power lines electrically coupled to the dummy conductive layer through power metal contacts.. ... Sk Hynix Inc

04/02/15 / #20150091184

Semiconductor memory apparatus

A semiconductor memory apparatus includes: a power distribution line disposed over a circumferential portion of a device formation region; a guard ring formed to surround the device formation region outside of the power distribution line; and one or more power reinforcement parts configured to electrically couple an edge part of the power distribution line to the guard ring.. . ... Sk Hynix Inc

04/02/15 / #20150091139

Semiconductor chip and stacked semiconductor package having the same

A semiconductor chip includes a substrate, through-electrodes passing through the substrate, and a dielectric layer formed between the substrate and the through-electrodes and having a dielectric constant decreasing structure.. . ... Sk Hynix Inc

04/02/15 / #20150091135

Semiconductor device

A semiconductor device includes an insulating layer formed on a substrate, and a capacitor including first and second electrodes formed in the insulating layer, wherein a lower surface of the first electrode is formed to have a greater depth than a lower surface of the second electrode in the insulating layer.. . ... Sk Hynix Inc

04/02/15 / #20150091096

Semiconductor memory device

A semiconductor memory device includes a pipe channel layer formed on a semiconductor substrate, a first channel layer, a second channel layer and a third channel layer, connected with the pipe channel layer, first conductive layers stacked while surrounding the first channel layer, second conductive layers stacked while surrounding the second channel layer, and third conductive layers stacked while surrounding the third channel layer, wherein the first to third conductive layers are separately controlled.. . ... Sk Hynix Inc

04/02/15 / #20150091081

Semiconductor device and method for fabricating the same

A semiconductor device includes a semiconductor substrate including a plurality of pillars, a gate electrode formed to surround a lower portion of the pillar and having a top surface lower than a top surface of the pillar, a salicide layer formed to cover the top surface of the pillar and surround an upper portion of the pillar, and an electrode formed to cover a top surface and a lateral surface of the salicide layer.. . ... Sk Hynix Inc

04/02/15 / #20150091070

Semiconductor device with buried bit line and method for fabricating the same

A method for fabricating a semiconductor device includes etching a semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines.. . ... Sk Hynix Inc

04/02/15 / #20150090951

Semiconductor apparatus having vertical channel transistor and method of fabricating the same

A semiconductor apparatus and a method of fabricating the same are provided. The method includes sequentially depositing a gate electrode material and a sacrificial insulating layer on a semiconductor substrate, patterning the gate electrode material and the sacrificial insulating layer to form one or more holes exposing a surface of the semiconductor substrate, forming a gate insulating layer on an inner sidewall of the hole, forming one or more pillar patterns each filled in the hole and recessed on a top thereof, forming a contact unit and an electrode unit on the pillar pattern, removing a patterned sacrificial insulating layer and forming a spacer nitride material on the semiconductor substrate from which the patterned sacrificial insulating layer is removed, and removing portions of the spacer nitride material and a patterned gate electrode material between the pillar patterns.. ... Sk Hynix Inc

04/02/15 / #20150090950

Semiconductor device and method of fabricating the same

A semiconductor device includes a first conductive layer extending in a first direction, a second conductive layer extending in a second direction and disposed over the first conductive layer, the first and second directions being substantially perpendicular to each other, and a variable resistance layer disposed over the first conductive layer, the variable resistance layer extending in the second direction. An upper portion of the variable resistance layer is disposed between lower portions of two neighboring second conductive layers including the second conductive layer.. ... Sk Hynix Inc

04/02/15 / #20150090948

Resistive memory apparatus and manufacturing method thereof

A resistive memory apparatus includes a first electrode formed on a semiconductor substrate, an insulating layer formed on the first electrode and including a hole exposing an upper surface of the first electrode, a data storage unit in which a first resistance-variable material and a second resistance-variable material are alternately formed in the hole at least once, and a second electrode formed on the data storage unit.. . ... Sk Hynix Inc

03/26/15 / #20150089326

Address detection circuit and memory including the same

An address detection circuit comprises first to n-th address storage units suitable for storing an address, first to n-th calculation units each suitable for performing a counting operation when an address is stored in a corresponding address storage unit among the address storage units or the address stored in the corresponding address storage unit is inputted, a control unit suitable for sequentially storing an input address in the address storage units, and storing the input address in a selected address storage unit among the address storage units when of the address storage units each store an address, and a detection unit suitable for detecting an address, which is inputted a reference number of times or more, among the addresses stored in the address storage units, based on outputs of the calculation units.. . ... Sk Hynix Inc

03/26/15 / #20150089323

Error recovery using erasures for nand flash

Error correction decoding is performed on a codeword where the codeword is unable to be successfully decoded. One or more bits in the codeword are selected to be replaced with an erasure. ... Sk Hynix Inc

03/26/15 / #20150089087

Electronic device

A semiconductor memory may include: a first stacked structure including a first word line disposed over a substrate and extended in a first direction, a first bit line disposed over the first word line and extended in a second direction crossing the first direction, and a first variable resistance layer interposed between the first word line and the first bit line; and a second stacked structure including a second bit line disposed over the first stacked structure and extended in the second direction, a second word line disposed over the second bit line and extended in the first direction, and a second variable resistance layer interposed between the second word line and the second bit line; and a first selecting element layer interposed between the first bit line and the second bit line.. . ... Sk Hynix Inc

03/26/15 / #20150087111

3 dimensional semiconductor device and method of manufacturing the same

A 3d semiconductor device and a method of manufacturing the same are provided. The method includes forming a first semiconductor layer including a common source node on a semiconductor substrate, forming a transistor region on the first semiconductor layer, wherein the transistor region includes a horizontal channel region substantially parallel to a surface of the semiconductor substrate, and source and drain regions branched from the horizontal channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, processing the first semiconductor layer to locate the common source node corresponding to the source region, forming a gate in a space between the source region and the drain region, forming heating electrodes on the source region and the drain region, and forming resistance variable material layers on the exposed heating electrodes.. ... Sk Hynix Inc

03/26/15 / #20150085596

Semiconductor devices having multi-channel regions and semiconductor systems including the same

The semiconductor device includes a first channel region suitable for including a first pad region and a first core region and receiving a first power signal through a first power line, a second channel region suitable for including a second pad region and a second core region and receiving the first power signal through a second power line, and a switch unit suitable for electrically disconnecting the second power line from a first power stabilization unit if a predetermined operation of the first channel region is performed and electrically disconnecting the first power line from the first power stabilization unit if the predetermined operation of the second channel region is performed.. . ... Sk Hynix Inc

03/26/15 / #20150085590

Semiconductor devices and semiconductor systems including the same

Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor device. ... Sk Hynix Inc

03/26/15 / #20150085584

Semiconductor memory device and operating method thereof

A semiconductor memory device and an operating method thereof are provided. The semiconductor memory device includes a memory cell array including a plurality of memory groups each including at least a drain-select transistor and a plurality of memory cells, a voltage generator suitable for generating a read voltage that is to be applied to a selected memory cell of the memory cells and a pass voltage that is to be applied to unselected memory cells other than the selected memory cell among the memory cells, and a control logic suitable for controlling the voltage generator to generate the pass voltage to have different levels depending on a distance between the drain-select transistor and the selected memory cell during a read operation.. ... Sk Hynix Inc

03/26/15 / #20150085583

Nonvolatile memory apparatus, program method thereof, and data processing system using the same

A nonvolatile memory apparatus includes: a memory cell area including a plurality of memory cells connected to a word line and a bit line; a program time controller configured to determine a program voltage application time for a selected word line, as the selected word line is selected in response to a program command and an address signal; and a controller configured to apply a program voltage to the selected word line according to the program voltage application time determined by the program time controller.. . ... Sk Hynix Inc

03/26/15 / #20150085582

Programming method of nonvolatile memory device

Provided is a programming method of a nonvolatile memory device which includes a plurality of strings each including a source select transistor, a plurality of memory cells, and a drain select transistor which are connected in series between a common source line and a bit line, the programming method includes: applying a first voltage to the common source line during a first period in which a channel of a plurality of memory cells of an unselected string is floated; and applying a second voltage increased more than the first in voltage to the common source line during a second period in which a selected memory cell is programmed, when a selected word line belongs to a word line group adjacent to the common source line.. . ... Sk Hynix Inc

03/26/15 / #20150085576

Semiconductor memory apparatus

A semiconductor memory apparatus includes a memory block including memory cells coupled between a bit line and a source line and operating in response to voltages applied to word lines, and a peripheral circuit suitable for performing operations relating to data input and output of the memory cells, wherein the peripheral circuit is suitable for applying a precharge voltage to the bit line when word lines adjacent to a selected word line are set to a floating state.. . ... Sk Hynix Inc

03/26/15 / #20150085572

Storage of read thresholds for nand flash storage using linear approximation

A first read threshold associated with a first page in a block and a second read threshold associated with a second page in the block are received, where the first page has a first page number and the second page has a second page number. A slope and a y intercept are determined based at least in part on the first read threshold, the second read threshold, the first page number, and the second page number. ... Sk Hynix Inc

03/26/15 / #20150085564

Memory and memory system including the same

A memory includes a plurality of word lines each coupled to one or more memory cells, an address storage unit suitable for storing an address of a word line selected for access by a control unit among the plurality of word lines at a first time point; and the control unit suitable for sequentially refreshing the plurality of word lines in response to application of a refresh command, refreshing one or more adjacent word lines adjacent to a word line corresponding to the address stored in the address storage unit in response to every nth application of the refresh command where n is a natural number and selecting one or more of the plurality of word lines for access, wherein the first time point is included in time section other than a refresh section in which the control unit refreshes one or more word lines in response to application of the refresh command.. . ... Sk Hynix Inc

03/26/15 / #20150085563

Memory and memory system including the same

A memory includes a plurality of word lines each coupled to one or more memory cells, an address storage unit suitable for storing an address of a word line selected for access by a control unit among the plurality of word lines at a first time point; and the control unit suitable for sequentially refreshing the plurality of word lines in response to application of a refresh command, refreshing one or more adjacent word lines adjacent to a word line corresponding to the address stored in the address storage unit in response to every nth application of the refresh command where n is a natural number and selecting one or more of the plurality of word lines for access, wherein the first time point is included in time section other than a refresh section in which the control unit refreshes one or more word lines in response to application of the refresh command.. . ... Sk Hynix Inc

03/26/15 / #20150085559

Electronic device and method for fabricating the same

According to embodiments, a semiconductor memory may include: a variable resistance pattern disposed over a substrate and extended in a first direction; first and second structures including a plurality of interlayer dielectric layers and a plurality of conductive layers which are alternately stacked over the substrate, and contacted with one side surface and the other side surface of the variable resistance pattern, respectively, wherein the first stacked structure has a line shape extended in a first direction and the second stacked structure has a pillar shape; and a pillar-shaped conductive pattern contacted with one side surface of the second stacked structure, which is not contacted with the variable resistance pattern.. . ... Sk Hynix Inc

03/26/15 / #20150084689

Semiconductor chip including a spare bump and stacked package having the same

A stacked package including: a semiconductor substrate, a circuit layer formed over the semiconductor substrate, a bump formed over the circuit layer, a spare bump formed correspondingly to the bump and over the circuit layer, and configured for replacing the bump with the spare bump, a through electrode configuring to pass through the semiconductor substrate on a same line as the bump and electrically coupled the bump or the spare bump in response to a selection signal, and a spare through electrode configured to pass through the semiconductor substrate on a same line as the spare bump and electrically coupled with the bump or the spare bump in response to a selection signal. When a bump has failed, a vertical input/output line of the semiconductor chips is established by a spare bump corresponding to the failed bump through the selective signal routing.. ... Sk Hynix Inc

03/26/15 / #20150084668

Semiconductor device and semiconductor system including the same

A semiconductor device includes a test control unit suitable for activating an on-die termination signal in response to a control signal activated in a test mode, and a data mask pad suitable for pull-down driving a data mask signal when the on-die termination signal is activated.. . ... Sk Hynix Inc

03/26/15 / #20150084667

Method and system for testing semiconductor device

A method for testing a semiconductor device includes testing the semiconductor device in a plurality of operation modes sequentially, and programming the semiconductor device to operate in at least one of the operation modes when the semiconductor device passes the testing.. . ... Sk Hynix Inc

03/26/15 / #20150084665

Method and system for testing semiconductor device

A method for testing a semiconductor device includes testing the semiconductor device in a plurality of operation modes sequentially, and programming the semiconductor device to operate in at least one of the operation modes when the semiconductor device passes the testing.. . ... Sk Hynix Inc

03/26/15 / #20150084155

Semiconductor device and method of fabricating the same

A method for fabricating a semiconductor device includes defining a curved active region by forming a plurality of trenches over a semiconductor substrate, forming an insulating layer to fill the plurality of trenches, and forming a pair of gate lines crossing the curved active region, so that it is possible to prevent leaning of an active region by forming a curved active region.. . ... Sk Hynix Inc

03/26/15 / #20150084115

Semiconductor device

Provided is a semiconductor device including a plurality of pillar columns, each of the plurality of pillar columns including a plurality of pillars arranged in one direction to be offset from each other, wherein an mth pillar and an (m+1)th pillar, among the plurality of pillars included in each pillar column, are aligned with each other (m is an integer of 0 or more).. . ... Sk Hynix Inc

03/19/15 / #20150079778

Vertical semiconductor device and method of manufacturing the same

A vertical semiconductor device includes a first active pillar vertically protruded from a semiconductor substrate; a first vertical gate connected to at least one side of the first active pillar and formed along a direction that crosses a buried bit line; and a first body line connected to at least one side of the first active pillar which is not connected to the first vertical gate.. . ... Sk Hynix Inc

03/19/15 / #20150079767

Semiconductor device having buried bit lines and method for fabricating the same

A semiconductor device includes semiconductor bodies formed substantially perpendicular to a semiconductor substrate, buried bit lines formed in the semiconductor bodies and including a metal silicide; and barrier layers formed under and over the buried bit lines and containing germanium.. . ... Sk Hynix Inc

03/19/15 / #20150079748

Nonvolatile memory device and method for fabricating the same

This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a lower part buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate; and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers. ... Sk Hynix Inc

03/19/15 / #20150079746

3d non-volatile memory device, memory system including the same, and method of manufacturing the same

A three-dimensional 3d nonvolatile memory device includes vertical channel layers protruding from a substrate; interlayer insulating layers and conductive layer patterns alternately deposited along the vertical channel layers; a barrier metal pattern surrounding each of the conductive layer patterns; a charge blocking layer interposed between the vertical channel layers and the barrier metal patterns; and a diffusion barrier layer interposed between the barrier metal patterns and the charge blocking layer.. . ... Sk Hynix Inc

03/19/15 / #20150079744

Semiconductor device with buried bit line and method for fabricating the same

A semiconductor device includes trenches defined in a substrate, buried bit lines partially filling the trenches, a first source/drain layer filling remaining portions of the trenches on the buried bit lines, stack patterns having a channel layer and a second source/drain layer stacked therein and bonded to the first source/drain layer, wherein the channel layer contacts with the first source/drain layer, and word lines crossing with the buried bit lines and disposed adjacent to sidewalls of the channel layer.. . ... Sk Hynix Inc

03/19/15 / #20150079741

3-d nonvolatile memory device and method of manufacturing the same

A three-dimensional (3-d) nonvolatile memory device includes a support protruded from a surface of a substrate and configured to have an inclined sidewall; channel structures each configured to comprise interlayer insulating layers and channel layers which are alternately stacked over the substrate including the support, bent along the inclined sidewall of the support, wherein each of the channel structures comprises a cell region and a contact region, and the channel layers are exposed in the contact region; select lines formed over the channel structures; and a pillar type channels coupled to respective channel layers at the contact region and penetrating the select lines.. . ... Sk Hynix Inc

03/19/15 / #20150079737

Junctionless semiconductor device having buried gate, apparatus including the same, and method for manufacturing the semiconductor device

A junctionless semiconductor device having a buried gate, a module and system each having the same, and a method for forming the semiconductor device are disclosed. A source, a drain, and a body of a semiconductor device having a buried gate are doped with the same type of impurities, so that the junctionless semiconductor device does not include a pn junction between the source and the body or between the body and the drain. ... Sk Hynix Inc

03/19/15 / #20150078107

Semiconductor memory device and method of operating the same

A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array including cell strings coupled between bit lines and a common source line, each of the cell strings comprising a plurality of memory cells stacked above a substrate. ... Sk Hynix Inc

03/19/15 / #20150078084

Generating read thresholds using gradient descent and without side information

A first bit position of a cell in solid state storage is read where a sorting bit is obtained using the read of the first bit position. A second bit position of the cell is read for a first time, including by setting a first read threshold associated with the second bit position to a first value and setting a second read threshold associated with the second bit position to a second value. ... Sk Hynix Inc

03/19/15 / #20150077595

Signal processing apparatus and method

A signal processing apparatus may comprise: a pixel array where a plurality of pixels for storing data values are arranged; and a noise removing unit suitable for reflecting a data value of an adjacent pixel that is adjacent to a selected pixel, and a gain value depending on a data value of the selected pixel, on the data value of the selected pixel, and outputting the reflected data value of the selected pixel.. . ... Sk Hynix Inc

03/19/15 / #20150077178

Semiconductor device

A semiconductor device is capable of generating an internal voltage having a voltage level that is dependent on an external power supply voltage. The semiconductor device includes an internal voltage generation unit configured to generate a plurality of internal voltages having different voltage levels by using an external power supply voltage, a voltage level detection unit configured to detect a voltage level of the external power supply voltage, and a selection unit configured to selectively output one of the internal voltages in response to a detection result of the voltage level detection unit.. ... Sk Hynix Inc

03/19/15 / #20150077077

Voltage generating apparatus

A voltage generating apparatus according to an embodiment of the present invention includes a voltage regulator determining a pass voltage at a pass node by comparing an output voltage at an output node with a reference voltage, and generating the output voltage by transferring an external power supply voltage to the output node in response to the pass voltage at the pass node, and a voltage stabilizer controlling a first current flowing from the pass node and a second current flowing from the output node in response to the output voltage.. . ... Sk Hynix Inc

03/19/15 / #20150076924

Semiconductor device

This technology provides a semiconductor device capable of controlling an equivalent series resistance (esr) generated from decoupling capacitors. To this end, the semiconductor device may include a plurality of decoupling capacitors electrically coupled between a first wire and a second wire in parallel, and a plurality of switches coupled between common source/drain terminals of two adjacent decoupling capacitors of the plurality of decoupling capacitors and the second wire.. ... Sk Hynix Inc

03/19/15 / #20150076703

Semiconductor memory device having pads

A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. ... Sk Hynix Inc

03/19/15 / #20150076693

Semiconductor device with damascene bit line and method for fabricating the same

A semiconductor device includes a substrate having a plurality of contact surfaces, an interlayer dielectric layer formed over the substrate and having a first open portion which exposes a part of the contact surfaces and a second open portion which exposes the other contact surfaces, a storage node contact (snc) plug filling the first open portion, and a damascene structure filing the second open portion and including a bit line, a spacer formed on both sidewalls of the bit line, a capping layer formed over the bit line and the spacer, and an air gap formed between the bit line and the spacer. The bit line includes a conductive material of which the volume is contracted by a heat treatment to form the air gap.. ... Sk Hynix Inc

03/19/15 / #20150076614

Semiconductor memory device having pads

A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. ... Sk Hynix Inc

03/19/15 / #20150076441

Variable resistance memory device and method of manufacturing the same

A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a multi-layered insulating layer including a plurality of holes formed on a semiconductor substrate, a lower electrode formed in a bottom of each of the holes, a first spacer formed on the lower electrode and a sidewall of each of the holes, a second spacer formed on an upper sidewall of the first spacer, a third spacer formed on a lower sidewall of the first spacer below the second spacer, a variable resistance part that is formed on the lower electrode has a height lower than a height of a top of each hole, and an upper electrode formed on the variable resistance part to be buried in each hole.. ... Sk Hynix Inc

03/12/15 / #20150074494

Self-repair device

A self-repair device includes an are (array rupture electrical fuse) array block configured to store fail addresses; an are control block configured to control a repair operation of fuse sets according to the fail addresses, compare a plurality of the fail addresses, and determine a failed state; and a redundancy block configured to store fuse data of the fail addresses, compare an input address with the fail addresses, and control row and column redundancy operations.. . ... Sk Hynix Inc

03/12/15 / #20150074476

Data storing system and operating method thereof

A data storing system performs a test operation on a memory block on which a read operation is determined to be failed, and determines whether the memory block is or is not a bad block based on a result of the test operation. The data storing system may improve reliability and yield of a device.. ... Sk Hynix Inc

03/12/15 / #20150072518

Bump structures in semiconductor packages and methods of fabricating the same

The bump structure includes a metal pattern disposed on an electrode pad to have a vertical sidewall and a recessed region surrounded by the vertical sidewalls, a metal post including a lower portion inserted into the recessed region and a protruded portion upwardly extending from the lower portion, and a passivation spacer on a sidewall of the metal post. The metal post is electrically connected to the electrode pad.. ... Sk Hynix Inc

03/12/15 / #20150072513

Semiconductor device and method for manufacturing the same

A semiconductor device comprises a bit line formed over a semiconductor substrate. The bit line has an upper portion and a lower portion, and the upper portion is narrower than the lower portion. ... Sk Hynix Inc

03/12/15 / #20150072502

Semiconductor device including buried gate, module and system, and method for manufacturing

An embodiment of the semiconductor device includes a recess formed in an active region, a gate buried in a lower part of the recess, a first capping insulation film formed over the gate, a second capping insulation film formed over the first capping insulation film, and a third capping insulation film formed over the second capping insulation film. In the semiconductor device including the buried gate, mechanical stress caused by a nitride film can be reduced by reducing the volume of a nitride film in a capping insulation film formed over a buried gate, and the ratio of silicon to nitrogen of the nitride film is adjusted, so that mechanical stress is reduced, resulting in improvement of operation characteristics of the semiconductor device.. ... Sk Hynix Inc

03/12/15 / #20150072492

Method for fabricating non-volatile memory device

A method for fabricating a non-volatile memory device includes alternately stacking a plurality of inter-layer dielectric layers and a plurality of sacrificial layers over a substrate, forming at least a channel hole that exposes the substrate by selectively etching the inter-layer dielectric layers and the sacrificial layers, forming a protective layer on sidewalls of the sacrificial layers that are exposed through the channel hole, sequentially forming a memory layer and a channel layer on the sidewalls of the channel hole, forming slit holes that penetrate through the inter-layer dielectric layers and the sacrificial layers on both sides of the channel hole, removing the sacrificial layers that are exposed through the slit holes, removing the protective layer, and forming gate electrodes in space from which the sacrificial layers and the protective layer are removed.. . ... Sk Hynix Inc

03/12/15 / #20150072491

3-dimensional nonvolatile memory device and method of manufacturing the same

The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another.. . ... Sk Hynix Inc

03/12/15 / #20150071047

Data transmission circuit and data transmission / reception system

A data transmission/reception system includes a data transmission circuit and a data reception circuit. The data transmission circuit includes a pattern detection unit configured to detect a pattern of data to be loaded on inner lines among a plurality of transmission lines and generate an inversion signal, and a transmission unit configured to transmit data to the plurality of transmission lines and the inversion signal to an inversion line, and invert some of the data to be loaded on the inner lines in response to the inversion signal. ... Sk Hynix Inc

03/12/15 / #20150071014

Data training device

A data training device includes a training control block configured to activate driving signals for driving a bit line sense amplifier, with a word line deactivated, when a write training operation is performed according to a mode register write command; and the bit line sense amplifier configured to store training data according to the driving signals from the training control block.. . ... Sk Hynix Inc

03/12/15 / #20150071009

Semiconductor device

A semiconductor device includes a data bus inversion (dbi) decision unit suitable for deciding whether a dbi operation mode is performed, based on a read data, and generating a dbi decision signal corresponding to a result of the decision; an output control unit suitable for generating an arrangement control signal in which a delay amount of time for the decision is reflected, in a dbi operation mode; a data synchronization unit suitable for synchronizing the read data with the arrangement control signal and output the synchronized read data and inverted signals of the synchronized read data, in the dbi operation mode; and a data output unit suitable for selectively outputting the synchronized read data and the inverted signals of the synchronized read data, to an external in response to the dbi decision signal, the arrangement control signal and an output control signal, in the dbi operation mode.. . ... Sk Hynix Inc

03/12/15 / #20150070996

Data storage system and method of operating the same

A data storage system and a method of operating the same are provided. The method includes performing a program operation on a first page of the pages of a memory block, deciding, when power is switched on after a sudden power-off is generated while the program operation is performed, whether to skip the program operation on a first erase page of the pages based on a second page on which the program operation is performed subsequent to the first page, and performing the program operation on the second page.. ... Sk Hynix Inc

03/12/15 / #20150070995

Semiconductor memory device and method of operating the same

A semiconductor memory device includes an i/o circuit suitable for inputting and outputting data signals, and a control logic suitable for controlling the i/o circuit. The control logic includes a flip-flop suitable for operating in response to a dock signal, which is irrelevant to the data signals, and feed a first output signal back, a first pulse generation circuit suitable for generating a data output control pulse in response to a second output signal of the flip-flop which is an inverted signal of the first output signal, and a second circuit suitable for generating a strobe signal in response to the second output signal.. ... Sk Hynix Inc

03/12/15 / #20150070988

Semiconductor device, memory system and operating method thereof

There are a semiconductor device including: a plurality of memory blocks including a plurality of pages; peripheral circuits configured to perform a least significant bit read operation and a most significant bit read operation of a selected page included in a selected block; and a control circuit including a least significant bit read-retry table and a most significant bit read-retry table which have a plurality of indexes, and configured to control the peripheral circuits to store an index used when error correction is possible among the least significant bit read-retry table in the least significant bit read operation and perform the most significant bit read operation by first selecting the stored index among the most significant bit read-retry table.. . ... Sk Hynix Inc

03/12/15 / #20150070987

Semiconductor memory device and programming method thereof

A programming method of a semiconductor memory device includes, in an n-th program loop, applying a first program pulse to a first memory cell group, applying a second program pulse to a second memory cell group, and determining first fast cells and first slow cells in the first memory cell group, and in an n+1-th program loop, applying a third program pulse, which is increased by a step voltage from the first program pulse, to the first fast cells in the first memory cell group, and applying a fourth program pulse, which is increased by the step voltage from the second program pulse, to the first slow cells in the first memory cell group and the second memory cell group.. . ... Sk Hynix Inc

03/12/15 / #20150070968

Memory device having a tunnel barrier layer in a memory cell, and electronic device including the same

An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction crossing the first direction, a resistance variable layer interposed between the first lines and the second lines, a tunnel barrier layer interposed between the resistance variable layer and the first lines, and an intermediate electrode layer interposed between the resistance variable layer and the tunnel barrier layer. ... Sk Hynix Inc

03/12/15 / #20150070958

Line layout for semiconductor memory apparatus

Provided is a line layout for a semiconductor memory apparatus, which is a line layout of a line layer formed over a memory region so as to cross the memory region. The line layout includes as unit lines: a data line disposed between a pair of shielding lines; a pair of address line groups disposed at one side of the shielding lines; and a power supply line disposed between the pair of address line groups.. ... Sk Hynix Inc

03/12/15 / #20150070568

Image sensor module and image processing system including the same

An image sensor module has a filler of a low refractive index and thus prevents deterioration of image quality due to a flare and a ghost image. The image sensor module includes an image sensor, a housing covering the image sensor, a filter coupled to the housing and disposed on the image sensor, and a filler filled in between the image sensor and the filter inside the housing and having a refractive index that is less than a refractive index of the filter.. ... Sk Hynix Inc

03/12/15 / #20150070068

Internal voltage generator and method of generating internal voltage

An internal voltage generator includes an internal voltage control unit suitable for generate an enable signal based on a voltage level of an internal voltage, a clock control unit suitable for generate a control clock having a restricted toggling period based on the enable signal and a clock while controlling the toggling number of the control clock, and an internal voltage generation unit suitable for generate the internal voltage based on the control clock.. . ... Sk Hynix Inc

03/12/15 / #20150070053

Internal voltage generation circuits and semiconductor devices including the same

An internal voltage generation circuit including a voltage generator and a detection voltage generator. The voltage generator generates a temperature reference voltage signal whose level depends on an internal temperature, a division reference voltage signal whose level is constant regardless of the internal temperature, and a selection reference voltage signal obtained by detecting a level of an internal voltage signal. ... Sk Hynix Inc

03/12/15 / #20150069616

Semiconductor device and method of manufacturing the same

A semiconductor device includes a substrate on which a plurality of contact regions are defined, a plurality of transistors formed in the plurality of contact regions, a support body formed over the plurality of transistors and including a top surface, portions of which have different heights in the plurality of contact regions, a plurality of stacked structures including a plurality of conductive layers stacked over the support body, slits located between the plurality of stacked structures, first lines coupled to first junctions of the plurality of transistors through the slits, and second lines coupled to second junctions of the plurality of transistors through the slits.. . ... Sk Hynix Inc

03/12/15 / #20150069582

Semiconductor device and method for manufacturing the same

A semiconductor device includes a semiconductor substrate, a plurality of pillars vertically extending from the semiconductor substrate, each pillar including a groove formed in an upper surface thereof, a salicide layer formed to cover the upper surface and a lateral circumference of an upper end of each pillar and a lower electrode formed to cover an upper surface and a lateral surface of the salicide layer.. . ... Sk Hynix Inc

03/12/15 / #20150069509

Semiconductor device

A semiconductor device includes a substrate having a supporting substrate, wherein a first epitaxial layer and a second epitaxial are sequentially stacked, an isolation region including a first buried impurity region of a second conductivity type and a second buried impurity region of the second conductivity type wherein the first buried impurity region is formed from the supporting substrate to the first epitaxial layer, and the second buried impurity region is formed from the first epitaxial layer to the second epitaxial layer and is in contact with an edge of the first buried impurity region, a third buried impurity region of a first conductivity type formed from the first epitaxial layer to the second epitaxial layer, located in the second buried impurity region and overlapped with the first buried impurity region, and a transistor formed over the second epitaxial layer and overlapped with the third buried impurity region.. . ... Sk Hynix Inc

03/12/15 / #20150069508

Semiconductor device

A semiconductor device includes a plurality of epitaxial layers stacked over a supportive substrate, a first buried impurity region formed to share the supportive substrate with a lowermost epitaxial layer among the multiple epitaxial layers, one or more second buried impurity regions formed to be coupled with the first buried impurity region and share an nth epitaxial layer and an (n+1)th epitaxial layer among the multiple epitaxial layers, where n is a natural number, a body region formed in an uppermost epitaxial layer among the multiple epitaxial layers and a deep well formed in the uppermost epitaxial layer to surround the body region and to be coupled with the second buried impurity regions that share the uppermost epitaxial layer.. . ... Sk Hynix Inc

03/12/15 / #20150069486

Non-volatile memory device

A non-volatile memory device includes an isolation layer formed over a substrate to define an active region, a floating gate formed over the substrate, a selection gate formed over the substrate on one side of the floating gate and formed to be adjacent to the floating gate with a first gap from the floating gate, a control plug formed over the isolation layer on the other side of the floating gate and formed to be adjacent to the floating gate with a second gap from the floating gate, and a charge blocking layer formed to gap-fill the first gap and the second gap.. . ... Sk Hynix Inc

03/12/15 / #20150069484

Semiconductor device and method of manufacturing the same

A semiconductor device includes stacked groups each including interlayer insulating patterns and conductive patterns and stacked in at least two tiers, wherein the insulating patterns and the conductive patterns are alternately stacked over a substrate and separated by slits, and a support body including holes and formed between the stacked groups.. . ... Sk Hynix Inc

03/05/15 / #20150067432

Semiconductor apparatus and system including the same

A semiconductor device include: a first reception inductor pad through configured to receive data from a first transmission inductor pad; a second reception inductor pad configured to receive a clock from a second transmission inductor pad; and a data recovery unit configured to generate an output data.. . ... Sk Hynix Inc

03/05/15 / #20150067430

Semiconductor integtrated circuit including test pads

A the semiconductor integrated circuit includes a test input/output port including test pads; an internal input interface configured to generate an internal clock, an internal address, an internal command, internal data and temporary storage data in response to external signals through the test input/output port; and an error detection block configured to determine whether the internal data and the temporary storage data are the same, and output a result through one test pad of the port. The internal input interface includes a data input/output block which generates the internal data and the data input/output block includes a temporary storage part which stores the internal data as the temporary storage data, a data output part which receives the temporary storage data, and a data input part which receives an output of the data output part and outputs it as the internal data.. ... Sk Hynix Inc

03/05/15 / #20150067315

Memory apparatus and computer system including the same

A semiconductor device includes a memory bank, a data line and a data line control unit. The memory bank stores data. ... Sk Hynix Inc

03/05/15 / #20150067274

Memory system

A memory system, including a plurality of stacked slices and a controller electrically coupled to the plurality of slices, includes: the plurality of slices configured to share a command in a preset number unit, wherein a slice performs a data input/output operation; and the controller configured to generate the command and a control signal for selecting slices in the preset number unit from the plurality of slices.. . ... Sk Hynix Inc

03/05/15 / #20150067201

Semiconductor device and method of operating the same

A semiconductor device includes a data storage suitable for storing a training data for a training operation, a data bus inversion (dbi) calculator suitable for calculating dbi information for the training data input from the data storage through global transmission lines, generating a dbi flag signal based on the dbi information and outputting a dbi data, which is the training data inverted according to the dbi flag signal, in response to a dbi signal, a first multiplexer suitable for selectively outputting the training data input from the data storage through the global transmission lines or the dbi data to a first channel in response to a training signal and the dbi signal and a second multiplexer suitable for selectively outputting the training data input from the data storage through the global transmission lines or the dbi flag signal to a second channel.. . ... Sk Hynix Inc

03/05/15 / #20150067193

Semiconductor chips, semiconductor chip packages including the same, and semiconductor systems including the same

Semiconductor chips are provided. The semiconductor chip includes a first data pad, a first data strobe pad and a second data pad sequentially arrayed from a command address pad in a first direction. ... Sk Hynix Inc

03/05/15 / #20150066185

Fail-over system and method for a semiconductor equipment server

A fail-over system and method relates to a fail-over technology of an equipment server managing a semiconductor fabrication equipment server. The fail-over system includes a semiconductor fabrication equipment group including a plurality of semiconductor fabrication equipment and configured to perform semiconductor fabrication processes; an equipment server group including a plurality of equipment servers and configured to control an operation of the semiconductor fabrication equipment group; and a management server configured to detect an error or a faulty operation in at least one equipment server in the equipment server group by communicating with the equipment server group, and execute a fail-over policy for a faulty equipment server in which the faulty operation is detected, wherein executing the fail-over policy includes allocating at least one application running in the faulty equipment server to at least one normal equipment server in which no faulty operation is detected in the equipment server group.. ... Sk Hynix Inc

03/05/15 / #20150064900

Three dimensional semiconductor device including pads

A semiconductor device includes a substrate in which a cell region and a contact region are defined, a pad structure including a plurality of first conductive layers and a plurality of first insulating layers formed alternately with each other in the contact region of the substrate, wherein an end of the pad structure is patterned stepwise, portions of the first conductive layers exposed at the end of the pad structure are defined as a plurality of pad portions, and the plurality of pad portions have a greater thickness than unexposed portions of the plurality of first conductive layers.. . ... Sk Hynix Inc

03/05/15 / #20150064894

Semiconductor memory device and method of fabricating the same

The semiconductor device includes a semiconductor substrate having a first active area defined by a first isolation layer; a gate insulating layer formed on the semiconductor substrate; a first conductive layer formed on the gate insulating layer; a dielectric layer formed on the first conductive layer; at least one first contact hole passing through the dielectric layer; a second conductive layer, formed on the dielectric layer, the second conductive layer filling the at least one first contact hole to contact the first conductive layer; and at least one first contact plug connected to the second conductive layer in the first active area, wherein the at least one first contact plug is offset from the at least one first contact hole to overlap the dielectric layer.. . ... Sk Hynix Inc

03/05/15 / #20150064866

Semiconductor memory device and method of manufacturing the same

The present technology includes a semiconductor memory device, including a channel layer and interlayer insulation layers surrounding the channel layer. The interlayer insulation layers are stacked with a trench interposed therebetween. ... Sk Hynix Inc

03/05/15 / #20150064843

Stacked semiconductor package and method for manufacturing the same

A stacked semiconductor package includes a first semiconductor chip having a first surface and a second surface which faces away from the first surface and including first bonding pads which are formed on the first surface and first through electrodes which pass through the first surface and the second surface; a second semiconductor chip stacked over the second surface of the first semiconductor chip, and including second bonding pads which are formed on a third surface facing the first semiconductor chip and second through electrodes which pass through the third surface and a fourth surface facing away from the third surface and are electrically connected with the first through electrodes; and a molding part formed to substantially cover the stacked first and second semiconductor chips and having openings which expose one end of the first through electrodes disposed on the first surface of the first semiconductor chip.. . ... Sk Hynix Inc

03/05/15 / #20150063053

Semiconductor appratus

A semiconductor apparatus includes a plurality of memory blocks including a plurality of unit memory blocks, respectively, a first area extending in a first direction among areas formed among the plurality of memory blocks, a second area extending in a second direction among the areas formed among the plurality of memory blocks, and a test mode-related circuit block arranged at an edge part of the first area.. . ... Sk Hynix Inc

03/05/15 / #20150063049

Semiconductor device

A semiconductor device includes a memory cell array including a normal memory cell array and a redundancy memory cell array, a normal refresh counter suitable for generating a normal address for performing a refresh operation to the normal memory cell array with a first period during a refresh mode and a redundancy refresh counter suitable for generating a redundancy address for performing a refresh operation to the redundancy memory cell with a second period shorter than the first period.. . ... Sk Hynix Inc

03/05/15 / #20150063047

Semiconductor memory device, method of operating the same and memory system including the same

A semiconductor memory device according to an embodiment of the present invention includes a memory block, a driving circuit performing a program operation on memory cells and a voltage detector generating a detection signal when an external power supply voltage is reduced to less than a reference voltage level. The driving circuit discharges a voltage applied to a drain selection line during the program operation in response to the detection signal.. ... Sk Hynix Inc

03/05/15 / #20150063044

Strobe signal generation device and memory apparatus using the same

A strobe signal generation device includes an enable signal generating section, a buffering section and a strobe signal driving section. The enable signal generation section generates a division enable signal in response a strobe signal. ... Sk Hynix Inc

03/05/15 / #20150062997

Fuse information storage circuit of semiconductor apparatus

A test mode decoder configured to decode a test mode signal inputted a plurality of times and to generate preliminary fuse information, a count latch configured to count the preliminary fuse information in response to a count clock signal and to generate fuse information, and a fuse array block configured to store the fuse information can be included.. . ... Sk Hynix Inc

03/05/15 / #20150061763

Amplification circuit of semiconductor apparatus

An amplification circuit of a semiconductor apparatus includes a first amplification unit configured to amplify a difference between an input voltage and a reference voltage and generate a preliminary amplification signal, a second amplification unit configured to secondarily amplify the preliminary amplification signal and generate an amplification signal, and a compensation unit configured to form an addition current path.. . ... Sk Hynix Inc

03/05/15 / #20150061755

Semiconductor apparatus

A negative voltage pumping unit including a driver configured to receive an external high-voltage and an external voltage and drive and output an oscillator signal, and a capacitor configured to perform a pumping operation and generate a negative voltage; and an internal circuit configured to receive a ground voltage and the voltage of a node.. . ... Sk Hynix Inc

03/05/15 / #20150061725

Semiconductor integrated circuit

A semiconductor integrated circuit includes a test bump pad, a first bump pad coupled to a first through-silicon-via (tsv), a second bump pad coupled to a second tsv, a latching unit, coupled between the test bump pad and the first bump pad, suitable for storing data, and a switching unit suitable for selectively coupling the first bump pad to the second bump pad in response to a test operation control signal.. . ... Sk Hynix Inc

03/05/15 / #20150061721

Semiconductor device and operating method of semiconductor device

A semiconductor device includes a plurality of stacked chips, a reference through silicon via (tsv) set passing through the plurality of stacked chips, a plurality of tsvs passing through the plurality of stacked chips, a reference delay information generation unit suitable for generating a reference delay information indicating an amount of delay of the reference tsv set and a determination unit suitable for determining abnormality of the plurality of tsvs by comparing a first test signal with each of a plurality of second test signals, wherein the first test signal is an initial test signal delayed by an amount of delay corresponding to the reference delay information, and wherein each of the plurality of second test signals is the initial test signal delayed by corresponding one of the plurality of tsvs.. . ... Sk Hynix Inc

03/05/15 / #20150061710

Semiconductor apparatus and test method

A test driver selection unit configured to enable a plurality of test driver selection signals in response to a test pulse and a test clock, and a plurality of drivers configured to receive the plurality of test driver selection signals, wherein each of the plurality of drivers is configured to output an output signal to a data bump in response to a test driver selection signal, data, and an output enable signal, and to receive a first driving voltage and a second driving voltage.. . ... Sk Hynix Inc

03/05/15 / #20150061120

Stack packages and methods of manufacturing the same

Embodiments of a stack package may include an upper chip on a lower chip, a backside passivation layer covering the backside surface of the lower chip and having a thickness which is substantially equal to a height of the protrusion portion of a lower through via electrode, a backside bump substantially contacting the protrusion portion, and a front side bump electrically connected to a chip contact portion of the upper chip and physically and electrically connected to the backside bump. The backside passivation layer may include a first insulation layer provided over a sidewall of the protrusion portion and the backside surface of the lower chip. ... Sk Hynix Inc

03/05/15 / #20150061080

Guard ring structure of semiconductor apparatus

A guard ring structure of a semiconductor apparatus includes a base wiring layer located above a semiconductor substrate, a first guard ring configured as a wiring stacked structure of two or more layers adjacent to the side of the device forming region above the base wiring layer, and a second guard ring configured to be stacked with the same number of layers as the first guard ring and separated from the first guard ring, the second guard ring formed adjacent to the side of a scribe lane above the base wiring layer.. . ... Sk Hynix Inc

03/05/15 / #20150061063

Image sensor and method for fabricating the same

An image sensor may include a substrate having photoelectric conversion regions respectively formed on a plurality of pixels and charge trap regions overlapping with the respective photoelectric conversion regions and having depths or thicknesses that are different, for each of the respective pixel.. . ... Sk Hynix Inc

03/05/15 / #20150061004

Semiconductor device and method for manufacturing the same

A semiconductor device and a method for manufacturing the same are disclosed, in which a buried gate region is formed, a nitride film spacer is formed at sidewalls of the buried gate region, and the spacer is etched in an active region in such a manner that the spacer remains in a device isolation region. Thus, if a void occurs in the device isolation region, the spacer can prevent a short-circuit from occurring between the device isolation region and its neighboring gates.. ... Sk Hynix Inc

03/05/15 / #20150060855

Semiconductor device

A semiconductor device includes a plurality of first pads, a plurality of data input and output units suitable for transmitting a data between a plurality of global lines and the plurality of first pads, respectively, a connection control unit suitable for coupling the plurality of first pads to each other in a test operation period, and a test operation unit suitable for controlling the plurality of data input and output units to transmit a test data in a set order through the plurality of first pads coupled to each other in the test operation period.. . ... Sk Hynix Inc

03/05/15 / #20150060854

Semiconductor device and method of manufacturing the same

A semiconductor device includes a main region suitable for performing a first test operation and a second test operation respectively based on a first test signal and a second test signal in a test mode, a first test region electrically connected to the main region and suitable for generating and transferring the first test signal to the main region in the test mode, and a second test region electrically connected to the main region or the first test region with a scribe lane disposed therebetween and suitable for generating and transferring the second test signal to the main region in the test mode.. . ... Sk Hynix Inc

03/05/15 / #20150060752

Three-dimensional semiconductor device and method of manufacturing the same

A 3d semiconductor device and a method of manufacturing the same are provided. The 3d semiconductor device includes a semiconductor substrate, a common source region formed on the semiconductor substrate and extending in a line shape, an active region formed on the common source region and including a lateral channel region, which is substantially in parallel to a surface of the semiconductor substrate, and source and drain regions that are branched from the lateral channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, and a gate formed in a space between the source region and the drain region.. ... Sk Hynix Inc

02/26/15 / #20150058566

Semiconductor memory apparatus

A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.. . ... Sk Hynix Inc

02/26/15 / #20150056801

Semiconductor device with air gap

A method of fabricating a semiconductor device may include forming isolation structures that include openings, over a substrate; forming sacrificial spacers on sidewalks of the openings; forming, on the sacrificial spacers, first conductive patterns that are recessed in the openings; removing the sacrificial spacers, and defining air gaps; forming a liner layer that caps the first conductive patterns and the air gaps; forming second conductive patterns through silicidation of the liner layer; and forming third conductive patterns over the second conductive patterns.. . ... Sk Hynix Inc

02/26/15 / #20150056779

Semiconductor device and method of manufacturing the same

A semiconductor device includes a semiconductor substrate divided into a cell region and a peripheral circuit region defined in a first direction, wherein the peripheral circuit region is divided into a first region and a second region defined in a second direction substantially orthogonal to the first direction; gate lines formed over the semiconductor substrate in the cell region and arranged in the second direction; and a capacitor including lower electrodes over the semiconductor substrate, a dielectric layer and an upper electrode, wherein the lower electrodes in the first and second regions, separated from each other in the first direction and coupled to each other in the first region, the dielectric layer is formed along surfaces of the lower electrodes in the second region, and the upper electrode is formed over the dielectric layer.. . ... Sk Hynix Inc

02/26/15 / #20150056772

Semiconductor device comprising buried gate and method for fabricating the same

The present invention provides a semiconductor device including a buried gate and a method for fabricating the same, in which the width of a contact plug may not exceed a predetermined width. The method including forming a plurality of trenches over a substrate using the mask pattern, forming a gate insulating film in each of the plurality of trenches, forming a plurality of gate electrodes filling portions of the plurality of trenches, removing an exposed gate insulating film formed over each of the plurality of gate electrodes in each of the plurality of the trenches, forming a plurality of sealing films filling remaining portions of the plurality of trenches, and forming a plurality of contact plugs over the substrate between the trenches.. ... Sk Hynix Inc

02/26/15 / #20150056769

Semiconductor device and method of manufacturing the same

A semiconductor device includes a substrate, and a gate line, located over the substrate, which includes a first conductive layer and one or more second conductive pattern layers located in the first conductive layer. The second conductive pattern layer comprises a metal layer to thus reduce resistance of a gate line.. ... Sk Hynix Inc

02/26/15 / #20150056755

Electronic device packages having bumps and methods of manufacturing the same

An electronic device package includes a bump having a post disposed on a contact portion of a semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post; an interconnection portion having a locking portion that substantially surrounds the enlarged portion and an upper sidewall of the post; and a dielectric layer substantially surrounding the bump and the locking portion to separate the interconnection portion from the semiconductor chip.. . ... Sk Hynix Inc

02/26/15 / #20150056541

Blank masks for extreme ultra violet lithography, methods of fabricating the same, and methods of correcting registration errors thereof

A blank mask includes a substrate having a first surface and a second surface which are opposite to each other. The substrate includes a trench having a predetermined depth from the second surface. ... Sk Hynix Inc

02/26/15 / #20150055423

Semiconductor memory apparatus

A data storage unit configured to generate a data voltage; and a data comparison unit including a first input terminal for receiving the data voltage and a second input terminal for receiving a reference voltage, and being configured to compare the voltage levels of the first and second input terminals are included, wherein the data comparison unit compares the voltage levels of the first and second input terminals.. . ... Sk Hynix Inc

02/26/15 / #20150055422

Semiconductor memory apparatus

A semiconductor memory apparatus includes a driving current control block configured to sense a resistance value of a dummy memory element, and generates a write driver control signal; and a write driving block configured to provide a driving voltage to a memory cell array in response to a write driver enable signal and the write driver control signal.. . ... Sk Hynix Inc

02/26/15 / #20150055421

Semiconductor device

A semiconductor device includes a memory array including memory cells, page buffers suitable for reading data from the memory cells, cache latch circuits suitable for latching read data from the page buffers, and transmitting latched data to data lines in response to a column selection signal, a column selector suitable for outputting the column selection signal to the cache latch circuits through column selection lines in response to a column address, and sense amplifiers suitable for outputting transmitted data of the data lines by sensing voltages of the data lines, in which the cache latch circuits are connected to the column selector and the sense amplifiers through the column selection lines and the data lines, respectively, and have inverse relationship between the column selection lines and the data lines in length.. . ... Sk Hynix Inc

02/26/15 / #20150055399

Reservoir capacitor and semiconductor device including the same

A reservoir capacitor includes a first capacitor group having two or more capacitors, which are serially coupled to each other between a first power voltage supply terminal and a second power voltage supply terminal, a second capacitor group having two or more capacitors, which are serially coupled to each other between a third power voltage supply terminal and a fourth power voltage supply terminal and a connection line suitable for electrically coupling a first coupling node between the capacitors of the first capacitor group to a second coupling node between the capacitors of the second capacitor group.. . ... Sk Hynix Inc

02/26/15 / #20150055397

Electronic device

An electronic device including a semiconductor memory. The semiconductor memory includes a bit line; a source line; a plurality of resistive memory cells among which a selected memory cell forms a current path between the bit line and the source line; a read current supply unit configured to supply read current to the bit line in a read operation; a sense amplifier configured to generate read data in response to a voltage level of the bit line in the read operation; and a variable switch element configured to flow current from the source line to a ground terminal in the read operation, and be decreased in its resistance value as a voltage level of the source line is high.. ... Sk Hynix Inc

02/26/15 / #20150054919

Three-dimensional image sensor module and method of generating three-dimensional image using the same

A 3d image sensor module includes an image sensor including a plurality of color pixels and a plurality of infrared pixels, and a variable filter suitable for selectively filtering visible rays or infrared rays from light, which is incident on the image sensor, in a time-division way.. . ... Sk Hynix Inc

02/26/15 / #20150054558

Phase mixing circuit, and semiconductor apparatus and semiconductor system including the same

A phase mixing circuit includes a first mixing unit configured to mix phases of first and second clocks at a predetermined ratio, and generate a first mixed signal; a second mixing unit configured to mix phases of an inverted signal of the first clock and an inverted signal of the second clock at the predetermined ratio, and generate a second mixed signal; and an output unit configured to generate an output signal based on of the first and second mixed signals.. . ... Sk Hynix Inc

02/26/15 / #20150054171

Semiconductor device and method of manufacturing the same

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate on which a contact region and a cell region are defined, sub-patterns formed in the contact region, on the substrate, and insulating patterns and conductive patterns stacked alternately along the sub-patterns.. ... Sk Hynix Inc

02/26/15 / #20150054169

Stack packages having token ring loops

Stack packages are provided. The stack package includes a substrate having first and second bond fingers and a plurality of semiconductor chips stacked on the substrate. ... Sk Hynix Inc

02/26/15 / #20150054066

Semiconductor devices including vertical transistors, electronic systems including the same and methods of manufacturing the same

The semiconductor device includes word lines on a semiconductor substrate, common gates connected to each of the word lines and vertically disposed in the semiconductor substrate, buried bit lines intersecting the word lines at a non-right angle in a plan view, and a pair of vertical transistors sharing each of the common gates. The pair of vertical transistors is disposed on both sides of one of the word lines. ... Sk Hynix Inc

02/26/15 / #20150054053

Nonvolatile memory device

A nonvolatile memory device includes a tunneling region and an erase region formed over a substrate, a selection gate formed over the substrate to overlap with the tunneling region, a floating gate formed over the substrate to be disposed adjacent to the selection gate with a gap therebetween and to overlap with the tunneling region and the erase region, and a charge blocking layer filling the gap.. . ... Sk Hynix Inc

02/26/15 / #20150054052

3-d non-volatile memory device and method of manufacturing the same

A three dimensional (3-d) non-volatile memory device includes a pipe gate including a first pipe gate, a second pipe gate formed on the first pipe gate, and a first interlayer insulating layer interposed between the first pipe gate and the second pipe gate, word lines alternately stacked with second interlayer insulating layers on the pipe gate, a pipe channel buried within the pipe gate, and memory cell channels coupled to the pipe channel and arranged to pass through the word lines and the second interlayer insulating layers.. . ... Sk Hynix Inc

02/26/15 / #20150053775

Integrated circuit and manufacturing method thereof

An integrated circuit and a manufacturing method thereof are provided. A chip size can be reduced by forming a memory device in which a ferroelectric capacitor region is laminated on a dram. ... Sk Hynix Inc

02/19/15 / #20150052419

Error correction capability improvement in the presence of hard bit errors

A soft output detector is programmed with a first set of parameters. Soft information is generated according to the first set of parameters, including likelihood information that spans a maximum likelihood range. ... Sk Hynix Inc

02/19/15 / #20150052415

Data storage device, operating method thereof and data processing system including the same

A data storage device includes a nonvolatile memory device; and a controller suitable for controlling an operation of the nonvolatile memory device in response to a request from an external device, wherein the controller comprises a victim block setup unit suitable for setting a victim block for performing a merge operation, based on an error count, which is detected when a read operation of the nonvolatile memory device is performed, and for storing information of the victim block.. . ... Sk Hynix Inc

02/19/15 / #20150052408

Generating soft read values which optimize dynamic range

A plurality of bins and a plurality of soft read values are stored in a lookup table where those bins that are either a leftmost bin or a rightmost bin correspond to soft read values having a maximum magnitude. Bin identification information is received for a cell in solid state storage. ... Sk Hynix Inc

02/19/15 / #20150052374

Data storage device and data processing system including the same

A data processing system includes a host device; and a data storage device including an interface unit which is configured to interface with the host device, and configured to store data provided from the host device or provide data to the host device, in response to a request from the host device, wherein the data storage device is configured to interrupt power supply to the interface unit while the host device operates in a power saving mode.. . ... Sk Hynix Inc

02/19/15 / #20150052310

Cache device and control method thereof

A cache device may include a first cache including a first set and a plurality of ways corresponding to the first set, and a second cache including a second set and a plurality of ways corresponding to the second set. The second set is related with the first set depending on a vacancy of the ways of the first set.. ... Sk Hynix Inc

02/19/15 / #20150052302

Electronic device and method for fabricating the same

The disclosed technology provides an electronic device and a fabrication method thereof, in which an etching margin in formation of a variable resistance element is secured and process difficulty is reduced. An electronic device according to an implementation includes a semiconductor memory, the semiconductor memory including: a variable resistance element including a stack of a first magnetic layer, a tunnel barrier layer and a second magnetic layer; a contact plug coupling a top of the variable resistance element and including a magnetism correcting layer; and a conductive line coupled to the variable resistance element through the contact plug including the magnetism correcting layer.. ... Sk Hynix Inc

02/19/15 / #20150052290

Data storage device and operating method thereof

An operating method of a data storage device includes comparing the number of address mapping table segments containing changed address mapping information with a backup reference value, and backing up the address mapping table segments containing the changed address mapping information in response to the comparison result.. . ... Sk Hynix Inc

02/19/15 / #20150050802

Method of manufacturing a nonvolatile memory device

A method of manufacturing a nonvolatile memory device comprises forming a gate insulating layer and a first conductive layer over a semiconductor substrate that defines a first area in which selection lines will be formed and a second area in which word lines will be formed, performing an etch process to lower a height of the first conductive layer in the first area, forming a dielectric layer and a second conductive layer over the first conductive layer with a height that is different from the height of the first conductive layer, and performing a gate patterning process to form the selection lines and the word lines.. . ... Sk Hynix Inc

02/19/15 / #20150050796

Capacitor and register of semiconductor device, memory system including the semiconductor device, and method of manufacturing the semiconductor device

A capacitor of a semiconductor device includes a capacitor structure configured to include electrode layers and dielectric layers alternately stacked, edge regions each stepwise patterned, and a central region disposed between the edge regions, sacrificial layers disposed within the respective electrode layers in the edge regions of the capacitor structure, and support plugs formed in the central region of the capacitor structure and configured to penetrate the electrode layers and the dielectric layers.. . ... Sk Hynix Inc

02/19/15 / #20150050794

Method for fabricating electronic devices having semiconductor memory unit

Devices and method based on disclosed technology include, among others, a method for capable of providing asymmetrical arrangement of hole patterns while improving non-uniformity of an electronic device. Specifically, a method for fabricating hole patterns in one implementation includes forming a mask pattern which is defined with hole patterns of an asymmetrical arrangement with different longitudinal and transverse intervals, over a layer to be etched; and etching the layer to be etched, using the mask pattern as an etch barrier.. ... Sk Hynix Inc

02/19/15 / #20150050790

Semiconductor device and method of manufacturing the same

A semiconductor device includes word lines and interlayer insulating layers alternately stacked, a channel layer penetrating the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding the channel layer, and first charge trap layers surrounding the tunnel insulating layer, interposed between the word lines and the tunnel insulating layer, respectively, and doped with first impurities.. . ... Sk Hynix Inc

02/19/15 / #20150049854

Shift registers

Shift registers are provided. The shift register includes a first clock buffer and a second clock buffer. ... Sk Hynix Inc

02/19/15 / #20150049567

Memory and memory system including the same

A memory includes a first cell block comprising a plurality of first word lines and one or more first redundancy word lines for replacing at least one of the plurality of first word lines; a second cell block comprising a plurality of second word lines and one or more second redundancy word lines for replacing at least one of the plurality of second word lines; and a control unit suitable for sequentially receiving one or more input addresses, during a target refresh section, selecting one of the first cell block and the second cell block and a word line included in the selected cell block in response to a first input address, and activating one or more adjacent word lines adjacent to the selected word line, which is selected based on the first input address, when the selected word line is adjacent to the redundancy word line, wherein the adjacent word lines comprise the redundancy word line.. . ... Sk Hynix Inc

02/19/15 / #20150049566

Memory and memory system including the same

A memory including a first cell block comprising a plurality of first word line groups, and one or more first redundancy word line groups each corresponding to one hit signal of a plurality of hit signals; a second cell block comprising a plurality of second word line groups, and one or more second redundancy word line groups each corresponding to one hit signal of the plurality of hit signals; and a control unit suitable for selecting a cell block and a word line in response to a first input address and refreshing a selected word line based on an input address inputted after the first input address, while refreshing one or more adjacent word lines adjacent to a first selected word line, which is selected by the first input address, in response to the first input address and the hit signals when the first selected word line is adjacent to a redundancy word line, wherein the first input address is first inputted in a target refresh section.. . ... Sk Hynix Inc

02/19/15 / #20150049561

Nonvolatile memory apparatus, and semiconductor system and computer device using the same

A nonvolatile memory apparatus includes a memory cell array including a plurality of sub arrays. A plurality of analog-to-digital converters (adcs) configured to sense sensing voltages outputted from memory cells of the plurality of sub arrays and a path selection unit configured to electrically couple the plurality of sub arrays with the plurality of adcs in one-to-one correspondence in a first operation mode, and electrically couple the plurality of adcs with a terminal of a power supply voltage in a second operation mode.. ... Sk Hynix Inc

02/19/15 / #20150049559

Semiconductor devices, semiconductor systems including the same, and methods of inputting data into the same

Semiconductor systems are provided. The semiconductor system includes a first semiconductor device and a second semiconductor device. ... Sk Hynix Inc

02/19/15 / #20150049552

Data storage device

A data storage device includes a nonvolatile memory device; and a controller electrically coupled with the nonvolatile memory device, and configured to control an operation of the nonvolatile memory device, wherein the controller is configured to change a frequency of an internal clock and a level of an internal voltage, according to whether data is being transmitted through a channel.. . ... Sk Hynix Inc

02/19/15 / #20150049544

Semiconductor memory device

A semiconductor memory device includes at least one cell string to include a plurality of dummy memory cells and a plurality of memory cells connected in series between the plurality of dummy memory cells; and the peripheral circuit to control the at least one cell string so that a first type of data represented by a first number of bits is stored in at least one of the dummy memory cells and a second type of data represented by a second number of bits, the second number smaller than the first number, is stored in at least two of the plurality of memory cells.. . ... Sk Hynix Inc

02/19/15 / #20150049537

Electronic device and method for fabricating the same

An electronic device includes a semiconductor device that includes: a substrate including a switching element having a buried gate electrode; a buried decoupling capacitor having a line width same as a line width of the buried gate electrode; and a variable resistance element, electrically coupled to the switching element, formed over the substrate.. . ... Sk Hynix Inc

02/19/15 / #20150049536

Electronic device

Provided an electronic device including a semiconductor memory unit. The semiconductor memory unit includes: a plurality of storage cells each including a variable resistance element of which resistance is changed in response to a current flowing across the variable resistance element and a selecting element coupled to one end of the variable resistance element; a plurality of word lines corresponding to the respective storage cells and each coupled to a selecting element of a corresponding storage cell; a first line coupled to one ends of the plurality of storage cells; a second line coupled to the other ends of the plurality of storage cells; a voltage adjuster configured to adjust the voltage levels of back bias voltages of the selecting elements of the plurality of storage cells; and an access control unit electrically coupled to the first and second lines and passing an access current to a selected storage cell among the plurality of storage cells.. ... Sk Hynix Inc

02/19/15 / #20150049534

Semiconductor memory device

A semiconductor memory device includes a plurality of first stacked structures including a plurality of first material layers at ends of which first contact regions are defined, a plurality of second stacked structures including a plurality of second material layers, wherein second contact regions are defined at ends of the second material layers and arranged between the first stacked structures so that the first contact regions and the second contact regions overlap each other, and a plurality of lines coupled in common to the first contact regions and the second contact regions.. . ... Sk Hynix Inc

02/19/15 / #20150048957

Data input/output device and system including the same

A data input/output (i/o) device includes a plurality of data units and an i/o assembly. The plurality of data units is coupled to a global i/o (gio) line through corresponding local i/o (lio) lines and configured to receive or transmit a plurality of data groups through the corresponding lio lines. ... Sk Hynix Inc

02/19/15 / #20150048870

Semiconductor device, semiconductor system including the same, and method for operating the same

A semiconductor device may include first to fourth output lines, an input signal latch unit suitable for latching first to fourth input signals that are sequentially inputted in response to first to fourth clocks having sequential phases, respectively, a valid signal latch unit suitable for latching a valid signal in response to one clock among the first to fourth clocks, where the valid signal corresponds to one input signal among the first to fourth input signals and represents whether the corresponding input signal is valid or not, and a signal transfer unit suitable for transferring the latched input signals, which are obtained by latching the input signals in response to the first to fourth clocks, to the first to fourth output lines based on a correspondence relationship that is decided based on a valid signal latch result of the valid signal latch unit.. . ... Sk Hynix Inc

02/19/15 / #20150048519

Semiconductor devices with through via electrodes, methods of fabricaring the same, memory cards including the same, and electronic systems including the same

A semiconductor device includes a via electrode penetrating a substrate and a back-side molding layer covering a back-side surface of the substrate. The back-side molding layer contacts a sidewall of a back-side end portion of the via electrode, which is a portion of the via electrode that protrudes from the back-side surface of the substrate.. ... Sk Hynix Inc

02/19/15 / #20150048435

Semiconductor device

A semiconductor device comprising four semiconductor pillars extending in a direction perpendicular to a substrate, a connection channel formed on the substrate and connected to one ends of the four semiconductor pillars, a source line connected to the other ends of first and second semiconductor pillars adjacent to each other among the four semiconductor pillars, a bit line connected to the other ends of third and fourth semiconductor pillars among the four semiconductor pillars, first to fourth stack structures, which are formed along the first to fourth semiconductor pillars, respectively, between the source and bit lines and the substrate, and each includes a pass word line, at least one word line and a select line which are stacked over the substrate, and a memory layer interposed between the word line and each of the first to fourth semiconductor pillars.. . ... Sk Hynix Inc

02/19/15 / #20150048296

Semiconductor device having fin gate, resistive memory device including the same, and method of manufacturing the same

A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same. The semiconductor device includes an active pillar formed on a semiconductor substrate, the active pillar including an inner region and an outer region surrounding the inner region, and a fin gate overlapping an upper surface and a lateral surface of the active pillar. ... Sk Hynix Inc

02/19/15 / #20150048295

Semiconductor device having fin gate, resistive memory device including the same, and method of manufacturing the same

A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same are provided. The semiconductor device includes an active pillar formed on a semiconductor substrate, and including a first region and a second region surrounding at least one surface of the first region, and a fin gate extending to overlap an upper surface and a lateral surface of the active pillar. ... Sk Hynix Inc

02/19/15 / #20150048294

Variable resistive memory device including vertical channel pmos transistor and method of manufacturing the same

A semiconductor device having a vertical channel, a variable resistive memory device including the same, and a method of manufacturing the same are provided. The semiconductor device having a vertical channel includes a vertical pillar formed on a semiconductor substrate and including an inner portion and an outer portion surrounding the inner portion, junction regions formed in the outer portion of the vertical pillar, and a gate formed to surround the vertical pillar. ... Sk Hynix Inc

02/19/15 / #20150048293

Three-dimensional semiconductor device, variable resistive memory device including the same, and method of manufacturing the same

A three-dimensional semiconductor device, a resistive variable memory device including the same, and a method of manufacturing the same are provided. The 3d semiconductor device includes a source formed of a first semiconductor material, a channel layer formed on the source and formed of the first semiconductor material, a lightly doped drain (ldd) region formed on the channel layer and formed of a second semiconductor material having a higher oxidation rate than that of the first semiconductor material, a drain formed on the ldd region and formed of the first semiconductor material, and a gate insulating layer formed on outer circumferences of the channel layer, the ldd region, and the drain.. ... Sk Hynix Inc

02/19/15 / #20150048292

Semiconductor device having vertical channel, resistive memory device including the same, and method of manufacturing the same

A semiconductor device, a resistive memory device including the same, and a method of manufacturing the same are provided. The semiconductor device includes a pillar extending substantially perpendicular from a semiconductor substrate, the pillar including an inner portion and an outer portion surrounding the inner portion. ... Sk Hynix Inc

02/12/15 / #20150046750

Error detection circuit and data processing apparatus using the same

An error operation unit configured to output an error detection code in response to a plurality of control signals, a plurality of vectors and data, a vector storage unit configured to store the plurality of vectors, and a vector switching unit configured to provide the plurality of vectors to the error operation unit in response to the plurality of control signals are included.. . ... Sk Hynix Inc

02/12/15 / #20150046743

Semiconductor device and system including the same

A semiconductor device includes a plurality of data output circuits suitable for outputting data to outside; an address training driver suitable for generating a plurality of address training data and a control signal; a plurality of data lines suitable for transferring the address training data to the data output circuits; and a self-correction circuit suitable for correcting a delay time of the address training data that reaches the data output circuits from the address training driver through the plurality of data lines, and correcting skew of the data that is outputted from the data output circuits.. . ... Sk Hynix Inc

02/12/15 / #20150046723

Sense-amplifier driving device and semiconductor device including the same

A sense-amplifier driving device includes: a power-supply driving unit configured to respectively provide a first pull-up voltage and a first pull-down voltage to a pull-up power line and a pull-down power line during a first over-driving time section, and provide the first pull-up voltage to the pull-up power line during a second over-driving time section; an over-driving controller configured to provide a second pull-down voltage lower than the first pull-down voltage to the pull-down power line during the second over-driving time section; and a drive-signal generator configured to generate a drive signal activated for the first and second over-driving time sections so as to control driving of the power-supply driving unit.. . ... Sk Hynix Inc

02/12/15 / #20150046722

Driver circuit of semiconductor apparatus

Provided is a driver circuit of a semiconductor apparatus that is capable of operating with improved reliability and consuming less current. The driver circuit comprises a driver configured to generate an internal voltage using a power voltage in response to a control voltage and a controller configured to change the control voltage to a level higher than a level of the power voltage in response to a stand-by mode signal.. ... Sk Hynix Inc

02/12/15 / #20150046666

Memory system

A memory system includes: a memory controller configured to change data to be stored in memory cells according to an address of a weak cell in order to store changed data having a lower program level than a highest program level among a plurality of program levels in peripheral cells adjacent to the weak cell; and a memory device configured to execute a program loop in order to store the changed data in a selected page.. . ... Sk Hynix Inc

02/12/15 / #20150044868

Semiconductor devices including spacers on sidewalls of conductive lines and methods of manufacturing the same

Semiconductor devices are provided that include spacers on sidewalls of conductive lines, as well as methods for manufacturing the same. A method for manufacturing a semiconductor device includes forming bit lines on a semiconductor substrate. ... Sk Hynix Inc

02/12/15 / #20150044836

Nonvolatile memory device and method for fabricating the same

The technology of the present invention relates to a non-volatile memory device and a fabrication method thereof. The non-volatile memory device includes channel layers protruding vertically from a substrate, a plurality of hole-supply layers and a plurality of gate electrodes, which are alternately stacked along the channel layers, and a memory film interposed between the channel layers and the gate electrodes and between the hole-supply layers and the gate electrodes. ... Sk Hynix Inc

02/12/15 / #20150043702

Counting circuit, delay value quantization circuit, and latency control circuit

A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.. . ... Sk Hynix Inc

02/12/15 / #20150043627

Noise detection circuit, delay locked loop and duty cycle corrector including the same

A noise detection circuit includes a first delay unit suitable for delaying a periodic wave to output a delayed periodic wave, a first divider unit suitable for dividing the delayed periodic wave to output a first periodic wave, a second divider unit suitable for dividing the periodic wave to output a divided periodic wave, a second delay unit suitable for delaying the divided periodic wave to output a second periodic wave, and a detection unit suitable for comparing the first periodic wave with the second periodic wave and outputting a noise detection signal.. . ... Sk Hynix Inc

02/12/15 / #20150043622

Transmitting / receiving circuit and transmitting / receiving system including the same

A transmitting/receiving circuit includes a transmitter suitable for transmitting a transmission signal to a channel, a receiver suitable for receiving a signal of the channel, a replica channel configured by replicating the channel, a replica transmitter suitable for transmitting the transmission signal to the replica channel, a replica receiver suitable for receiving a signal of the replica channel, and a restoring unit suitable for synthesizing the signal of the channel, which is received by the receiver, and the signal the replica channel, which is received by the replica receiver, and restoring a reception signal from the signal of the channel.. . ... Sk Hynix Inc

02/12/15 / #20150043297

Active control device and semiconductor device including the same

An active control device and a semiconductor device including the same are disclosed, which can control an active command in response to a pin change of a command address. The active control device includes: a bank decoding unit configured to decode a bank address to output a bank selection signal; an active controller configured to output a first active control signal, a second active control signal, and an active delay signal to control an active operation of a bank in response to the bank selection signal, a first active signal, and a second active signal; an address latch unit configured to latch a row address to output an address delay signal; and an address output unit configured to output an address corresponding to the address delay signal.. ... Sk Hynix Inc

02/12/15 / #20150043294

Memory device, memory system and operating method thereof

A memory device comprises a cell array having a plurality of word lines, an address counting unit suitable for generating a counting address that is changed whenever one or more of the plurality of word lines are refreshed, and a control unit suitable for selecting a word line corresponding to the counting address among the plurality of word lines and refreshing the selected word line within a first period in response to a refresh command during a first operation mode, within a second period that is longer than the first period during a second operation mode, and within a third period that is shorter than the second period in a high frequency section after the second operation mode begins.. . ... Sk Hynix Inc

02/12/15 / #20150043293

Semiconductor memory device

A semiconductor memory device includes a plurality of banks; a counting block suitable for counting the activation number of the respective banks, and selecting a bank of which the activation number is larger than or equal to a given number; and a refresh control block suitable for performing a normal refresh operation on the banks in response to a refresh command, and performing an additional refresh operation n times on the selected bank, n being a positive integer.. . ... Sk Hynix Inc

02/12/15 / #20150043292

Memory, memory system including the same and method for operating memory

A memory may include a plurality of word lines to which one or more memory cells are connected, and a control unit suitable for activating and precharging a first word line that is selected based on an address of a high-activated word line during a target refresh operation while sequentially activating and precharging the plurality of word lines in a refresh operation, wherein the control unit is suitable for writing a test data to one or more first memory cells connected to the first word line during the target refresh operation in a test mode, wherein the high-activated word line is a word line activated over a reference number or a reference frequency, among the plurality of word lines.. . ... Sk Hynix Inc

02/12/15 / #20150043291

Method for testing semiconductor apparatus and test system using the same

This technique may include a semiconductor apparatus configured to perform data read/write operations in a test mode or a normal mode and a tester configured to simultaneously perform a data test and a leakage current test through a write operation using data read by a read operation in the normal mode after writing data into the semiconductor apparatus in the test mode.. . ... Sk Hynix Inc

02/12/15 / #20150043289

Semiconductor memory device

A semiconductor memory device includes a pad configured to receive a first write data from outside of the semiconductor memory device, and a write circuit configured to generate a plurality of second write data which are to be written in memory cells of all banks to be tested in response to a test mode signal, data strobe signals, a write enable signal, and the first write data transferred through the pad.. . ... Sk Hynix Inc

02/12/15 / #20150043288

Semiconductor memory device having fuse cell array

A semiconductor memory device includes a plurality of fuses arranged in an array suitable for storing n number of repair column addresses, each having m bits and corresponding to a repair target memory cell, a fuse selection unit suitable for selecting m fuses corresponding to one of the n number of repair column addresses in the plurality of fuses in response to an active command and an external row address, which are applied from outside, and outputting one of the n number of repair column addresses corresponding to the selected m fuses, and a repair determination unit suitable for determining whether or not a column address applied from the outside corresponds to the repair target memory cell based on the repair column address outputted by the fuse selection unit.. . ... Sk Hynix Inc

02/12/15 / #20150043287

Memory device and memory system including the same

A memory system includes a controller suitable for providing a data to be written on a memory cell array and a control data for indicating whether or not the data has a preset data pattern and a memory device suitable for selectively writing an patterned data or the data provided by the controller on the memory cell array in response to the control data, wherein the patterned data is stored in the memory device and has the preset data pattern.. . ... Sk Hynix Inc

02/12/15 / #20150043286

Semiconductor memory device, memory system including the same and operating method thereof

A semiconductor memory device includes a program and read unit suitable for programming program data in a memory cell array and for reading read data stored in the memory cell array, and a control unit suitable for generating a control signal for controlling the program and read unit in response to a command input from the outside of the semiconductor memory device, in which the control unit controls the program and read unit to read the read data in a state of storing a first bit data of the program data when a read command is input while programming the program data.. . ... Sk Hynix Inc

02/12/15 / #20150043268

Phase change memory device having multi-level and method of driving the same

A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. ... Sk Hynix Inc

02/12/15 / #20150042394

Buffer circuit

A buffer circuit includes a buffering unit suitable for buffering an input signal and outputting an output signal and a feedback control unit suitable for adjusting a slew rate of the input signal in response to the output signal.. . ... Sk Hynix Inc

02/12/15 / #20150042388

Semiconductor memory apparatus

A semiconductor memory apparatus includes an enable signal generation unit configured to be inputted with a plurality of clocks which have different phases, and generate a plurality of enable signals; and a plurality of sampling units configured to output input data as sampling data in response to respective pairs of clocks of the plurality of clocks and respective ones of the plurality of enable signals.. . ... Sk Hynix Inc

02/12/15 / #20150042387

Data recovery circuit and operating method thereof

A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal.. . ... Sk Hynix Inc

02/12/15 / #20150042385

Semiconductor device and semiconductor system including the same

A semiconductor device includes a buffer unit suitable for outputting a first signal of differential input signals as a positive signal, and a second signal of differential input signals as a negative signal in response to a setting signal, and a setting control unit suitable for generating the setting signal based on a level state of the positive signal and the negative signal in response to a reset signal.. . ... Sk Hynix Inc

02/12/15 / #20150042296

Voltage regulator soft start

A linear voltage regulator is disclosed. The linear voltage regulator includes an amplifier. ... Sk Hynix Inc

02/12/15 / #20150041989

Semiconductor appratus and semiconductor system using the same

A semiconductor apparatus includes first and second through vias, a first path setting unit, and a second path setting unit. The first and second through vias connect first and second chips. ... Sk Hynix Inc

02/12/15 / #20150041971

Stacked semiconductor apparatus

A stacked semiconductor apparatus includes a main die, a plurality of slave dies, and a vertical interposer. The vertical interposer is vertically stacked on the main die.. ... Sk Hynix Inc

02/12/15 / #20150041939

Image sensor having lens type color filter and method for fabricating the same

The image sensor includes lens-type color filters having a uniform shape for a plurality of pixels. The image sensor includes a plurality of pixels formed in a substrate, a plurality of color filter housings formed over outer boundaries of the respective pixels, and a plurality of color filters filled in spaces defined by the respective color filter housings, wherein the clock filter housings surround edges of the respective color filters with a given curvature.. ... Sk Hynix Inc

02/12/15 / #20150041903

Semiconductor device and method of manufacturing the same

A semiconductor device includes a plurality of transistors formed over a substrate, a support body including a horizontal portion and protrusions, wherein the horizontal portion covers at least one of the transistors, and the protrusions are formed over the horizontal portion and located between the transistors, and conductive layers and insulating layers alternately stacked over the support body and protruding upwardly along the sidewalls of the protrusions.. . ... Sk Hynix Inc

02/12/15 / #20150041902

Semiconductor apparatus

A semiconductor apparatus includes a first junction region formed over an active region; a gate region formed over the active region to substantially surround the first junction region; a second junction region formed over the active region outside the gate region on a first side of the first junction region; and a third junction region formed over the active region outside the gate region on a second side of the first junction region which is opposite to the first side, wherein the second junction region and the third junction region are disposed such that the gate region exists between the second junction region and the third junction region.. . ... Sk Hynix Inc

02/12/15 / #20150041901

Semiconductor memory device

A semiconductor memory device may include a string including at least one drain select transistor, a plurality of first memory cells, a first connection element, a plurality of second memory cells, a second connection element, a plurality of third memory cells, and at least one source select transistor, wherein the at least one drain select transistor, the plurality of first memory cells, the plurality of second memory cells, the plurality of third memory cells, and the at least one source select transistor connected serially via the first connection element and the second connection element.. . ... Sk Hynix Inc

02/12/15 / #20150041888

Semiconductor device including buried bit line, and electronic device using the same

A semiconductor device includes: an active region defined by a device isolation film, an upper portion of which is divided into a first active pillar and a second active pillar; a first gate formed to proceed between the first active pillar and the second active pillar so as to obliquely cross the active region, and formed to contact the first active pillar; a second gate formed to proceed between the first active pillar and the second active pillar so as to obliquely cross the active region, and formed to cross the second active pillar; a conductive line formed below the first gate and the second gate, and commonly coupled to the first pillar and the second pillar; and an insulation film formed to enclose the conductive line within the active region.. . ... Sk Hynix Inc

02/05/15 / #20150039948

Data storage device and operating method thereof

A data storage device includes: a nonvolatile memory device comprising a plurality of memory blocks, each including a plurality of pages; and a controller suitable for controlling an operation of the nonvolatile memory device in response to a request from an external device, wherein the controller determines whether or not a memory block including damaged pages in which stored data are damaged occurs in the memory blocks, sets a memory block including the damaged pages to an invalid memory block based on the determination result, and regenerates free pages of the memory block set as the invalid memory block into a valid memory block.. . ... Sk Hynix Inc

02/05/15 / #20150039785

Electronic device and method for fabricating the same

An electronic device includes a semiconductor memory. The semiconductor memory includes an odd-numbered layer structure disposed over a substrate and including a plurality of first lines which extend in a first direction; an even-numbered layer structure disposed over the substrate and including a plurality of second lines which extend in a second direction crossing the first direction; and resistance variable layers interposed between the first lines, between the second lines, and between the first lines and the second lines, wherein the odd-numbered layer structure and the even-numbered layer structure are alternately stacked over the substrate.. ... Sk Hynix Inc

02/05/15 / #20150036441

Current generation circuit and semiconductor device having the same

A current generation circuit includes a mirroring circuit suitable for being charged by using a bias voltage, wherein a voltage level of the charged voltage varies corresponding to changes in a voltage level of a power voltage, a comparison circuit suitable for comparing the charged voltage with a feedback voltage, and a current driving circuit suitable for generating a current based on a voltage output from the comparison circuit.. . ... Sk Hynix Inc

02/05/15 / #20150036440

Semiconductor devices and semiconductor systems including the same

Semiconductor devices are provided. The semiconductor device includes a counter configured to output a first internal address signal counted in synchronization with a refresh clock signal during a refresh operation, an address transmitter configured to output a first external signal as a second internal address signal in response to a refresh pulse, and a bank address generator configured to decode the first internal address signal or the second internal address signal in response to a selection signal to generate a bank address signal for accessing a bank.. ... Sk Hynix Inc

02/05/15 / #20150036439

Semiconductor device

A semiconductor device includes a command combination circuit suitable for generating a combined level signal driven in synchronization with a write command and an internal write command; and a column selection circuit suitable for generating a pulse signal which includes a pulse generated at a level transition time of the combined level signal, and a column select signal.. . ... Sk Hynix Inc

02/05/15 / #20150036438

Semiconductor apparatus

A semiconductor apparatus includes an input buffer configured to buffer and output data inputted from a data input/output pad; a data input control unit configured to transfer data outputted from the input buffer; a data output control unit configured to transfer inputted data to an output buffer; the output buffer configured to buffer data outputted from the data output control unit, and output the buffered data to the data input/output pad; a test data input/output unit configured to latch test inputted data inputted and output test latch data or latch an output of the input buffer and output the test latch data; and a test loop control unit configured to transfer data or the test latch data to the data output control unit.. . ... Sk Hynix Inc

02/05/15 / #20150036433

Semiconductor memory device and methods of operating the same

A semiconductor memory device comprises a memory cell array including a plurality of memory blocks each including a plurality of pages, wherein each of the plurality of pages includes at least one flag cell indicating whether data is in a corresponding page, and a peripheral circuit configured to read data of flag cells of a selected memory block in response to an erase request and to omit an erase operation on the selected memory block based on the data of the flag cells.. . ... Sk Hynix Inc

02/05/15 / #20150036429

Semiconductor memory device

A semiconductor memory device includes a memory block including memory strings formed between bit lines and a source line, wherein the bit lines and the source line are formed on a substrate, each of the memory strings includes a superordinate cell string connected between the bit line and pipe transistors formed on the substrate and a subordinate cell string connected between the source line and the pipe transistors, and an operation circuit configured to apply operation voltages to the memory strings to perform a program operation and apply different voltages to the pipe transistors of the memory strings connected to the same bit line in the memory block.. . ... Sk Hynix Inc

02/05/15 / #20150036412

Nonvolatile memory device and semiconductor system using the same

Provided is a nonvolatile memory device including a resistive memory cell and semiconductor system using the same that is capable of setting the reference resistance value using resistance values of a plurality of memory cells. The nonvolatile memory device comprises one or more column lines, two or more row lines, a plurality of memory cells configured to be connected to the column lines and each of the row lines, and a reference resistance setting unit configured to enable a subset or all of the column lines and row lines and to set a reference resistance value.. ... Sk Hynix Inc

02/05/15 / #20150035590

Internal voltage generation circuits

An internal voltage generation circuit including a drive control signal generator and an internal voltage driver. The drive control signal generator generates a drive control signal in response to an active pulse signal and a drive signal. ... Sk Hynix Inc

02/05/15 / #20150035575

Data output circuits

Data output circuits are provided. The data output circuit includes a latch control signal generator and a data output portion. ... Sk Hynix Inc

02/05/15 / #20150035374

Wireless transceiver circuit, wireless power transmission circuit, wireless power reception circuit, and wireless power transmission/reception system including the same

A wireless power transmission/reception system includes a wireless power transmission circuit and a wireless power reception circuit. The wireless power transmission circuit includes an oscillator, a dc-ac converter that converts a direct current to an alternating current and is turned on/off in response to a control signal, a power transmission coil that transmits ac power, a signal reception coil, and a signal receiver that transfers the control signal to the dc-ac converter. ... Sk Hynix Inc

02/05/15 / #20150035050

Semiconductor device with air gap and method for fabricating the same

A semiconductor device includes a plurality of first conductive structures formed over a substrate, second conductive structures each formed between neighboring first conductive structures of the first conductive structures, air gaps each formed between the second conductive structures and the neighboring first conductive structures thereof, third conductive structures each capping a portion of the air gaps, and capping structures each capping the other portion of the air gaps.. . ... Sk Hynix Inc

02/05/15 / #20150035022

Semiconductor device having passing gate and method for fabricating the same

A semiconductor device includes passing gates. In the semiconductor device, a passing gate formed in a device isolation film is vertically positioned at a deeper and lower level than an operation gate formed in an active region defined by the device isolation film such that the passing gate does not overlap with a junction region. ... Sk Hynix Inc

01/29/15 / #20150033095

Buffer management in a turbo equalization system

A plurality of partially-decoded codewords that have been processed at least once by a first and a second error correction decoder is stored. A plurality of metrics associated with how close a corresponding partially-decoded codeword is to being successfully decoded is stored. ... Sk Hynix Inc

01/29/15 / #20150033093

Advance clocking scheme for ecc in storage

A system for clocking a decoder is disclosed. The system includes: a channel front end configured to receive input data, a first clock configured to provide a first clock signal as input to the channel front end, a decoder configured to receive intermediate data associated with the output of the channel front end, and a second clock configured to provide a second clock signal as input to the decoder. ... Sk Hynix Inc

01/29/15 / #20150033089

Semiconductor device

A semiconductor device includes a compression block configured to compare and compress data of a plurality of core array blocks, by a unit of a group; a combination block configured to combine outputs of the compression block and output compression data; and a control block configured to latch the compression data and output latched data, and drive the latched data and the compression data and output resultant data to a first data line and a second data line.. . ... Sk Hynix Inc

01/29/15 / #20150032960

Electronic devices having semiconductor memory units and method of fabricating the same

Electronic devices have a semiconductor memory unit including a magnetization compensation layer in a contact plug. One implementation of the semiconductor memory unit includes a variable resistance element having a stacked structure of a first magnetic layer, a tunnel barrier layer, and a second magnetic layer, and a contact plug arranged in at least one side of the variable resistance element and comprising a magnetization compensation layer. ... Sk Hynix Inc

01/29/15 / #20150031210

Methods of fabricating fine patterns

Methods of forming fine patterns are provided. The method includes reinforcing a hydrophobic property of a hard mask layer using a surface treatment process to form a neutral layer, forming a block co-polymer layer on the neutral layer, and phase-separating the block co-polymer layer into first domains and second domains.. ... Sk Hynix Inc

01/29/15 / #20150031185

Methods of fabricating semiconductor devices and semiconductor devices fabricated thereby

The method includes forming an array of first separation walls on an underlying layer. A block co-polymer (bcp) layer is formed to fill inside regions of the first separation walls and gaps between the first separation walls. ... Sk Hynix Inc

01/29/15 / #20150031180

Vertical channel transistor with self-aligned gate electrode and method for fabricating the same

A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on both sidewalls of the pillars; forming first gate electrodes which cover any one sidewalls of the pillars and shield gate electrodes which cover the other sidewalls of the pillars and have a height lower than the first gate electrodes, over the gate dielectric layer; and forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes.. . ... Sk Hynix Inc

01/29/15 / #20150029805

Semiconductor memory device

A semiconductor memory device includes a plurality of first regions formed in a line-type and extending in a first direction, and a plurality of second regions and a plurality of third regions arranged between adjacent first regions in a zigzag manner.. . ... Sk Hynix Inc

01/29/15 / #20150029792

Semiconductor memory device and method of operating the same

A semiconductor memory device and a method of operating the same are provided. When threshold voltages of memory cells are boosted to use the memory cells as a selection transistor, a threshold voltage of an outermost memory cell may be boosted to the highest level so that a leakage current can be reduced and a channel boosting level can be increased to reduce the influence of program disturbance.. ... Sk Hynix Inc

01/29/15 / #20150029779

Electronic device and method for fabricating the same

This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a lower electrode, a variable resistance element over the lower electrode, an upper electrode disposed over the variable resistance element and including metal, and a metal compound layer configured to surround a side of the upper electrode. ... Sk Hynix Inc

01/29/15 / #20150029624

Protection circuit and protection apparatus including the same

A protection circuit includes a high voltage detection unit configured to activate a high voltage detection signal where a first voltage exceeds a predetermined voltage; and a discharge unit coupled with the first voltage in response to the high voltage detection signal, and configured to discharge the first voltage to a ground voltage in response to a voltage level acquired by dropping the first voltage.. . ... Sk Hynix Inc

01/29/15 / #20150029368

Dead pixel correction apparatus, image sensor having the same, and operation method of image sensor

A dead pixel correction apparatus includes a storage unit suitable for storing position information of dead pixels obtained from pixel data, a data scanning section suitable for scanning the position information stored in the storage unit, a valid data determination section suitable for determining valid data with respect to the scanned position information, a valid data pre-processing section suitable for pre-processing the determined valid data, and a dead pixel correction section suitable for correcting pixel values corresponding to the dead pixels in current pixel data based on the pre-processed valid data, and outputting the corrected pixel data.. . ... Sk Hynix Inc

01/29/15 / #20150028914

Semiconductor device and method for forming the same

A semiconductor device includes a through silicon via (tsv) formed in a semiconductor substrate including a first-type impurity; and a first doping region formed in the semiconductor substrate located below the tsv. The first doping region is configured to include a second-type impurity and selectively electrically coupled to the tsv.. ... Sk Hynix Inc

01/29/15 / #20150028492

Semiconductor devices having bit line structures disposed in trenches, methods of fabricating the same, packages including same, modules including the same, and systems including the same

Semiconductor devices are provided. The semiconductor device includes a bit line contact plug and a storage node contact plug electrically connected to an active region of a substrate. ... Sk Hynix Inc

01/29/15 / #20150028473

Stack packages and methods of fabricating the same

Stack packages are provided. The stack package includes a first chip and a second chip. ... Sk Hynix Inc

01/29/15 / #20150028472

Stacked package and method for manufacturing the same

The stacked package includes: a substrate having an upper surface formed with connection pads, a lower surface, and four side surfaces; a first semiconductor chip mounted over the upper surface of the substrate; a first adhesive member that covers a portion of the substrate including the first semiconductor chip; and a second semiconductor chip formed with bumps on edges of a first surface and mounted over the substrate with interposition of the first semiconductor chip and the first adhesive member such that a center of the first surface is attached over the first adhesive member and the bumps are bonded onto the connection pads, with a second surface opposing to the first surface being polished evenly.. . ... Sk Hynix Inc

01/29/15 / #20150028453

Semiconductor device and method for forming the same

A semiconductor device in which a gettering layer is formed in a semiconductor substrate, and a method for forming the same are disclosed, resulting in increased reliability of the semiconductor substrate including the gettering layer. The semiconductor device includes a semiconductor substrate; a gettering layer formed of a first-type impurity and a second-type impurity in the semiconductor substrate so as to perform gettering of metal ion; and a deep-well region formed over the gettering layer in the semiconductor substrate.. ... Sk Hynix Inc

01/29/15 / #20150028425

Three dimensional semiconductor device having lateral channel and method of manufacturing the same

A 3d semiconductor device and a method of manufacturing the same are provided. The 3d semiconductor device includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active line including a source region and a drain region formed on the insulating layer, a gate electrode located on a portion of the active line, corresponding to a region between the source region and the drain region, and extending to a direction substantially perpendicular to the active line, and a line-shaped common source node formed to be electrically coupled to the source region and extending substantially in parallel to the gate electrode in a space between gate electrodes.. ... Sk Hynix Inc

01/29/15 / #20150028424

Method for fabricating semiconductor device

A semiconductor device includes a substrate including a first region and a second region, a gate dielectric layer formed on the substrate, and a metal electrode layer formed on the gate dielectric layer and including a compound of carbon and nitrogen, wherein a metal electrode formed from the metal electrode layer in the first region has a work function lower than a work function of a metal electrode formed from the metal electrode layer in the second region and a nitrogen concentration of the metal electrode of the first region is smaller than a nitrogen concentration of the metal electrode of the second region.. . ... Sk Hynix Inc

01/29/15 / #20150028411

Semiconductor device and method for forming the same

A semiconductor device includes a first gate structure formed in a semiconductor substrate; a second gate structure formed over the semiconductor substrate and over the first gate structure; and a bit line formed in the semiconductor substrate, and formed below the first gate structure.. . ... Sk Hynix Inc

01/22/15 / #20150026512

Integrated circuit and memory device

A memory device includes a boot-up control unit configured to control a start of boot-up operation by starting the boot-up operation when an initialization signal is activated, and ignore the initialization signal after a complete signal is activated, a nonvolatile memory unit configured to store repair data, and output the stored repair data during the boot-up operation, a plurality of registers configured to store the repair data outputted from the nonvolatile memory unit, a plurality of memory banks configured to replace a normal cell with a redundant cell, using the repair data stored in the corresponding registers among the plurality of resistors, and a verification unit configured to generate the complete signal to notify that the boot-up operation is completed.. . ... Sk Hynix Inc

01/22/15 / #20150026364

Semiconductor device and memory system having the same

A semiconductor device includes a plurality of bus lines, a plurality of bus bar lines grouped in pairs with the plurality of bus lines, respectively, and a parameter register including a plurality of parameter groups coupled to the plurality of bus lines and a plurality of bus bar lines, wherein the parameter groups store parameters for different operating modes.. . ... Sk Hynix Inc

01/22/15 / #20150024571

Resistive memory device and fabrication method thereof

A resistive memory device capable of implementing a multi-level cell (mlc) and a fabrication method thereof are provided. The resistive memory device includes a lower electrode connected to a switching device and including a first node and a second node formed on a top thereof to be spaced at a fixed interval, a phase-change material pattern formed on the first node and the second node, an upper electrode formed on the phase-change material pattern, a conductive material layer formed on a top and outer sidewall of the upper electrode, a first contact plug formed on one edge of the upper electrode to be connected to the upper electrode and the conductive material layer, and a second contact plug formed on the other edge of the upper electrode to be connected to the upper electrode and the conductive material layer.. ... Sk Hynix Inc

01/22/15 / #20150023119

Semiconductor device and semiconductor system having the same

A semiconductor device includes a column command generation unit suitable for generating a column command delayed by a first delay time from a source command, in response to a first control signal and the source command, a bank address generation unit suitable for generating a bank address delayed by the first delay time from a bank source address, in response to the first control signal and the bank source address, a precharge command generation unit suitable for generating a precharge command delayed by a second delay time from the column command, in response to a second control signal and the column command, and a precharge bank address generation unit suitable for generating a precharge bank address delayed by the second delay time from the bank address, in response to the second control signal and the bank address.. . ... Sk Hynix Inc

01/22/15 / #20150023103

Semiconductor device and method of operating the same

A semiconductor device includes first memory blocks arranged in a longitudinal direction, and including a plurality of strings, wherein the strings are formed along a vertical direction, and the strings adjacent to each other share bit lines or source lines with each other, each string including a drain selection transistor coupled to an odd drain selection line or an even drain selection line, memory cells coupled to word lines, and a source selection transistor coupled to an odd source selection line or an even source selection line, page buffers suitable for storing data, a selection switch unit suitable for transferring the data stored in the page buffers or various voltages supplied from an external source to the bit lines and the source lines; and a control circuit suitable for controlling the page buffers and the selection switch unit.. . ... Sk Hynix Inc

01/22/15 / #20150021604

Cmos image sensor having optical block area

A cmos image sensor includes an active pixel structure suitable for sensing light incident from outside and converting a sensed light into an electrical signal, and an optical block structure suitable for blocking a visible light and passing a uv light to check and evaluate an electrical characteristic of the active pixel area. The uv pass filter includes first and second insulation layers comprising an insulator, and a metal layer formed between the first and second insulation layers.. ... Sk Hynix Inc

01/15/15 / #20150019934

Data storage device, operating method thereof, and data processing system including the same

A data storage device and a method of operating the same. The method of operating the data storage device may include reading a first data group, detecting errors contained in the first data group and correcting the errors of the first data group, if the errors detected from the first data group can be corrected, and estimating a read retry estimation voltage based on error correction data generated based on the step of correcting the errors of the first data group.. ... Sk Hynix Inc

01/15/15 / #20150019926

Manufacturing testing for ldpc codes

An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. ... Sk Hynix Inc

01/15/15 / #20150019904

Data processing system and operating method thereof

Provided is an operating method of a data processing system which includes a data storage device and a host device. The operating method includes reading data at the data storage device based on a request from the host device, and performing an error correction code (ecc) decoding operation on the read data, and performing an additional ecc decoding operation at the host device when the ecc decoding operation performed by the data storage device fails.. ... Sk Hynix Inc

01/15/15 / #20150019886

Integrated circuit, semiconductor memory device, and operating method thereof

An integrated circuit includes an internal circuit including a input/output unit suitable for inputting/outputting data, and a voltage supplying circuit suitable for supplying a first operating voltage to the internal circuit in response to a first control signal during a general operation, and supplying a second operating voltage that is higher than the first operating voltage to the input/output unit in response to a second control signal during an output of the data.. . ... Sk Hynix Inc

01/15/15 / #20150019853

Boot-up method of e-fuse, semiconductor device and semiconductor system including the same

A semiconductor device includes a power-up signal generation unit suitable for receiving a first power supply voltage and a second power supply voltage higher the first power supply voltage and generating a power-up signal when the first and second power supply voltage increase to reach target levels, respectively, a voltage level adjusting unit suitable for generating a third power supply voltage by adjusting a voltage level of the second power supply voltage, a boot-up signal generation unit suitable for generating a boot-up signal in response to the power-up signal, and a circuit operation unit suitable for performing a boot-up operation using the third power supply voltage in response to the boot-up signal.. . ... Sk Hynix Inc

01/15/15 / #20150019832

Semiconductor device and method of operating the same

A semiconductor device includes a pipeline latch unit including a plurality of write pipelines, and suitable for latching data, and a control unit suitable for controlling at least one write pipeline of the write pipelines based on an idle signal.. . ... Sk Hynix Inc

01/15/15 / #20150019796

Data storage device and operating method thereof

An operating method of a data storage device, which includes a first memory area and a second memory area, includes selecting a victim block for securing a free area from the first memory area, calculating a first cost required when a merge operation for the victim block is performed in the first memory area, calculating a second cost required when the merge operation for the victim block is performed in the second memory area, and performing the merge operation in the first memory area or the second memory area based on the first and second costs.. . ... Sk Hynix Inc

01/15/15 / #20150019794

Data storage device and operating method thereof

A data storage device and a method of operating the same. The data storage device includes a nonvolatile memory device and a working memory device. ... Sk Hynix Inc

01/15/15 / #20150019791

Control circuit of semiconductor device and semiconductor memory device

A control circuit includes a rom suitable for generating rom data based on a rom address corresponding to a predetermined operation, a command analyzing unit suitable for outputting the rom address corresponding to the predetermined operation, generating an address storing signal in response to an operation suspension command for suspending the predetermined operation, and generating an address output signal in response to an operation resumption command for resuming the predetermined operation, an address storing unit suitable for storing a rom address, which corresponds to the rom address at a time point where the predetermined operation is suspended, in response to the address storing signal, and an address output unit suitable for outputting the rom address corresponding to said time point in response to the address output signal, wherein the rom generates rom data for resuming the predetermined operation based on the rom address corresponding to said time point.. . ... Sk Hynix Inc

01/15/15 / #20150019767

Semiconductor memory device having data compression test circuit

A semiconductor memory device includes a data transmission unit configured to transmit first input data to only a first global line driver or to the first global line driver and a second global line driver in response to a test signal, and a transmission element configured to transmit second input data only to the second global line driver in response to the test signal.. . ... Sk Hynix Inc

01/15/15 / #20150019610

Full adder circuit

A full adder circuit includes a first logical operation unit suitable for outputting an inverse of the second input signal and a first output signal corresponding to either a second input signal or the inverse of the second input signal in response to a first input signal, a second logical operation unit suitable for outputting an inverse of the first output signal and a sum signal corresponding to either the first output signal or the inverse of the first output signal in response to a carry input signal, and a third logical operation unit suitable for outputting a carry output signal in response to the inverse of the second input signal, the first output signal, the inverse of the first output signal, and the sum signal.. . ... Sk Hynix Inc

01/15/15 / #20150017779

Semiconductor device having stacked storage nodes of capacitors in cell region separated from peripheral region

Methods of fabricating a semiconductor device are provided. The method includes forming a first mold layer on a in a cell region and a peripheral region, forming first storage nodes penetrating the first mold layer in the cell region and a first contact penetrating the first mold layer in the peripheral region, forming a second mold layer on the first mold layer, forming second storage nodes that penetrate the second mold layer to be connected to respective ones of the first storage nodes, removing the second mold layer in the cell and peripheral regions and the first mold layer in the cell region to leave the first mold layer in the peripheral region, and forming a second contact that penetrates a first interlayer insulation layer to be connected to the first contact. ... Sk Hynix Inc

01/15/15 / #20150017773

Semiconductor device and method for manufacturing the same

In the semiconductor device, a line-type buried gate is formed by burying a non-operating gate (isolation gate) with a polysilicon material to reduce a work function and a gate induced drain leakage (gidl) caused by the non-operating gate, resulting in improvement of refresh characteristics of the semiconductor device. Operating gates including a metal conductive material may be formed in a separate step.. ... Sk Hynix Inc

01/15/15 / #20150017771

3d non-volatile memory device and method of manufacturing the same

A 3d non-volatile memory device includes a pipe gate, at least one first channel layer including a first pipe channel layer formed in the pipe gate and a pair of first source side channel layer and first drain side channel layer connected to the first pipe channel layer, and at least one second channel layer including a second pipe channel layer formed in the pipe gate and positioned over the first pipe channel layer and a pair of second source side channel layer and second drain side channel layer connected to the second pipe channel layer.. . ... Sk Hynix Inc

01/15/15 / #20150017770

3-d non-volatile memory device and method of manufacturing the same

A three dimensional (3-d) non-volatile memory device includes a pipe gate including a first pipe gate, a second pipe gate formed on the first pipe gate, and a first interlayer insulating layer interposed between the first pipe gate and the second pipe gate, word lines alternately stacked with second interlayer insulating layers on the pipe gate, a pipe channel buried within the pipe gate, and memory cell channels coupled to the pipe channel and arranged to pass through the word lines and the second interlayer insulating layers.. . ... Sk Hynix Inc

01/15/15 / #20150017769

Vertical semiconductor device, module and system each including the same, and method for manufacturing the vertical semiconductor device

A vertical semiconductor device having a vertical channel region is disclosed. The vertical semiconductor device includes a pillar having a vertical channel region, a bit line buried in a semiconductor substrate located at a lower part of the pillar, and a body connection unit configured to couple at least one sidewall of the pillar to the semiconductor substrate. ... Sk Hynix Inc

01/15/15 / #20150016201

Semiconductor device

A semiconductor device includes first and second bank groups coupled to first and second data lines which are electrically isolated from each other. The semiconductor device includes a register unit suitable for providing predetermined data to the second data line in a specific mode, a data transfer and output unit suitable for externally outputting the predetermined data loaded onto the second data line and simultaneously transferring the predetermined data to the first data line in the specific mode, and a data output unit suitable for externally outputting the predetermined data loaded onto the first data line in the specific mode.. ... Sk Hynix Inc

01/15/15 / #20150016196

Data input circuit

A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated. ... Sk Hynix Inc

01/15/15 / #20150016194

Semiconductor memory device and memory system including the same

A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device includes a first memory unit and a plurality of second memory unit, each including a plurality of memory cells and page buffers corresponding to the memory cells, and a redundancy memory unit including a plurality of redundancy memory cells and a plurality of redundancy page buffers corresponding to the redundancy memory cells. ... Sk Hynix Inc

01/15/15 / #20150016189

Semiconductor memory device and method of operating the same

Disclosed are a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell block including a plurality of memory cells, a voltage providing unit suitable for providing a pass voltage or a read voltage to word lines coupled with the memory cells and a control circuit suitable for controlling the voltage providing unit to adjust a pass voltage applied to the memory cells disposed at one side of a selected memory cell and a pass voltage applied to the memory cells disposed at the other side of the selected memory cell based on an address of a word line of the selected memory cell among the memory cells during a read operation or a verification operation.. ... Sk Hynix Inc

01/15/15 / #20150015310

Clock delay detecting circuit and semiconductor apparatus using the same

Provided is a clock delay detecting circuit and semiconductor apparatus using the same that is capable of generating a period signal whose period is a delay time of a clock, dividing the period signal, and counting the divided period signal. The clock delay detection circuit comprises a period signal generating unit configured to generate a counting control signal, a period signal dividing unit configured to generate a counting enable signal by dividing the counting control signal, and a counting unit configured to generate a delay information signal by counting the counting enable signal with a clock, wherein the counting control signal has a period with a predetermined time.. ... Sk Hynix Inc

01/15/15 / #20150014763

Semiconductor memory device and method of manufacturing the same

A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film; a gate electrode filled in the active region; a bit line contact structure coupled to an active region between the gate electrodes; and a line-type bit line electrode formed over the bitline contact structure. The bit line contact structure includes a bit line contact formed over the active region; and an ohmic contact layer formed over the bit line contact.. A semiconductor memory device and a method of manufacturing the same are provided. The device includes interlayer insulating patterns and conductive patterns stacked alternately, vertical channel layers formed through the interlayer insulating patterns and the conductive patterns, a tunnel insulating layer formed to surround sidewalls of each of the vertical channel layers, and a multifunctional layer formed to surround the tunnel insulating layer. ... Sk Hynix Inc

01/15/15 / #20150014759

Semiconductor device with air gap and method for fabricating the same

A semiconductor device includes a dielectric structure which has an opening exposing a surface of a substrate; and a conductive structure which is formed in the opening, wherein the conductive structure comprises: a first conductive pattern recessed in the opening; a second conductive pattern covering a top surface and sidewalls of the first conductive pattern; an air gap defined between sidewalls of the opening and the second conductive pattern; and a third conductive pattern capping the second conductive pattern and the air gap.. . ... Sk Hynix Inc