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Sk Hynix Inc patents (2016 archive)


Recent patent applications related to Sk Hynix Inc. Sk Hynix Inc is listed as an Agent/Assignee. Note: Sk Hynix Inc may have other listings under different names/spellings. We're not affiliated with Sk Hynix Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Sk Hynix Inc-related inventors


Magnetoresistive element

According to one embodiment, there is provided a magnetoresistive element, including a first magnetic layer, a nonmagnetic layer on the first magnetic layer, and a second magnetic layer on the nonmagnetic layer, wherein one of the first and second magnetic layers include one of co and fe, and a material having a higher standard electrode potential than co and fe.. . ... Sk Hynix Inc

Semiconductor device having air gap and method for manufacturing the same, memory cell having the same and electronic device having the same

A method for fabricating a semiconductor device may include: forming a plurality of first isolation trenches and a plurality of line-shaped active regions by etching a semiconductor substrate; forming a line-shaped device isolation region in each of the plurality of first isolation trenches; forming a plurality of second isolation trenches extending in a second direction by etching the plurality of line-shaped active regions and the plurality of line-shaped device isolation regions; forming a connection trench to connect the plurality of second isolation trenches to each other; forming a shielding line in each of the plurality of second isolation trenches; and forming a shielding line interconnection in the connection trench.. . ... Sk Hynix Inc

Magnetic memory and method of manufacturing magnetic memory

According to one embodiment, a magnetic memory includes a first metal layer including a first metal, a second metal layer on the first metal layer, the second metal layer including a second metal which is more easily oxidized than the first metal, the second metal layer having a first sidewall portion which contacts the first metal layer, and the second metal layer having a second sidewall portion above the first sidewall portion, the second sidewall portion which steps back from the first sidewall portion, a magnetoresistive element on the second metal layer, a third metal layer on the magnetoresistive element, and a first material which contacts a sidewall portion of the magnetoresistive element and the second sidewall portion of the second metal layer, the first material including an oxide of the second metal.. . ... Sk Hynix Inc

Semiconductor device and method of manufacturing the same

A semiconductor device may include pipe channel layer, and a pipe gate surrounding the pipe channel layer. The semiconductor device may include an oxidization layer formed between the pipe gate and the pipe channel layer. ... Sk Hynix Inc

Semiconductor package including a step type substrate

Disclosed herein are semiconductor packages. A semiconductor package may include a substrate configured to include a first face and a second face opposite the first face and to have a recess formed in the first face. ... Sk Hynix Inc

Semiconductor packages including interposer and methods of manufacturing the same

A semiconductor package may include a semiconductor die mounted on a first surface of an interposer die so that a die connection portion of the semiconductor die faces to the first surface of the interposer die, a protection portion may be disposed on the first surface of the interposer die to cover the semiconductor die, and an interconnection structure disposed in and on the interposer die. The interconnection structure may include an external connection portion that is located on a second surface of the interposer die opposite to the semiconductor die, a through electrode portion that penetrates the interposer die to have an end portion combined with the die connection portion, and an extension portion that connects the through electrode portion to the external connection portion. ... Sk Hynix Inc

Memory system performing status read operation and method of operating the same

A method of operating a controller includes, determining whether an address corresponding to a program operation indicates a lower page or an upper page; waiting for a first waiting time for the program operation to the lower page when the address indicates the lower page; waiting for a second waiting time for the program operation to the upper page when the address indicates the upper page, wherein the second waiting time is longer than the first waiting time; and performing a status read operation on the semiconductor memory device after one of the first waiting time or the second waiting time.. . ... Sk Hynix Inc

Controller, semiconductor memory system and operating method thereof

An operating method of a controller includes generating error reliability of data based on reliability information of one or more error-corrected bits of the data, wherein the data is read out from a semiconductor memory device and a hard decision ecc decoding to the data through a bch code is determined as successful; and determining miscorrection of the data based on the error reliability.. . ... Sk Hynix Inc

Controller, semiconductor memory system and operating method thereof

An operating method of a controller includes: a first step of generating an internal codeword including an ecc unit data and an internal parity code by performing ecc decoding operation to an input data; a second step of updating an external parity code based on the ecc unit data, which is included in the internal codeword currently generated, and the ecc unit data, which is included in the internal codeword previously generated; and a third step of storing in a semiconductor memory device one or more internal codewords and the updated external parity code, which are generated through repetition of the first and second steps, by a unit of predetermined storage size.. . ... Sk Hynix Inc

Controller controlling semiconductor memory device and operating method thereof

An operating method for controlling a semiconductor memory device according to an embodiment may include storing read commands in a command queue managed on first-in first-out basis; providing one of the read commands to the semiconductor memory device; determining whether the provided read command passes or fails based on read data, which is provided from the semiconductor memory device in response to the provided read command; and aborting remaining read commands in the command queue when the provided read command passes.. . ... Sk Hynix Inc

Memory system and method of operating the same

A memory system includes a semiconductor memory device including a plurality of ways suitable for storing normal data and reading stored data, and a system way suitable for storing system data, and a controller suitable for controlling the semiconductor memory device to perform overall operations of the plurality of ways and an update operation of the system data of the system way.. . ... Sk Hynix Inc

Enhanced chip-kill schemes by using ecc syndrome pattern

Memory systems may include a memory storage, and a controller suitable for receiving a plurality of codewords, determining whether each codeword is decodable, estimating a location of an error in a codeword determined to be undecodable by calculating a syndrome of the undecodable codeword when at least two codewords of the plurality of codewords are determined to be undecodable, performing error recovery on the undecodable codewords, and hard decoding the plurality of codewords including the error recovered codewords.. . ... Sk Hynix Inc

Enhanced chip-kill schemes by using sub-trunk crc

Memory systems may include a memory storage, and a controller suitable for, receiving a plurality of codewords, each codeword including a user bits portion divided into a number of sub-trunks, determining whether a codeword in the plurality of codewords is decidable, identifying a location of an erroneous sub-trunk in a codeword determined to be undecodable, and recovering the erroneous sub-trunk by summing sub-trunks of other codewords that have a location in their respective codewords that is the same as the location of the erroneous sub-trunk.. . ... Sk Hynix Inc

Semiconductor device

A semiconductor device may include a first channel provided in a first die. The semiconductor device may include a second channel provided in a second die and disposed adjacent to the first channel, and configured to exchange signals and data with the first channel. ... Sk Hynix Inc

12/22/16 / #20160373096

Semiconductor device including delay circuit and operating method thereof

A semiconductor device includes a calibration code generation circuit suitable for generating a calibration code by adjusting a period of a short-term oscillation signal oscillating at a period less than a reference period, based on a reference oscillation signal oscillating at the reference period; and a delay circuit suitable for setting a delay value based on the calibration code.. . ... Sk Hynix Inc

12/22/16 / #20160373066

Differential amplifier circuit

A differential amplification circuit may include a differential amplification unit including a first input transistor and a second input transistor, and suitable for differentially amplifying input signals inputted through the first and second input transistors; a first input control section suitable for turning off the first input transistor when the differential amplification circuit is disabled and transferring a first input signal to the first input transistor when the differential amplification circuit is enabled; and a second input control section suitable for turning off the second input transistor when the differential amplification circuit is disabled and transferring a second input signal to the second input transistor when the differential amplification circuit is enabled.. . ... Sk Hynix Inc

12/22/16 / #20160372595

Semiconductor substrate and fabrication method thereof, and semiconductor apparatus using the same and fabrication method thereof

A semiconductor substrate and a fabrication method thereof, and a semiconductor apparatus using the same and a fabrication method thereof are provided. The semiconductor substrate includes a semiconductor wafer, a silicon germanium (sige)-based impurity doping region formed on the semiconductor wafer, and a protection layer formed on the sige-based impurity doping region.. ... Sk Hynix Inc

12/22/16 / #20160372519

Method of manufacturing a semiconductor integrated circuit device including a transistor with a vertical channel

In a method of manufacturing a semiconductor integrated circuit device, a pillar may be formed on a semiconductor substrate. A hard mask pattern may be formed on a top surface and a portion of a sidewall of the pillar. ... Sk Hynix Inc

12/22/16 / #20160372437

Semiconductor package

A semiconductor package including a first metal layer configured for use as a bonding pad, a second metal layer formed over the first metal layer, and the second metal layer having a separation allowing for the second metal layer to be positioned above distal ends of the first metal layer. The semiconductor package also including a third metal layer formed over the second metal layer, and the third metal layer having a separation allowing for the third metal layer to be positioned above distal ends of the first metal layer, a trench defined by the separation of the third metal layer and second metal layer, and extending through the third metal layer and the second metal layer to expose the first metal layer, and a bonding ball located within the trench.. ... Sk Hynix Inc

12/22/16 / #20160372214

Self repair device and method thereof

A self repair device may include: an electrical fuse array configured to store bit information of a failed address in a fuse; an electrical fuse controller configured to store a row address or column address corresponding to a failed bit when a failure occurs, generate a repair address by comparing a failed address inputted during a test to the address stored therein, output a rupture enable signal for controlling a rupture operation of the electrical fuse array, and output row fuse set data or column fuse set data in response to the failed address; and a row/column redundancy unit configured to perform a row redundancy or column redundancy operation in response to the row fuse set data or the column fuse set data applied from the electrical fuse array.. . ... Sk Hynix Inc

12/22/16 / #20160372208

Read disturb reclaim policy

Memory systems may include a memory including a plurality of memory blocks and a controller. The controller calculates an effective read disturb based on both a direct neighbor read disturb count and a non-direct neighbor read disturb count. ... Sk Hynix Inc

12/22/16 / #20160372204

Semiconductor device and operating method thereof

Disclosed are a semiconductor device and an operating method thereof. The semiconductor device includes a plurality of memory blocks including cell strings coupled between bit lines and a source line, a peripheral circuit configured to perform an erase operation on a selected memory block among the plurality of memory blocks; and a control circuit configured to control the peripheral circuit, so that when an erase command is received, local word lines coupled to a non-selected memory block among the plurality of memory blocks are pulled to ground, the local word lines coupled to the non-selected memory block float after a pre-erase voltage lower than an erase voltage is applied to the source line, and the erase operation of the selected memory block is performed by applying the erase voltage to the source line.. ... Sk Hynix Inc

12/22/16 / #20160372186

Nonvolatile memory system and operating method thereof

A nonvolatile memory system includes a nonvolatile memory device including a nonvolatile memory device including a multi-level cell which stores m-bit data, m being an integer equal to or greater than 3, at a time and m number of latches for respectively storing m-bit data on a single bit basis; and a controller suitable for sequentially latching m-bit data of the multi-level cell into the m number of latches, respectively, during a first half read period, and sequentially outputting the latched m-bit data in the m number of latches during a second half read period.. . ... Sk Hynix Inc

12/22/16 / #20160372178

Semiconductor devices and semiconductor systems including the same

A semiconductor system includes a controller and a semiconductor device. The controller outputs pre-order address signals, post-order address signals, and an update signal including pulses periodically generated. ... Sk Hynix Inc

12/22/16 / #20160372176

Sense amplifier driving device

A sense amplifier driving device, and more particularly, a technology for improving the post overdriving operation characteristic of a semiconductor device. A sense amplifier driving device includes a driving signal generation block configured to compare a reference voltage set by a voltage trimming signal and a level of a power supply voltage, and generate a pull-up driving signal for controlling an operation of a sense amplifier; and a sense amplifier driving block configured to supply a driving voltage to a pull-up power line of the sense amplifier for an active operation period in correspondence to the pull-up driving signal, the driving signal generation block including a voltage divider configured to divide the power supply voltage, and output a divided voltage; and a voltage comparison section configured to compare the reference voltage and the divided voltage, and output a control signal for controlling an overdriving operation of the sense amplifier.. ... Sk Hynix Inc

12/22/16 / #20160372175

Multi-chip package and operating method thereof

A multi-chip package includes a plurality of semiconductor devices each having an address which is designated based on unique values corresponding to the respective semiconductor devices; and a controller suitable for activating each of the semiconductor devices based on the address, and controlling the activated semiconductor device to perform a normal operation.. . ... Sk Hynix Inc

12/22/16 / #20160372173

Semiconductor devices and semiconductor systems including the same

A semiconductor device may include a buffer control signal generation circuit, an input control signal generation circuit and an internal data generation circuit. The buffer control signal generation circuit may be configured to generate a buffer control signal. ... Sk Hynix Inc

12/22/16 / #20160372172

Semiconductor memory apparatus

A semiconductor memory apparatus may include a driving voltage-applying unit and a sub-word line-driving unit. The driving voltage-applying unit may be configured to generate a driving voltage in response to an active signal, a word line-enabling signal and a sub-word line selection signal. ... Sk Hynix Inc

12/22/16 / #20160372171

Semiconductor device, semiconductor system, and method for use in operating the same based on operation mode information

A semiconductor device includes a flag signal generating circuit, a reference voltage generating circuit, and a first buffer. The flag signal generating circuit generates a flag signal based on an internal command and a training control code which are extracted from an external signal. ... Sk Hynix Inc

12/22/16 / #20160372166

Input/output circuit and input/output device including the same

An input/output circuit according to an embodiment includes a plurality of memory cell units configured to independently perform output operations, each of the memory cell units including an input/output line, a selection circuit including a plurality of selection units, each selection unit setting a path to a global input/output line connected to each of the selection units, the number of the selection units being the same as the number of the memory cell units, the selection circuit selecting one of the plurality of memory cell units based on a path control signal and electrically connecting the input/output line of the selected memory cell unit to the global input/output lines of the plurality of selection units, and a plurality of input/output pad groups coupled to the global input/output lines.. . ... Sk Hynix Inc

12/22/16 / #20160372162

Sense amplifier driving device and semiconductor device including the same

An embodiment relates to a sense amplifier driving device for stabilizing bit line precharge power when a post-overdriving operation is performed. The sense amplifier driving device includes a power driving unit configured to supply a first pull-up voltage and a pull-down voltage to a pull-up power line and a pull-down power line during a post-overdriving period and a driving signal generation unit configured to generate a pull-up driving signal and a pull-down driving signal activated during the post-overdriving period in order to control the driving of the power driving unit. ... Sk Hynix Inc

12/22/16 / #20160372161

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory apparatus including a target region; and a controller suitable for performing a read voltage adjustment operation including setting a plurality of test read voltages based on a reference read voltage and an offset value, reading a plurality of codewords from the target region by using the plurality of test read voltages, respectively, calculating a plurality of parity check sums respectively corresponding to the plurality of codewords, and selecting a final read voltage based on the plurality of parity check sums.. . ... Sk Hynix Inc

12/22/16 / #20160371195

Data storage device and operating method thereof

A data storage device includes a plurality of logical regions that form n number of logical zones, each including k number of logical regions, wherein the plurality of logical regions are grouped into k number of logical region groups based on their offset values; and a processor suitable for, when receiving a write request for a target logical region, increasing a first access count stored in a first entry of a first table, corresponding to a logical zone including the target logical region, and increasing a second access count stored in a second entry of a second table, corresponding to a logical region group including the target logical region.. . ... Sk Hynix Inc

12/22/16 / #20160371024

Memory system and operating method thereof

A memory system includes a memory device including a plurality of memory blocks; and a controller suitable for performing read and write operations respectively in response to read and write commands, and update map data, which is stored in a buffer, as a result of the operations according to priority information of data stored in the memory blocks.. . ... Sk Hynix Inc

12/22/16 / #20160371004

Memory system and operating method thereof

A memory system includes a memory device; a memory suitable for temporarily storing data transferred between a host and the memory device; and a controller suitable for classifying data provided from the host into first classification data of relatively great size based on a reference size and second classification data of relatively small size based on the reference size, classifying one or more of the second classification data, which is repeatedly provided more than a threshold value of repetition, as third classification data, and managing the third classification data only in the memory.. . ... Sk Hynix Inc

12/22/16 / #20160370847

Memory system

A memory system includes a memory device, to which a first power is supplied, and in which data is stored; a controller, to which s second power is supplied, and which is configured to control the memory device; an interface, to which a third power is supplied, and which is configured to transmit a command and data between the controller and the memory device; and a low dropout (ldo) regulator configured to convert the first power into the third power and supply the third power to the interface.. . ... Sk Hynix Inc

12/22/16 / #20160370820

Reference voltage generator and reference voltage generator for a semiconductor device

A reference voltage generator may include a voltage division unit configured to receive an external voltage, and divide the external voltage into a plurality of divided voltages. The reference voltage generator may include reference voltage output units configured to trim the divided voltages received from the voltage division unit according to a division control signal, and output supply reference voltages. ... Sk Hynix Inc

12/22/16 / #20160370428

Portable test apparatus for a semiconductor apparatus, and test method using the same

A portable test apparatus may be provided. The portable test apparatus may include a socket board configured to allow mounting of a semiconductor apparatus decapsulated for package testing. ... Sk Hynix Inc

12/15/16 / #20160366358

Counting circuit, image sensing device with the counting circuit and read-out method of the image sensing device

A read-out method of an image sensing device includes: firstly counting a reset signal of a pixel signal based on a first analog gain during a first period of a unit row period; storing a result of the first counting as a previous counting result; secondly counting the reset signal based on a second analog gain; thirdly counting a data signal of the pixel signal based on the second analog gain during a second period following the first period in the unit row period; storing a first counting signal corresponding to results of the second counting and the third counting; fourthly counting the data signal based on the first analog gain during a third period following the second period in the unit row period; and storing a second counting signal corresponding to the previous counting result and a result of the fourth counting.. . ... Sk Hynix Inc

12/15/16 / #20160366357

Image sensing device and read-out method of the same

An image sensing device includes a pixel suitable for outputting a pixel signal through a read-out line during a read-out section and a precharge block suitable for precharging the read-out line to a voltage level corresponding to an initial voltage level of the pixel signal during a row non-selection section adjacent to the read-out section.. . ... Sk Hynix Inc

12/15/16 / #20160365855

Impedance calibration circuit

An impedance calibration circuit is disclosed, which relates to a technology for improving precision of pad resistance. The impedance calibration circuit includes: a first on die termination (odt) circuit selected by a first selection signal, configured to tune its own resistance using a first code signal, and output a first resistance value to an output terminal; and a second odt circuit selected by a second selection signal, configured to tune its own resistance using a second code signal, and output a second resistance value to the output terminal.. ... Sk Hynix Inc

12/15/16 / #20160365851

Output driver, semiconductor apparatus, system, and computing system using the same

A semiconductor apparatus may include an output driver configured to output an internal signal to an external device. The output driver may include a pad coupled to the external device, a pull-up driver coupled to the pad at an end thereof, a first resistance element coupled to the pull-up driver at an end thereof, and configured to receive a first source voltage at the other end thereof, a pull-down driver coupled to the pad at an end thereof, and a second resistance element coupled to the pull-down driver at an end thereof, and configured to receive a first ground voltage at the other end thereof.. ... Sk Hynix Inc

12/15/16 / #20160365384

Electronic device

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a vertical electrode formed over a substrate; a plurality of first memory elements and a plurality of first interlayer dielectric layers alternately stacked along a first side surface of the vertical electrode; and a plurality of second memory elements and a plurality of second interlayer dielectric layers alternately stacked along a second side surface of the vertical electrode, and the plurality of first memory elements correspond to the plurality of second interlayer dielectric layers, respectively, in the vertical direction.. ... Sk Hynix Inc

12/15/16 / #20160365375

Image sensor having vertical transfer gate and method for fabricating the same

The present disclosure provides an image sensor. An image sensor may include: a transfer gate formed over a first substrate, and having a through-hole; a column-shaped epitaxial body having a first portion filled in the through-hole and a second portion formed over the transfer gate; a photoelectric conversion element formed in the second portion of the epitaxial body; and a floating diffusion region formed in the first substrate, and contacting the first portion of the epitaxial body.. ... Sk Hynix Inc

12/15/16 / #20160365354

Semiconductor device and method of manufacturing the same

There are provided a semiconductor device and a method of manufacturing the same. A semiconductor device includes a memory block having local lines; a peripheral circuit disposed below the memory block; and a plurality of connection lines connecting the peripheral circuit and the local lines to each other, wherein the plurality of connection lines is stacked in a step shape.. ... Sk Hynix Inc

12/15/16 / #20160365158

Memory system including plurality of memory regions and method of operating the same

A method of a memory system including memory regions includes performing error corrections for chunks in each of the memory regions, and computing trust levels corresponding respectively to the memory regions based on the error corrections, setting test-reading periods corresponding respectively to the memory regions, based on the trust levels for the memory regions, counting a number of normal-reading times for each of the memory regions, and managing access counts corresponding respectively to the memory regions based on the counted numbers and when an access count for a first memory region among the memory regions reaches a time corresponding to a test-reading period for the first memory region, performing one or more test-readings for the first memory region.. . ... Sk Hynix Inc

12/15/16 / #20160365134

Memory system

A memory system is disclosed, which relates to a technology for reducing current consumption needed to perform a refresh operation in a dual in-line memory module. The memory system includes a memory module, which includes a volatile memory and a non-volatile memory, and a host configured to provide a refresh command to the memory module during the refresh operation. ... Sk Hynix Inc

12/15/16 / #20160365131

Memory device with parallel odd and even column access and methods thereof

A memory device includes: a plurality of first lines; a plurality of second lines; a plurality of bank groups each including a predetermined number of banks; and a column signal transmission unit suitable for transmitting one or more column command signals and one or more column address signals to the bank groups through the first lines based on an odd-numbered column command, and transmitting the column command signals and the column address signals to the bank groups through the second lines based on an even-numbered column command.. . ... Sk Hynix Inc

12/15/16 / #20160365127

Memory system and operating method thereof

There are provided a memory system and an operating method thereof. A memory system includes a memory device suitable for storing data therein; and a memory controller suitable for initializing the memory device, or maintaining or changing a mode of the memory device according to power of the memory device during a wake-up operation.. ... Sk Hynix Inc

12/15/16 / #20160364309

Input/output (i/o) line test device and method for controlling the same

An input/output (i/o) line test device and a method for controlling the same are disclosed, which may relate to a technology for testing a base die having no cell using various patterns. The i/o line test device may include an interface controller configured to perform signal transmission/reception between a pad and an input/output line (iol), and a signal transceiver configured to perform signal transmission/reception between the iol and a through silicon via (tsv). ... Sk Hynix Inc

12/15/16 / #20160364292

Efficient encoder based on modified ru algorithm

Memory systems may include a memory portion, and a controller suitable for receiving information data, generating first stage data, generating a first portion parity information, generating a second portion parity information based at least in part on the first portion parity information and the first stage data, and outputting the second portion parity information.. . ... Sk Hynix Inc

12/15/16 / #20160364291

Memory system and method of operating and testing the memory system

A memory system may include a plurality of chips configured to have an operation speed of a predetermined target speed or less. The memory system may include an error correction code (ecc) circuit configured to correct an error of each chip having an operation speed of higher than the target speed from among the plurality of chips.. ... Sk Hynix Inc

12/15/16 / #20160363855

Photomask blank and photomask for suppressing heat absorption

A photomask blank and/or photomask includes a light transmitting substrate, a highly reflective material layer disposed on the light transmitting substrate, and a transfer pattern layer disposed on the highly reflective material layer. The highly reflective material layer reflects light to be transmitted through the light transmitting substrate, with a predetermined reflectivity.. ... Sk Hynix Inc

12/08/16 / #20160360135

Image sensing device and read-out method of the same

An image sensing device includes a read-out control block suitable for generating a selection address signal and one or more address clock signals based on a source address signal, and a judge clock signal having a higher frequency than a source clock signal; and a read-out block suitable for reading out a plurality of pixel signals in response to the selection address signal, the address clock signals and the judge clock signal.. . ... Sk Hynix Inc

12/08/16 / #20160359553

Semiconductor device, semiconductor memory device and communication system

A semiconductor device may include: a conversion value generator suitable for detecting first and second transition factors that are independent of each other, and generating first and second conversion values corresponding to the first and second transition factors, respectively; and a signal converter suitable for generating an output signal by reflecting the first and second conversion values into an input signal.. . ... Sk Hynix Inc

12/08/16 / #20160359502

One-shot decoder for two-error-correcting bch codes

A decoder includes a syndrome generator for receiving a codeword and generating at least two syndromes based on the codeword, an error location polynomial generator for generating an error-location polynomial based on the syndromes, an error location determiner for determining at least one error location based on the error-location polynomial, and an error corrector for correcting the codeword based on the one error location. The error location polynomial generator includes a logic for receiving the syndromes and generating a combination of the syndromes as a combination of coefficients of the error-location polynomial, and a key equation solver for generating the error-location polynomial based on the combination of the coefficients and finding at least one root of the error-location polynomial. ... Sk Hynix Inc

12/08/16 / #20160359111

Semiconductor device including a resistive memory layer and method of manufacturing the same

A method of semiconductor device fabrication that includes sequentially forming an interfacial conductive layer and an etch stop layer on a resistive memory layer; forming a main conductive layer on the etch stop layer; exposing a portion of the etch stop layer by patterning the main conductive layer; exposing a portion of the interfacial conductive layer by patterning the portion of the etch stop layer; forming an upper electrode structure by patterning the portion of the interfacial conductive layer; cleaning a surface of the upper electrode structure and an exposed surface of the resistive memory layer; and patterning the resistive memory layer using the upper electrode structure as an etch mask.. . ... Sk Hynix Inc

12/08/16 / #20160358975

Electronic device and method for fabricating the same

An electronic device with improved variable resistance characteristics and a method for fabricating the same are provided. In an embodiment of the disclosed technology, a method for forming an electronic device with a semiconductor memory includes forming a crystalized doped layer over a substrate; forming a barrier layer over the doped layer; forming a metal layer over the barrier layer; and reacting the barrier layer with a portion of the metal layer. ... Sk Hynix Inc

12/08/16 / #20160358931

Methods of fabricating embedded electronic devices including charge trap memory cells

A method of fabricating an embedded electronic device including charge trap memory cells that includes forming a tunnel insulation layer, a charge trap layer and a sacrificial insulation layer on a substrate having a first region and a second region. The tunnel insulation layer, the charge trap layer and the sacrificial insulation layer which are stacked on the second region of the substrate are selectively removed. ... Sk Hynix Inc

12/08/16 / #20160358855

Nonvolatile memory device and method for fabricating the same

A nonvolatile memory device may include a stair-shaped structure including a first interlayer dielectric layer and a memory cell repeatedly stacked. The nonvolatile memory device may include an etch stop layer and a second interlayer dielectric layer formed over the stair-shaped structure. ... Sk Hynix Inc

12/08/16 / #20160358771

Methods of forming different sized patterns

A method includes forming a template portion to provide a first opening trench portion surrounding a first isolated pattern, and forming an array of pillars on an underlying layer; forming a separation wall layer including first separation wall portions surrounding sidewalls of the pillars, and forming second separation wall portions covering sidewalls of the first opening trench portion; forming a block copolymer layer on the separation wall layer; forming first domains in gaps between the pillars, and forming second domains surrounding and separating the first domains by annealing the block copolymer layer; forming second openings by selectively removing the first domains; forming third openings between the second openings, and forming a fourth opening adjacent to the first isolated pattern by selectively removing the pillars and the template portion; and forming fifth openings, which extend from the second and third openings and penetrate the underlying layer, and forming a sixth opening, which extends from the fourth opening and penetrates the underlying layer.. . ... Sk Hynix Inc

12/08/16 / #20160358671

Memory chip and stack type semiconductor apparatus including the same

A memory chip may include a plurality of channels including a plurality of memory banks and having a separate input/output interface, and each of the plurality of channels may be configured to simultaneously latch compression data groups obtained by compressing respective unit data groups outputted from the plurality of memory banks, sequentially output latched data as test read data according to a read start signal or a read end signal, and generate the read end signal which defines that final data output has ended.. . ... Sk Hynix Inc

12/08/16 / #20160358663

Modeling method of threshold voltage distributions

Memory systems may include a memory including a plurality of wordlines, each wordline including a plurality of cells, and a controller suitable for obtaining an initial voltage threshold and a target state for each of the plurality of cells, applying a pulse based on a pulse value to the plurality of cells, and calculating at least one coupling effect to neighboring cells.. . ... Sk Hynix Inc

12/08/16 / #20160358658

Method and controller for programming non-volatile memory

A method is provided for programming a non-volatile memory having a plurality of word lines, the method comprising: applying a pass voltage to a selected word line among the plurality of word lines; and applying one of first and second program voltages to the selected word line by increasing the pass voltage, wherein the applying of one of the first and second program voltages increases the pass voltage with a single increment.. . ... Sk Hynix Inc

12/08/16 / #20160357480

Memory system and operating method thereof

A memory system includes a memory device including a plurality of blocks each comprising first and second regions of pages; and a controller suitable for storing a plurality of data in the first region and hot/cold information respectively corresponding to the plurality of data in the second region.. . ... Sk Hynix Inc

12/08/16 / #20160357472

Memory system and operating method thereof

A memory system includes a semiconductor memory device including memory cells and an internal random access memory (ram); and a controller suitable for transmitting read retry table information to the semiconductor memory device when a read operation for the memory cells fails, wherein the internal ram stores a read retry table during operation of the memory system, and wherein the semiconductor memory device performs a read retry operation with a read retry voltage determined based on the read retry table and the read retry table information.. . ... Sk Hynix Inc

12/08/16 / #20160357453

Semiconductor memory device

A semiconductor memory device includes a data input/output unit suitable for storing a plurality of pieces of data in a plurality of bank areas through a first data bus and a second data bus, and outputting the plurality of pieces of data to an external data pin from the plurality of bank areas; and a plurality of unit banks each including a first bank area which stores data corresponding to a lower bit of a bit group to be first inputted/outputted though the first data bus, and a second bank area which stores data corresponding to an upper bit of the bit group to be inputted/outputted though the second data bus after input/output of the data corresponding to the lower bit.. . ... Sk Hynix Inc

12/08/16 / #20160357205

Voltage compensation circuit including low dropout regulators and operation method thereof

A method of recovering a voltage drop at an output terminal of a voltage compensation circuit connected to a load including a variable load current according to a condition of the load. A circuit portion for a regulator having an output terminal connected to a load including a variable load current may be provided, the circuit portion may include a plurality of stages connected in parallel to said output terminal. ... Sk Hynix Inc

12/08/16 / #20160356848

Apparatus and method of generating test pattern, test system using the same, and computer program therefor

A test pattern generation apparatus includes an input unit, an output unit, and a pattern generating unit configured to, when a source code based on a system description language is created through the input unit, store an execution file created from the source code, generate a test pattern from the execution file according to an external command for testing a semiconductor apparatus as a dut, and output the generated test pattern through the output unit.. . ... Sk Hynix Inc

12/01/16 / #20160353033

Differential circuit and image sensing device including the same

A differential circuit includes a differential selection block suitable for generating differential selection signals corresponding to differential input signals in response to an enable signal and a differential loading block suitable for loading differential output signals corresponding to the differential input signals on differential lines in response to the differential selection signals.. . ... Sk Hynix Inc

12/01/16 / #20160352995

Apparatus for generating image and method thereof

An apparatus includes an image conversion unit suitable for converting a short exposure block according to an exposure ratio; a motion and saturation detection unit suitable for receiving a long exposure block and an l short exposure block converted by the image conversion unit, and detecting motion and saturation; a radiance map generation unit suitable for fusing the long and l short exposure blocks using a guided filter, and generating a radiance map; a luminance acquirement unit suitable for acquiring luminance of the radiance map, and generating luminance using the l short exposure block or respectively generating luminance using the long and l short exposure blocks; and a dynamic range compression unit suitable for performing global tone mapping using the luminance acquired by the luminance acquirement unit, and compressing a dynamic range.. . ... Sk Hynix Inc

12/01/16 / #20160352343

Integrated circuit and clock data recovery circuit

An integrated circuit includes a comparator capable of generating an up/down signal by comparing a feedback signal with a reference signal; a restoration signal generation unit capable of enabling a restoration signal when the up/down signal maintains an identical value for greater than or equal to a first specific time and changes afterwards; a processing circuit including one or more stages for sequentially processing the up/down signal, wherein a last one of the one or more stages holds a process result thereof for a second specific time when the restoration signal is enabled; and a feedback unit capable of generating the feedback signal in response to the process result of the last stage.. . ... Sk Hynix Inc

12/01/16 / #20160351707

Power integrated devices, electronic devices including the same, and electronic systems including the same

A power integrated device includes a semiconductor layer having first conductivity, a source region and a drain region each having second conductivity and disposed in the semiconductor layer, wherein the source region and the drain region are spaced apart from each other, a first drift region having the second conductivity, disposed in the semiconductor layer, and surrounding the drain region a second drift region having the second conductivity, disposed in the semiconductor layer, contacting a sidewall of the first drift region, and having an impurity concentration lower than an impurity concentration of the first drift region, a gate insulation layer disposed over a channel region between the source region and the second drift region and extending, over the second drift region a field insulation plate disposed over the second drift region and the first drift region, contacting a sidewall of the gate insulation layer, and having a planar structure, and a gate conductive pattern disposed over the gate insulation layer, wherein the gate conductive pattern extends over the field insulation plate.. . ... Sk Hynix Inc

12/01/16 / #20160351672

Semiconductor memory device including slimming structure

Disclosed is a semiconductor memory device, including: a slimming structure extended from a cell structure in a direction parallel to the semiconductor substrate, the cell structure having a plurality of cell transistors stacked over a semiconductor substrate; vertical insulating materials extended in a direction crossing the semiconductor substrate and configured to divide the cell structure and the slimming structure into a plurality of memory blocks; contact plugs passing through the vertical insulating materials, respectively, within an area in which the slimming structure is formed; and junctions formed within the semiconductor substrate under the vertical insulating materials, in which the junctions are coupled to the contact plugs, respectively.. . ... Sk Hynix Inc

12/01/16 / #20160351605

Image sensor and electronic device having the same

An image sensor includes a substrate including photoelectric conversion elements for a plurality of unit pixels, which are two-dimensionally arranged in a pixel array; a light transmission member on the substrate; a grid structure in the light transmission member and having multiple layers; and a light collection member on the light transmission member, wherein the grid structure is tilted for respective chief ray angles of the plurality of unit pixels according to locations of the plurality of unit pixels in the pixel array.. . ... Sk Hynix Inc

12/01/16 / #20160351581

Semiconductor device and manufacturing method of the same

A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.. . ... Sk Hynix Inc

12/01/16 / #20160351534

Printed circuit boards having blind vias, method of testing electric current flowing through blind via thereof and method of manufacturing semiconductor packages including the same

A method of manufacturing a semiconductor package is provided. The method includes providing a strip substrate having a plurality of unit substrate regions that are spaced apart from each other by a periphery region and have blind vias, a peripheral conductive pattern layer disposed in the periphery region, and a connection pattern layer electrically connecting the blind vias to the peripheral conductive pattern layer. ... Sk Hynix Inc

12/01/16 / #20160351501

Semiconductor device having air-gap and method for manufacturing the same

A semiconductor device in which an air-gap located at a side of a bit line stack is extended to an upper part of the bit line stack is disclosed. An embodiment includes: a bit line stack; a plurality of storage node contacts located at both sides of the bit line stack; and an air-gap located between the bit line stack and the storage node contacts, and extended above the bit line stack.. ... Sk Hynix Inc

12/01/16 / #20160351277

Semiconductor memory device and test operation method thereof

A semiconductor memory device includes: a word line driving unit suitable for performing activation operations for a plurality of normal word lines and a plurality of redundancy word lines in response to test addresses; and a test control unit suitable for controlling a number of activations of each of the plural normal and redundancy word lines to be equal based on repair information corresponding to a repair target word line among the plural normal word lines during a test operation.. . ... Sk Hynix Inc

12/01/16 / #20160351276

Smart self repair device and method

A smart self-repair device includes an are array configured to store information on respective bits of a fail address in fuses; a self-repair control block configured to store a row address and a column address corresponding to a fail bit when a fail occurs, analyze a fail mode by comparing the fail address inputted in a test and the stored addresses, and output fail address information and row fuse set information or column fuse set information according to the fail mode; a data control block configured to output repair information to the are array according to the fail address information and the row fuse set information or the column fuse set information; and a rupture control block configured to control a rupture operation of the are array.. . ... Sk Hynix Inc

12/01/16 / #20160351272

Non-volatile memory and a method of operating the same

A non-volatile memory includes a current sensing checking block including a programming status input block comprising a plurality of sub-blocks connected with each other in parallel with respect to a first node; a reference block comprising a plurality of sub-blocks connected with each other in parallel with respect to a second node; an operational amplifier operable to compare voltage levels of the first node and the second node to determine whether a actual number of programming failures for a desired group of cells exceeds a reference number of allowable programming failures of the reference block.. . ... Sk Hynix Inc

12/01/16 / #20160351248

Memory device

A memory device includes a plurality of banks suitable for including a plurality of word lines, a plurality of latch units each suitable for generating a first address by inverting a predetermined bit of an address of an activated word line of a corresponding bank and latching the first address as a target address in sections other than a target refresh section, and latching an operation address as the target address once in an all-bank refresh section of the target refresh section, wherein all of the plurality of banks are refreshed in the all-bank refresh section. All the plurality of banks are refreshed in the all-bank refresh section, and an address operation unit suitable for generating the operation address by adding or subtracting an operation value to or from the target address. ... Sk Hynix Inc

12/01/16 / #20160351241

Electronic device

An electronic device including a semiconductor memory. The semiconductor memory includes a bit line; a source line; a plurality of resistive memory cells among which a selected memory cell forms a current path between the bit line and the source line; a read current supply unit configured to supply read current to the bit line in a read operation; a sense amplifier configured to generate read data in response to a voltage level of the bit line in the read operation; and a variable switch element configured to flow current from the source line to a ground terminal in the read operation, and be decreased in its resistance value as a voltage level of the source line is high.. ... Sk Hynix Inc

12/01/16 / #20160351240

Electronic device including a semiconductor memory

This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a contact plug; a first stack structure disposed over the contact plug and coupled to the contact plug, wherein the first stack structure includes a pinning layer controlling a magnetization of a pinned layer; and a second stack structure disposed over the first stack structure and coupled to the first stack structure, wherein the second stack structure includes a mtj (magnetic tunnel junction) structure which includes the pinned layer having a pinned magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer interposed between the pinned layer and the free layer, wherein a width of the first stack structure is larger than a width of the contact plug and a width of the second stack structure.. ... Sk Hynix Inc

12/01/16 / #20160351239

Electronic devices having semiconductor memory units and method of fabricating the same

Electronic devices have a semiconductor memory unit including a magnetization compensation layer in a contact plug. One implementation of the semiconductor memory unit includes a variable resistance element having a stacked structure of a first magnetic layer, a tunnel barrier layer, and a second magnetic layer, and a contact plug arranged in at least one side of the variable resistance element and comprising a magnetization compensation layer. ... Sk Hynix Inc

12/01/16 / #20160351237

Semiconductor device and semiconductor system

A semiconductor system may include a controller and a semiconductor device. The controller may output command/address signals. ... Sk Hynix Inc

12/01/16 / #20160351236

Semiconductor device and operating method thereof

A semiconductor device includes memory blocks including a plurality of strings in which memory cells are coupled between select transistors; a peripheral circuit suitable for erasing or programming the select transistors and the memory cells, which are included in a selected memory block among the memory blocks; and a control circuit suitable for controlling the peripheral circuit to erase the select transistors and the memory cells, increasing a threshold voltage of the select transistors within a range below an erase level, and increasing the threshold voltage of the select transistors up to a program level.. . ... Sk Hynix Inc

12/01/16 / #20160351235

Semiconductor devices having initialization circuits and semiconductor systems including the same

A semiconductor device may include a boot-up operation circuit configured for executing a boot-up operation during a boot-up operation period after a power supply voltage signal reaches a predetermined level. The boot-up operation circuit may be configured for generating a boot-up period signal. ... Sk Hynix Inc

12/01/16 / #20160350316

Data processing circuit, data storage device including the same, and operating method thereof

A data processing circuit includes a plurality of transformation blocks suitable for respectively transforming in parallel a plurality of input bit groups into a plurality of output bit groups, wherein each of the transformation blocks transforms a corresponding input bit group into a corresponding output bit group by using a random pattern.. . ... Sk Hynix Inc

12/01/16 / #20160350025

Data storage device

A data storage device includes a nonvolatile memory device; and a controller suitable for controlling an operation of the nonvolatile memory device based on a request from a host device, wherein the controller includes a first core activated in a normal mode and a second core activated in a standby mode.. . ... Sk Hynix Inc

12/01/16 / #20160349784

Internal voltage generation device

An internal voltage generation device includes a voltage generation block configured to compare a reference voltage and a divided voltage, and generate an output voltage; and an internal voltage driving block including a pull-up driving unit which selectively pull-up drives an internal voltage according to the output voltage, and configured to output the output voltage to the pull-up driving unit through different paths according to a test signal.. . ... Sk Hynix Inc

12/01/16 / #20160349777

Regulator with enhanced slew rate

A regulator includes a first operational amplifier configured to receive a reference voltage and a feedback voltage and to output a node voltage based on a difference of the feedback voltage and the reference voltage; a first switch unit configured to receive the node voltage and to supply a recover current based on the node voltage; an output unit configured to output an output voltage and the feedback voltage according to a supply of the recover current; a comparison unit configured to receive the reference voltage and a feedback voltage and to sense a voltage drop of the output voltage; and a second switch unit configured to discharge the first switch unit according to the difference of the reference voltage and the feedback voltage.. . ... Sk Hynix Inc

12/01/16 / #20160349321

Test device

A test device includes: a test control unit suitable for detecting a deterioration-expected unit circuit among a plurality of unit: circuits included in a test-subject device according to operation histories of the plural unit circuits, and detecting a deterioration degree according to a test output value of the deterioration-expected unit circuit; and an interface unit suitable for routing control operation results and test results between the test control unit and the test-subject device during a test operation.. . ... Sk Hynix Inc

11/24/16 / #20160344426

Performance optimization in soft decoding for turbo product codes

Systems for performing turbo product code decoding may include an error intersection identifier suitable for determining a set of one or more error intersections using a set of error-containing codewords, and updating, based at least in part on chase decoding performed on the set of error-containing codewords, the set of error intersections to obtain an updated set of one or more error intersections, a bit location selector suitable for selecting, from the set of error intersections, a set of one or more least reliable bit locations using soft information associated with the set of error-containing codewords, and a chase decoder suitable for performing chase decoding on the set of error-containing codewords based on a first value being a number of least reliable bit locations and a second value being a maximum number of allowable flips allowed out of the number of least reliable bit locations.. . ... Sk Hynix Inc

11/24/16 / #20160343839

Electronic device

Provided is an electronic device including a semiconductor memory. The semiconductor memory includes first and second selecting elements coupled to a variable resistance element, and each of the first and second selecting elements includes a single-electron transistor.. ... Sk Hynix Inc

11/24/16 / #20160343726

Electronic device and method for fabricating the same

A method for fabricating an electronic device including a semiconductor memory may include: forming a stack structure in which an interlayer dielectric layer and a material layer are alternately stacked on a substrate; forming a plurality of holes arranged to have a substantially constant interval while exposing the substrate by passing through the stack structure; forming a channel layer in a first hole of the plurality of holes; forming a dummy layer in a second hole of the plurality of holes; forming a mask pattern on a resultant structure including the dummy layer and the channel layer to expose an area extending in a first direction while overlapping the dummy layer arranged in the first direction; and forming a slit by etching the stack structure using the mask pattern as an etching barrier and removing the dummy layer.. . ... Sk Hynix Inc

11/24/16 / #20160343669

Semiconductor device

A semiconductor device may include pillars and a plurality of conductive layers being stacked while surrounding the pillars and including a plurality of first regions including non-conductive material layers and a plurality of second regions including conductive material layers, wherein the first regions and the second regions are alternately arranged.. . ... Sk Hynix Inc

11/24/16 / #20160343447

Voltage generator, semiconductor memory device having the same, and method of operating semiconductor memory device

A voltage generator that includes an operation mode determination circuit suitable for determining an active mode or a standby mode based on a chip enable signal to activate an active mode signal or a standby mode signal according to a result of the determination; and a bulk voltage generation circuit outputting a bulk voltage having an internal power voltage when the active mode signal is activated, and outputting the bulk voltage having an external power voltage when the standby mode signal is activated.. . ... Sk Hynix Inc

11/24/16 / #20160343414

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a memory cell array including a plurality of pages; a peripheral circuit suitable for performing a program operation and a read operation on the memory cell array; and a control logic suitable for controlling the peripheral circuit to apply first and second pass voltages respectively to first and second word lines adjacent to a selected word line during a program verify operation or the read operation.. . ... Sk Hynix Inc

11/24/16 / #20160342467

Generalized product codes for flash storage

Memory systems may include an encoder suitable for arranging data in rows of data blocks as a plurality of codewords, and permuting the data block rows and constructing row parities on the permuted rows, and a decoder suitable for decoding the codewords, and correcting stuck error patterns when decoding of the codewords fails.. . ... Sk Hynix Inc

11/24/16 / #20160342458

Hybrid read disturb count management

Memory systems may include a memory including a plurality of blocks, and a controller suitable for counting, with a counter, a number of reads to a block of the plurality of blocks, updating wordline information of a plurality of wordlines in the counted block when the number of reads exceeds a block read count threshold, selecting a wordline from the plurality of wordlines, determining an error rate of a neighbor wordline to the selected wordline, and reclaiming data in the block when the error rate exceeds an error threshold.. . ... Sk Hynix Inc

11/24/16 / #20160342332

Semiconductor device and operating method thereof

The semiconductor memory device includes: a memory unit including a plurality of memory blocks; a decoder suitable for storing bad block information about the plurality of memory blocks, and outputting the bad block information in response to an address signal; and a control logic suitable for controlling the memory unit and the decoder to update a status register (sr) code in response to the bad block information when the semiconductor memory device at a ready state enters a busy state, and to perform a general operation according to the updated sr code and a command.. . ... Sk Hynix Inc

11/17/16 / #20160336969

Miscorrection avoidance for turbo product codes

Systems may include a memory storage suitable for storing data, an encoder suitable for encoding data into codewords arranged in an array of a number of rows and a number of columns, and a decoder suitable for receiving the encoded codewords, decoding the encoded codewords, and detecting miscorrections in the decoding.. . ... Sk Hynix Inc

11/17/16 / #20160336948

Apparatus for correcting gain error of analog-to-digital converter

A bias generator may include: an operational amplifier, a resister string, and a control circuit. The operational amplifier includes a first input terminal suitable for receiving a bandgap reference voltage, a second input terminal with an offset voltage and an output terminal. ... Sk Hynix Inc

11/17/16 / #20160336414

Dual work function buried gate-type transistor, method for forming the same, and electronic device including the same

A transistor includes: a source region and a drain region that are formed in a substrate to be spaced apart from each other; a trench formed in the substrate between the source region and the drain region; and a buried gate electrode inside the trench, wherein the buried gate electrode includes: a lower buried portion which includes a high work-function barrier layer including an aluminum-containing titanium nitride, and a first low-resistivity layer disposed over the high work-function barrier layer; and an upper buried portion which includes a low work-function barrier layer disposed over the lower buried portion and overlapping with the source region and the drain region, and a second low-resistivity layer disposed over the low work-function barrier layer.. . ... Sk Hynix Inc

11/17/16 / #20160336376

Semiconductor integrated circuit device having vertical channel and method of manufacturing the same

A semiconductor integrated circuit device having a vertical channel and a method of manufacturing the same are provided. A plurality of active lines are formed in a semiconductor substrate. ... Sk Hynix Inc

11/17/16 / #20160336362

Image sensor and method for fabricating the same

An image sensor includes: a first inter-layer dielectric layer formed over a front side of a substrate including photoelectric conversion regions; isolation structures each of which penetrates through the first inter-layer dielectric layer and has a portion buried in the substrate; first metal lines formed over the first inter-layer dielectric layer to correspond to the photoelectric conversion regions; and an optical filter and a light condenser formed over a back side of the substrate.. . ... Sk Hynix Inc

11/17/16 / #20160336311

Semiconductor device including capacitor and method for manufacturing the same

A semiconductor device includes a semiconductor substrate having a first region and a second region; a first planar type capacitor including a gate electrode which is positioned in any one region of the first region and the second region; a non-planar type capacitor including a plurality of non-planar type electrodes which are positioned in the other region of the first region and the second region; a second planar type capacitor including a planar type electrode which is positioned over the first planar type capacitor to overlap with the first planar type capacitor; and a common node under the non-planar type capacitor.. . ... Sk Hynix Inc

11/17/16 / #20160336267

Semiconductor device

A semiconductor device may include pillars and a plurality of conductive layers being stacked while surrounding the pillars and including a plurality of first regions including non-conductive material layers and a plurality of second regions including conductive material layers, wherein the first regions and the second regions are alternately arranged.. . ... Sk Hynix Inc

11/17/16 / #20160336220

Semiconductor devices and methods of manufacturing the same

A semiconductor device includes a substrate including a memory cell region and a contact region, a string structure including conductive layers and first interlayer insulating layers alternately stacked over the substrate and protruded toward a lower layer from the memory cell region toward the contact region, barrier rib patterns spaced apart from one another over the conductive layers in the contact region and configured to open the layers of the conductive layers in the contact region through the spaced spaces, and first contact plugs filled into the space between barrier rib patterns adjacent to each other and coupled to the conductive layers in the contact region.. . ... Sk Hynix Inc

11/17/16 / #20160336196

Apparatus and method for removing particles present on a wafer using photoelectrons and an electric field

A wafer processing apparatus includes a particle charger for charging particles adsorbed onto a wafer with photoelectrons emitted from an emitter metal layer and a particle remover for applying an electric field to the wafer, which removes the charged particles from the wafer.. . ... Sk Hynix Inc

11/17/16 / #20160336180

Method for etching high-k metal gate stack

A method for etching a gate includes forming a high-k material layer over a substrate; forming an overlying layer over the high-k material layer; performing a first etching process for etching the overlying layer to form an overlying layer pattern; forming a spacer on a sidewall of the overlying layer pattern; and performing a second etching process using plasma including a etch gas and an additive gas, to etch the high-k material layer, wherein an amount of the additive gas is substantially the same as the main etch gas to increase an etch selectivity with respect to the substrate.. . ... Sk Hynix Inc

11/17/16 / #20160336077

Semiconductor device and semiconductor system

A semiconductor system includes a controller configured to generate a boot-up signal; and a semiconductor device configured to, if addresses, which increase by a predetermined value, have the same combination of bits as fuse data, initialize fuse data in response to the boot-up signal or a reset signal, and generate the fuse data by using latched internal fuse data after the fuse data are initialized.. . ... Sk Hynix Inc

11/17/16 / #20160336071

Semiconductor memory device including dummy memory cells and method of operating the same

A method of operating a semiconductor memory device including a plurality of cell strings coupled to dummy word lines and normal word lines includes performing a first sub-program operation on selected normal memory cells by sequentially applying first program pulses to a selected normal word line and performing a second sub-program operation on the selected normal memory cells by sequentially applying second program pulses greater than the first program pulses to the selected normal word line, wherein at least one of the dummy word lines is biased in a same manner as the selected normal word line whenever each of the first program pulses is applied to the selected normal word line.. . ... Sk Hynix Inc

11/17/16 / #20160336061

Memory device and memory system including the same

A memory device includes a plurality of memory blocks; an address counter suitable for generating a counted address which is used for a normal refresh operation and changed when all the memory blocks are refreshed; a target address generator suitable for generating a target address used for a target refresh operation, wherein the target address corresponds to an address of a word line to be additionally refreshed in the memory blocks; and a refresh controller suitable for controlling the memory blocks to be refreshed at different times during a first normal refresh operation, controlling a memory block among the memory blocks, which is first refreshed in the first normal refresh operation, to be refreshed through the target refresh operation, and controlling the memory block, which is first refreshed in the first normal refresh operation, to be refreshed last during a second normal refresh operation, based on the refresh command.. . ... Sk Hynix Inc

11/17/16 / #20160336058

Semiconductor device and semiconductor system including the same

A semiconductor device includes: a command decoding unit suitable for decoding external command signals to generate an internal command signal; and a pulse control unit suitable for controlling a pulse width of the internal command signal.. . ... Sk Hynix Inc

11/17/16 / #20160335179

Data separation by delaying hot block garbage collection

Memory systems may include a memory including a plurality of blocks, and a controller suitable for determining a pool of blocks from the plurality of blocks as garbage collection (gc) victim block candidates based on a number of valid pages left in each of the plurality of blocks, and selecting a block from the pool of blocks having a minimum number of valid pages as a victim block for garbage collection.. . ... Sk Hynix Inc

11/17/16 / #20160335144

Adaptive read disturb reclaim policy

Memory systems may include a memory including a plurality of memory blocks, and a controller suitable for, incrementing a first counter corresponding to a block of the plurality of blocks when the block is read, incrementing a second counter when the first counter reaches a predefined count number, determining an error count of the block when the second counter is incremented, and initiating a reclaim function when the error count exceeds an error threshold.. . ... Sk Hynix Inc

11/17/16 / #20160334999

Reduction of maximum latency using dynamic self-tuning for redundant array of independent disks

Memory systems may include a redundant array of inexpensive disks (raid) group including a plurality of disks, and a storage access layer including a raid engine suitable for requesting data from the raid group, determining whether a disk in the plurality of disks is busy based on a latency threshold, when the disk is determined to be busy, determining whether the requested data can be obtained from other non-busy disks in the plurality of disks, and obtaining the requested data when the data is determined to be obtainable from the other non-busy disks.. . ... Sk Hynix Inc

11/17/16 / #20160334827

Semiconductor device and semiconductor system including the same

A semiconductor system may include a first semiconductor device configured to output a command signal, a first power supply voltage, a second power supply voltage and a third power supply voltage. The semiconductor system may include a second semiconductor device configured to drive an internal power supply voltage with the first power supply voltage in response to an internal command signal generated by decoding the command signal, generate first output data from first internal data by being supplied with the internal power supply voltage and the second power supply voltage, and generate second output data from second internal data by being supplied with the internal power supply voltage and the second power supply voltage.. ... Sk Hynix Inc

11/10/16 / #20160330387

Ramp signal generator and image sensor including the same

A ramp signal generator may include: a differential amplification unit suitable for generating an amplified signal corresponding to a voltage difference between a reference voltage and a feedback voltage; a driving unit suitable for driving an output terminal of the feedback voltage to a ground voltage in response to the amplified signal, and generating the feedback voltage corresponding to the reference voltage; and a ramp signal generation unit suitable for generating a ramp signal using a ramp supply voltage and the feedback voltage.. . ... Sk Hynix Inc

11/10/16 / #20160329887

Transmitting/receiving system

A transmitting/receiving system may include a transmitting circuit and a receiving circuit. The transmitting circuit may include: a pull-up element suitable for pull-up driving a first node in response to a signal; a pull-down element suitable for pull-down driving a second node in response to the signal; and a voltage tailor coupled between the first and second nodes, and transmitting a low-swing signal obtained by reducing the swing amplitude of the signal to a transmission line, and the receiving circuit may include: a reference voltage generator having a replica circuit of the receiving circuit and suitable for generating a reference voltage; and a differential amplifier suitable for differentially amplifying the reference voltage and the low-swing signal received through the transmission line.. ... Sk Hynix Inc

11/10/16 / #20160329491

Electronic device and operation method thereof

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a plurality of first lines extending in a first direction and arranged in parallel to each other; a plurality of second lines extending in a second direction crossing the plurality of first lines and arranged in parallel to each other; and a plurality of memory cells disposed in intersection regions of the plurality of first lines and the plurality of second lines, respectively, and wherein each of the memory cells may include: a selecting element including a switching element and a thermoelectric element that are coupled to each other, the switching element having a non-linear current-voltage characteristic; a variable resistance element coupled to the selecting element; and a heat insulating member surrounding at least a sidewall of the selecting element.. ... Sk Hynix Inc

11/10/16 / #20160329337

Semiconductor device including air gaps and method for fabricating the same

Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. ... Sk Hynix Inc

11/10/16 / #20160329298

Package-on-package type semiconductor device including fan-out memory package

A semiconductor device may include a bottom package embedded with a first semiconductor chip. The semiconductor device may include a middle package stacked over the bottom package, and embedded with at least two second semiconductor chips in a fan-out structure. ... Sk Hynix Inc

11/10/16 / #20160329277

Switched-capacitor dc-to-dc converters

A switched-capacitor dc-to-dc converter includes a first p-channel mos transistor, a first n-channel mos transistor, a second p-channel mos transistor, and a second n-channel mos transistor which are connected in series. Drain terminals of the first p-channel mos transistor and the first n-channel mos transistor are connected to each other through a first node, and drain terminals of the second p-channel mos transistor and the second n-channel mos transistor are connected to each other through a second node. ... Sk Hynix Inc

11/10/16 / #20160329109

Semiconductor memory device and method of operating the same

A semiconductor memory device and a method of operating the same are provided. The method of operating the semiconductor memory device includes detecting a first group of changed bits between first and second page data, by comparing the first and second page data, which are read out using first and second test voltages from the memory cells, respectively, detecting a second group of changed bits between the second page data and a third page data, by comparing the second page data with the third page data read out from the memory cells using a third test voltage, comparing the numbers of the first and second groups of changed bits, and determining one of the first to third test voltages as a read voltage according to the comparing of the numbers of the first and second groups of changed bits.. ... Sk Hynix Inc

11/10/16 / #20160329108

Semiconductor memory apparatus

A semiconductor memory apparatus may include a decoding unit configured to enable one of a plurality of sub word line driver enable signals by decoding a plurality of addresses while the decoding unit operates in a normal mode, and enables specific sub word line driver enable signals among the plurality of sub word line driver enable signals regardless of the plurality of addresses while the decoding unit is operating in a test mode. The semiconductor memory apparatus may include a sub word line driver group configured to include a plurality of sub word line drivers, the plurality of sub word line drivers configured for activation in response to the plurality of sub word line driver enable signals. ... Sk Hynix Inc

11/10/16 / #20160329105

Semiconductor memory device and method of operating the same

A semiconductor memory device includes memory cells coupled to a word line; and a peripheral circuit configured to read first to kth page data from the memory cells by sequentially applying first to kth test voltages to the word line, where k is a natural number greater than 3, wherein the peripheral circuit is configured to gradually reduce times during which the first to kth test voltages are applied to the word line.. . ... Sk Hynix Inc

11/10/16 / #20160329096

Semiconductor apparatus for reading stored information of a resistor or cell

A semiconductor apparatus includes a variable resistor, a variable resistor selection unit configured to electrically couple the variable resistor to a sense amplifier in response to a resistor selection signal, a power supply unit configured to apply a first voltage to the variable resistor selection unit in response to a read signal, and a switch driving unit configured to generate the resistor selection signal in response to a resistor selection control signal, and to raise a voltage of the resistor selection signal when the first voltage is applied to the variable resistor selection unit.. . ... Sk Hynix Inc

11/10/16 / #20160329089

Semiconductor memory device

A semiconductor memory device includes: a plurality of memory areas; a target area setting unit suitable for designating a target area according to a number of accesses to the respective memory areas; a random address generation unit suitable for generating a random address within the respective memory areas in a random manner; a target address generation unit suitable for generating a target address based on the target area and the random address; and a driving unit suitable for performing a smart refresh operation according to the target address.. . ... Sk Hynix Inc

11/10/16 / #20160329088

Semiconductor memory apparatus

A semiconductor memory apparatus includes a plurality of cell arrays; and a use information storage block configured to determine whether a data write operation has already been performed for the plurality of cell arrays, and generate a plurality of control signals, wherein the semiconductor memory apparatus is configured to control a refresh operation for the plurality of cell arrays according to the plurality of control signals.. . ... Sk Hynix Inc

11/10/16 / #20160329084

Memory system including semiconductor memory device and program method thereof

A method of programming a memory system includes: reading a target page included in a selected memory block in response to a program request when at least one of the pages included in the selected memory block contains data; and performing a program for the target page when, among the data bits included in the data read from the target page, the number of data bits having a first logic value is equal to or less than a preset value.. . ... Sk Hynix Inc

11/10/16 / #20160329083

Memory system, semiconductor device and methods of operating the same

A memory system, a semiconductor memory device and methods of operating the same may perform a read operation on the basis of flag data stored in a flag register, without reading the flag data stored in a memory array, when performing the read operation, so that a time taken for the read operation may be reduced.. . ... Sk Hynix Inc

11/10/16 / #20160329082

Storage device and operating method thereof

A storage device includes a memory controller suitable for outputting a program command or a read command; and a memory device suitable for performing a program operation in response to the program command, and immediately performing a read operation when the read command is received during the program operation.. . ... Sk Hynix Inc

11/10/16 / #20160328287

Controller, semiconductor memory system and operating method thereof

An operating method of a memory controller includes: generating a soft decision read data for stored data read from a semiconductor memory device according to a soft decision read voltage, wherein the stored data is stored in the semiconductor memory device through sequential operations of ecc encoding and scrambling; and generating a first de-scrambled data by performing de-scrambling operation to a sign bit of the soft decision read data.. . ... Sk Hynix Inc

11/10/16 / #20160328171

Semiconductor memory device, operating method thereof, and data storage device including the same

A semiconductor memory device includes a setting information area suitable for storing setting information necessary for driving of memory cells, a control logic suitable for loading the setting information stored in the setting information area on a content-addressable memory (cam) block, a cam state information storage block suitable for storing information on whether the setting information loaded on the cam block is changed, wherein when a reloading operation of the setting information stored in the setting information area on the cam block is requested, the control logic selectively performs the reloading operation based on the information stored the cam state information storage block.. . ... Sk Hynix Inc

11/10/16 / #20160328163

Memory module, module controller of memory module, and operation method of memory module

An operation method for a memory module that includes communicating with a host; receiving a backup command from the host; reading a setting value of a volatile memory and storing the read setting value as a first storage value; setting a setting value suitable for a backup operation in the volatile memory; performing the backup operation by storing data stored in the volatile memory in a non-volatile memory; setting the first storage value in the volatile memory; and resuming communication with the host.. . ... Sk Hynix Inc

11/10/16 / #20160328160

Data storage device

A data storage device includes a first memory device suitable for performing an internal operation in response to a first internal operation command; and a state checking block suitable for performing a state read operation by transmitting a state read command one or more times to the first memory device during one of an initial mode and a repeat mode which is set based on a type of the internal operation.. . ... Sk Hynix Inc

11/10/16 / #20160328155

Memory system and operating method thereof

A memory system includes multiple blocks each including multiple pages; a selective copy unit suitable for determining whether data stored in each of multiple valid pages included in a victim block has a predetermined pattern, and copying a valid normal data to a free block; and a storage unit suitable for updating mapping information of a logical address for a valid pattern data to the predetermined pattern of the valid pattern data. The valid normal data does not have the predetermined pattern. ... Sk Hynix Inc

11/10/16 / #20160328150

Memory system

A memory system includes a plurality of memory devices; and a controller suitable for: dividing a plurality of commands applied from a host into first and second group commands according to a preset division reference, storing first and second group commands in first and second storage spaces, respectively, and alternately providing the first and second group commands to the plurality of memory devices according to a preset change reference.. . ... Sk Hynix Inc

11/10/16 / #20160327976

Memory module including battery

A memory module may include a module substrate having first and second surfaces facing away from each other, a plurality of first memories mounted over one or more of the first and second surfaces, one or more second memories and a controller each mounted over one of the first and second surfaces of the module substrate, and a plurality of batteries mounted over one or more of the first and second surfaces of the module substrate.. . ... Sk Hynix Inc

11/03/16 / #20160322976

Temperature sensing apparatus

An apparatus for temperature sensing may include: a bias generator suitable for generating a complementary-to-absolute-temperature (ctat) bias voltage; a regulator suitable for regulating a bias voltage by using ctat bias voltage and outputting a regulated bias voltage; and a ring oscillator suitable for receiving the regulated bias voltage and generating an oscillation signal based on the regulated bias voltage.. . ... Sk Hynix Inc

11/03/16 / #20160322382

Manufacturing method of semiconductor device

A method of manufacturing a semiconductor device includes forming on a lower structure, a first stack structure in which first material layers and second material layers are alternately stacked, forming, on the first stack structure, a second stack structure in which third material layers and fourth material layers are alternately stacked, forming preliminary holes penetrating the second stack structure, forming a fifth material layer covering the preliminary holes on the second stack structure to define a first air-gap inside the preliminary holes, and forming through holes connected to the preliminary holes by penetrating from the fifth material layer overlapping the preliminary holes to the first stack structure.. . ... Sk Hynix Inc

11/03/16 / #20160322376

Three-dimensional semiconductor device

Disclosed is a three-dimensional semiconductor device, including: a peripheral circuit; a memory cell array stacked on the peripheral circuit and including a memory region and a slimming region which are defined in a first direction, wherein the slimming region includes contact regions and step regions alternately defined in the first direction, wherein the slimming region further includes pad regions defined in a second direction orthogonal to the first direction, wherein the pad regions overlap with some of the contact regions and some of the step regions, wherein gate lines are included in the step regions and arranged in a step form in the first direction, and wherein gate lines are included in a region in which the contact regions, the step regions, and the pad regions overlap each other and have steps in the second direction.. . ... Sk Hynix Inc

11/03/16 / #20160322370

Semiconductor device and method of manufacturing the same

A semiconductor device includes a substrate having a memory array region and a peripheral region, isolation layers formed in the peripheral region to define an active region, offset insulating layers separated from each other and formed in the active region, and a gate electrode having edges overlapping with the offset insulating layers and arranged in the active region between the offset insulating layers.. . ... Sk Hynix Inc

11/03/16 / #20160322365

Semiconductor device having air gap, a method for manufacturing the same, a memory cell having the same and an electronic device having the same

A semiconductor device may include: a semiconductor substrate comprising a plurality of active regions and a device isolation region for isolating the plurality of active regions; and a conductive shield pillar formed in the device isolation region and connected to the semiconductor substrate. Each of the active regions may include: a body portion formed in the substrate; a pillar floating from the body portion and positioned over the body portion; a side portion provided over a side surface of the pillar and connected to the body portion; and an embedded spacer positioned between the side portion and the pillar, the pillar may be coupled to the substrate through the side portion.. ... Sk Hynix Inc

11/03/16 / #20160322364

Semiconductor device for reducing coupling capacitance

A semiconductor device includes a spacer having a nitride/oxide/nitride (non) structure. The spacer is disposed between a sidewall of a bit line and a bit line contact and a sidewall of a storage node contact plug to reduce coupling capacitance between the bit line and a storage node contact plug and between the bit line contact and the storage node contact plug.. ... Sk Hynix Inc

11/03/16 / #20160322297

Semiconductor device and manufacturing method thereof

A semiconductor device and a manufacturing method thereof are provided. A semiconductor device includes a stack structure including conductive layers stacked in a step shape, a first interlayer insulating layer formed over the stack structure, the first interlayer insulating layer including contact holes with a uniform depth, which expose the conductive layers, lower contact plugs formed in the contact holes, the lower contact plugs being respectively contacted with the conductive layers, and lower contact pads respectively connected to the contact plugs.. ... Sk Hynix Inc

11/03/16 / #20160322118

Parallel test device and method

A parallel test device and method are disclosed, which relates to a technology for performing a multi-bit parallel test by compressing data. The parallel test device includes: a pad unit through which data input/output (i/o) operations are achieved; a plurality of input buffers configured to activate write data received from the pad unit in response to a buffer enable signal, and output the write data to a global input/output (gio) line; a plurality of output drivers configured to activate read data received from the global i/o (gio) line in response to a strobe delay signal, and output the read data to the pad unit; and a test controller configured to activate the buffer enable signal and the strobe delay signal during a test mode in a manner that the read data received from the plurality of output drivers is applied to the plurality of input buffers such that the read data is operated as the write data.. ... Sk Hynix Inc

11/03/16 / #20160322087

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory apparatus including a plurality of pages coupled to a single word line; and a controller suitable for accessing the nonvolatile memory apparatus during one of first and second modes, wherein, the second mode is enabled when the nonvolatile memory apparatus has reached a lifetime limit, and wherein the controller stores the same data in both of a source page and a dummy page during the second mode.. . ... Sk Hynix Inc

11/03/16 / #20160320789

Semiconductor integrated circuit device having bulk bias control function and method of driving the same

A semiconductor integrated circuit device having a bulk bias control function is provided. The semiconductor integrated circuit device may be configured to output the first external voltage as a bulk voltage of a transistor in a power-up period, and to output a second external voltage having a higher level than the first external voltage as the bulk voltage of the transistor in a power-down mode.. ... Sk Hynix Inc

11/03/16 / #20160318184

System and method of controlling a robot

A system for controlling a robot moving vertically and horizontally using a motor is provided. The system includes a detector suitable for generating a feedback signal by detecting physical status of the motor; and a controller suitable for detecting loading of a substrate on the robot based on the feedback signal during a vertical moving interval of the robot, and generating a control command in accordance with the detection of the loading of the substrate.. ... Sk Hynix Inc

10/27/16 / #20160316561

Printed circuit boards having supporting patterns and method of fabricating the same

A printed circuit board includes an inner layer having a supporting pattern and via pad patterns that are disposed to be spaced apart from each other in a lateral direction, an outer layer disposed over or below the inner layer and including a circuit pattern, a via plug connecting the circuit pattern layer to any one of the via pad patterns. The supporting pattern is stiffer than the via pad patterns, and at least two of the via pad patterns are electrically connected to each other by a via pad connecting pattern located at substantially the same level as the via pad patterns.. ... Sk Hynix Inc

10/27/16 / #20160316559

Semiconductor packages having interconnection members

A semiconductor package may include a first substrate including a first connection portion disposed on a surface of the first substrate and a second substrate including a second connection portion disposed on a surface of the second substrate. The second substrate may be disposed over the first substrate and the second connection portion facing the first connection portion. ... Sk Hynix Inc

10/27/16 / #20160315602

Ramp signal generator and cmos image sensor using the same

Disclosed are a ramp signal generator capable of reducing the size of a feedback capacitor by using a current subtraction and a cmos image sensor using the same. The ramp signal generator may include a current supply unit suitable for supplying a first current; a current subtraction unit suitable for subtracting the first current from a second current, or the second current from the first current; and a ramp signal generation unit suitable for generating a ramp signal according to a third current and a reference voltage. ... Sk Hynix Inc

10/27/16 / #20160315592

Sense amplifier of semiconductor device

A sense amplifier of a semiconductor device is disclosed. The sense amplifier of a semiconductor device may include a pmos latch transistor and an nmos latch transistor formed in a cross-coupled latch type, and may be configured to sense and amplify a signal of a pair of bit lines. ... Sk Hynix Inc

10/27/16 / #20160315088

Semiconductor device having buried gate structure and method for manufacturing the same, memory cell having the same and electronic device having the same

A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer.. . ... Sk Hynix Inc

10/27/16 / #20160314854

Semiconductor memory device and method of operating the same

A semiconductor memory device includes a memory cell array having a first group of main blocks, a second group of main blocks and redundancy blocks replacing the first group of main blocks or the second group of main blocks, a repair logic suitable for enabling a replacement signal when one or more of the second group of main blocks are defective, a control logic suitable for generating an address for the second group of main blocks in response to a dedicated command for access to one or more of the second group of main blocks, and an address decoder suitable for selecting one or more of the redundancy blocks based on the address for the second group of main blocks when the replacement signal is enabled.. . ... Sk Hynix Inc

10/27/16 / #20160314842

Memory system and operating method thereof

A memory system includes: a memory device comprising at least a page; and a controller suitable for setting a seed offset according to a size of a restricted region in the page, randomizing data using the seed offset at each cycle, and storing the randomized data in the page.. . ... Sk Hynix Inc

10/27/16 / #20160314835

Electronic device and method for operating electronic device

An electronic device comprising a semiconductor memory unit that may a variable resistance element configured to be changed in its resistance value in response to current flowing through both ends thereof; an information storage unit configured to store switching frequency information corresponding to a switching frequency which minimizes an amplitude of a voltage to be applied to both ends of the variable resistance element to change the resistance value of the variable resistance element and switching amplitude information corresponding to a minimum amplitude; and a driving unit configured to generate a driving voltage with the switching frequency and the minimum amplitude in response to the switching frequency information and the switching amplitude information and apply the driving voltage to both ends of the variable resistance element.. . ... Sk Hynix Inc

10/27/16 / #20160314830

Semiconductor memory device

A semiconductor memory device may include: a plurality of banks suitable for performing an all bank refresh operation or single bank refresh operation; an address output control unit suitable for generating a plurality of output control signals in response to a single bank refresh pulse signal; an address latch unit suitable for outputting a target row address of a bank corresponding to an activated output control signal; and an address output unit suitable for outputting a row address adjacent to the target row address to a selected bank.. . ... Sk Hynix Inc

10/27/16 / #20160314041

Error correction circuit and semiconductor memory device including the same

An error correction circuit includes: a failure detection unit suitable for detecting failed data among a plurality of data; a data output control unit suitable for selectively outputting test data corresponding to a predetermined amount of data excluding the failed data; and an error correction unit suitable for performing a unit ecc operation on the test data.. . ... Sk Hynix Inc

10/27/16 / #20160313946

Controller adaptation to memory program suspend-resume

Memory systems may include a memory including a plurality of dies, and a controller suitable for receiving a host read request during programming of one of the plurality of dies; determining a suspendable die among the plurality of dies based on a suspension threshold; and suspending the determined suspendable die and performing the received request.. . ... Sk Hynix Inc

10/27/16 / #20160313931

Memory system and operating method thereof

A memory system includes a memory device including a plurality of memory chips, each of which includes a plurality of planes suitable for storing data and a plurality of page buffers respectively corresponding to the planes; and a controller suitable for transferring write data stored in a write buffer thereof to a first page buffer of a first chip, releasing the write buffer and a first plane corresponding to the first page buffer in the first chip after the transfer to the first page buffer, and programming the write data in the first planes after the release from the first plane.. . ... Sk Hynix Inc

10/27/16 / #20160313928

Storage device including memory controller and memory system including the same

Disclosed is a storage device, including: a memory controller configured to generate mode maintenance information or mode change information in response to a command received from a host; and a memory device configured to perform a selected operation in a previous mode when the mode maintenance information is received, and change a mode and perform the selected operation when the mode change information is received.. . ... Sk Hynix Inc

10/20/16 / #20160309109

Image sensing device

An image sensing device includes: a clock signal control block suitable for generating first and second clock control signals to have variable logic combinations for each unit row time; a frequency division block suitable for generating first and second clock signals having different phases based on a reference clock signal and controlling a first delay time reflected in the first clock signal and a second delay time reflected in the second clock signal for each unit row time based on the first and a second clock control signals; and a pixel signal processing block suitable for converting a pixel signal inputted for each unit row time into a digital signal based on the first and second clock signals.. . ... Sk Hynix Inc

10/20/16 / #20160308532

Semiconductor apparatus

A semiconductor apparatus may include an internal voltage level controller configured to output either a normal trimming code or a test voltage code as a voltage control code in response to a test mode signal, a specific operation start signal, and a specific operation end signal. The semiconductor apparatus may include an internal voltage generator configured to generate an internal voltage and control a voltage level of the internal voltage in response to the voltage control code.. ... Sk Hynix Inc

10/20/16 / #20160308127

Method for fabricating electronic device with variable resistance material layer

A method for fabricating an electronic device including a semiconductor memory may include: forming a first interlayer dielectric layer over a substrate to have an opening exposing the substrate; forming a bottom electrode in a portion of the opening to have an exposed top surface; forming a variable resistance material layer along sidewalls of the remaining portion of the opening and the exposed top surface of the bottom electrode; forming a top electrode over the variable resistance material layer so as to fill the opening; etching the first interlayer dielectric layer to a predetermined depth to expose a part of the variable resistance material layer surrounding sidewalls of the top electrode; and removing the part of the variable resistance material layer to form a unit cell.. . ... Sk Hynix Inc

10/20/16 / #20160308121

Electronic device

This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the pinned layer and the free layer, wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.. ... Sk Hynix Inc

10/20/16 / #20160308116

Electronic device and method for fabricating the same

This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a magnetic tunnel junction (mtj) structure including a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the pinned layer and the free layer; a magnetic correction layer located under the mtj structure and operates to reduce an influence of a stray magnetic field generated by the pinned layer; and an under layer located under the magnetic correction layer and including a metal oxide layer.. ... Sk Hynix Inc

10/20/16 / #20160308114

Electronic device

Provided an electronic device including a semiconductor memory. The semiconductor memory may include: a selecting element; a variable resistance element electrically coupled to the selecting element through a first conductive plug; a first line electrically coupled to the variable resistance element through a second conductive plug; a second line electrically coupled to the selecting element through a third conductive plug; and one or more barrier layers arranged to form one or more electrical connections with the variable resistance element or the selecting element or the both and operated as an insulator or conductor according to a resistance state of the variable resistance element during a read operation.. ... Sk Hynix Inc

10/20/16 / #20160308113

Electronic device

An electronic device is provided to include a semiconductor memory including a variable resistance element. The variable resistance element may include a variable resistance pattern including a first electrode layer, a variable resistance layer, and a second electrode layer that are sequentially stacked; and a switching assist structure spaced from a side wall of the variable resistance pattern to surround the variable resistance pattern and including multilayered conductive structures that are vertically spaced from one another.. ... Sk Hynix Inc

10/20/16 / #20160308047

Semiconductor device and method for manufacturing the same

A semiconductor device and a method for manufacturing the same are disclosed, which include a gate electrode material in a recess or a buried gate cell structure, a polysilicon material doped with impurities over a sidewall of a recess located over the gate electrode material, and a junction formed by an annealing or a rapid thermal annealing (rta) process, thereby establishing a degree overlap between a gate electrode material of a buried gate and a junction.. . ... Sk Hynix Inc

10/20/16 / #20160308030

Semiconductor device having a gate that is buried in an active region and a device isolation film

A semiconductor device includes an active region with a first gate trench formed when a gate region is etched to a first depth, a device isolation film defining the active region and including a second gate-trench formed when a gate region is etched to a second depth, a gate buried below the first gate trench and the second gate trench, and a source plug and a drain plug formed when a conductive material is deposited in a source region and a drain region of the active region.. . ... Sk Hynix Inc

10/20/16 / #20160307999

Semiconductor device having air gap and method for manufacturing the same, memory cell having the same and electronic device having the same

A semiconductor device including a substrate including an active region and a device isolation region that isolates the active region, and a buried bit line and a buried gate electrode formed in the substrate. The device isolation region includes a first device isolation region extending in a first direction and a second device isolation region extending in a second direction crossing with the first direction and having an formed air gap.. ... Sk Hynix Inc

10/20/16 / #20160307962

Electronic device

An electronic device may be provided to include: first and second active regions arranged adjacent to each other in a second direction; a gate structure extended in the second direction; a first source region and a first drain region formed in the first active region; a second source region and a second drain region formed in the second active region; a source line contact formed over the first and second source regions and connected to the first and second source regions; a source line connected to the source line contact over the source line contact and extended in a first direction; first and second stacked structures formed over the first and second drain regions; and first and second bit lines formed over the first and second stacked structures, wherein the first and second bit lines are extended in the first direction.. . ... Sk Hynix Inc

10/20/16 / #20160307900

Semiconductor device having air gap and method for manufacturing the same, memory cell having the same and electronic device having the same

A semiconductor device including a semiconductor substrate including a plurality of active regions and a device isolation region for isolating the plurality of active regions; and a buried bit line and a buried gate electrode which are formed in the semiconductor substrate. The device isolation region includes a first device isolation region extending in a first direction and a second device isolation region extending in a second direction crossing with the first direction and having a shield pillar formed therein.. ... Sk Hynix Inc

10/20/16 / #20160307867

Semiconductor packages including interconnection members

A semiconductor package may include a main substrate, a sub-substrate spaced apart from the main substrate by a gap, and a semiconductor chip disposed on the main substrate. The semiconductor package may include an interconnection member configured to connect the semiconductor chip to the sub-substrate and including twisted wires of a plurality of strands. ... Sk Hynix Inc

10/20/16 / #20160307846

Semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device includes forming stepped stack structures each including conductive patterns stacked in a shape of steps while exposing respective ends thereof and surrounding channel layers, the stepped stack structures being separated from one another by slits, forming first and second contact plugs connected to the ends of the conductive patterns to extend along an extending direction of the channel layers, and simultaneously forming, using a spacer patterning technology (spt), bit lines connected to one or more of the channel layers and extending along a first direction, first connecting lines extending along a second direction intersecting the first direction, and contact pads extending from the first connecting lines to be connected to the first contact plugs.. . ... Sk Hynix Inc

10/20/16 / #20160307644

Built-in self-test circuit and semiconductor device including the same

A built-in self-test circuit includes a command storage unit that stores commands inputted from an external device, an input/output control unit that controls the command storage unit to sequentially store the commands and sequentially output stored commands as internal commands in a test operation, and a command decoder unit that decodes the internal commands outputted from the command storage unit and outputs a test command.. . ... Sk Hynix Inc

10/20/16 / #20160307639

Semiconductor device and method of driving the same

A semiconductor device may include: a control block suitable for generating a boot-up select signal in response to a boot-up mode signal and a fuse select signal; and a fuse block suitable for performing a program operation of rupturing one or more first fuse cells among a plurality of fuse cells in response to the fuse select signal, and performing a boot-up operation on a partial fuse region including the one or more first fuse cells in response to the boot-up select signal.. . ... Sk Hynix Inc

10/20/16 / #20160307625

Electronic device

An electronic device includes a semiconductor memory unit, which includes resistive memory cells; an access circuit to apply, during a write operation, a write voltage across a selected one of the resistive memory cells in a first or second direction; first switching units, each of which is disposed between the access circuit and a first end of a corresponding one of the resistive memory cells and turned on in response to a first voltage having a level higher than a predetermined level when the corresponding resistive memory cell is selected during the write operation; and second switching units, each of which is disposed between the access circuit and a second end of the corresponding resistive memory cell and turned on in response to a second voltage having a level equal to or lower than the predetermined level when the corresponding resistive memory cell is selected during the write operation.. . ... Sk Hynix Inc

10/20/16 / #20160307618

Sense amplifier and semiconductor device for securing operation margin of sense amplifier

A sense amplifier includes an equalization unit configured to precharge a pair of bit lines to a level of a bit line precharge voltage in response to a bit line equalizing signal; and an amplification unit configured to sense and amplify voltages of the pair of bit lines, supply, during an active operation, a ground voltage to a pull-down node of a latch section, and supply, when a precharge signal is enabled, a first voltage lower than the ground voltage to the pull-down node of the latch section for a predetermined time.. . ... Sk Hynix Inc

10/20/16 / #20160307616

Semiconductor devices and semiconductor systems

A semiconductor device may include a power control signal generator and a sense amplifier circuit. The power control signal generator may generate a first power control signal, an enablement moment of the first power control signal controlled according to a logic level combination of temperature code signals in response to a mode signal. ... Sk Hynix Inc

10/20/16 / #20160307614

Semiconductor apparatus

A semiconductor apparatus may include: a data storage group including first to eight data storage areas; a first channel select pad configured to transmit a first channel select signal to the first and third data storage areas; a second channel select pad configured to transmit a second channel select signal to the second and fourth data storage areas; a third channel select pad configured to transmit the first channel select signal to the sixth and eighth data storage areas; a fourth channel select pad configured to transmit the second channel select signal to the fifth and seventh data storage areas; a first clock enable pad configured to transmit a first clock enable signal to the first and third data storage areas; a second clock enable pad configured to transmit a second clock enable signal to the second and fourth data storage areas; a third clock enable pad configured to transmit the first clock enable signal to the fifth and seventh data storage areas; and a fourth clock enable pad configured to transmit the second clock enable signal to the sixth and eighth data storage areas.. . ... Sk Hynix Inc

10/20/16 / #20160306756

Memory system, memory module and method to backup and restore system using command address latency

A memory system having a plurality of memory devices includes a controller for separately accessing the memory devices. The memory system includes a data bus for transferring data, a control bus for transferring a command and address cal, and first and second memory devices coupled to the data bus and the control bus. ... Sk Hynix Inc

10/20/16 / #20160306381

Semiconductor devices and semiconductor systems including the same

The semiconductor device includes a command generator, an information signal storage unit, a termination signal generator and a code generator. The command generator generates a mode register write command signal, a start command signal and a termination command signal from external command signals. ... Sk Hynix Inc

10/20/16 / #20160306273

Photo mask including pre-alignment keys and photolithography apparatus performing a pre-alignment process for the photo mask

A photo mask includes a pre-alignment key used in a pre-alignment process performed in a photolithography apparatus. The pre-alignment key includes a pre-alignment pattern including a light transmitting area and a light blocking area surrounding the pre-alignment pattern. ... Sk Hynix Inc

10/20/16 / #20160305983

Interposer for inspecting semiconductor chip

An interposer for inspecting reliability of a semiconductor chip is disclosed. The interposer for inspection includes: at least one active pad disposed in an active region of a first surface, and including: pads through which data and a control signal for testing an inspection target chip are received (input) and sent (output) during an active mode; and pads for receiving a power-supply voltage needed to operate the inspection target chip and the interposer during the active mode; at least one passive pad disposed in a passive region of the first surface, and including: pads receiving data for testing the inspection target chip during a passive mode, and a power-supply voltage needed to operate the inspection target chip and the interposer during the passive mode; and at least one bump pad disposed over a second surface facing the first surface, and to be coupled to the inspection target chip.. ... Sk Hynix Inc

10/13/16 / #20160301883

Ramp signal generator and cmos image sensor using the same

A ramp signal generator and a cmos image sensor using the same are disclosed. The ramp signal generator includes a reference voltage generation unit that generates a reference voltage, a gain adjustment unit that adjusts a gain in cooperation with the reference voltage generation unit, a ramp bias voltage sampling unit that samples a ramp bias voltage of the gain adjustment unit, and a ramp signal generation unit that generates a ramp signal according to the ramp bias voltage sampled in the ramp bias voltage sampling unit.. ... Sk Hynix Inc

10/13/16 / #20160301550

Transmitting device for high speed communication, interface circuit and system including the same

A transmission device may include a main driver configured to drive an output node based on an input signal, and may generate an output signal with multiple levels. The transmission device may include a variable emphasis driver configured to drive the output node with various driving forces based on transition information of the input signal.. ... Sk Hynix Inc

10/13/16 / #20160301412

Power control device

A power control is disclosed, which relates to a technology for stably performing a power ramp-up operation during a power-up operation of an integrated circuit (ic) having heterogeneous power. The power control device includes: an amplifier configured to perform level shifting of a second power-supply voltage level to a first power-supply voltage level according to an input signal during an initial power-up operation section, and output the level-shifted output signal; an initialization unit configured to set an output signal level of the amplifier to the first power-supply voltage level according to a control signal during the initial power-up operation section, and output the first power-supply voltage level; and a latch unit configured to latch an output signal of the initialization unit according to the second power-supply voltage level during the initial power-up operation section.. ... Sk Hynix Inc

10/13/16 / #20160301402

Semiconductor integrated circuit apparatus

A semiconductor integrated circuit apparatus may include a clock-distributing unit, an internal circuit unit and an output-controlling unit. The clock-distributing unit may drive an input clock to output a distribution clock. ... Sk Hynix Inc

10/13/16 / #20160301393

Semiconductor device

A semiconductor device includes: a pre-emphasis control signal generation block suitable for generating first and second pre-emphasis control signals for controlling a pre-emphasis operation; at least one first output driver suitable for being selectively enabled in response to a selection code signal and driving a pad in response to a first output signal; and at least one second output driver suitable for being selectively enabled in response to the selection code signal and the first pre-emphasis control signal, performing the pre-emphasis operation with a driving force corresponding to a calibration code signal, and performing the pre-emphasis operation with a maximum driving force in response to the second pre-emphasis control signal.. . ... Sk Hynix Inc

10/13/16 / #20160301390

Integrated circuit

An integrated circuit includes a first signal generation unit suitable for generating a first enable signal which is activated during an initial setting period; a second signal generation unit suitable for generating a second enable signal which is activated in response to a command for performing a preset operation, after the initial setting period; and a temperature code generation unit suitable for generating temperature codes in response to activation of the first and second enable signals.. . ... Sk Hynix Inc

10/13/16 / #20160300886

Vertical transistor and variable resistive memory device including the same

A vertical transistor may include a pillar, a gate and an electric field-buffering region. The pillar may be vertically extended from a surface of a semiconductor substrate. ... Sk Hynix Inc

10/13/16 / #20160300873

Pixel amplification apparatus, cmos image sensor including the same and operation method thereof

Disclosed are a pixel amplification apparatus and a cmos image sensor thereof. The pixel amplification apparatus includes a pixel bias sampling unit that samples a first pixel bias voltage, a pixel bias current supply unit that supplies an output node of a pixel signal with a first pixel bias current based on a sampled bias voltage outputted from the pixel bias sampling unit, and a pixel bias current adding unit that additionally supplies the output node with a second pixel bias current in response to a second pixel bias voltage and a period control signal.. ... Sk Hynix Inc

10/13/16 / #20160300843

Anti-fuse, anti-fuse array and method of operating the same

An anti-fuse, an anti-fuse array and a method of operating the same are disclosed. The anti-fuse array includes: an active region formed in a semiconductor substrate; a slit region formed at both edge portions of the active region in a first direction; a plurality of select gates extending in a second direction perpendicular to the first direction of the active region, and coupled to a select word line; a plurality of first program gates spaced apart from the select gates, formed over the active region isolated by the slit region, and coupled to a first program word line; a plurality of second program gates spaced apart from the select gates, formed over the active region isolated by the slit region, and coupled to a second program word line; and a bit line perpendicular to the select word line.. ... Sk Hynix Inc

10/13/16 / #20160300818

Semiconductor device

A semiconductor device includes a package substrate having a plurality of external connection terminals disposed on a first surface thereof and a plurality of internal connection terminals disposed on a second surface thereof and electrically connected with corresponding one of the external connection terminals, a first semiconductor chip stacked over the second surface of the package substrate and having a first flag pad for providing first information and a first internal circuit for adjusting a parameter by a first correction value in response to the first information provided from the first flag pad, and a second semiconductor chip stacked over the first semiconductor chip and having a second flag pad for providing second information and a second internal circuit for adjusting the parameter by a second correction value in response to the second information provided from the second flag pad.. . ... Sk Hynix Inc

10/13/16 / #20160300815

Semiconductor packages with interposers and methods of manufacturing the same

A semiconductor package may include a first semiconductor chip, a second semiconductor chip disposed to overlap with a portion of the first semiconductor chip and connected to the first semiconductor chip through first coupling structures. The semiconductor package may include an interposer disposed to overlap with another portion of the first semiconductor chip and may be connected to the first semiconductor chip through second coupling structures. ... Sk Hynix Inc

10/13/16 / #20160300787

Substrates and semiconductor packages including the same, electronic systems including the semiconductor packages, and memory cards including the semiconductor packages

A substrate may include a body having a first surface and a second surface opposite to each other, at least one first wiring pattern disposed on the first surface of the body to include a bonding finger, an upper insulating pattern disposed on the first surface of the body to cover the overall surface of the at least one first wiring pattern except the bonding finger, and a second wiring pattern disposed on the second surface of the body. The substrate may include a lower insulating pattern disposed on the second surface of the body to cover the second wiring pattern, and a first via electrode penetrating the body from the first surface to the second surface and coupling the at least one first wiring pattern to the second wiring pattern. ... Sk Hynix Inc

10/13/16 / #20160300627

Semiconductor memory device

A semiconductor memory device includes a first fuse set block including a fuse array for storing first repair information, and a control block configured to store second repair information in a first mode, and generate an output control signal when input addresses applied from an external source and the second repair information are the same, in a second mode, wherein the first fuse set block enables a first match signal for accessing a first redundancy memory cell when the stored first repair information and the input addresses are the same, and disables the first match signal in response to the output control signal.. . ... Sk Hynix Inc

10/13/16 / #20160300626

Semiconductor system and method for testing semiconductor device

A semiconductor device includes a plurality of first input pins; a parity check unit suitable for performing a parity check for command/address signals inputted to the plurality of first input pins, and determining the parity check result as a pass or fail; and one or more registers suitable for storing the inputted command/address signals when the parity check result is determined as the fail, wherein during a test operation, the number of signals having a first logic value among the command/address signals inputted to the plurality of first input pins does not correspond to the logic value of a parity bit.. . ... Sk Hynix Inc

10/13/16 / #20160300625

Semiconductor apparatus and test method thereof

A semiconductor apparatus may include a first data processing block electrically coupled between a first input/output pad array and a first memory array. The semiconductor apparatus may include a second data processing block electrically coupled between a second input/output pad array and a second memory array. ... Sk Hynix Inc

10/13/16 / #20160300624

Semiconductor memory apparatus, repair system therefor, and method for managing apparatus quality

A semiconductor memory apparatus may include a chip area configured to include one or more semiconductor memory chips. The semiconductor memory apparatus may include a repair system configured to perform a test for the chip area while the chip area is in a test mode, to determine whether the chip area has been repaired, and to generate the determination of whether the chip area has been repaired as quality information in response to a failure detection signal enabled while the chip area is in the test mode.. ... Sk Hynix Inc

10/13/16 / #20160300615

Non-volatile semiconductor memory device and improved verfication and programming method for the same

Provided herein are semiconductor memory devices and operating methods thereof. A semiconductor memory device may include a memory cell array including a plurality of cell strings, and a peripheral circuit. ... Sk Hynix Inc

10/13/16 / #20160300611

Volatile memory, memory module including the same, and method for operating the memory module

A memory module includes an emergency power supplier, a plurality of ranks each including one or more volatile memories, a non-volatile memory, and a controller suitable for backing up data of the ranks into the non-volatile memory by using the emergency power supplier during a power failure, wherein the ranks are sequentially backed up, and while one rank is backed up among the ranks, the other ranks are controlled in a self-refresh mode.. . ... Sk Hynix Inc

10/13/16 / #20160300603

Stacked memory device and system

A stack memory device may include a core chip and a base chip. The core chip may include a data receiver, a strobe signal generation unit, and a test register. ... Sk Hynix Inc

10/13/16 / #20160300602

Semiconductor memory apparatus

A semiconductor memory apparatus may include: a command decoder configured to decode an external command and output the decoded command as an internal command; a command transmitter configured to determine a delay time in response to a voltage level of an external voltage being applied to the semiconductor memory apparatus, delay the internal command by the determined delay time, and output the delayed internal command as a delayed command; and a data storage area configured to receive the delayed command, and perform an operation according to the delayed command.. . ... Sk Hynix Inc

10/13/16 / #20160299687

Controller transmitting output commands and method of operating the same

A controller includes a host command sensor suitable for generating a target ratio between first typed host commands and second typed host commands; an output command generator suitable for generating first and second typed output commands respectively corresponding to the first and second typed host commands; and an arbiter suitable for sequentially transmitting the first and second typed output commands from the output command queue to a channel, and generating a channel ratio between first and second typed output commands transmitted from to the output command queue to the channel. The arbiter transmits one of the first and second typed output commands from the output command queue to the channel by comparing the channel ratio with the target ratio.. ... Sk Hynix Inc

10/13/16 / #20160299427

Method of forming fine patterns

A method of forming fine patterns includes performing an exposure process to generate acids in first regions of a chemically amplified resist (car) layer, removing the exposed first regions using a first development process to form a first resist pattern, diffusing acids in sidewall portions of the first resist pattern into a bulk region of the first resist pattern to form second regions in which the acids are diffused and to form a plurality of third regions between the second regions, and removing the third regions using a second development process to form second resist patterns.. . ... Sk Hynix Inc

10/13/16 / #20160299190

Semiconductor apparatus and test method thereof

A semiconductor apparatus includes a plurality of through-silicon vias, and a self repair block. The self repair block charges the plurality of through-silicon vias for a preset threshold time so that pass-state through-silicon vias reaches a reference voltage level, make pass/fail decisions according to voltage levels of the plurality of through-silicon vias, and repair a through-silicon via which is in a fail state.. ... Sk Hynix Inc

10/06/16 / #20160295698

Semiconductor package modules, memory cards including the same, and electronic systems including the same

A semiconductor package module may include a first substrate, and a second substrate disposed to face the first substrate. The semiconductor package module may include an interconnection member electrically connecting the first substrate to the second substrate and including a plurality of wires. ... Sk Hynix Inc

10/06/16 / #20160295150

Counting apparatus and image sensor including the same

A counting apparatus that includes a global counting unit suitable for performing a counting operation by controlling a counting bit number based on a count masking signal; a one-shot pulse generation unit suitable for generating a storage instruction signal based on the count masking signal; a latch unit suitable for storing a counting value outputted from the global counting unit based on the storage instruction signal; and a storage unit suitable for storing the counting value loaded from the latch unit.. . ... Sk Hynix Inc

10/06/16 / #20160295143

Pixel amplification apparatus and cmos image sensor including the same

A pixel amplification apparatus includes a single common current source suitable for supplying an identical current to columns, a plurality of column selection units each suitable for selecting each column to allow a corresponding current to flow, a plurality of pixel bias sampling units each suitable for sampling the corresponding current flowing through each of the column selection units as a pixel bias, and a plurality of amplification units each suitable for amplifying to a pixel signal based on the sampled pixel bias.. . ... Sk Hynix Inc

10/06/16 / #20160294391

Semiconductor devices

A semiconductor device may include a data output circuit and control signal output circuit. The data output circuit may convert a first input signal and a second input signal sequentially inputted thereto into output data and may compare the first and second input signals with a storage datum to generate a first comparison signal and a second comparison signal. ... Sk Hynix Inc

10/06/16 / #20160294193

Voltage generator

A voltage generator includes a first voltage generation unit and a second voltage generation unit suitable for generating a second power supply voltage using a first power supply voltage, and being selectively driven, and a control signal generation unit suitable for activating the first voltage generation unit until the second power supply voltage reaches a specific level and activating the second voltage generation unit after the second power supply voltage reaches the specific level. The first voltage generation unit has less driving ability than the second voltage generation unit.. ... Sk Hynix Inc

10/06/16 / #20160293836

Platinum and cobalt/copper-based multilayer thin film having low saturation magnetization and fabrication method thereof

A multilayer thin film for magnetic random access memory that includes thin platinum layers and thin cobalt-copper layers, and more particularly, to a multilayer thin film having magnetic layers including non-magnetic material copper that replaces a portion of the magnetic material cobalt.. . ... Sk Hynix Inc

10/06/16 / #20160293615

Nonvolatile memory cells, nonvolatile memory cell arrays including the same, and methods of fabricating the same

Nonvolatile memory devices includes a charge storage element having a mos capacitor structure and including a control gate terminal connected to a word line and a body terminal connected to a body bias line, a first half-mos transistor having a first selection gate terminal connected to the word line and a first impurity junction terminal connected to a bit line and sharing the body terminal with the charge storage element, and a second half-mos transistor having a second selection gate terminal connected to the word line and a second impurity junction terminal connected to a source line and sharing the body terminal with the charge storage element. The charge storage element is coupled between the first and second half-mos transistors so that the first half-mos transistor, the charge storage element, and the second half-mos transistor are connected in series.. ... Sk Hynix Inc

10/06/16 / #20160293612

Antifuse memory cells and arrays thereof

An antifuse memory cell includes an antifuse element and a gate pn diode. The antifuse element includes a gate terminal coupled to a word line, a drain terminal coupled to a bit line, and a body terminal. ... Sk Hynix Inc

10/06/16 / #20160293565

Semiconductor packages with socket plug interconnection structures

A semiconductor package may include a first substrate and a second substrate. Socket bumps may be disposed on the first substrate to provide insertion grooves within the socket bumps. ... Sk Hynix Inc

10/06/16 / #20160293486

Method for fabricating electronic devices having semiconductor memory unit

Devices and methods based on disclosed technology include, among others, an electronic device including silicide layers capable of effectively reducing contact resistance in the electronic device including buried gates and a method for fabricating the electronic device. Specifically, an electronic device in one implementation includes a plurality of buried gates formed in a substrate and silicide layers formed over the substrate between the buried gates and protruding upwardly from the buried gates.. ... Sk Hynix Inc

10/06/16 / #20160293443

Methods of forming different sized patterns

A method includes forming a template portion to provide a first opening trench portion surrounding a first isolated pattern, and forming an array of pillars on an underlying layer; forming a separation wall layer including first separation wall portions surrounding sidewalls of the pillars, and forming second separation wall portions covering sidewalls of the first opening trench portion; forming a block copolymer layer on the separation wall layer; forming first domains in gaps between the pillars, and forming second domains surrounding and separating the first domains by annealing the block copolymer layer; forming second openings by selectively removing the first domains; forming third openings between the second openings, and forming a fourth opening adjacent to the first isolated pattern by selectively removing the pillars and the template portion; and forming fifth openings, which extend from the second and third openings and penetrate the underlying layer, and forming a sixth opening, which extends from the fourth opening and penetrates the underlying layer.. . ... Sk Hynix Inc

10/06/16 / #20160293442

Methods of forming patterns

A method of forming patterns includes forming an array of pillars on an underlying layer stacked on an etch target layer, forming a separation wall layer on the pillars to provide separation walls covering sidewalls of the pillars, forming a block copolymer layer on the separation wall layer, annealing the block copolymer layer to form first domains located between the pillars, and a second domain surrounding and isolating the first domains, selectively removing the first domains to form second openings, selectively removing the pillars to form fourth openings, forming fifth openings that extend from the second and fourth openings to penetrate the underlying layer, forming a sealing pattern that covers and seals dummy openings among the fifth openings, and forming seventh openings that extend from the fifth openings exposed by the sealing pattern to penetrate the etch target layer.. . ... Sk Hynix Inc

10/06/16 / #20160293278

Semiconductor memory device and operating method thereof

A semiconductor memory device may include: a plurality of first to third memory cells, each memory cell being a dram memory cell; a plurality of fuses suitable for storing repair information for replacing failed first memory cells with corresponding second memory cells; a normal operation unit suitable for accessing and refreshing one or more of the first and second memory cells according to the repair information during a normal mode; and a repair operation unit suitable for providing the repair information from the fuses to the third memory cells during a boot-up mode, and for providing the repair information from the third memory cells to the normal operation unit and for refreshing the third memory cells during a normal mode.. . ... Sk Hynix Inc

10/06/16 / #20160293275

Semiconductor memory device outputting status fail signal and operating method thereof

In a method of operating a semiconductor memory device, a program command is received, and a program operation is performed to increase threshold voltages of memory cells to be programmed by applying a program pulse to a word line. Page data is read from the selected memory cells by applying a verification voltage to the word line, and it is determined whether the number of memory cells corresponding to a program pass is greater than a determined number, based on the page data. ... Sk Hynix Inc

10/06/16 / #20160293271

Semiconductor device and operating method thereof

A method of operating a semiconductor memory device includes applying a program pulse at least once to each of a plurality of pages; performing a pre-read operation on a reference page among the plurality of pages through an initial test voltage; repeating the pre-read operation by controlling the initial test voltage until a result of the pre-read operation is a pass; setting the initial test voltage of when the result of the pre-read operation is the pass as a reference test voltage; and detecting a defective page among the plurality of pages by performing read operations on the plurality of pages through the reference test voltage.. . ... Sk Hynix Inc

10/06/16 / #20160293267

Semiconductor memory device and memory system including the same

A semiconductor memory device includes a command buffering unit suitable for receiving and buffering a command signal based on an enable control signal, a fuse array suitable for programming data based on the command signal, and an enable control unit suitable for generating the enable control signal, wherein an activation operation on the command buffering unit by the enable control signal is controlled during a programming operation period of the fuse array.. . ... Sk Hynix Inc

10/06/16 / #20160293259

Semiconductor apparatus and operating method thereof

A nonvolatile memory apparatus includes a plurality of memory cells coupled to a word line and respectively coupled to different bit lines, and a control block configured to apply one or more program voltages to the word line in a program loop, and increase the one or more program voltages in increments each time of the program loop is repeated, wherein at least one of the increments is different.. . ... Sk Hynix Inc

10/06/16 / #20160293243

Semiconductor memory device

A semiconductor memory device may include a memory bank having a plurality of word lines arranged at a predetermined address interval, an address latching unit suitable for storing a target address corresponding to a target word line of the plurality of word lines, and a refresh control unit suitable for performing a refresh operation on first to nth word lines having different address intervals from the target word line based on the target address in response to a smart refresh command, wherein n is a natural number.. . ... Sk Hynix Inc

10/06/16 / #20160293238

Semiconductor integrated circuit including cas latency setting circuit

A semiconductor memory apparatus includes a cas latency setting circuit configured to change an initially-set cas latency value in response to control signal pulses which are sequentially applied, during a test mode without changing settings of a mode register set during each test.. . ... Sk Hynix Inc

10/06/16 / #20160293235

Control signal generation circuit and non-volatile memory device including the same

A control signal generation circuit may include: a counting unit suitable for generating counting information; a first signal generation unit suitable for activating/deactivating a first signal based on the counting information, first rising information, and first falling information; a second signal generation unit suitable for activating/deactivating a second signal based on the counting information, second rising information, second falling information, and the first falling information; and a control signal driving unit suitable for driving a control signal in response to the first and second signals.. . ... Sk Hynix Inc

10/06/16 / #20160293233

Semiconductor memory apparatus

A semiconductor memory apparatus includes a driving current control block configured to sense a resistance value of a dummy memory element, and generates a write driver control signal; and a write driving block configured to provide a driving voltage to a memory cell array in response to a write driver enable signal and the write driver control signal.. . ... Sk Hynix Inc

10/06/16 / #20160293229

Memory device and operation method thereof

A memory device may include a plurality of cell arrays, a first interface suitable for inputting/outputting first data between the plurality of cell arrays and a host apparatus, a second interface suitable for inputting/outputting second data between the plurality of cell arrays and a device other than the host apparatus, and a data erasure circuit suitable for erasing the first data of the plurality of cell arrays when a first mode in which the first interface is used switches to a second mode in which the second interface is used.. . ... Sk Hynix Inc

10/06/16 / #20160293228

Memory device and operation method thereof

A memory device may include a cell array including a plurality of memory cells and a bit line coupled to the plurality of memory cells; a sense amplifier suitable for amplifying a voltage difference between a first line and a second line; and a separation unit suitable for electrically coupling the bit line and the first line, and electrically separating the bit line and the first line during an initial period of an operation of the sense amplifier.. . ... Sk Hynix Inc

10/06/16 / #20160292090

Data processing system capable of controlling peripheral devices using group identification information and control method thereof

A data processing system includes a plurality of peripheral devices in which device identification information and group identification information are stored, and a controller. The peripheral devices of the same species device group have the same group identification information, and peripheral devices from different peripheral device groups have different group identification information. ... Sk Hynix Inc

10/06/16 / #20160291878

Memory controller including host command queue and method of operating the same

Disclosed is a memory controller, including: a host interface suitable for queueing a plurality of host commands from a host in a host command queue; a state register suitable for storing ready set bits respectively corresponding to the plurality of host commands; a memory command generating unit suitable for generating and queueing memory commands and state update information corresponding to the queued host commands in a memory command queue, respectively; and the memory command performing unit suitable for performing an operation in response to the queued memory commands. The memory command performing unit obtains state update information corresponding to the performed memory command from the memory command queue, and updates a ready set bit of a host command corresponding to the performed memory command based on the obtained state update information.. ... Sk Hynix Inc

10/06/16 / #20160291871

Data storage device and operating method thereof

A data storage device capable of improving operation performance by optimizing internal operations is disclosed. The operation method of the data storage device includes grouping memory blocks based on the number of valid pages included in each of the memory blocks; and determining whether to perform a merging process on the groups of memory blocks based on a merging determination value.. ... Sk Hynix Inc

10/06/16 / #20160291630

Semiconductor devices and semiconductor systems

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output a training entry signal and a transmission signal. ... Sk Hynix Inc

10/06/16 / #20160291459

Photomask including transfer patterns for reducing a thermal stress

A photomask includes a light transmission substrate, and a transfer pattern disposed over the light transmission substrate, a shape of the transfer pattern being transferred onto a wafer by an exposure process. The transfer pattern comprises a first transfer pattern having a closed loop shape and having a first thickness, and a plurality of second transfer patterns disposed in an opening surrounded by the first transfer pattern, the plurality of second transfer patterns being arrayed in a first direction such that adjacent second transfer patterns are spaced apart from each other by a first distance, the second transfer patterns having a second thickness which is less than the first thickness of the first transfer pattern.. ... Sk Hynix Inc

10/06/16 / #20160291082

Semiconductor devices, semiconductor systems including the same, methods of testing the same

A semiconductor system includes a controller and a semiconductor device. The controller outputs a burn-in test signal, a clock signal and command/address signals. ... Sk Hynix Inc

10/06/16 / #20160290860

Image sensing device

An image sensing device includes a ramp voltage generation block suitable for generating a ramp voltage adjusted by a predetermined voltage in each predetermined cycle, based on a bias signal and a plurality of first ramp control signals; and a ramp voltage correction block suitable for correcting the ramp voltage in each predetermined cycle based on the bias signal and at least one second ramp control signal.. . ... Sk Hynix Inc

09/29/16 / #20160285372

Power driving device and semiconductor device including the same

. . A power driving circuit including a voltage generation unit configured to generate a release control signal and an output voltage. The power driving circuit including a release controller configured to enable a release signal during an activation section of a flag signal in response to the release control signal. ... Sk Hynix Inc

09/29/16 / #20160284992

Electronic device and method for fabricating the same

An electronic device includes a semiconductor memory. The semiconductor memory includes a vertical electrode layer formed over a substrate and extending in a vertical direction substantially perpendicular to a surface of the substrate; an interlayer dielectric layer and a structure formed over the substrate and alternately stacked along the vertical electrode layer, wherein the structure includes a horizontal electrode layer and a base layer which is conductive and located over or under the horizontal electrode layer; a variable resistance layer interposed between the vertical electrode layer and the base layer, and including a common element with the base layer; and a groove interposed between the vertical electrode layer and the horizontal electrode layer and insulating the vertical electrode layer and the horizontal electrode layer from each other.. ... Sk Hynix Inc

09/29/16 / #20160284818

Semiconductor device and method for forming the same

A semiconductor device is disclosed. The semiconductor device comprising: a semiconductor substrate having first type conductivity and including an active region and a device isolation film, a doping layer having second type conductivity and buried in a bottom part of the semiconductor substrate of the active region, a recess formed in the semiconductor substrate, a gate electrode provided in the recess.. ... Sk Hynix Inc

09/29/16 / #20160284791

Capacitor and semiconductor device including the same

A capacitor having a capacitance that is required by a device within a limited area. The capacitor may include: a first electrode, an insulation layer, and a second electrode, wherein the first electrode may include a plurality of first vertical electrodes and a plurality of first horizontal electrodes, wherein the plurality of first vertical electrodes are spaced apart from one another by a predetermined distance in a first direction and a second direction perpendicular to the first direction, wherein the plurality of first horizontal electrodes extend in a third direction obliquely crossing with the first direction and are connected with the plurality of first vertical electrodes disposed in the third direction, wherein the second electrode may include a plurality of second vertical electrodes and a plurality of second horizontal electrodes, wherein the plurality of second vertical electrodes are disposed between the plurality of first vertical electrodes in the first direction and the second direction, wherein the plurality of second horizontal electrodes extend in the third direction and are connected with the plurality of second vertical electrodes disposed in the third direction, and wherein the plurality of first vertical electrodes and the plurality of second vertical electrodes may pass through the insulation layer.. ... Sk Hynix Inc

09/29/16 / #20160284721

Semiconductor device and method of manufacturing the same

A semiconductor device may include a substrate provided in a peripheral region, first and second insulation pillars formed in the substrate, and a gate electrode extending in a first direction from over the first insulation pillar to over the second insulation pillar, wherein the gate electrode includes first and second etch stop patterns, wherein the first etch stop pattern extends in the first direction from inside the gate electrode to over the first insulation pillar, and wherein the second etch stop pattern extends in the first direction from inside the gate electrode to over the second insulation pillar.. . ... Sk Hynix Inc

09/29/16 / #20160284710

Method for forming buried bit line, semiconductor device having the same, and fabricating method thereof

A method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies separated from one another by a plurality of trenches; forming a protective layer with open parts to expose both sidewalls of each of the bodies; forming buried bit lines in the bodies by silicidizing exposed portions of the bodies through the open parts; and forming a dielectric layer to gap-fill the trenches and define air gaps between adjacent buried bit lines.. . ... Sk Hynix Inc

09/29/16 / #20160284423

Semiconductor memory apparatus

A semiconductor memory apparatus includes a plurality of stacked semiconductor dies including a first semiconductor die comprising a first internal circuit configured to control input timing of a test control signal that is output as a plurality of delayed test control signals to the plurality of stacked semiconductor dies according to the controlled input timing in response to a test mode signal.. . ... Sk Hynix Inc

09/29/16 / #20160284410

Semiconductor memory device

A semiconductor memory device includes a plurality of memory cells and an x-decoder. The plurality of memory cells are connected to a word line. ... Sk Hynix Inc

09/29/16 / #20160284391

Sense amplifier driving device and semiconductor device including the same

A sense amplifier driving device may include a sense amplifier driving block configured to supply a post overdriving voltage to a pull-up power line coupled to a sense amplifier, the post overdriving voltage supplied to the sense amplifier during a post overdriving operation period in correspondence to a pull-up driving signal. The sense amplifier driving device may include a driving signal generation block configured to compare a reference voltage, set by a voltage trimming signal, with a level of a power supply voltage, and generate the pull-up driving signal for controlling whether to perform a post overdriving operation.. ... Sk Hynix Inc

09/29/16 / #20160284389

Semiconductor memory device and driving method thereof

A semiconductor memory device includes a memory cell array, and a voltage generator suitable for generating voltages supplied to the memory cell array. The memory cell array includes cell strings each including memory cells extending in a first direction and arranged in a second direction and a third direction; bit lines extending in the second direction and electrically coupled to the cell strings; and word lines extending in the third direction and electrically coupled to corresponding memory cells, wherein the word lines includes dummy word lines. ... Sk Hynix Inc

09/29/16 / #20160284384

Semiconductor device including a redistribution layer

A semiconductor device may include a first redistribution layer configured to allow for input and output of a first signal through the first redistribution layer. The semiconductor device may include a second redistribution layer configured to allow for input and output of a second signal through the second redistribution layer. ... Sk Hynix Inc

09/29/16 / #20160283401

Memory system and operating method for improving rebuild efficiency

Methods may include after a power loss, determining a most recently saved section of a logical block addressing (lba) table, a previous section saved prior to the most recently saved section of the lba table, and a least recently saved section of the lba table, reading an open super block and updating entries in the lba table from the most recently saved section through to the least recently saved section, reading a newest closed super block from a plurality of closed super blocks and updating entries in the lba table from the previous section saved prior to the most recently saved section through to the least recently saved section, and reading an oldest super block and updating entries in the lba table in the least recently saved section.. . ... Sk Hynix Inc

09/29/16 / #20160283397

Memory system and operating method thereof

A memory system may include a memory device including a plurality of a super blocks a list, and a controller suitable for updating the list with block information regarding one of the super blocks when a super block is opened or closed; and at power up, reading the block information from the list and rebuilding a logical block addressing (lba) table based on the block information.. . ... Sk Hynix Inc

09/29/16 / #20160283323

Error detection using a logical address key

A logical address key is generated based at least in part on a logical address. Encoded data is generated by systematically error correction encoding the logical address key and write data. ... Sk Hynix Inc

09/29/16 / #20160283138

Memory system and operating method thereof

Memory systems may include a memory device with multiple dies, a first super block, and a second super block, the first super block including a first meta-page stored at a location on a die and the second super block including a second-meta page stored at a location on a die; and a controller suitable for reading the meta-pages in the super blocks, wherein the stored location of the first meta-page is staggered with respect to the stored location of the second meta-page such that the first meta-page and the second meta-page are read by the controller during a single read.. . ... Sk Hynix Inc

09/29/16 / #20160283120

Memory device and memory system including the same

A memory device may include an application chip set including a plurality of applications. The memory device may include a chip decoder configured to select one application among the applications in response to input data and a test fuse signal, and output function data so that a function to be performed by the selected application is selected.. ... Sk Hynix Inc

09/22/16 / #20160277691

Image sensing device and method for driving the same

An image sensing device may include a temperature estimation block suitable for generating a temperature code signal based on a temperature table in response to a digital code signal corresponding to a pixel signal, and a calibration block suitable for removing noise reflected in the pixel signal at current temperature in response to the temperature code signal.. . ... Sk Hynix Inc

09/22/16 / #20160277041

Incremental llr generation for flash memories

Methods for decoding information stored on a memory may include performing a hard read at an initial threshold and determining a first distribution percentage, performing a hard read at a subsequent threshold and determining a second distribution percentage, generating a least-likelihood ratio (llr) based on the hard reads performed at the initial and subsequent thresholds, and based on the first and second distribution percentages, and soft decoding the information based on the generated llr.. . ... Sk Hynix Inc

09/22/16 / #20160277010

Comparator, analog-to-digital converting system and method of driving the same

A comparator may include: a first comparison unit suitable for generating a comparison voltage by performing a comparison operation between a pixel signal and a ramp signal; a time point detection unit suitable for detecting specific timing points of the comparison operation in response to the comparison voltage and a reference voltage, and generating a detection signal corresponding to the specific timing points; a period determination unit suitable for determining an additional supply period in response to the detection signal and a period determination control signal; and an additional current supply unit suitable for supplying an additional current to the first comparison unit during the additional supply period.. . ... Sk Hynix Inc

09/22/16 / #20160276273

Semiconductor device with air gap and method for fabricating the same

A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the substrate in the memory cell region; forming a planar gate structure over the substrate in the peripheral circuit region; forming a bit line structure over the substrate in the memory cell region; forming a first air spacers over a sidewalls of the planar gate structure; and forming a second air spacers over a sidewalls of the bit line structure.. . ... Sk Hynix Inc

09/22/16 / #20160276261

Semiconductor device

A semiconductor device includes a first memory block and a second memory block in a cell region and a first transistor and a second transistor, respectively corresponding to the first and second memory blocks, in a pass transistor region located below the cell region, wherein each of the first and second transistors includes: a first gate electrode coupled to the first memory block and a second gate electrode coupled to the second memory block.. . ... Sk Hynix Inc

09/22/16 / #20160276039

Memory controller and operating method thereof

A method for operating a memory controller includes: performing a hard decision read operation to read hard decision data from a memory device; if a hard decoding for the hard decision data fails, assigning log likelihood ratio (llr) values to cells falling in a plurality of voltage regions corresponding to a plurality of read reference voltages; performing a soft decision read operation based on the llr values and a soft decoding for the soft decision data to generate an error free data; performing a read operation to read data from the memory device using each of the plurality of read reference voltages to generate raw data for each of the plurality of read reference voltages; and determining an optimal read reference voltage among the plurality of the read reference voltages based on the raw data and the error free data.. . ... Sk Hynix Inc

09/22/16 / #20160276036

System optimization in flash memories

Methods of determining distributions may include performing a number of hard reads, performing a number of background reads at a frequency based on the number of hard reads, and estimating a conditional probability density of a cell voltage based on the hard reads and the background reads.. . ... Sk Hynix Inc

09/22/16 / #20160276033

Nonvolatile memory device, operating method thereof, and test system having the same

A nonvolatile memory device may include a plurality of memory blocks. The nonvolatile memory device may include a controller configured to perform an erase operation by repeating an erase loop, and may generate and store a test result based on a pass erase loop count of the erase operation in response to a result processing command. ... Sk Hynix Inc

09/22/16 / #20160276003

Semiconductor memory apparatus and operating method thereof

A semiconductor memory apparatus may include: a memory area; and a controller including a register configured to store parameter setting data, and to provide the parameter setting data to the memory area based on a data transmission enable signal enabled according to a parameter setting command or parameter get command.. . ... Sk Hynix Inc

09/22/16 / #20160275998

Regulator circuit and semiconductor memory apparatus having the same

A regulator circuit may include a comparison unit configured to compare a reference voltage with a feedback voltage and generate a first switching signal. The regulator circuit may include a current supply unit configured to receive a pumping voltage, and determine a level of a second switching signal in response to the first switching signal. ... Sk Hynix Inc

09/22/16 / #20160275997

Voltage generation circuit, semiconductor memory apparatus having the same, and operating method thereof

A voltage generation circuit may include: a comparison unit configured to compare a reference voltage and a feedback voltage and output a comparison signal to a node; an output unit configured to generate an internal voltage and the feedback voltage according to a voltage level applied to the node; and a control unit configured to discharge the node when a level of the internal voltage drops to less than a preset level.. . ... Sk Hynix Inc

09/22/16 / #20160275994

Three-dimensional (3d) non-volatile semiconductor memory device for loading improvement

A three-dimensional (3d) non-volatile semiconductor memory device is disclosed. The three-dimensional (3d) non-volatile semiconductor memory device includes: a cell region having a plurality of memory cells; a page buffer formed to store data of the cell region in units of a page; a decoder formed below the cell region, configured to provide a word line voltage to word lines of the cell region; a first upper line formed above the cell region, configured to transfer the word line voltage; a lower interconnection structure formed below the cell region, configured to transfer the word line voltage to the decoder; and a first via disposed between the cell region and the page buffer, configured to couple the first upper line to the lower interconnection structure.. ... Sk Hynix Inc

09/22/16 / #20160274917

Memory system, computing system including the same and method of operating memory system

Disclosed is a memory system including: a semiconductor memory device; and a memory controller suitable for controlling the semiconductor memory device, and receiving a first command for accessing the semiconductor memory device, and a second command of a different type from that of the first command from a host. The memory controller completes preparation to perform an operation corresponding to the first command by performing a first booting operation when power is up, and outputs a first command ready signal to the host. ... Sk Hynix Inc

09/22/16 / #20160274808

Scalable spor algorithm for flash memories

Methods of sudden power off recovery may include reading dirty-block meta-pages from memory blocks on a dirty block list, recording mapping in formation in open-block meta-pages, serving host commands by looking up logical block addresses (lbas) in the dirty-block meta-pages and the open-block meta-pages and when an lba is not found in the dirty-block meta-pages and the open-block meta-pages, reading new mapping information from a dirty table and saving the new mapping information in host-write meta-pages.. . ... Sk Hynix Inc

09/22/16 / #20160274791

Memory system and operating method thereof

A memory system includes a memory device including a plurality of memory chips each including a plurality of memory blocks grouped as one or more super blocks, wherein the memory blocks each include a plurality of pages suitable for storing write data requested from a host, and a controller suitable for checking a size of the write data and free pages of the super blocks, determining a first super block corresponding to the checked size of the write data based on the checked free pages among the super blocks, and programming the write data in memory blocks of the first super block.. . ... Sk Hynix Inc

09/22/16 / #20160273961

Image sensor

An image sensor includes a light receiving section suitable for generating photocharges corresponding to incident light, a first driving section suitable for transferring a first output voltage corresponding to a first voltage to a first column line based on the photocharges, a second driving section suitable for transferring a second output voltage corresponding to a second voltage to a second column line based on the photocharges, and an output section suitable for outputting an image signal based on the first and second output voltages.. . ... Sk Hynix Inc

09/15/16 / #20160269169

Clock generation circuit

A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.. . ... Sk Hynix Inc

09/15/16 / #20160269039

Preamplifier, comparator and analog-to-digital converting apparatus including the same

A preamplifier may include: a common active load suitable for providing output impedance; an output polarity changing unit suitable for changing an output polarity of output nodes; a multi-differential input stage suitable for receiving an input voltage, a coarse ramping voltage, a fine ramping voltage and a common mode voltage, and sampling the common mode voltage and the coarse ramping voltage for amplification operations; and a coupling blocking unit suitable for blocking a coupling between the output nodes and input nodes that are included in the multi-differential input stage.. . ... Sk Hynix Inc

09/15/16 / #20160269014

Duty cycle correction circuit and image sensing device including the same

A duty cycle correction circuit includes an inversion block suitable for generating a first inverted clock that is in an inversion relationship with a first clock and a second inverted clock that is in an inversion relationship with a second clock, in response to the first clock and the second clock, and a correction block suitable for generating a first corrected clock having a corrected duty cycle relative to the first clock and a second corrected clock having a corrected duty cycle relative to the second clock, based on a logic state of the first clock, a logic state of the second clock, a logic state of the first inverted clock, and a logic state of the second inverted clock.. . ... Sk Hynix Inc

09/15/16 / #20160269013

Duty cycle correction circuit and image sensing device including the same

A duty cycle correction circuit includes a detection block suitable for detecting a duty cycle of a first clock in response to the first clock and a second clock, and a correction block suitable for generating a first corrected clock having a corrected duty cycle relative to the first clock and a second corrected clock having a corrected duty cycle relative to the second clock, based on a detection result of the detection block.. . ... Sk Hynix Inc

09/15/16 / #20160269005

Comparator, analog-to-digital converting apparatus including the same, and analog-to-digital converting method

A comparator includes a common mode voltage sampling unit suitable for sampling a common mode voltage based on a sampling control signal; a coarse ramping voltage sampling unit suitable for sampling a coarse ramping voltage based on the sampling control signal; a preamplifier suitable for amplifying a difference between an input voltage and the sampled coarse ramping voltage to output a coarse conversion result, and amplifying a difference between a fine ramping voltage and the sampled common mode voltage to output a fine conversion result; and a signal processing unit suitable for generating the sampling control signal based on the coarse conversion result, and generating a comparison signal based on the coarse conversion result and the fine conversion result.. . ... Sk Hynix Inc

09/15/16 / #20160268263

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate in which a cell region and contact regions located at both sides of the cell region are defined, a first source layer formed over the substrate, a second source layer formed over the first source layer, a reinforcement pattern formed in the second source layer, a stacked structure including conductive layers and insulating layers alternately stacked over the second source layer and the reinforcement pattern, channel layers passing through the stacked structure and the second source layer and electrically coupled to the second source layer, and an isolation insulating pattern passing through at least one top conductive layer of the conductive layers.. . ... Sk Hynix Inc

09/15/16 / #20160268262

Semiconductor device and method for forming the same

A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film; a gate electrode filled in the active region; a bit line contact structure coupled to an active region between the gate electrodes; and a line-type bit line electrode formed over the bitline contact structure. The bit line contact structure includes a bit line contact formed over the active region; and an ohmic contact layer formed over the bit line contact.. ... Sk Hynix Inc

09/15/16 / #20160267956

Mram with magnetic material surrounding contact plug

This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a contact plug which is disposed over a substrate and extends in a vertical direction; a variable resistance element which is coupled to the contact plug and includes a first magnetic layer having a variable magnetization direction, a second magnetic layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the first magnetic layer and the second magnetic layer; and a third magnetic layer which surrounds a sidewall of the contact plug and has a same magnetization direction as the second magnetic layer.. ... Sk Hynix Inc

09/15/16 / #20160266969

Controller, semiconductor memory system and operating method thereof

An operating method of a memory controller includes performing a soft read operation to read data stored in a semiconductor memory device using a soft read voltage, performing a soft decision ecc decoding operation to the read data based on a first log likelihood ratio (llr) value, and performing the soft decision ecc decoding operation to the read data based on a second llr value when the soft decision ecc decoding operation based on the first llr value fails. The first and second llr values are selected between a default llr value and an updated llr value. ... Sk Hynix Inc

09/15/16 / #20160266967

Memory device and system including the same

Disclosed is a memory device including: a plurality of memory blocks suitable for storing data; peripheral circuits suitable for temporarily storing data read from a selected memory block, performing a randomization operation to the read data, and performing an ecc decoding operation to the randomized data; and a control logic suitable for controlling the peripheral circuits to repeat the randomization operation and the ecc decoding operation until the ecc decoding operation is successful, and a system including the same.. . ... Sk Hynix Inc

09/15/16 / #20160266845

Semiconductor memory device and method of driving the same

Disclosed is a method of driving a semiconductor memory device, which programs first page data and second page data in a selected page of a memory cell array, the method including: transmitting a first data buffer control signal to a data buffer so that a data buffer receives the first page data; transmitting a second data buffer control signal to the data buffer so that the data buffer receives the second page data; determining a program option of the first page data; and programming the first page data and the second page data in the selected page, in which the data buffer receives at least some elements of the second page data while the determining of the program option of the first page data is performed.. . ... Sk Hynix Inc

09/15/16 / #20160266823

Data storage device and operating method thereof

A data storage device may include: a nonvolatile memory device comprising a plurality of memory blocks, each having a plurality of pages, wherein each of the pages is divided into a plurality of segments having predetermined segment offset values, and the plurality of segments are grouped into a plurality of segment groups, each comprising segments having the same segment offset value; and a controller suitable for storing data in a first segment group among the plurality of segment groups until the first segment group includes no more empty segments.. . ... Sk Hynix Inc

09/08/16 / #20160261437

Integrated circuit including equalizer and method for adjusting gain of equalizer

An integrated circuit is provided that includes an equalizing unit suitable for equalizing input data that is successively inputted, a sampling unit suitable for sampling centers and edges of the input data that is equalized by the equalizing unit using two or more multi-phase clocks, and a gain adjustment unit suitable for adjusting a gain of the equalizing unit using the centers of the input data and the edges of the input data that are sampled by the sampling unit.. . ... Sk Hynix Inc

09/08/16 / #20160260735

Semiconductor device and method of manufacturing the same

Disclosed is a semiconductor device, including: stack structures including interlayer insulating patterns and conductive line patterns, which are alternately stacked, and separated by a first slit; string pillars passing through the stack structures; and dummy holes passing through top portions of the stack structures to be spaced apart from bottom surface of the stack structures and disposed between the string pillars.. . ... Sk Hynix Inc

09/08/16 / #20160260725

Semiconductor device

Disclosed is a semiconductor device, including: a vertical channel layer formed on a semiconductor substrate; first stack conductive layers stacked on the semiconductor substrate at a predetermined interval to surround one side surface of the vertical channel layer; second stack conductive layers stacked on the semiconductor substrate at the predetermined interval to surround the other side surface of the vertical channel layer; a first charge storage layer disposed between the vertical channel layer and the first stack conductive layers; and a second charge storage layer disposed between the vertical channel layer and the second stack conductive layers.. . ... Sk Hynix Inc

09/08/16 / #20160260716

Semiconductor device and method of manufacturing the same

Disclosed is a semiconductor device. The semiconductor device may include a first pipe gate including a trench extended in a first direction. ... Sk Hynix Inc

09/08/16 / #20160260698

Semiconductor memory device

A semiconductor memory device to which a peri under cell (puc) structure is applied is disclosed. The semiconductor memory device includes a word line multilayered structure formed in a cell region, and extending from across the cell region; and a slimming region including a step-shaped pad structure in the word line multilayered structure.. ... Sk Hynix Inc

09/08/16 / #20160260504

Semiconductor memory device

A semiconductor memory device may include: a first fuse set unit suitable for storing a first repair address during a first mode; a second fuse set unit suitable for storing an input address during a second mode; and a comparison unit suitable for comparing the input address with the first repair address, wherein the first fuse set unit is reset when the first repair address is the same as the input address.. . ... Sk Hynix Inc

09/08/16 / #20160260502

Semiconductor memory device and operation method thereof

Disclosed are a semiconductor memory device and an operation method thereof. The semiconductor memory device includes a main buffer suitable for storing input data during a first operation period of a write operation, a repair operation unit suitable for selectively latching the input data based on whether the input data is used for repair during the first operation period of the write operation; a repair buffer suitable for storing the latched input data during a second operation period subsequent to the first operation period, and a column operation unit suitable for controlling an operation to write the input data stored in the main buffer or the repair buffer in a main memory cell or a repair memory cell during the second operation period of the write operation.. ... Sk Hynix Inc

09/08/16 / #20160260493

Semiconductor device including memory cells

A semiconductor device includes memory cells; an operation circuit suitable for performing a read operation on the memory cells; and a check circuit suitable for comparing the number of memory cells of which threshold voltages are divided by the read operation, wherein the operation circuit changes a read voltage to be applied to the memory cells in the read operation, based on a result of the comparison.. . ... Sk Hynix Inc

09/08/16 / #20160260492

A read voltage setting method for a memory system including memory cells having plurality of logic states

In a method of operating a memory system including memory cells having a plurality of voltage states, a plurality of page data are acquired from a selected page while sequentially applying, to a selected word line, a plurality of test voltages between a minimum voltage level and a maximum voltage level. Center voltages corresponding to at least some voltage states among the plurality of voltage states are detected based on the plurality of page data. ... Sk Hynix Inc

09/08/16 / #20160260485

Semiconductor device

Disclosed is a semiconductor device, including: a memory block including a plurality of memory strings, each of the memory strings including a drain select transistor coupled to a bit line, a source select transistor coupled to a common source line, memory cells coupled to the drain select transistor and the source select transistor, and dummy memory cells coupled to the drain select transistor and the memory cell; and an operation circuit configured to perform a program operation on the memory cells. The operation circuit generates operation voltages applied to the dummy memory cells so that electric charges are generated by a band to band tunneling effect in the dummy memory cell adjacent to the drain select transistor during the program operation.. ... Sk Hynix Inc

09/08/16 / #20160260484

Semiconductor memory device and operating method thereof

Disclosed are a semiconductor memory device, and an operating method thereof. The semiconductor memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program pulse application operation and a verification operation on the memory cell array; a pass/fail check circuit configured to output a pass/fail signal according to a result of the verification operation; and a control logic configured to control the peripheral circuit to perform the program pulse application operation and the verification operation such that two or more program pulses are continuously applied during the program pulse application operation, and first and second verification operations are continuously performed during the verification operation.. ... Sk Hynix Inc

09/08/16 / #20160260477

Variable resistive memory device and method of operating the same

A variable resistive memory device may include a memory region and controller. The memory region may include a plurality of unit memory cells each electrically connected between a word line and a bit line. ... Sk Hynix Inc

09/08/16 / #20160260470

Semiconductor device and semiconductor system

A semiconductor system may include a first semiconductor configured to output a command signal and an address signal. The semiconductor system may include a second semiconductor device configured to include a first operation circuit including a first mos transistor and a second operation circuit including a second mos transistor. ... Sk Hynix Inc

09/08/16 / #20160260464

Semiconductor memory apparatus

A semiconductor memory apparatus may include a write driver, a data sensing section, and a programming control section. The write driver may write an input data into a memory cell in response to a write signal. ... Sk Hynix Inc

09/08/16 / #20160260463

Power supply circuit and semiconductor memory device including the same

A power supply circuit includes a first transistor and a second transistor electrically coupled between a power supply terminal and an output terminal. When a first current path, in which output terminal through the first transistor, is formed, a voltage level of the output terminal may be controlled to be greater than or equal to a predetermined level. ... Sk Hynix Inc

09/08/16 / #20160259744

Semiconductor device including plurality of function blocks and operating method thereof

Disclosed is a semiconductor device including: a bus; a slave function block coupled to the bus; a master function block coupled to the bus through a bus interface, and suitable for providing a bus id to the slave function block together with a request when transmitting the request to the slave function block; and a subordinate slave function block suitable for monitor the bus interface. The subordinate slave function block catches the data communicated together with the bus id is matched to any one of a plurality of determined bus ids.. ... Sk Hynix Inc

09/08/16 / #20160259674

Method of operating semiconductor memory device and memory system including semiconductor memory device

Disclosed is a method of operating a semiconductor memory device including a plurality of pages, including: receiving a program command, an address, and program data; reading page data from a selected page corresponding to the address in response to the program command; determining whether the number of bits of data corresponding to a program state among the page data is greater than a threshold value; and outputting a state fail signal without performing a program operation on the selected page based on a result of the determination.. . ... Sk Hynix Inc

09/08/16 / #20160259595

Encoder and decoder design for near-balanced codes

Methods of encoding a near-symbol balanced (nsb) sequence may include selecting, with a controller, a constraint based on an amount of bits, determining, with the controller, a plurality of sections in a codebook based on permutations defined by the selected constraint, and partitioning, with the controller, a section among the plurality of sections into a plurality of partitions until each of the plurality of partitions include a number of entries equal to or less than a predetermined number of entries.. . ... Sk Hynix Inc

09/08/16 / #20160259585

Memory system and operation method thereof

A memory system may include a command storage unit for storing maximum n commands received from a host, k memory devices each for storing maximum m commands based on the maximum n commands and performing each set operation in response to the stored maximum m commands in order of input, and a resetting unit for resetting execution sequences of the maximum n commands based on execution information regarding each of the maximum n commands and the maximum m commands in each of the k memory devices whenever the commands received from the host are stored in the command storage unit, and distributing the n commands to the k memory devices. The execution information includes a logical address, a physical address, a length, and a use time of a corresponding command.. ... Sk Hynix Inc

09/08/16 / #20160259359

Voltage level control circuit and semiconductor system

A semiconductor system may include a controller configured to output data and first and second test mode signals. The controller may be configured to count the output of the first and second test mode signals. ... Sk Hynix Inc

09/01/16 / #20160254931

Termination circuit, and interface circuit and system including the same

An interface circuit may include a termination resistor and a termination voltage generation unit. The termination resistor may be coupled between a reception pad and a termination node. ... Sk Hynix Inc

09/01/16 / #20160254814

Interface circuit including buffer circuit for high speed communication, semiconductor apparatus and system including the same

A buffer circuit may include an amplification unit and an active load unit. The amplification unit is electrically coupled to an output node and configured to sense and amplify first and second signals. ... Sk Hynix Inc

09/01/16 / #20160254805

Data transmission circuit

A data transmission circuit includes a first data selection unit suitable for alternately outputting data of first and second input lines as first driving data in synchronization with a clock; a data delay unit suitable for generating first and second delay data by delaying the data of the first and second input lines in synchronization with the clock; a second data selection unit suitable for: alternately outputting the data of the first and second input lines as second driving data in synchronization with the clock during a first mode, and alternately outputting inverted first and second delay data, which are inverted from the first and second delay data, as the second driving data in synchronization with the clock during a second mode; a first driving unit suitable for driving an output line in response to the first driving data; and a second driving unit suitable for driving the output line in response to the second driving data.. . ... Sk Hynix Inc

09/01/16 / #20160254802

Semiconductor devices and semiconductor systems including the same

Semiconductor devices are provided. One of the semiconductor devices may include a synthetic clock generator and a flag signal generator. ... Sk Hynix Inc

09/01/16 / #20160254801

Semiconductor apparatus

A semiconductor apparatus may include a data alignment block configured to convert parallel type data into rising data and falling data, and output the rising data and the falling data as serial type synchronous data. The semiconductor apparatus may include a driving control block configured to compare levels of respective bits of the serial type synchronous data, and generate a driving control signal. ... Sk Hynix Inc

09/01/16 / #20160254272

Three-dimensional (3d) semiconductor device

A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.. . ... Sk Hynix Inc

09/01/16 / #20160254251

Semiconductor device

A semiconductor device includes a substrate, an elastic buffer layer disposed on a surface of the substrate, wiring patterns disposed on a first surface of the elastic buffer layer, and a semiconductor chip disposed on a second surface of the elastic buffer layer facing away from the first surface of the elastic buffer layer. The semiconductor chip includes trenches formed on a surface facing the elastic buffer layer. ... Sk Hynix Inc

09/01/16 / #20160254213

Stack package and semiconductor integrated circuit device including a variable voltage

A stack package may include a first chip, a second chip, a through silicon via (tsv) and an interface circuit unit. The first chip may include a first internal circuit unit driven by an internal voltage. ... Sk Hynix Inc

09/01/16 / #20160254154

Methods of forming patterns with block copolymer

A method of forming patterns includes forming a guide pattern and first peripheral patterns on an underlying layer. The guide pattern provides first openings and the first peripheral patterns provide a fifth opening used in alignment of the guide pattern. ... Sk Hynix Inc

09/01/16 / #20160254153

Methods of forming patterns having different shapes

A method of forming patterns includes forming pillars and first peripheral patterns on an underlying layer, forming a separation wall layer covering sidewalls of the pillars and the first peripheral patterns, forming blocking portions on the separation wall layer to fill first openings between the first peripheral patterns, forming a block copolymer layer filling gap regions between the pillars, annealing the block copolymer layer to form first domains and a second domain surrounding the first domains, removing the first domains and removing portions of the separation wall layer to form second openings, removing the second domain and the blocking portions, removing the pillars and the first peripheral patterns to form third openings and fourth openings, and patterning the underlying layer to form fifth openings that extend from the second and third openings and sixth openings that extend from the fourth openings.. . ... Sk Hynix Inc

09/01/16 / #20160254064

Memory device

A memory device including first to fourth cell blocks, each including a plurality of normal columns and one or more redundancy columns and a control unit suitable for repairing the normal columns using the redundancy columns in the first and the second cell blocks using first repair information and repairing the normal columns using the redundancy columns in the third and the fourth cell blocks using second repair information when the memory device is set as a first mode, and suitable for repairing the normal columns using the redundancy columns in the first and the third cell blocks using the first repair information and repairing the normal columns using the redundancy columns in the second and the fourth cell blocks using the second repair information when the memory device is set as a second mode.. . ... Sk Hynix Inc

09/01/16 / #20160254043

Semiconductor memory device and method of operating the same

A semiconductor memory device includes a refresh cycle generation unit capable of generating a first cycle signal and a second cycle signal having a cycle shorter than the first cycle signal; and a refresh control unit capable of generating a plurality of row addresses based on the first or second cycle signal.. . ... Sk Hynix Inc

09/01/16 / #20160254039

Memory device and memory system including the same

A memory device may include a plurality of memory banks, a row control signal input unit suitable for receiving a plurality of row control signals, a column control signal input unit suitable for receiving a plurality of column control signals, a row control unit suitable for selecting a memory bank and a row in response to the row control signals, and controlling a row operation for the selected row, and a column control unit suitable for selecting a memory bank and column in response to the column control signals, and controlling a column operation for the selected column.. . ... Sk Hynix Inc

09/01/16 / #20160254037

Semiconductor device and method for operating the same

A semiconductor device may include: a plurality of data pads; a plurality of data buffers each suitable for buffering a signal inputted through a first input node using a voltage inputted through a second input node, and outputting the buffered signal; and a calibration control unit suitable for generating a test signal in a calibration mode, adjusting the level of the test signal, receiving outputs of the plurality of data buffers while adjusting the level of the test signal, and adjusting offsets of the data buffers such that the logical values of the outputs of the data buffers transit when the test signal has a target level.. . ... Sk Hynix Inc

09/01/16 / #20160254034

Internal voltage generating circuit

An internal voltage generation circuit may include a temperature information generation unit configured to generate a temperature code having a code value corresponding to a temperature. The temperature information generation unit may include a process variation information generation unit configured to generate a process code having a code value corresponding to a process variation. ... Sk Hynix Inc

09/01/16 / #20160254033

Semiconductor device and semiconductor system

A semiconductor device may include a target voltage generation section configured to generate first and second target voltages. The semiconductor device may include a comparison signal generation section configured to compare levels of the first and second target voltages with levels of first and second internal voltages, and generate first and second comparison signals. ... Sk Hynix Inc

09/01/16 / #20160253279

System including interface circuit for high speed communication

A system includes a data transmission unit, a termination resistor and a data reception unit. The data transmission unit may drive a data transmission line based on data, and drive the data transmission line to a voltage level corresponding to a termination voltage during a specified operation period. ... Sk Hynix Inc

09/01/16 / #20160253266

Data storage device and operating method thereof

A data storage device includes a plurality of memory apparatuses, a searching unit configured to search for “k” physical addresses mapped to “k” continuous logical addresses, and a processor configured to determine numerical consecutiveness of “i” logical addresses mapped to “i” continuous physical addresses consecutive to an kth physical address of the “k” physical addresses, and transmit a first pre-read command with respect to a first pre-read memory area corresponding to the “i” continuous physical addresses and first read-estimated physical addresses consecutive to the “i” continuous physical addresses when the numerical consecutiveness is admitted.. . ... Sk Hynix Inc

09/01/16 / #20160253257

Data processing system and operating method thereof

A data processing system includes a host device suitable for assigning a context identifier to data based on attribute information of the data, and a data storage device suitable for performing a garbage collection operation based on the context identifier.. . ... Sk Hynix Inc

09/01/16 / #20160253239

Data storage device and operating method thereof

An operating method of a data storage device includes encoding write data using an error correction code (ecc), inserting an error in encoded data, and storing error-inserted data.. . ... Sk Hynix Inc

09/01/16 / #20160253228

Error detection circuit and semiconductor apparatus using the same

An error detection circuit may include a selection unit that sequentially selects a primary data group and a secondary data group according to a first control signal and generates an output signal; a first operation unit that performs an error detection operation on the output signal and outputs a preliminary error operation signal; a storage unit that latches the preliminary error operation signal and output a latched signal according to a second control signal; a second operation unit that performs an error detection operation on a previous preliminary error operation signal outputted from the storage unit and a current preliminary error operation signal outputted from the first operation unit and generates an internal error operation signal; and a comparison unit that compares the internal error operation signal with an external error operation signal and outputs a result of the comparison as an error detection signal.. . ... Sk Hynix Inc

09/01/16 / #20160253124

Nonvolatile memory device, operating method thereof, and data storage device including the same

A nonvolatile memory device includes a memory cell array including a data cell area, and a mode cell area that stores write mode information of the data cell area, a mode information storage block storing previous write mode information read out from the mode cell area in a previous read operation, and a control logic reading out the write mode information from the mode cell area comparing the read-out write mode information and the previous write mode information, and reading the data cell area in a read mode selected based on a comparison result.. . ... Sk Hynix Inc

09/01/16 / #20160252572

Semiconductor integrated circuit device including variable frequency type probe test pad and semiconductor system

A semiconductor integrated circuit device including a variable frequency type probe test pad and a semiconductor system are disclosed. The semiconductor integrated circuit device includes a plurality of probe test pads formed on a semiconductor substrate and configured to induce non-contact electrical coupling with a probe card, and a frequency control unit electrically coupled to each of the plurality of probe test pads, and configured to vary a frequency of each of the plurality of probe test pads.. ... Sk Hynix Inc

08/25/16 / #20160248996

Voltage generator and image sensing device including the same

A voltage generator includes a supply voltage conversion block suitable for converting a supply voltage into an internal voltage, and a supply voltage control block suitable for supplying the supply voltage to the supply voltage conversion block, wherein the supply voltage has different voltage levels that correspond to generation sections of the internal voltage.. . ... Sk Hynix Inc

08/25/16 / #20160248447

Scheme to avoid miscorrection for turbo product codes

A method includes identifying a stuck error pattern including failing constituent codes and decoding the stuck error pattern by conducting possible flipping patterns for the failing constituent codes, obtaining a number of successfully decoded codewords after conducting the possible flipping patterns, and selecting the most probable code word from the number of successfully decoded codewords.. . ... Sk Hynix Inc

08/25/16 / #20160248409

Ramp voltage generator and image sensing device including the same

A ramp voltage generator includes a first ramp voltage generation block suitable for generating a first ramp voltage with a first slope in response to a bias signal and a first ramp control signal, and a second ramp voltage generation block suitable for generating a second ramp voltage with a second slope corresponding to the first slope in response to the bias signal, a second ramp control signal, and a slope correction signal.. . ... Sk Hynix Inc

08/25/16 / #20160248391

Amplification circuit adjusting duty cycle of output signal and receiver including the same

A receiver includes a first stage buffer, a second stage buffer and a third stage buffer. The first stage buffer includes an input portion electrically coupled to a first voltage node, and configured to change a voltage level of an output node in response to an input signal, first and second load portions electrically coupled between a second voltage node and the output node, and electrically coupled to each other and a duty cycle adjustment portion electrically coupled between the first and second load portions, and configured to provide a correction current to the output node through the first load portion.. ... Sk Hynix Inc

08/25/16 / #20160248009

Electronic device

An electronic device includes a semiconductor unit. The semiconductor unit includes a first electrode and a second electrode spaced apart from each other in a first direction; and a first material layer interposed between the first electrode and the second electrode and having a variable resistance characteristic or a threshold switching characteristic, wherein the first electrode, or the second electrode, or both includes a plurality of sub-electrodes and a plurality of second material layers that are alternately arranged in the first direction, and wherein each of the second material layers has a thickness that is sufficiently small to enable the second material layers to exhibit an ohmic-like behavior for a current flowing therein at an operating current of the semiconductor unit.. ... Sk Hynix Inc

08/25/16 / #20160247858

Electronic device

An electronic device includes a semiconductor unit. The semiconductor unit includes a first electrode and a second electrode spaced apart from each other in a first direction; and a first material layer interposed between the first electrode and the second electrode and having a variable resistance characteristic or a threshold switching characteristic, wherein the first electrode, or the second electrode, or both comprises: a first sub-electrode and a second sub-electrode spaced apart from each other in the first direction; and a second material layer interposed between the first sub-electrode and the second sub-electrode and having a thickness sufficiently small to enable the second material layer to exhibit an ohmic-like behavior for a current flowing therein at an operating current of the semiconductor unit. ... Sk Hynix Inc

08/25/16 / #20160247856

Electronic device having buried gate and method for fabricating the same

Electronic devices having semiconductor elements and methods for fabricating such devices including, a method for fabricating an electronic device including a semiconductor memory, which includes: forming a sacrificial layer on a substrate including a first region and a second region; selectively etching the sacrificial layer and the substrate of the first region to form a trench; forming a first gate that fills a part of the trench in the first region; forming a gate protection layer on the first gate to fill the remaining part of the trench; removing the sacrificial layer of the first region to form a grooved portion surrounded by the gate protection layer; forming a conductive plug to cover the grooved portion; removing the sacrificial layer of the second region; and forming a second gate on the substrate of the second region.. . ... Sk Hynix Inc

08/25/16 / #20160247844

Image sensor and method for fabricating the same

An image sensor may include a substrate having photoelectric conversion regions respectively formed on a plurality of pixels and charge trap regions overlapping with the respective photoelectric conversion regions and having depths or thicknesses that are different, for each of the respective pixel.. . ... Sk Hynix Inc

08/25/16 / #20160247781

Semiconductor packages

Semiconductor packages are provided. A semiconductor package may include an embedding substrate including a cavity therein and a connection window in a bottom portion of the cavity. ... Sk Hynix Inc

08/25/16 / #20160247760

Semiconductor device with air gap and method for fabricating the same

A semiconductor device includes a dielectric structure which has an opening exposing a surface of a substrate; and a conductive structure which is formed in the opening, wherein the conductive structure comprises: a first conductive pattern recessed in the opening; a second conductive pattern covering a top surface and sidewalls of the first conductive pattern; an air gap defined between sidewalls of the opening and the second conductive pattern; and a third conductive pattern capping the second conductive pattern and the air gap.. . ... Sk Hynix Inc

08/25/16 / #20160247711

Semiconductor device including air gaps and method of fabricating the same

A semiconductor device including air gaps and a method of fabricating the same. The semiconductor device in accordance with an embodiment may include a bit line structure having a bit line formed over a first contact plug, a second contact plug formed adjacent to the first contact plug and the bit line structure, an air gap structure comprising two or more air gaps to surround the second contact plug and have an outer sidewall in contact with the bit line structure, and one or more capping support layers separating the air gaps, a third contact plug capping a part of the air gap structure and being formed over the second contact plug, and a capping layer for capping a remainder of the air gap structure.. ... Sk Hynix Inc

08/25/16 / #20160247576

Memory controller and operating method thereof

An operating method of a memory controller includes: performing a first hard decision read operation based on a read retry table including an index representing a read environment of a semiconductor memory device, wherein the read retry table defines hard read voltage values for a plurality of hard read voltage levels of a multi-level cell; and performing a second hard decision read operation by independently changing each of the hard read voltage levels based on the hard read voltage values of the read retry table when the first hard decision read operation fails.. . ... Sk Hynix Inc

08/25/16 / #20160247566

Electronic device

An electronic device comprising a semiconductor memory unit that may include a cell array including a plurality of storage cells; a first line connected to one ends of the plurality of storage cells; a second line connected to the other ends of the plurality of storage cells; a first driver connected to one end of the first line at a first contact location on one side of the cell array, and configured to apply a first electrical signal to the one end of the first line; and a second driver connected to one end of the second line at a second contact location on a side of the cell array opposing the side of the cell array where the first contact location is located, and configured to apply a second electrical signal to the one end of the second line.. . ... Sk Hynix Inc

08/25/16 / #20160246673

Controller, semiconductor memory system and operating method thereof

An operating method of a controller that includes: when a first ecc decoding on data read from a semiconductor memory device according to a hard read voltage fails, generating one or more quantization intervals based on the number of unsatisfied syndrome check (usc), which is a result of the first ecc decoding; and performing a second ecc decoding on the data by generating soft read data according to soft read voltages determined by the hard read voltage and the quantization intervals.. . ... Sk Hynix Inc

08/25/16 / #20160246530

Efficient mapping scheme with deterministic power transition times for flash storage devices

A memory system may include a memory device and a controller. The memory device may include a plurality of storage areas. ... Sk Hynix Inc

08/25/16 / #20160246166

Photomasks for reducing thermal stress generated by heat

A photomask includes a light transmission substrate having a transfer region and a frame region, a light-transmitting region exposing a portion of the light transmission substrate in the transfer region corresponding to a transfer pattern, and a light-blocking region disposed in the transfer region and surrounding the light-transmitting region, wherein the light-blocking region includes a first light-blocking region surrounding the light-transmitting region, and a second light-blocking region that surrounds the first light-blocking region, and wherein a first light-blocking pattern is disposed on the light transmission substrate in the first light-blocking region, and a plurality of second light-blocking patterns are disposed on the light transmission substrate in the second light-blocking region.. . ... Sk Hynix Inc

08/18/16 / #20160241361

Embedded system and method thereof

An embedded system may include an embedded device and a host device. The embedded device may provide a packet for a service, and generate a first transmission control protocol (tcp) segment including a piece of the packet and a first header with no checksum value. ... Sk Hynix Inc

08/18/16 / #20160241141

Voltage generator

A voltage generator may include: an internal voltage generation unit suitable for generating an internal voltage by pumping an external voltage in response to a pumping cycle signal; and a capacitance adjusting unit comprising a capacitive element which receives and transmits the pumping cycle signal to the internal voltage generation unit, and is suitable for adjusting a capacitance of the capacitive element based on the external voltage.. . ... Sk Hynix Inc

08/18/16 / #20160240662

Power integrated devices, electronic devices and electronic systems including the same

A power integrated device includes a channel region, a source region, a drift region, and a drain region. A stacked gate includes a gate insulation layer and a gate electrode. ... Sk Hynix Inc

08/18/16 / #20160240658

Power integrated devices, electronic devices including the same, and electronic systems including the same

A power integrated device includes a semiconductor layer having first conductivity, a source region and a drain region each having second conductivity and disposed in the semiconductor layer, wherein the source region and the drain region are spaced apart from each other, a first drift region having the second conductivity, disposed in the semiconductor layer, and surrounding the drain region, a second drift region having the second conductivity, disposed in the semiconductor layer, contacting a sidewall of the first drift region, and having an impurity concentration lower than an impurity concentration of the first drift region, a gate insulation layer disposed over a channel region between the source region and the second drift region and extending over the second drift region, a field insulation plate disposed over the second drift region and the first drift region, contacting a sidewall of the gate insulation layer, and having a planar structure, and a gate conductive pattern disposed over the gate insulation layer, wherein the gate conductive pattern extends over the field insulation plate.. . ... Sk Hynix Inc

08/18/16 / #20160240544

Non-volatile memory device

A non-volatile memory device includes: a floating gate having a plurality of fingers; a first coupling unit including an active control gate which overlaps with the floating gate in a vertical direction; a second coupling unit including a plurality of control plugs which overlap with the floating gate in a horizontal direction; and a control unit which electrically connects the active control gate to the control plugs and controls a bias to be applied to the active control gate.. . ... Sk Hynix Inc

08/18/16 / #20160240542

Charge trapping nonvolatile memory devices, methods of fabricating the same, and methods of operating the same

A charge trapping nonvolatile memory device includes a source region and a drain region disposed in an upper portion of a substrate and spaced apart from each other by a first trapping region, a channel region, and a second trapping region. A gate stack structure is disposed over the channel region. ... Sk Hynix Inc

08/18/16 / #20160240538

Semiconductor device having buried gate, method of fabricating the same, and module and system having the same

A semiconductor device includes junction regions formed in upper portions of both sidewalls of a trench formed in a semiconductor substrate, a first gate electrode buried in the trench and having a stepped upper surface, and a second gate electrode formed on the first gate electrode to overlap a junction region.. . ... Sk Hynix Inc

08/18/16 / #20160240240

Semiconductor memory device, semiconductor memory system and operation method thereof

Disclosed herein is a semiconductor memory device which performs a refresh operation. The semiconductor memory device may include an information detection unit suitable for detecting a refresh characteristic of a memory cell, a control signal generation unit suitable for generating a refresh control signal having a refresh cycle corresponding to the refresh characteristic, and a refresh driving unit suitable for driving a refresh operation on the memory cell with the refresh cycle in response to the refresh control signal.. ... Sk Hynix Inc

08/18/16 / #20160240234

Semiconductor apparatus configured to manage an operation timing margin

A semiconductor apparatus may include a read path configured to transmit data from the semiconductor apparatus in response to a read command and at least one read operation control signal, and an operation control circuit configured to receive a plurality of divided clock signals and the read command to identify the one of the plurality of divided clock signals that is relatively better matched to the received read command to manage timings associated with at least one of the read operation control signals.. . ... Sk Hynix Inc

08/18/16 / #20160240232

Semiconductor device having high-voltage transistor

A semiconductor device includes a semiconductor device, comprising a memory cell array including a plurality of memory cells connected to a first bit line and a second bit line, respectively, a page buffer group, and bit line selection circuits including a plurality of selection circuit blocks to connect the first bit lines or the second bit lines to the page buffer group, wherein each of the selection circuit blocks includes a first contact region and a second contact region to which the first and second bit lines coupled, and same bit lines of the first and second bit lines are coupled to contact regions adjacent to one another of the first and second contact regions included in bit line selection circuits adjacent to one another of the bit line selection circuits.. . ... Sk Hynix Inc

08/18/16 / #20160239206

Semiconductor system performing status read for semiconductor device and operating method thereof

A semiconductor system includes a semiconductor device suitable for receiving and performing a plurality of commands and a controller suitable for determining whether the semiconductor device completes an operation for each of the plurality of commands by performing one or more status reads for the semiconductor device whenever each of the plurality of commands is issued to the semiconductor device. The controller issues a first command among the plurality of commands to the semiconductor device, performs the one or more status reads for the semiconductor device to store a time taken to perform the first command as operation time information. ... Sk Hynix Inc

08/18/16 / #20160238938

Methods of forming patterns

Methods of forming patterns includes guide patterns on a neutral layer. A self-assembling block copolymer (bcp) layer on the guide patterns and the neutral layer. ... Sk Hynix Inc

08/18/16 / #20160238926

Photomask blanks, photomasks fabricated using the same, and methods of fabricating photomask using the same

Photomask blanks are provided. One of the photomask blanks includes a light transmission substrate, a light blocking layer disposed on a top surface of the light transmission substrate, and a heat radiation layer disposed on sidewalls and a bottom surface of the light transmission substrate. ... Sk Hynix Inc

08/18/16 / #20160238632

Electrostatic protection circuit and semiconductor device including the same

An electrostatic protection circuit may include a test pad configured to receive a first signal in a test mode. The electrostatic protection circuit may include a bump array configured to receive a second signal in a normal mode. ... Sk Hynix Inc

08/11/16 / #20160233765

Internal voltage generation circuit

Disclosed herein is an internal voltage generation circuit for generating a pumping voltage. The internal voltage generation circuit may include a pumping unit suitable for generating a pumping voltage by pumping an input voltage and a control unit suitable for stepwise controlling a voltage level of the input voltage based on the breakdown voltage information of the pumping unit.. ... Sk Hynix Inc

08/11/16 / #20160233231

Semiconductor device and method of manufacturing the same

A semiconductor device, including: interlayer insulating patterns and conductive patterns alternately stacked on a substrate; a channel structure passing through the interlayer insulating patterns and the conductive patterns; and tapered patterns interposed between the channel structure and the interlayer insulating patterns, spaced apart with any one of the conductive patterns interposed therebetween, and having widths decreased toward the substrate.. . ... Sk Hynix Inc

08/11/16 / #20160233229

3d nonvolatile memory device

A 3d nonvolatile memory device is disclosed. The 3d nonvolatile memory device includes a word line stack in which a plurality of word lines are stacked therein and includes a cell region and a slimming region, and pass transistors located below the word line stack, and electrically coupled to the slimming region. ... Sk Hynix Inc

08/11/16 / #20160233222

Anti-fuse of semiconductor device, semiconductor module and system each including the semiconductor device, and method for forming the anti-fuse

An anti-fuse based on a field nitride trap (fnt) is disclosed. The anti-fuse includes a first active pillar including a first junction, a second active pillar including a second junction, a selection line buried between the first active pillar and the second active pillar, and a trap layer for electrically coupling the first junction to the second junction by trapping minority carriers according to individual voltages applied to the first junction, the second junction and the selection line. ... Sk Hynix Inc

08/11/16 / #20160232975

Semiconductor memory device and programming method of the same

A semiconductor memory device may include a memory array including memory strings coupled between bit lines and a common source line. The semiconductor memory device may include a peripheral circuit coupled to the memory array through the bit lines. ... Sk Hynix Inc

08/11/16 / #20160232961

Semiconductor device and operating method thereof

A semiconductor memory device includes a plurality of memory cell blocks each including a plurality of word lines and suitable for being selectively activated based on an active command and a row address, wherein word lines are selected from the respective activated memory cell blocks based on the active command and the row address, and a column decoding block sequentially accessing the activated memory cell blocks to input/output data thereof by decoding a column address based on the row address.. . ... Sk Hynix Inc

08/11/16 / #20160232960

Memory device and memory system including the same

A memory device includes: a plurality of memory blocks; an address counting block suitable for generating a counting address that is changed when all the memory blocks are refreshed; a target address generation block suitable for generating a target address, which is an address of a word line requiring an additional refresh operation, in the memory blocks; and a refresh control block suitable for controlling a 1st number of the memory blocks to be refreshed when a refresh command is inputted a 1st number of times and controlling a 2nd number of the memory blocks to be refreshed when the refresh command is inputted a 2nd number of times, wherein the refresh control block controls a word line corresponding to the counting address to be refreshed and controls a word line corresponding to the target address to be refreshed during a target refresh operation.. . ... Sk Hynix Inc

08/11/16 / #20160232957

Semiconductor memory apparatus and operating method of semiconductor system using the same

A semiconductor memory apparatus includes an address determination block configured to output an address as one of a row address and a column address according to an internal command; a row address decoding block configured to decode the row address and enable a word line; a column address decoding block configured to decode a partial column address of the column address and enable a column select signal; a data select signal generation block configured to enable a data select signal according to the row address and a remaining column address of the column address; and a data storage region configured to store or output data according to the word line, the column select signal and the data select signal.. . ... Sk Hynix Inc

08/11/16 / #20160232954

Semiconductor device and operating method thereof

A semiconductor device includes: memory blocks including main data storage units and cycling information storage units; a circuit group that performs a wear leveling operation on the memory blocks; and a control circuit that sets a threshold value based on the cycling information, and controls the circuit group so that the wear leveling operation is performed based on the set threshold value.. . ... Sk Hynix Inc

08/04/16 / #20160226503

Interface circuit for high speed communication, and semiconductor apparatus and system including the same

An interface circuit of a semiconductor apparatus may include a pulse generation unit, a data clock synchronization unit and a system clock synchronization unit. The pulse generation unit may be configured to generate a burst end pulse from a burst end signal according to a data clock signal. ... Sk Hynix Inc

08/04/16 / #20160226493

Semiconductor integrated circuit device regarding the detection of degradation

A semiconductor integrated circuit device may include a target pmos transistor, a target nmos transistor, a first stress-applying circuit, a second stress-applying circuit, a third stress-applying circuit and a fourth stress-applying circuit. An inverter may include the target pmos transistor and the nmos transistor. ... Sk Hynix Inc

08/04/16 / #20160226476

Duty cycle detection circuit and duty cycle correction circuit including the same

A duty cycle detection circuit includes a reset unit suitable for resetting a first capacitor and a second capacitor based on a reset signal, a first charging/discharging unit suitable for charging the first capacitor while a clock is in a first level and discharging the first capacitor while the clock is in a second level, a second charging/discharging unit suitable for charging the second capacitor while the clock is in the second level and discharging the second capacitor while the clock is in the first level, and a differential amplifier suitable for amplifying a voltage difference between the first capacitor and the second capacitor based on an amplification enable signal and generating a detection signal as a result of the amplification.. . ... Sk Hynix Inc

08/04/16 / #20160226475

Decoding circuit and method of decoding signal

A decoding circuit may include a section information generation unit suitable for generating section information corresponding to a section in which an input signal has a first value, a period information generation unit suitable for generating period information corresponding to a period of the input signal, a reference information generation unit suitable for generating reference information by dividing a value of the period information by a given value, and a comparison unit suitable for determining a logic value of the input signal by comparing the section information with the reference information.. . ... Sk Hynix Inc

08/04/16 / #20160225989

Variable resistance memory device and method of manufacturing the same

A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device may include a multi-layered insulating layer formed on a semiconductor substrate, on which a lower electrode is formed. ... Sk Hynix Inc

08/04/16 / #20160225985

Variable resistance memory device and method of manufacturing the same

A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device may include a multi-layered insulating layer formed on a semiconductor substrate, on which a lower electrode is formed. ... Sk Hynix Inc

08/04/16 / #20160225984

Electronic device and method for fabricating the same

An electronic device includes a semiconductor device that includes: a substrate including a switching element having a buried gate electrode; a buried decoupling capacitor having a line width same as a line width of the buried gate electrode; and a variable resistance element, electrically coupled to the switching element, formed over the substrate.. . ... Sk Hynix Inc

08/04/16 / #20160225900

Semiconductor device and method for forming the same

A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. ... Sk Hynix Inc

08/04/16 / #20160225754

Semiconductor device and manufacturing method thereof

Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device includes: source select lines, word lines, drain select lines, and a bit line stacked on a substrate in which a first cell string region and a second cell string region are defined; channel layers and memory layers vertically passing through the source select lines, the word lines, and the drain select lines in each of the first cell string region and the second cell string region; and a common source line vertically passing through the source select lines, the word lines, and the drain select lines at centers of the first cell string region and the second cell string region, and extended to a lower side of the source select lines.. ... Sk Hynix Inc

08/04/16 / #20160225744

Semiconductor packages, methods of fabricating the same, memory cards including the same and electronic systems including the same

A semiconductor package includes a package substrate having a cavity therein and a second internal contact portion, a semiconductor die disposed in the cavity of the package substrate and having a first internal contact portion, a bonding wire connecting the first internal contact portion to the second internal contact portion, and an encapsulation part covering surfaces of the semiconductor die and the package substrate and providing an opening that exposes a first external contact portion of the bonding wire. Related memory cards and related electronic systems are also provided.. ... Sk Hynix Inc

08/04/16 / #20160225743

Package-on-package type stack package and method for manufacturing the same

A bottom package having a first semiconductor chip and first connection members; and a top package disposed over the bottom package, and having a second semiconductor chip and second connection members electrically coupled with the first connection members. The bottom package includes an interposer having electrodes arranged along edges; first bond fingers arranged by being separated from the edges of the interposer; a first semiconductor chip disposed over the interposer to expose the electrodes, and having first bonding pads; first bonding wires electrically coupling the first bonding pads and the electrodes; second bonding wires electrically coupling the electrodes and the first bond fingers; and a first encapsulation member formed to cover the first bond fingers, the upper and side surfaces of the interposer and the first semiconductor chip, and the first and second bonding wires, and having via holes which expose portions of the second bonding wires.. ... Sk Hynix Inc

08/04/16 / #20160225710

Semiconductor device with line-type air gaps and method for fabricating the same

A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.. . ... Sk Hynix Inc

08/04/16 / #20160225697

Semiconductor device and method of manufacturing the same

A semiconductor device is provided. The semiconductor device may include stacks including conductive layers and insulating layers. ... Sk Hynix Inc

08/04/16 / #20160225663

Semiconductor device having stable structure and method of manufacturing the same

The semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked; semiconductor patterns configured to pass through the stacked structure; and contact plugs electrically coupled to the conductive layers, respectively, wherein each of the conductive layers includes a first region which has a first thickness, and a second region electrically coupled to the first region and a second thickness greater than the first thickness, and a second region of a lower conductive layer located under a second region of an upper conductive layer.. . ... Sk Hynix Inc

08/04/16 / #20160225452

Flash memory device

A flash memory device is disclosed. The flash memory device includes: a cell array region; an x-decoder region arranged adjacent to the cell array region in a first direction; a discharge transistor region disposed between the cell array region and the x-decoder region; a first metal line formed to pass through the x-decoder region, the discharge transistor region, and the cell array region, and arranged to extend in the first direction; and a second metal line including a first line patterns arranged parallel to the first metal line between the first metal lines, and a second line pattern interconnecting both ends of the first line patterns and extending in a second direction crossing the first direction.. ... Sk Hynix Inc

08/04/16 / #20160225435

Memory device and memory system including the same

A memory device may include a temperature sensor suitable for generating temperature information and a smart refresh circuit suitable for activating a smart refresh signal when an internal refresh signal is activated a set number of times, and controlling the set number based on the temperature information.. . ... Sk Hynix Inc

08/04/16 / #20160225432

Semiconductor device performing refresh operation and method for driving the same

A semiconductor device includes a first memory block, a second memory block, a first refresh control block for generating a first block control signal and a second block control signal in response to a refresh pulse signal, a second refresh control block for generating a first refresh control pulse signal and a second refresh control pulse signal corresponding to a first refresh operation section of the first memory block and a second refresh operation section of the second memory block, respectively, in response to the refresh pulse signal and the first and second block control signals, and a third refresh control block for controlling the first and second memory blocks so that a first refresh operation of the first memory block and a second refresh operation of the second memory block are discontinuously performed in response to the first and second refresh control pulse signals.. . ... Sk Hynix Inc

08/04/16 / #20160225425

Electronic devices having semiconductor memory units having magnetic tunnel junction element

Disclosed are electronic devices comprising a semiconductor memory unit capable of reducing the switching current of a variable resistance element for switching between different resistance states. One implementation of a disclosed electronic device may include a first magnetic layer having an easy magnetization axis in a first direction and having a variable magnetization direction, a third magnetic layer having a magnetization direction pinned in the first direction, a second magnetic layer interposed between the first magnetic layer and the third magnetic layer, and having a magnetization direction pinned in a second direction different from the first direction, a tunnel barrier layer interposed between the first magnetic layer and the second magnetic layer, and a non-magnetic layer interposed between the second magnetic layer and the third magnetic layer.. ... Sk Hynix Inc

08/04/16 / #20160225418

Driving circuit and driving method using the same

A driving circuit includes a write operation controller configured to generate a write control signal according to a write command and a column address; a row controller configured to generate an auto refresh flag according to an auto refresh command and a row address; and a sense amplifier controller configured to enable the write control signal or the auto refresh flag according to a temperature flag, and generate an overdriving signal according to the enabled write control signal or the enabled auto refresh flag.. . ... Sk Hynix Inc

08/04/16 / #20160225417

Data transmission circuit

A data transmission circuit may include data line groups and pass sections arranged among the data line groups to allow the data line groups to form one line. The data transmission circuit may include an input/output unit configured to be coupled to the data line groups and to process write data to be transmitted to the data line groups or read data transmitted from the data line groups. ... Sk Hynix Inc

08/04/16 / #20160225415

Semiconductor device and operating method thereof

A method of operating a semiconductor device having memory blocks including cell strings corresponding to drain select lines, word lines, and source select lines, includes: performing an erase operation on memory cells included in a selected memory block; and simultaneously performing erase-verify operations on the memory cells included in the selected memory block, wherein positive voltages lower than preset voltages are applied to some lines among of the bit lines, the drain select lines, and the source select lines connected to the selected memory block during the erase and verification operation.. . ... Sk Hynix Inc

08/04/16 / #20160224589

Method and system for endurance enhancing, deferred deduplication with hardware-hash-enabled storage device

A storage system may include at least one storage device and a server. The storage device may store an incoming data, calculate a hash value for the incoming data, and store the hash value as meta data. ... Sk Hynix Inc

08/04/16 / #20160224588

Data integrity and loss resistance in high performance and high capacity storage deduplication

A memory system for utilizing a deduplication process may include a controller, a storage media, and a non-volatile ram including a metadata journal and a metadata cache, the metadata cache including an address table and a fingerprinting table, and the metadata journal including a plurality of transactions indicating whether a transaction is successfully written on the storage media.. . ... Sk Hynix Inc

08/04/16 / #20160224506

Interface circuit for high speed communication, and semiconductor apparatus and system including the same

A semiconductor apparatus may include a burst operation sensing unit and the interface circuit. The burst operation sensing unit may be configured to generate operation mode conversion signals based on current operation state information and a level variation of at least one signal transmission line. ... Sk Hynix Inc

08/04/16 / #20160224480

Semiconductor memory apparatus and data input/output method thereof

A semiconductor memory apparatus may include a write data bus inversion unit and a write data polarity change unit. The write data bus inversion unit may invert a level of an input data and may generate an inversion change data when a majority of the input data have a predetermined level. ... Sk Hynix Inc

08/04/16 / #20160224466

Memory system and operation method thereof

A memory system may include a first memory device including a first input/output buffer, a second memory device including a second input/output buffer, and a cache memory suitable for selectively and temporarily storing first and second data to be respectively programmed in the first and second memory devices. The first data is programmed to the first memory device in a first program section by being stored in the cache memory only in a first monopoly section of the first program section. ... Sk Hynix Inc

08/04/16 / #20160224440

Semiconductor memory device, memory system including the same, and operating method thereof

A semiconductor memory device includes a memory cell array including a plurality of memory cells, a read and write circuit temporarily storing program data to be programmed into the memory cell array during a program operation, and reading data stored in the memory cell array and temporarily storing read data during a read operation, and a control logic detecting an error in the program operation by comparing the program data with the read data,. . ... Sk Hynix Inc

08/04/16 / #20160224413

Semiconductor memory device and method of checking operation state thereof

Disclosed are a semiconductor memory device and a method of checking an operation state thereof. The semiconductor memory device includes: a micro configured to output a data generating code according to a state checking operation command; and a step code generating unit configured to generate a step code for an operation currently performed by a storage device according to the data generating code, and output rom data including the step code, in which the micro generates a state code for the operation currently performed by the storage device and an operation code for a segmentalized step of the operation according to the rom data.. ... Sk Hynix Inc

08/04/16 / #20160224050

Internal voltage generation circuit and semiconductor device including the same

An internal voltage generation circuit includes a first control signal generation unit suitable for generating a first control signal activated to a level of a second external voltage when a first external voltage is activated, a second control signal generation unit suitable for generating a second control signal that equals the higher of the second external voltage and an internal voltage, and a voltage generation unit suitable for generating the internal voltage by performing a charge pumping operation based on the second external voltage and an oscillation signal while blocking a current flowing through a generation node from which the internal voltage is generated, based on the first and second control signals.. . ... Sk Hynix Inc

08/04/16 / #20160223609

Semiconductor integrated circuit device having function for detecting degradation of semiconductor device and method of driving the same

A semiconductor integrated circuit device having a function for detecting degradation of a semiconductor device and a method of driving the same are disclosed. The semiconductor integrated circuit device includes an nmos transistor electrically coupled to a pmos transistor and configured to constitute an inverter together with the pmos transistor, a first stress application unit electrically coupled to the pmos transistor and configured to apply stress to the pmos transistor, and a second stress application unit electrically coupled to the nmos transistor and configured to apply the stress to the nmos transistor.. ... Sk Hynix Inc

07/28/16 / #20160218713

Semiconductor device

A semiconductor device is disclosed, which relates to a technology for reducing current consumption of a semiconductor chip configured to operate a transmitter (tx) at a high speed. The semiconductor device includes a data driving unit configured to output a pull-up drive signal and a pull-down drive signal by level-shifting an input signal according to a clock signal; and a data output unit configured to adjust slew rates of the pull-up drive signal and the pull-down drive signal according to a code signal, and output impedance-adjusted signals to an output terminal.. ... Sk Hynix Inc

07/28/16 / #20160218701

Phase control circuits and data output devices including the same

Phase control circuits are provided. The phase control circuit may include a phase controller. ... Sk Hynix Inc

07/28/16 / #20160218619

Data pin reference voltage generation circuit and semiconductor device including the same

A data pin reference voltage generation circuit may include a voltage difference storage block configured to accumulatively store a difference between an input signal received through a data pin and a reference voltage for a preset time. The data pin reference voltage generation circuit may include a code generator configured to generate a voltage generation code based on the voltage difference stored in the voltage difference storage block. ... Sk Hynix Inc

07/28/16 / #20160218136

Image sensor packages and methods of fabricating the same

An image sensor package includes a die having an active side surface and a backside surface opposite to each other and having a bonding pad disposed on the active side surface, a through via penetrating the die and being electrically connected to the bonding pad, and a first dielectric layer disposed between the through via and the die. The first dielectric layer extends to cover the backside surface of the die. ... Sk Hynix Inc

07/28/16 / #20160218107

Three-dimensional semiconductor device

A semiconductor device includes a stacked structure having first conductive layers stacked stepwise and first insulating layers interposed between the first conductive layers, wherein undercuts are formed under the first conductive layers and each of the first conductive layers includes a first region covered by the first conductive layer and a second region extending from the first region, contact pads coupled to the second regions of the respective first conductive layers, and a liner layer formed on the contact pads and filling the undercuts.. . ... Sk Hynix Inc

07/28/16 / #20160218081

Semiconductor packages including an interposer

A semiconductor package may include a first semiconductor chip, second semiconductor chips disposed to respectively overlap with portions of the first semiconductor chip, a interposer disposed to overlap with a portion of the first semiconductor chip, and a package substrate disposed on backside surfaces of the second semiconductor chips opposite to the first semiconductor chip. The interposer may be disposed between the first semiconductor chip and the package substrate. ... Sk Hynix Inc

07/28/16 / #20160217873

Post package repair device

A post package repair (ppr) device is disclosed, which relates to a technology for masking a rupture operation in case of a post package repair (ppr) operation. The post package repair (ppr) device includes: a plurality of bank groups, each including a fuse indicating repair information, configured to share a predetermined number of fuses; a resource detection unit configured to generate a resource signal which determines whether the fuses from among the plurality of bank groups are available; and a masking controller configured to output a masking signal which prevents repeated execution of a rupture operation when there is no unused fuse in response to the resource signal and a bank active signal.. ... Sk Hynix Inc

07/28/16 / #20160217866

Semiconductor device being capable of improving the breakdown characteristics

A semiconductor device, wherein the semiconductor device includes a high-voltage supply circuit suitable for supplying a high voltage; a discharge circuit suitable for discharging the high voltage; and an auxiliary-voltage supply circuit suitable for supplying a first auxiliary voltage, which varies according to an operation state of the high-voltage supply circuit, to a reference node of the discharge circuit.. . ... Sk Hynix Inc

07/28/16 / #20160217863

Semiconductor device

A semiconductor device includes a plurality of memory blocks including a plurality of memory cells, wherein the plurality of memory cells are divided into a plurality of pages; and an operation circuit configured to output operating voltages to local lines of a selected memory block, among the plurality of memory blocks, to perform a program operation, a read operation and an erase operation on the selected memory block, wherein the operation circuit is configured to apply a dummy pulse having a positive potential to the local lines of the selected memory block after completing the program operation, the read operation and the erase operation. . ... Sk Hynix Inc

07/28/16 / #20160217859

Semiconductor device

A semiconductor device includes a memory block including memory cells coupled to word lines, and an operation circuit configured to perform a program loop on memory cells coupled a selected word line, wherein the operation circuit is configured to change a program permission voltage applied to a bit line of a program target memory cell when a number of times the program loop is performed exceeds a reference number.. . ... Sk Hynix Inc

07/28/16 / #20160217846

Semiconductor devices configured to generate a bank active signal

A semiconductor device may include a refresh controller and a bank active signal generator. The refresh controller may be suitable for generating a level signal, setting a level of the level signal in response to a refresh pulse signal while operating in a test mode, and suitable for receiving a refresh flag signal and generating a first period signal and a second period signal in response to the level signal. ... Sk Hynix Inc

07/28/16 / #20160217844

Semiconductor devices and semiconductor systems including the same

A semiconductor device includes an output controller and a data strobe signal generator. The output controller generates a period signal and a control clock signal according to a read operation signal generated to execute a read operation, an internal clock signal generated in synchronization with a clock signal, and an expansion control signal. ... Sk Hynix Inc

07/28/16 / #20160217841

Reconfigurable semiconductor memory apparatus and operating method thereof

A reconfigurable semiconductor memory apparatus may include a memory cell array including a plurality of sub arrays. The reconfigurable semiconductor memory apparatus may include an information storage unit configured to store status information for each sub array, and a reset address according to the status information.. ... Sk Hynix Inc

07/28/16 / #20160217838

Semiconductor device

A semiconductor device may include an active controller configured to count pulses of an active signal, and activate an active masking signal for masking an active operation when the counted number of the active signal is greater than predetermined activation times of the active signal during a predetermined bank active section.. . ... Sk Hynix Inc

07/28/16 / #20160217837

Semiconductor device

A semiconductor device may include a first channel configured to output a first rising clock, a first falling clock, first rising data, and first falling data. The semiconductor device may include a second channel configured to output a second rising clock, a second falling clock, second rising data, and second falling data. ... Sk Hynix Inc

07/28/16 / #20160217836

Semiconductor device

A semiconductor device includes a buffer block configured to generate a strobe signal by buffering an external strobe signal inputted through a first pad, output the strobe signal to a first node of a first input/output line, generate data by buffering external data inputted through a second pad, and output the data to a second node of a second input/output line; a first channel configured to store the data loaded on the second input/output line in synchronization with the strobe signal loaded on the first input/output line; and a second channel configured to store the data loaded on the second input/output line in synchronization with the strobe signal loaded on the first input/output line.. . ... Sk Hynix Inc

07/28/16 / #20160217833

Sense amplifier and semiconductor device including the same

A sense amplifier may include an amplifying section configured to amplify data of a segment line pair when an enable signal is activated and output amplified data to a local line pair, and including latches electrically coupled in a cross-coupled type. The sense amplifier may include a switching section configured to selectively electrically couple the segment line pair and the local line pair in response to an input/output switch signal.. ... Sk Hynix Inc

07/28/16 / #20160217034

Reading and writing to nand flash memories using charge constrained codes

A charge constrained bit sequence is processed to obtain a lower bound on a number of bit errors associated with the charge constrained bit sequence. The lower bound is compared against an error correction capability threshold associated with an error correction decoder. ... Sk Hynix Inc

07/28/16 / #20160216325

Test mode circuit and semiconductor device including the same

A test mode circuit of a semiconductor device includes a test mode activating signal generation unit suitable for generating a test mode activating signal in response to a test signal; a test clock generation unit suitable for generating a plurality of test clocks in response to the test mode activating signal and a control clock; a test control signal generation unit suitable for generating test control signals based on the plurality of test clocks of a control signal input cycle, wherein the plurality of test clocks have the control signal input cycle and a data input cycle; and an internal control signal generation unit suitable for generating a plurality of control signals to perform a test operation in response to the test control signals and input data.. . ... Sk Hynix Inc

07/28/16 / #20160216315

Degradation detection circuit and degradation adjustment apparatus including the same

A degradation detection circuit may include a degradation unit including multiple delay elements driven by a high voltage for degradation. The high voltage for degradation value may be higher than an operation voltage. ... Sk Hynix Inc

07/28/16 / #20160216312

Test device and test system of semiconductor device and test method for testing semiconductor device

A test device of a semiconductor device for testing semiconductor device including a plurality of interface pads includes a plurality of coupling units each configured to be coupled to a corresponding one of the plurality of interface pads, a channel configured to be coupled to the plurality of coupling units, a voltage generating unit configured to generate a test voltage applied to the channel, and a current measuring unit configured to measure a current that flows on the channel in response to the test voltage.. . ... Sk Hynix Inc

07/21/16 / #20160211366

Lateral double diffused mos transistors

A lateral double diffused mos transistor including a substrate, a source region and a drain region disposed in the substrate, a first contact and a second contact connected to the source region and the drain region, respectively, a gate insulation layer and a gate electrode on the substrate, a first field plate extending from the gate electrode toward the drain region, a coupling gate disposed between the second contact and the first field plate on the substrate, the coupling gate having a coupling voltage by coupling operation with the second contact, and a second field plate disposed between the coupling gate and the first field plate on the substrate, the second field plate being electrically connected to the second field plate.. . ... Sk Hynix Inc

07/21/16 / #20160211363

Nonvolatile memory devices having single-layered gates and methods of fabricating the same

A nonvolatile memory device includes an active region extending in a first direction and including a source region and a drain region that are respectively disposed at both ends of the active region, a gate electrode pattern extending in a second direction and disposed between the source region and the drain region, wherein the second direction extends across the first direction, a gate insulation pattern disposed between the gate electrode pattern and the active region, a source contact plug and a drain contact plug respectively coupled to the source region and the drain region, and a coupling contact plug disposed over the gate electrode pattern and insulated from the gate electrode pattern.. . ... Sk Hynix Inc

07/21/16 / #20160211188

Semiconductor packages, methods of manufacturing the same, electronic systems including the same, and memory cards including the same

A semiconductor package includes an adhesive member disposed on a package substrate to have a trapezoid cross-section view, and a semiconductor chip disposed on the adhesive member and attached to the package substrate by the adhesive member. The semiconductor chip has a first surface and a second surface facing the first surface, and the second surface of the semiconductor chip contacts the adhesive member. ... Sk Hynix Inc

07/21/16 / #20160211183

Semiconductor device with metal gate and high-k dielectric layer, cmos integrated circuit, and method for fabricating the same

A semiconductor device includes a gate dielectric layer over a substrate, a metal layer over the gate dielectric layer, a capping layer over the metal layer, wherein the capping layer includes a plurality of dipole forming elements concentrated at the interface between the metal layer and the capping layer.. . ... Sk Hynix Inc

07/21/16 / #20160211025

Semiconductor memory device and operating method thereof

The invention relates to a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a first plane and a second plane each including a plurality of memory blocks, a first read and write circuit and a second read and write circuit suitable for sensing and temporarily storing data programmed into the first and second planes, respectively, and a control logic suitable for controlling the first and second read and write circuits to perform a read operation on the first and second planes, respectively, wherein the control logic controls the first and second read and write circuits to set the temporarily stored data as setting data, performs a new read operation to store new data, or maintains the temporarily stored data, depending on whether the first and second planes are in an lsb program state or an msb program state.. ... Sk Hynix Inc

07/21/16 / #20160210235

Data processing system having combined memory block and stack package

A data processing system includes a central processing unit (cpu), a control block configured to interface with the cpu, a cache memory configured to interface with the control block and arranged to be spaced from the cpu by a first distance, and a combined memory block configured to interface with the control block, arranged to be spaced from the cpu by a second distance larger than the first distance, and configured of a working memory and a storage memory. The combined memory block is configured of a plurality of stacked memory layers, each configured of a plurality of variable resistance memory cells. ... Sk Hynix Inc

07/21/16 / #20160210124

Methods of system optimization by over-sampling read

Methods for programming word lines in a block include identifying the block to be programmed, opening the block for programming, and programming a first word line in the block and a second word line in the block. The first word line and the second word line are separated by a number of word lines that are skipped during programming, and the number of word lines that are skipped being based on a predetermined interval.. ... Sk Hynix Inc

07/21/16 / #20160209741

Reflective mask and method of fabricating the same

A reflective mask includes a first reflection layer disposed on a mask substrate, a first capping layer disposed on the first reflection layer, a second reflection pattern disposed on a portion of the first capping layer, and a phase shifter disposed between the second reflection pattern and the first capping layer to cause a phase difference between a first light reflecting from the first reflection layer and a second light reflecting from the second reflection pattern. Related methods are also provided.. ... Sk Hynix Inc

07/14/16 / #20160204653

Semiconductor device being capable of improving the breakdown characteristics

A semiconductor device, wherein the semiconductor device includes a high-voltage supply circuit suitable for supplying a high voltage; a discharge circuit suitable for discharging the high voltage; and an auxiliary-voltage supply circuit suitable for supplying a first auxiliary voltage, which varies according to an operation state of the high-voltage supply circuit, to a reference node of the discharge circuit.. . ... Sk Hynix Inc

07/14/16 / #20160204163

Variable resistance memory device and method of manufacturing the same

A variable resistance memory device includes a semiconductor substrate having a vertical transistor with a shunt gate that increases an area of a gate of the vertical transistor.. . ... Sk Hynix Inc

07/14/16 / #20160204119

Semiconductor device

A semiconductor device may include: a plurality of source-side half channels positioned in a first region and arranged in first to 2nth rows, wherein n is an integer equal to or greater than 2; a plurality of first drain-side half channels positioned in a second region at one side of the first region and arranged in first to nth rows; a plurality of second drain-side half channels positioned in a third region at the other side of the first region and arranged in first to nth rows; a plurality of first pipe channels suitable for connecting the first to nth rows of source-side half channels to the first to nth rows of first drain-side half channels, respectively; and a plurality of second pipe channels suitable for connecting the (n+1)th to 2nth rows of source-side half channels to the first to nth rows of second drain-side half channels, respectively.. . ... Sk Hynix Inc

07/14/16 / #20160204115

Semiconductor device and method of fabricating the same

A semiconductor device includes stacked structure, openings passing through stacked structure, semiconductor patterns formed over inner walls of the openings, liner layers formed in the openings over the semiconductor patterns, and gap-fill insulating layers formed over the liner layers to fill the openings, wherein each of the gap-fill insulating layers seals an upper portion of the opening and includes at least one air gap.. . ... Sk Hynix Inc

07/14/16 / #20160204025

Transistor, semiconductor device and method of manufacturing the same

A semiconductor device including a central region, side regions located in both sides of the central region, and conductive layers including a first barrier pattern formed in the central region, a material pattern formed in the first barrier pattern and having an etch selectivity with respect to the first barrier pattern, and a second barrier pattern formed in the material pattern; and insulating layers alternately stacked with the conductive layers.. . ... Sk Hynix Inc

07/14/16 / #20160203872

Semiconductor memory device

A semiconductor device includes a memory block including memory cells and an operation circuit configured to perform a read operation which reads lsb data or msb data stored in the memory cells using different levels of read voltages, wherein when the msb data is stored in the memory cells, the operation circuit is configured to read the msb data and the lsb data from the memory cells.. . ... Sk Hynix Inc

07/14/16 / #20160203853

Semiconductor apparatus capable of preventing refresh error and memory system using the same

A semiconductor apparatus includes a plurality of memory banks configured to perform a refresh operation in response to an address count value and row active signals; a refresh control block configured to update refresh bank informations which define a bank designated to perform the refresh operation in response to a refresh command and bank addresses, and activate a count control signal in response to the refresh bank informations; and a counter configured to change the address count value in response to activation of the count control signal.. . ... Sk Hynix Inc

07/14/16 / #20160202934

Methods of system optimization by over-sampling read

A method of controller optimization utilizing over-sampling read (osr) in a memory device includes performing a first internal read at a predetermined threshold level and transferring the first internal read measurement to the controller, performing a second internal read in a range that is between the predetermined threshold level plus a first predetermined value and the predetermined threshold level minus a second predetermined value, and determining whether a cell level falls in the range and transferring the second internal read measurement to the controller.. . ... Sk Hynix Inc

07/14/16 / #20160202718

Voltage generation circuit

A voltage generation circuit includes a plurality of voltage generation units each configured to include an internal voltage with a reference voltage, generate a detection signal based on a comparison result between the internal voltage and the reference voltage, and adjust the level of the internal voltage in response to an oscillation signal, a control unit configured to generate an oscillation control signal in response to the detection signals, an oscillator configured to generate the oscillation signal in response to the oscillation control signal, and a selective output unit configured to selectively supply the oscillation signal to one or more of the plurality of voltage generation units in response to the detection signals.. . ... Sk Hynix Inc

07/14/16 / #20160202314

Test circuit and method of semiconductor device

A test method of a semiconductor device may include receiving a first encrypted test program externally from the semiconductor device, decrypting the first encrypted test program based on an encryption key, and generating a first test signal by driving the decrypted first test program.. . ... Sk Hynix Inc

07/07/16 / #20160197624

Reliability-assisted bit-flipping decoding algorithm

A method for decoding low-density parity check (ldpc) codes, includes computing an initial syndrome of an initial output, obtaining an initial number of unsatisfied checks based on the computed initial syndrome, and when the initial number of unsatisfied checks is greater than zero, computing a reliability value with a parity check, performing a bit flip operation, computing a subsequent syndrome of a subsequent output, and ending decoding when a number of unsatisfied checks obtained based on the computed subsequent syndrome is equal to zero.. . ... Sk Hynix Inc

07/07/16 / #20160197606

Semiconductor devices and semiconductor systems including the same

The semiconductor device includes a first drive control signal generator suitable for generating a first drive control signal from a test input signal, a first output driver suitable for being controlled according to the first drive control signal, a second drive control signal generator suitable for generating a second drive control signal from the first drive control signal, and a second output driver suitable for being controlled according to the second drive control signal.. . ... Sk Hynix Inc

07/07/16 / #20160197389

Electromagnetic interference suppressing structure and electronic device having the same

An electromagnetic interference suppressing structure including a multi-layered substrate; a differential pair including first and second signal lines which are disposed on a first layer of the multi-layered substrate; and two grounding recess structures disposed symmetrically in a second layer of the multi-layered substrate which is positioned under the first layer, and on both sides, respectively, of the differential pair, wherein no electrical coupling element extends across a region lying directly under the differential pair, between the two grounding recess structures.. . ... Sk Hynix Inc

07/07/16 / #20160197153

Nonvolatile memory devices having single-layered floating gates

A nonvolatile memory device includes a plurality of twin cells arrayed on a substrate. Each of the plurality of twin cells includes a drain mesa protruding from a surface of a substrate. ... Sk Hynix Inc

07/07/16 / #20160197040

Power line structure for semiconductor apparatus

A semiconductor apparatus has one or more semiconductor chips. The semiconductor apparatus may include a power supply pad; power lines disposed on one side of the power supply pad, and including a first power line and a second power line; and connection lines connecting the power supply pad and the power lines. ... Sk Hynix Inc

07/07/16 / #20160197036

Electronic device including a semiconductor memory unit that includes cell mats of a plurality of planes vertically stacked

An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of planes vertically stacked over a substrate. ... Sk Hynix Inc

07/07/16 / #20160197003

Semiconductor device with air gap and method of fabricating the same

A method of fabricating a semiconductor device and a semiconductor device formed by the method. The method includes form a stack conductive structure by stacking a first conductive pattern and an insulation pattern over a substrate; forming a sacrificial pattern over sidewalls of the stack conductive structure; forming a second conductive pattern having a recessed surface lower than a top surface of the stack conductive structure; forming a sacrificial spacer to expose sidewalls of the insulation pattern by removing an upper portion of the sacrificial pattern; reducing a width of the exposed portion of the insulation patters; forming a capping spacer to cap the sidewalls of the insulation pattern having the reduced width over the sacrificial spacer; and forming an air gap between the first conductive pattern and the second conductive pattern by converting the sacrificial spacer to volatile byproducts.. ... Sk Hynix Inc

07/07/16 / #20160196982

Method of fabricating semiconductor device

A method of fabricating a semiconductor device includes forming line patterns over a first region of an etch target layer and a pre-pad pattern over second and third regions of the etch target layer; forming pillars over the line patterns and a sacrificial pad pattern over the pre-pad pattern; forming first spacers over sidewalls of the pillars such that the first spacers contact one another and form first pre-openings therebetween; removing the pillars to form second pre-openings; cutting the line patterns through the first and second pre-openings, and forming cut patterns; etching the pre-pad pattern using the sacrificial pad pattern as an etch mask, and forming a pad pattern; and etching the etch target layer using the cut patterns and the pad pattern as an etch mask, to define first patterns and a second pattern over the first region and the second region, respectively.. . ... Sk Hynix Inc

07/07/16 / #20160196881

Repair information storage circuit and semiconductor apparatus including the same

A repair information storage circuit may include a fuse block, a controller, and a fuse latch array. The fuse block provides a boot-up enable signal and repair information. ... Sk Hynix Inc

07/07/16 / #20160196877

Semiconductor memory device including three-dimensional array structure

A semiconductor memory device may include source selection transistors coupled to a common source line, source side dummy memory cells coupled between the source selection transistors and the normal memory cells, and drain selection transistors coupled to a bit line. The semiconductor memory device may include drain side dummy memory cells coupled between the drain selection transistors and the normal memory cells. ... Sk Hynix Inc

07/07/16 / #20160196857

Stacked memory device and system

A stack memory device may include a core chip and a base chip. The core chip may include a data receiver, a strobe signal generation unit, and a test register. ... Sk Hynix Inc

07/07/16 / #20160196855

Cas latency setting circuit and semiconductor memory apparatus including the same

A semiconductor memory apparatus includes a cas latency setting circuit configured to change an initially-set cas latency value in response to control signal pulses which are sequentially applied, during a test mode without changing settings of a mode register set during each test.. . ... Sk Hynix Inc

07/07/16 / #20160196209

Memory controller, method of controlling the same, and semiconductor memory device having both

A memory controller, a method of controlling the same, and a semiconductor memory device having the same are provided. The memory controller includes a cache memory provided between an external host and a nonvolatile memory; and a memory manager suitable for storing a plurality of determination values respectively corresponding to a plurality of addresses of the cache memory, wherein the memory manager selects one of the plurality of addresses as a load address corresponding to data to be loaded in the cache memory based on the plurality of the determination values, and initialize the determination value corresponding to the load address based on a type of a command from the host.. ... Sk Hynix Inc

07/07/16 / #20160195889

Semiconductor device and semiconductor system including a voltage detection block

A semiconductor device may include an internal voltage generation circuit including at least one resistor element and a plurality of mos transistors, and configured to change amounts of current flowing through the plurality of mos transistors according to a level of the first node and control driving of an internal voltage. The semiconductor device may include an internal circuit configured to operate by being supplied with the internal voltage. ... Sk Hynix Inc

06/16/16 / #20160173835

Color filter array and image sensor having the same

A color filter array includes a plurality of first pixels transmitting light having visible wavelengths, a plurality of second pixels transmitting light having a first range of wavelengths in the visible spectrum, a plurality of third pixels transmitting light having a second range of wavelengths in the visible spectrum, and a plurality of crosstalk detection pixels each including a first half pixel and a second half pixel, wherein the first half pixel transmits light having first wavelengths in a part of the first range, and wherein the second half pixel partially transmits light having second wavelengths in a part of the second range.. . ... Sk Hynix Inc

06/16/16 / #20160173270

Semiconductor apparatus and system

A semiconductor apparatus includes a transmission block and a reception block. The transmission block may convert an input signal into two or more synchronization signals, some bits of which have longer data valid windows than the other bits, and output the two or more synchronization signals. ... Sk Hynix Inc

06/16/16 / #20160172488

Semiconductor device having dual work function gate structure, method for fabricating the same, transistor circuit having the same, memory cell having the same, and electronic device having the same

A semiconductor device including a substrate in which a trench is formed, a first impurity region and a second impurity region formed in the substrate separated from each other by the trench, a gate electrode formed to fill a lower part of the trench, and a capping layer formed over the gate electrode to fill an upper part of the trench. The gate electrode includes a first work function liner formed over a bottom surface and sidewalls of the lower part of the trench without overlapping with the first impurity region and the second impurity region, and including an aluminum-containing metal nitride; and a second work function liner formed over the sidewalls of the lower part of the trench over the first work function liner, overlapping with the first impurity region and the second impurity region, and including a silicon-containing non-metal material.. ... Sk Hynix Inc

06/16/16 / #20160172433

Surface treatment method for semiconductor device

A surface treatment method for a semiconductor device includes providing a substrate where a plurality of projected patterns are formed, forming a hydrophobic coating layer on a surface of each of the plurality of projected patterns, rinsing the substrate with deionized water, and drying the substrate, wherein the hydrophobic coating layer is formed using a coating agent that includes phosphate having more than one hydrocarbon group, phosphonate having more than one hydrocarbon group, or a mixture thereof.. . ... Sk Hynix Inc

06/16/16 / #20160172398

Image sensor and method for fabricating the same

An image sensor includes a plurality of filters, an air spacer formed between the plurality of filters, and a protection layer including a first part formed on the plurality of filters and a second part formed on the air spacer. The second part of the protection layer may have a convex lens shape that protrudes over the plurality of filters.. ... Sk Hynix Inc

06/16/16 / #20160172393

Curved image sensor, method for fabricating the same, and electronic device having the same

A curved image sensor includes a supporting substrate, a bonding pattern provided over the supporting substrate a sensing substrate provided over the supporting substrate and in contact with the bonding pattern, and having a curved surface receiving incident light, and a fixing pattern provided over the supporting substrate and surrounding a periphery of the sensing substrate.. . ... Sk Hynix Inc

06/16/16 / #20160172374

Three-dimensional nonvolatile memory device

A semiconductor device includes word lines stacked in a cell region of a substrate and each of the word lines includes a first conductive layer. At least one selection line is stacked on top of the word lines and includes a second conductive layer. ... Sk Hynix Inc

06/16/16 / #20160172371

Semiconductor device and method of manufacturing the same

A semiconductor device includes interlayer insulating films spaced apart from each other and stacked over each other, and wherein first ends of the interlayer insulating films form a stepped structure; a slit penetrating the interlayer insulating films and dividing the interlayer insulating films into a plurality of stack structures; line patterns arranged between adjacent interlayer insulating films and separated from each other by the slit; pad patterns connected to the line patterns, formed over the first ends of the interlayer insulating films, and separated from each other by the slit; and at least one punch prevention pattern formed over sidewalls of the pad patterns adjacent to the slit and formed over the first ends of the interlayer insulating films.. . ... Sk Hynix Inc

06/16/16 / #20160172364

Semiconductor device and method for forming the same

A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film, a bit line contact plug that is coupled to the active region and that includes a first ion implantation region buried in a first inner void, and a storage node contact plug that is coupled to the active region and includes a second ion implantation region buried in a second inner void. ... Sk Hynix Inc

06/16/16 / #20160172331

Semiconductor package including a plurality of stacked chips

A semiconductor package may include a substrate having a first surface and a second surface facing away from the first surface, a window defined through a center portion of the substrate, and a plurality of first bond fingers, a plurality of second bond fingers, and a plurality of external electrodes arranged on the second surface; two or more first semiconductor chips each having a plurality of first bonding pads arranged adjacent to edges of the first semiconductor chips, and each of the first semiconductor chips separately attached to the first surface of the substrate in a face-down type position exposing the first bonding pads; and a second semiconductor chip having a plurality of second bonding pads arranged at a center portion of the second semiconductor chip, and attached to each of the first semiconductor chips in a face-down type position exposing the second bonding pads through the window.. . ... Sk Hynix Inc

06/16/16 / #20160172304

Semiconductor device including air gaps and method of fabricating the same

This technology provides a semiconductor device and a method of fabricating the same, which may reduce parasitic capacitance between adjacent conductive structures, the method of fabricating a semiconductor device may include forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers over sidewalis of the contact holes, forming first plugs recessed into the respective contact holes, forming air gaps by removing the sacrificial spacers, forming capping structures capping the air gaps while exposing top surfaces of the first plugs, and forming second plugs over the first plugs.. . ... Sk Hynix Inc

06/16/16 / #20160172056

Semiconductor device

A semiconductor device includes a memory array including a plurality of memory blocks, wherein the memory blocks are grouped into sub-block groups, and the sub-block groups are grouped into main block groups; an operation circuit suitable for performing a read operation and a test read operation on memory cells included in the memory block; and a read counter suitable for counting a first number of read operations for each word line in the respective main block groups and a second number of read operations for the respective sub-block groups.. . ... Sk Hynix Inc

06/16/16 / #20160172050

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program pulse applying operation and a verify operation on the memory cell array, a pass/fail check circuit performing a pass/fail check operation on a program operation including the program pulse applying operation and the verify operation, and a control logic controlling the peripheral circuit and the pass/fall check circuit to perform the pass/fail check operation during the program pulse applying operation.. . ... Sk Hynix Inc

06/16/16 / #20160172049

Semiconductor device and method of operating the same

A semiconductor device and a method of operating the same are provided. The method includes determining whether a read operation on a selected page is a beginning read operation on the selected page; performing a least significant bit (lsb) read operation on the selected page when the read operation is the beginning read operation on the selected page according to a determination result, and performing a first sub-read operation on the selected page according to a result of the lsb read operation; and performing a second sub-read operation including the lsb read operation or a most significant bit (msb) read operation on the selected page according to stored program state data when the read operation is not the beginning read operation on the selected page according to the determination result.. ... Sk Hynix Inc

06/16/16 / #20160172048

Semiconductor memory device

A semiconductor memory device is provided. The semiconductor memory device includes memory strings including drain-side memory cells connected between a bit line and a pipe transistor, and source-side memory cells connected between the pipe transistor and a source line, and a peripheral circuit suitable for applying a pipe gate voltage to a pipe gate of the pipe transistor before applying pass voltages to turn on non-selected memory cells among the drain-side memory cells and the source-side memory cells during a read operation.. ... Sk Hynix Inc

06/16/16 / #20160172047

Semiconductor device and operating method thereof

A semiconductor device includes a memory array including memory blocks; and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the program loop is performed by controlling a target threshold voltage value of the selection transistors based on a difference between a cell current value of the selected memory block and a reference cell current value.. . ... Sk Hynix Inc

06/16/16 / #20160172043

Semiconductor device and method of operating the same

A semiconductor device and a method of operating the same are provided. The method includes performing a multi-plane erase operation on selected planes; determining that the multi-plane erase operation has failed when a number of erase loops reaches a maximum number without successful completion of the multi-plane erase operation; determining whether there are passed planes amongst the selected planes; and performing a soft program operation on the passed planes.. ... Sk Hynix Inc

06/16/16 / #20160172042

Semiconductor device and method of operating the same

A method of operating a semiconductor device includes dividing an operation of the semiconductor device into a plurality of periods, and determining a plurality of state codes respectively corresponding to the periods; performing the operation according to a received command; when a pause command is received, pausing the operation and storing a state code of the plurality of state codes corresponding to a paused period among the plurality of periods; and performing the operation starting from a period determined according to the stored state code when a resumption command is received.. . ... Sk Hynix Inc

06/16/16 / #20160172039

Semiconductor memory device and method of operating the same

A semiconductor memory device and a method of operating the same are provided. The device includes a memory cell array including a plurality of memory cells is arranged in a plurality of columns, a peripheral circuit configured to program selected memory cells of the memory cells when a program operation is performed, and a control logic configured to control the peripheral circuit during the program operation. ... Sk Hynix Inc

06/16/16 / #20160172012

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a plurality of data buffering units corresponding to a data line, wherein the data buffering units include a first data buffering unit suitable for latching data stored in a memory cell in a data read operation, and second data buffering units, an output unit suitable for outputting the data latched in the first data buffering unit, and a control block suitable for controlling a current path to be formed between the second data buffering units and the output unit in the data read operation.. . ... Sk Hynix Inc

06/16/16 / #20160170898

Controller including map table, memory system including semiconductor memory device, and method of operating the same

A memory system and a method of operating the same are provided. The method includes storing a first map table including a mapping relation between first physical addresses specifying pages of memory blocks having multi-level cells and first logical addresses, storing first logical address groups of the first logical addresses as meta information, determining a second logical address group of a request address, detecting whether the second logical address group is in the first logical address groups of the meta information, and searching for the request address in the first map table based on the detecting result.. ... Sk Hynix Inc

06/16/16 / #20160170648

Data storage device and operating method thereof

An operating method of a data storage device includes receiving a read request from a host device, and selectively collecting position information of read-requested data.. . ... Sk Hynix Inc

06/16/16 / #20160170432

Reference voltage generator

A reference voltage generator includes a mirroring circuit generating a first sub-voltage and a second sub-voltage that are constant, a first voltage generator including a first switch generating a first voltage based on the first sub-voltage, and a second voltage generator including a second switch generating a second voltage that is lower than the first voltage based on the second sub-voltage, wherein the second switch has a threshold voltage that is lower than the first switch to keep a voltage difference between the first voltage and the second voltage as a first reference voltage.. . ... Sk Hynix Inc

06/16/16 / #20160169944

Electronic apparatus

An electronic apparatus includes a first voltage detection circuit which detects when a voltage, becomes higher than a first level after the voltage starts to be supplied to a peripheral circuit, and detects when the voltage becomes lower than a second level after a supply of the voltage to the peripheral circuit starts to be interrupted, and a second voltage detection circuit which detects when the voltage becomes lower than a reference level while the peripheral circuit operates. The second level is lower than the reference level.. ... Sk Hynix Inc

06/09/16 / #20160164667

Clock and data recovery circuit and system using the same

A clock and data recovery circuit may include: a phase detection unit configured to generate an early phase detection signal and a late phase detection signal by comparing a clock signal and data; a filtering unit configured to generate an up signal and a down signal based on a number of generation times of the early phase detection signal and a number of generation times of the late phase detection signal; a phase information summing unit configured to receive an output of the filtering unit at each cycle of the clock signal, and generate first and second phase control signals by summing up numbers of the up signals and the down signals received from the filtering unit during a summing-up time; and a phase interpolator configured to adjust a phase of the clock signal according to the first and second phase control signals.. . ... Sk Hynix Inc

06/09/16 / #20160164666

Clock and data recovery circuit and system using the same

A clock and data recovery circuit may include a phase detection unit, a first filtering unit, a second filtering unit, and a phase interpolation unit. The phase detection unit compares a clock signal with data and generates a plurality of early phase detection signals and a plurality of late phase detection signals. ... Sk Hynix Inc

06/09/16 / #20160164543

Turbo product codes for nand flash

A method of encoding data in a data block includes generating a first xor parity from an xor of all data bits in the data block and an xor of all row parities of all rows in the data block besides a last row, storing the first xor parity in the last row, and generating a second xor parity from an xor of all column parities of all columns in the data block and an xor of a parity of the last row.. . ... Sk Hynix Inc

06/09/16 / #20160164521

Semiconductor device

A semiconductor device may include a first channel provided in a first die. The semiconductor device may include a second channel provided in a second die and disposed adjacent to the first channel, and configured to exchange signals and data with the first channel. ... Sk Hynix Inc

06/09/16 / #20160164513

Voltage generation apparatus

A voltage generation apparatus may include an external voltage sensing circuit configured to generate a first start signal and a second start signal by sensing the magnitude of a first external voltage and the magnitude of a second external voltage. The voltage generation apparatus may include an internal voltage sensing circuit configured to generate a voltage generation signal by comparing an internal voltage with a target voltage. ... Sk Hynix Inc

06/09/16 / #20160164504

Latch circuit

A latch circuit includes a first pmos transistor suitable for pull-up driving a second node based on a voltage of a first node, a first nmos transistor suitable for pull-down driving the second node based on a voltage of the first node, a second pmos transistor suitable for pull-up driving the first node based on a voltage of the second node, a second nmos transistor suitable for pull-down driving the first node based on a voltage of the second node, a first separation element suitable for electrically separating the first nmos transistor from the second node when the first pmos transistor is turned on, and a second separation element suitable for electrically separating the second nmos transistor from the first node when the second pmos transistor is turned on.. . ... Sk Hynix Inc

06/09/16 / #20160164501

Semiconductor apparatus

A semiconductor apparatus includes a pipe input/output signal generation block configured to generate a plurality of pipe input signals and a plurality of pipe output signals according to a pipe enable signal, and be initialized according to an error detection signal; a pipe latch group including a plurality of pipe latches, each of the plurality of pipe latches being configured to receive and store an input signal according to a corresponding pipe input signal and output a stored signal as an output signal according to a corresponding pipe output signal; and an error detection block configured to generate the error detection signal according to a pipe end signal, the pipe enable signal, the plurality of pipe input signals and the plurality of pipe output signals.. . ... Sk Hynix Inc

06/09/16 / #20160164499

Signal input circuit and operating method thereof

An input circuit includes: an input buffering unit suitable for receiving one or more input data, wherein each toggling time is defined according to a value of each input data; and a data transformation unit suitable for transforming the input data into an output data according to a mapping table and the toggling time of the input data during a data input duration.. . ... Sk Hynix Inc

06/09/16 / #20160164465

Buffer circuit capable of improving amplification performance

A buffer circuit may include an amplification reference voltage generation unit and an amplification unit. The amplification reference voltage generation unit may generate an amplification reference voltage. ... Sk Hynix Inc

06/09/16 / #20160164459

Oscillator and semiconductor device including the same

An oscillator may include first to n-th delay signal generation units, each of which delays and inverts an input signal thereof. Each of the first to n-th delay signal generation units includes an inverter suitable for driving a first node with a low level voltage when a voltage of an input node thereof is higher than a first reference voltage, and driving the first node with a high level voltage when the voltage of the input node thereof is lower than the first reference in voltage; a rc delay unit electrically coupled between the first node and a second node, and suitable for to delaying a signal of the first node and outputting the delayed signal of the first node to the second node; and a buffer suitable for outputting a high level signal when a voltage of the second node is higher than a second reference voltage, and outputting a low level signal when the voltage of the second node is lower than the second reference voltage.. ... Sk Hynix Inc

06/09/16 / #20160163734

Three-dimensional nonvolatile memory device, semiconductor system including the same, and method of manufacturing the same

A three-dimensional nonvolatile memory device includes a first vertical channel layer and a second vertical channel layer extending from a substrate, a plurality of memory cells, first selection transistors and second selection transistors spaced apart from each other along the first vertical channel layer and the second vertical channel layer, a pad, a contact plug and a bit line in a stacked configuration over the first vertical channel layer, and a common source line formed over the second vertical channel layer.. . ... Sk Hynix Inc

06/09/16 / #20160163678

Semiconductor apparatus having electrical connections with through-via and a metal layer and stacking method thereof

A semiconductor apparatus may include a first metal layer including a first unit pad. The semiconductor apparatus may include a second metal layer including first and second unit pads. ... Sk Hynix Inc

06/09/16 / #20160163619

Semiconductor chip and stack type semiconductor apparatus using the same

A semiconductor may include a core block configured to store and output data, and may be configured to output internal information. The semiconductor may include a through via configured for signal transfer with another semiconductor chip. ... Sk Hynix Inc

06/09/16 / #20160163607

Semiconductor device, semiconductor system and method of testing semiconductor device

A semiconductor device may include a semiconductor substrate doped with a first type impurity; a through electrode inserted in the semiconductor substrate; an active area formed in the semiconductor substrate to surround an upper portion of sidewalls of the through electrode, and doped with a second type impurity; an insulating layer formed between the semiconductor substrate and the through electrode, and between the active area and the through electrode; a drive circuit suitable for applying a first voltage to the through electrode in a test operation; and a test pad connected to the active area electrically in the test operation, to which a voltage is applied from outside.. . ... Sk Hynix Inc

06/09/16 / #20160163594

Method for forming void-free polysilicon and method for fabricating semiconductor device using the same

A method for fabricating a semiconductor device includes forming a buried gate electrode in a semiconductor substrate. An insulating layer is formed over the buried gate electrode and is etched to form a contact hole exposing the semiconductor substrate. ... Sk Hynix Inc

06/09/16 / #20160163394

Semiconductor memory apparatus and method for reading data from the same

A semiconductor memory apparatus includes a memory block including memory cells coupled between a bit line and a source line and operating in response to voltages applied to word lines, and a peripheral circuit suitable for performing operations relating to data input and output of the memory cells, wherein the peripheral circuit is suitable for applying a precharge voltage to the bit line when word lines adjacent to a selected word line are set to a floating state.. . ... Sk Hynix Inc

06/09/16 / #20160163390

Semiconductor device

A semiconductor device includes a memory array including a plurality of memory blocks. Each memory block includes a pipe transistor, a drain select transistor and a first memory cell connected between the pipe transistor and a bit line, and a source select transistor and a second memory cell connected between the pipe transistor and a common source line. ... Sk Hynix Inc

06/09/16 / #20160163381

Memory system including semiconductor memory device and method of operating the same

A semiconductor memory device and a method of operating the same are provided. The method includes determining the number of valid pages of a first memory block as a first count value, determining the number of valid pages of a second memory block as a second count value, applying a weight to the first count value and generating a comparison count value which is greater than the first count value, and defining the first and second memory blocks as a victim block by comparing the comparison count value and the second count value with a threshold value.. ... Sk Hynix Inc

06/09/16 / #20160163375

Memory device

A memory device may include: first to nth cell blocks; first to (n−1)th bit line sense amplifiers, of which a kth bit line sense amplifier amplifies a potential difference between a bit line of a kth cell block and a bit line of a (k+1)th cell block; one or more first outermost bit line sense amplifiers suitable for amplifying a potential difference between a first node and a bit line of the first cell block, wherein drivability for driving the first node is different from drivability for driving the bit line of the first cell block; and one or more second outermost bit line sense amplifiers suitable for amplifying a potential difference between a second node and a bit line of the nth cell block, wherein drivability for driving the second node is different from drivability for driving the bit line of the nth cell block.. . ... Sk Hynix Inc

06/09/16 / #20160163372

Semiconductor memory device and refresh control method thereof

A semiconductor memory device includes a memory bank including a plurality of word lines, and a refresh operation control unit suitable for performing a first refresh operation for a first adjacent word line group of a target word line of the plurality of word lines, and performing a second refresh operation for a second adjacent word line group of the target word line after the first refresh operation, in response to a smart refresh command.. . ... Sk Hynix Inc

06/09/16 / #20160163368

Address comparator circuit, memory device and memory system including the same

An address comparator circuit includes a first determination unit suitable for activating a first control signal when a first address corresponding to a previous read command is identical with a second address corresponding to a current read command; a second determination unit suitable for activating a second control signal when the previous and current read commands are consecutively inputted to the address comparator circuit with an interval of a specific number of clocks or less; and a blocking signal generation unit suitable for generating a blocking signal that blocks data transmission between a memory array and an external device based on the first and the second control signals.. . ... Sk Hynix Inc

06/09/16 / #20160163367

Semiconductor memory apparatus

A semiconductor memory apparatus may include a decoding control block configured to generate a first decoding control signal and a second decoding control signal in response to a double enable signal and a first address. The semiconductor memory apparatus may include a decoding block configured to enable only one word line among a plurality of word lines or may simultaneously enable at least two word lines among the plurality of word lines, in response to the first and second decoding control signals and a second address.. ... Sk Hynix Inc

06/09/16 / #20160163365

Semiconductor device

A semiconductor device may include a mat array, and a plurality of memory cell mats each including bit lines. The memory cell mats may be included in the mat array. ... Sk Hynix Inc

06/09/16 / #20160163364

Semiconductor memory device

Disclosed is a semiconductor memory device including: a sense amplifier capable of sensing and amplifying data loaded on a data-line pair based on a pull-up driving voltage and a pull-down driving voltage; a pull-up driving unit capable of supplying a first voltage as the pull-up driving voltage for first and third active sections of an active mode, and supplying a second voltage having a voltage level lower than the first voltage as the pull-up driving voltage for a second active section of the active mode, between the first and third active sections of the active mode; and a pull-down driving unit capable of supplying a third voltage as the pull-down driving voltage for the first to third active sections of the active mode and for an initial section of a precharge mode after the active mode.. . ... Sk Hynix Inc

06/09/16 / #20160163363

Semiconductor memory apparatus and input buffer therefor

A semiconductor memory apparatus may include an input buffer configured to receive an external signal, boost the external signal to a frequency according to an operation mode signal, and generate an internal signal; and an internal circuit configured to operate by receiving the internal signal.. . ... Sk Hynix Inc

06/09/16 / #20160163362

Input circuit of semiconductor apparatus and semiconductor system using the same

An input circuit of a semiconductor apparatus may include a first input buffer configured to receive a signal through a test input terminal and to output a first input signal, a second input buffer configured to receive a signal through a normal input terminal and to output a second input signal. The input circuit of the semiconductor apparatus may include a switching unit configured to transfer the signal inputted through the test input terminal to the second input buffer according to a test mode signal. ... Sk Hynix Inc

06/09/16 / #20160163361

Data output circuit

A data output circuit includes a first trigger unit and a signal generation unit. The first trigger unit is inputted with first data in a first mode and a second mode, and outputs the first data in response to a first trigger signal. ... Sk Hynix Inc

06/09/16 / #20160163360

Latch circuit and latch circuit array including the same

A latch circuit may include first to fourth storage nodes; first to fourth transistor pairs, each including a pmos transistor and an nmos transistor connected in series through a corresponding one of the first to fourth storage nodes, wherein each of the first to fourth storage nodes is connected to a gate of an nmos transistor of a transistor pair in a previous stage and a gate of a pmos transistor of a transistor pair in a next stage; a first connection unit suitable for connecting a data bus with a kth storage node of the first to fourth storage nodes when read and write operations are performed, wherein k is an integer from 1 to 4; and second connection units suitable for connecting the data bus with one or more of the first to fourth storage nodes, except for the kth storage node, when the write operation is performed.. . ... Sk Hynix Inc

06/09/16 / #20160163359

Data sense amplifier and memory device including the same

A data sense amplifier may include: first and second external nodes, wherein a potential difference occurs between the first and second external nodes when a memory cell is selected; an amplification unit suitable for generating and amplifying a potential difference between first and second nodes in response to the potential difference between the first and second external nodes; and a switching unit suitable for electrically coupling the first and second external nodes to the first and second nodes, respectively, after a predetermined time elapses from when the memory cell is selected.. . ... Sk Hynix Inc

06/09/16 / #20160162351

Parity check circuit and memory device including the same

A parity check circuit may include a first signal combination unit for generating first to nth combination signals by combining first to nth signals, wherein a kth (k is a natural number of 2≦k≦n) combination signal of the first to nth combination signals is obtained by combining the first to kth signals of the first to nth signals, a parity check unit for detecting whether an error is present in the first to nth signals in response to the nth combination signal, a second signal combination unit for generating first to nth reconstruction signals by combining the first to nth combination signals, wherein a kth reconstruction signal of the first to nth reconstruction signals is obtained by combining a (k−1)th combination signal and the kth combination signal of the first to nth combination signals, and a signal storage unit for storing the first to nth reconstruction signals.. . ... Sk Hynix Inc

06/09/16 / #20160162300

Semiconductor device and method for driving the same

A semiconductor device includes an internal signal processing block suitable for generating an internal enable signal and an internal control signal that correspond to an external enable signal and an external control signal, and a monitoring unit suitable for outputting a monitoring signal that corresponds to a predetermined internal signal, based on the internal enable signal and the internal control signal, in an initial operation period.. . ... Sk Hynix Inc

06/09/16 / #20160162191

Operation apparatus module

An operation apparatus module includes a plurality of operation apparatuses disposed in a preset pattern. Each of the plurality of operation apparatuses includes a storage block suitable for storing self-identification information for identifying a corresponding operation apparatus and peer identification information for identifying one or more peer operation apparatuses of the corresponding operation apparatus; and an identification block suitable for managing the preset pattern by comparing the self-identification information stored in the storage block with the peer identification information transmitted from the peer operation apparatuses.. ... Sk Hynix Inc

06/09/16 / #20160161969

Semiconductor device

A semiconductor device may include: a first reference voltage generation unit: suitable for outputting an external voltage as a first reference voltage and clamping the first reference voltage based on a preset voltage in a positive direction from a ground voltage; a first internal voltage generation unit suitable for receiving the external voltage to drive an internal voltage terminal with a drivability corresponding to the first reference voltage; and a second internal voltage generation unit suitable for receiving the external voltage to drive the internal voltage terminal based on a second reference voltage greater than the preset voltage in the positive direction from the ground voltage.. . ... Sk Hynix Inc

06/09/16 / #20160161968

Semiconductor apparatus including multichip package

A semiconductor apparatus including a multichip package is disclosed. The semiconductor apparatus includes a slave chip having a slave region and a master region. ... Sk Hynix Inc

06/02/16 / #20160155937

Vertical type semiconductor device, fabrication method thereof and operation method thereof

A vertical type semiconductor device and a fabrication method thereof are provided. The vertical type semiconductor device includes a pillar structure having a stacking structure of a conductive layer and a data storage material and formed on a common source region, and a gate electrode formed to surround the data storage material of the pillar structure.. ... Sk Hynix Inc

06/02/16 / #20160155933

Electronic device and method for fabricating the same

Provided is an electronic device. The electronic device according to an implementation of the disclosed technology includes a semiconductor memory, the semiconductor memory including: a substrate; an interlayer insulating layer formed over the substrate; a metal-containing insulating layer formed over the interlayer insulating layer and including a second metal; a contact hole formed through the interlayer insulating layer and the metal-containing insulating layer; a contact plug filling a portion of the contact hole; a contact pad formed over the contact plug so as to fill the remaining portion of the contact hole; and a variable resistance element formed over the contact pad, wherein the contact pad includes a metal-containing material including a first metal, and the second metal has a higher electron affinity than the first metal.. ... Sk Hynix Inc

06/02/16 / #20160155810

Semiconductor device with buried gates and fabrication method thereof

A semiconductor device includes a substrate having a cell region and a peripheral region, a buried gate formed over the substrate of the cell region, a peripheral gate formed over the substrate of the peripheral region and comprising a conductive layer, an inter-layer dielectric layer that covers the substrate, and a peripheral bit line formed inside the inter-layer dielectric layer and contacting the conductive layer.. . ... Sk Hynix Inc

06/02/16 / #20160155779

Stack type semiconductor memory device

A stack type memory device and a method of manufacturing the same are provided. The stack type memory device includes a semiconductor substrate, a plurality of active layers stacked on the semiconductor substrate, and a gate structure overlapping the plurality of active layers. ... Sk Hynix Inc

06/02/16 / #20160155673

Semiconductor device having tungsten gate electrode and method for fabricating the same

The present invention provides a semiconductor device in which the threshold voltage of nmos and the threshold voltage of pmos are independently controllable, and a method for fabricating the same. The method includes: forming a gate insulating film over an nmos region and a pmos region of a semiconductor substrate; forming a carbon-containing tungsten over the gate insulating film formed over one of the nmos region and the pmos region; forming a carbon-containing tungsten nitride over the gate insulating film formed over the other one of the pmos region or the nmos region; forming a tungsten film over the carbon-containing tungsten and the carbon-containing tungsten nitride; post-annealing the carbon-containing tungsten and the carbon-containing tungsten nitride; and etching the tungsten film, the carbon-containing tungsten, and the carbon-containing tungsten nitride, to form a gate electrode in the nmos region and the pmos region. ... Sk Hynix Inc

06/02/16 / #20160155659

Interconnection structure including air gap, semiconductor device including air gap, and method of manufacturing the same

A semiconductor device includes a first insulating layer, a second insulating layer formed on the first insulating layer, a plurality of interconnection lines formed in the second insulating layer, and a first air gap disposed between the first insulating layer and the second insulating layer to surround a lower part of the interconnection lines.. . ... Sk Hynix Inc

06/02/16 / #20160155511

Nonvolatile memory device and operating method thereof

A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with p-type impurities.. . ... Sk Hynix Inc

06/02/16 / #20160155509

Memory string and semiconductor device including the same

A memory string includes a pass transistor, first memory cells connected in series to a drain terminal of the pass transistor, and first to kth memory cell groups connected in parallel to a source terminal of the pass transistor and each including a plurality of second memory cells connected in series. Here, ‘k’ denotes an integer that is equal to or greater than ‘2’.. ... Sk Hynix Inc

06/02/16 / #20160155504

Semiconductor memory device

Disclosed is a semiconductor memory device. The semiconductor memory device includes a plurality of first memory cells included in a first memory cell group and coupled to a plurality of first bit lines, respectively, a plurality of first switches coupled to the first bit lines, respectively, and coupled to a voltage node, a driver configured to supply a constant voltage to the voltage node for a write operation, and a switch control unit configured to selectively turn on one or more of the first switches when the write operation is performed.. ... Sk Hynix Inc

06/02/16 / #20160155503

Electronic device having resistance element

An electronic device includes a first electrode, a second electrode spaced apart from the first electrode, a resistance variable element interposed between the first electrode and the second electrode, and a conductor arranged at least one of a first side and a second side of the resistance variable element to apply an electric field to the resistance variable element while being spaced apart from the resistance variable element, the first side facing the second side.. . ... Sk Hynix Inc

06/02/16 / #20160155498

Vertical type semiconductor device, fabrication method thereof and operation method thereof

A vertical type semiconductor device and a fabrication method thereof are provided. The vertical type semiconductor device includes a pillar structure having a stacking structure of a conductive layer and a data storage material and formed on a common source region, and a gate electrode formed to surround the data storage material of the pillar structure.. ... Sk Hynix Inc

06/02/16 / #20160155494

Memory system and method of operating the same

A memory system and a method of operating the same are provided. The method includes reading least significant bit (lsb) data of a first physical page based on a first pre-read voltage and performing a most significant bit (msb) program based on the lsb data of the first physical page when the msb program is performed on the first physical page, defining a management area by comparing the number of error bits included in msb data of the first physical page with a first threshold value, preforming an lsb program on a second physical page of the management area, reading lsb data of the second physical page based on a second pre-read voltage, which is lower than the first pre-read voltage, and performing the msb program on the second physical page based on the lsb data of the second physical page.. ... Sk Hynix Inc

06/02/16 / #20160155490

Memory device and memory system including the memory device

A memory device includes a first memory bank comprising first and second memory blocks; a second memory bank comprising third and fourth memory blocks; and a bank selection unit suitable for selecting a memory bank corresponding to a bank address among the first and the second memory banks when an active command is applied, wherein the selected memory bank performs row access on a word line of an unselected memory block, while activating a word line of a memory block that is selected by a block address among memory blocks of the selected memory bank.. . ... Sk Hynix Inc

06/02/16 / #20160155483

Semiconductor device and semiconductor system including the same

A semiconductor device includes a pipe latch suitable for sequentially latching data in response to a pipe input control signal and sequentially outputting data in response to a pipe output control signal, a pipe latch control unit suitable for generating the pipe input/output control signals in response to a command signal and latency information, and resetting the pipe input/output control signals in response to a pipe reset signal, and an error detection unit suitable for receiving the pipe input control signal and the pipe output control signal, detecting a latency error, and generating the pipe reset signal. . ... Sk Hynix Inc

06/02/16 / #20160154765

Storage node based on pci express interface

A storage node includes a storage element module. The module includes a first peripheral component interconnect express (pcie) switch suitable for uplink connection, a second pcie switch coupled to the first pcie switch, and at least one connection element coupled to the second pcie switch, suitable for coupling with at least one storage element. ... Sk Hynix Inc

06/02/16 / #20160154151

Color filter array, image sensor including the same, and infrared data acquisition method using the same

A color filter array includes first pixels, second pixels, third pixels, and fourth pixels. The first pixels transmit light with visible and infrared (ir) wavelengths. ... Sk Hynix Inc

05/26/16 / #20160150168

Image sensor having vertical transfer gate and electronic device having the same

An image sensor may include: a photoelectric conversion element; a transfer gate formed over the photoelectric conversion element; a plurality of active pillars electrically coupled to the photoelectric conversion element by penetrating the transfer gate; a reset transistor coupled to the plurality of active pillars; and a source follower transistor having a gate electrically coupled to one or more active pillars among the plurality of active pillars.. . ... Sk Hynix Inc

05/26/16 / #20160149592

Apparatus and method for turbo product codes

An apparatus for a turbo product codes includes a codeword generator and an interleaver. The codeword generator receives a data in a matrix, and generate a turbo product code (tpc) codeword including the data, row parities and column parities. ... Sk Hynix Inc

05/26/16 / #20160149575

Buffer circuit and operation method thereof

A buffer circuit includes an amplification unit suitable for sensing and amplifying an input signal and a reference voltage, a buffer enable unit suitable for enabling the amplification unit based on a buffer enable signal, and a buffer enable signal generation unit suitable for generating the buffer enable signal based on a first or second operation control signal, selected according to a high voltage detection signal.. . ... Sk Hynix Inc

05/26/16 / #20160149485

Internal voltage generation circuits

An internal voltage generation circuit may include a pump controller and an internal voltage generator. The pump controller suitable for generating a first control signal enabled if a level of an internal voltage signal is lower than a target voltage level and a second control signal enabled if a level of the internal voltage signal is lower than the target voltage level after a predetermined period elapses from a point of time that the internal voltage signal is pumped. ... Sk Hynix Inc

05/26/16 / #20160149125

Resistive memory device and fabrication method thereof

A semiconductor integrated circuit device and a fabrication method thereof are disclosed. The resistive memory device includes a lower electrode, a resistive layer formed in a resistance change region on the lower electrode, an upper electrode formed on the resistive layer, and an insertion layer configured to allow a reset current path of the resistive layer, which is formed from the upper electrode to the lower electrode, to be bypassed in a direction perpendicular to or parallel to a surface of the lower electrode.. ... Sk Hynix Inc

05/26/16 / #20160149121

Electronic device and method for fabricating the same

This technology provides an electronic device and method for fabricating the same. A method for fabricating an electronic device comprising a transistor includes forming a junction region which is partially amorphized in the semiconductor substrate at a side of the gate; forming a metal layer over the junction region; and performing a heat treatment process on the metal layer into a metal-semiconductor compound layer while crystallizing the junction region.. ... Sk Hynix Inc

05/26/16 / #20160149120

Electronic device and method for fabricating the same

This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes an interlayer dielectric layer formed over a substrate and having a hole; a conductive pattern filled in the hole and having a top surface located at a level substantially same as a top surface of the interlayer dielectric layer; and an mtj (magnetic tunnel junction) structure formed over the conductive pattern to be coupled to the conductive pattern and including a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein an upper portion of the conductive pattern includes a first amorphous region.. ... Sk Hynix Inc

05/26/16 / #20160148979

Electronic device and method for fabricating the same

An electronic device is provided. An electronic device according to an example of the disclosed technology includes a semiconductor memory, the semiconductor memory including: a substrate including a recess formed in the substrate; a gate including at least a portion that is buried in the substrate; a junction formed at both sides of the gate in the substrate; and a memory element electrically connected to the junction at one side of the gate, wherein the junction includes: a barrier layer formed over the recess such that a thickness of the barrier layer formed over a bottom surface of the recess is different from that of the barrier layer formed over a side surface of the recess; a contact pad formed over the barrier layer so as to fill the recess; and an impurity region formed in the substrate and located under the contact pad.. ... Sk Hynix Inc

05/26/16 / #20160148974

Electronic device and method for fabricating the same

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an interlayer dielectric layer formed over a substrate including first and second areas; a first contact plug contacted with the substrate through the interlayer dielectric layer of the second area; an anti-peeling layer formed over the interlayer dielectric layer including the first contact plug; a second contact plug contacted with the substrate through the anti-peeling layer and the interlayer dielectric layer in the first area; and a variable resistance pattern contacted with the second contact plug.. ... Sk Hynix Inc

05/26/16 / #20160148948

Semiconductor device and method of manufacturing the same

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a core insulating film, a channel film surrounding the core insulating film and extending to a higher level than an upper surface of the core insulating film to have a first end of the channel film exposed over the core insulating film, a channel pad formed over an inner wall of the first end of the channel film exposed over the core insulating film, and a contact plug coupled to the channel pad.. ... Sk Hynix Inc

05/26/16 / #20160148941

Semiconductor device and manufacturing method of the same

A semiconductor device may include semiconductor patterns. The semiconductor device may include insulating layers including first regions surrounding the semiconductor patterns and second regions isolated from each other by island-type first openings and connecting the first regions adjacent to each other. ... Sk Hynix Inc

05/26/16 / #20160148938

Semiconductor device having a gate and a conductive line in a pillar pattern

A semiconductor device including a vertical gate and a method for manufacturing the same are disclosed, which prevent a floating body phenomenon, thereby increasing a cell threshold voltage and reducing leakage current, resulting in improved refresh properties of the semiconductor device. The semiconductor device includes a plurality of pillar patterns, including first pillar patterns arranged along a first direction and second pillar patterns arranged along a second direction, formed over a semiconductor substrate; a gate extending in the first direction, arranged along sidewalls of the first pillar patterns, and configured to couple the first pillar patterns; a junction region formed in an upper portion of the pillar patterns; and a conductive line arranged along the sidewalls of the first pillar patterns and provided in a region disposed below the junction region and over the gate.. ... Sk Hynix Inc

05/26/16 / #20160148934

Semiconductor device including gate structure for threshold voltage modulation in transistors and method for fabricating the same

A method for fabricating a semiconductor device includes forming an nmos region and a pmos region in a substrate, forming a first stack layer including a first gate dielectric layer and a first work function layer that is disposed over the first gate dielectric layer and contains aluminum, over the pmos region of the substrate, forming a second stack layer including a second gate dielectric layer, a threshold voltage modulation layer that is disposed over the second gate dielectric layer and contains lanthanum, and a second work function layer that is disposed over the threshold voltage modulation layer, over the nmos region of the substrate, and annealing the first stack layer and the second stack layer, thereby forming a first dipole-interface by diffusion of the aluminum in the first gate dielectric layer and a second dipole-interface by diffusion of the lanthanum in the second gate dielectric layer, respectively.. . ... Sk Hynix Inc

05/26/16 / #20160148908

Multi-chip package system

A multi-chip package system includes a signal transmission line commonly coupled to a plurality of semiconductor chips to transfer data to/from the semiconductor chips from/to outside; and a termination controller suitable for detecting a loading value of the signal transmission line and controlling a termination operation on the signal transmission line based on the loading value.. . ... Sk Hynix Inc

05/26/16 / #20160148884

Memory apparatus having power pad

A memory apparatus includes a pad, an internal circuit that is connected with the pad, a power connection unit connected with power meshes, and a first switching unit suitable for selectively connecting the pad with the power connection unit based on a package control signal.. . ... Sk Hynix Inc

05/26/16 / #20160148696

Semiconductor memory device and method of operating the same

A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes a plurality of memory layers stacked on a semiconductor substrate, wherein each of the plurality of memory layers includes one or more connection control transistors, one or more drain select transistors, a plurality of memory cells, and a source select transistor electrically coupled in series between a plurality of bit lines and a common source line, and the plurality of memory layers share the plurality of bit lines, and the common source lines electrically coupled to each of the plurality of memory layers are electrically disconnected.. ... Sk Hynix Inc

05/26/16 / #20160148695

Data storage device and method of programming memory cells

A method of programming a non-volatile memory device includes programming memory cells selected from the plurality of memory cells by increasing turn values of program loops based on an incremental step pulse program (ispp) algorithm; detecting a first turn value of a first program loop wherein, in the first program loop, a first number or a first ratio of first unprogrammed memory cells is smaller than or equal to a first set value; calculating a second turn value of a second program loop based on the first turn value wherein, in the second program loop, a second number or a second ratio of second unprogrammed memory cells is expected to be smaller than or equal to a second set value, the second set value being smaller than the first set value; executing subsequent program loops on the unprogrammed memory cells up to the second program loop; detecting a third number or a third ratio of third unprogrammed memory cells in the second program loop; comparing the third number or the third ratio of the third unprogrammed memory cells to the second set value; determining a program pass when the third number or the third ratio of the third unprogrammed memory cells is smaller than or equal to the second set value; and determining a program fail when the third number or the third ratio of the unprogrammed memory cell exceeds the second set value.. . ... Sk Hynix Inc

05/26/16 / #20160148693

Semiconductor device

A semiconductor device is provided. The semiconductor device may include a memory block including memory cells, the memory cells connected to a word line. ... Sk Hynix Inc

05/26/16 / #20160148690

Semiconductor memory device and operating method thereof

The present invention relates to a semiconductor memory device and an operating method thereof. The semiconductor memory device may include at least two memory blocks sharing a row decoder, and a peripheral circuit performing a read operation on a selected memory block, between the at least two memory blocks, wherein the peripheral circuit applies a discharge voltage to an unselected memory block, between the at least two memory blocks, for a preset time after a period in which a read voltage is applied to the selected memory block is terminated.. ... Sk Hynix Inc

05/26/16 / #20160148668

Cell array, memory, and memory system including the same

A memory includes a first cell array configured to include a plurality of first memory cells connected to a plurality of word lines, a second cell array configured to include a plurality of second memory cells connected to the plurality of word lines, wherein a group of the plurality of second memory cells which are connected to a corresponding word line stores the number of activations for the corresponding word line, and an activation number update unit configured to update a value stored in the corresponding group of the plurality of second memory cells connected to the activated word line of the plurality of word lines.. . ... Sk Hynix Inc

05/26/16 / #20160147624

Semiconductor device and method of operating the same

A semiconductor device and a method of operating the same are provided. The method includes determining the degree of deterioration of a selected memory block, performing a program operation of the selected memory block in a first program operating condition when it is determined that the selected memory block is not deteriorated and performing the program operation of the selected memory block in a second program operating condition when it is determined that the selected memory is deteriorated, and updating the program operating time of the selected memory block.. ... Sk Hynix Inc

05/26/16 / #20160147250

Semiconductor package and semiconductor system including the same

A semiconductor package may include a first die, a second die disposed adjacent to the first die, and configured to share an address with the first die. The semiconductor package may include a first address pin included with the first die, and configured for receiving the address. ... Sk Hynix Inc

05/26/16 / #20160146677

Temperature sensor

A temperature sensor includes a first current generating circuit configured to generate a first current being constant regardless of temperature changes, a cascode circuit configured to generate a cascode voltage, a second current generating circuit configured to generate a second current being in inverse proportion to temperature, and a compensated voltage output circuit configured to output a compensated voltage having various temperature coefficients in response to the first current and the second current.. . ... Sk Hynix Inc

05/19/16 / #20160142155

Semiconductor packages with optical interconnection structures, memory cards including the same, and electronic systems including the same

A semiconductor package includes a first transceiver disposed on a top surface of a substrate; and a second transceiver disposed on a bottom surface of the substrate. The first and second transceivers optically communicate with each other through optical signals that permeate the substrate.. ... Sk Hynix Inc

05/19/16 / #20160142060

Delay locked loop circuit and operation method thereof

A delay locked loop (dll) circuit may include: an input clock control unit suitable for transmitting first and second internal clocks generated based on an external clock, and controlling transmission of the second internal clock based on a clock control signal which is activated during a predetermined period; a clock delay unit suitable for generating a first delay locked clock by delaying the first internal clock by a delay time required for locking, and generating a second delay locked clock by delaying the second internal clock based on the clock control signal; and an output clock control unit suitable for outputting the first delay locked clock and the second delay locked clock during a period in which the clock control signal is activated.. . ... Sk Hynix Inc

05/19/16 / #20160142058

Delay circuit

A delay circuit may include a fine timing measurement unit suitable for measuring fine timing information on whether an input signal corresponds to the timing of any one of an even cycle or an odd cycle based on a clock, a coarse delay unit suitable for delaying the input signal whose fine timing has been measured by the fine timing measurement unit in synchronization with a frequency divided clock and outputting a delayed signal, and a fine timing application unit suitable for applying the fine timing information to the delayed signal of the coarse delay unit.. . ... Sk Hynix Inc

05/19/16 / #20160141302

Semiconductor device and method of manufacturing the same

A semiconductor device includes stacked groups each including interlayer insulating patterns and conductive patterns and stacked in at least two tiers, wherein the insulating patterns and the conductive patterns are alternately stacked over a substrate and separated by slits, and a support body including holes and formed between the stacked groups.. . ... Sk Hynix Inc

05/19/16 / #20160141245

Radio-frequency integrated circuits including inductors and methods of fabricating the same

A radio-frequency integrated circuit (rfic) includes a substrate, an n-type deep well region disposed in an upper region of the substrate and having a top surface coplanar with a top surface of the substrate, an inductor disposed over the n-type deep well region; and an insulation layer disposed between the inductor and the n-type deep well region, wherein the inductor is electrically insulated from the n-type deep well region by the insulation layer.. . ... Sk Hynix Inc

05/19/16 / #20160141049

Anti-fuse type one-time programmable memory cell array and method of operating the same

An anti-fuse type one-time programmable (otp) memory cell array includes a plurality of unit cells which are respectively located at cross points of a plurality of rows and a plurality of columns, a well region shared by the plurality of unit cells, a plurality of anti-fuse gates respectively disposed in the plurality of columns to intersect the well region, a plurality of source/drain regions respectively disposed in portions of the well region between the plurality of anti-fuse gates, and a plurality of drain regions respectively disposed in portions of the well region located at one sides of the anti-fuse gates arrayed in a last column, which are opposite to the anti-fuse gates arrayed in a first column. Each of the unit cells includes one anti-fuse transistor having a mos transistor structure without a selection transistor.. ... Sk Hynix Inc

05/19/16 / #20160141043

Semiconductor device

A semiconductor device is provided. The semiconductor device may include a memory block including memory strings connected to respective bit lines coupled to a substrate and commonly connected to a common source line coupled to the substrate. ... Sk Hynix Inc

05/19/16 / #20160141038

Semiconductor device

A semiconductor device includes memory blocks including a plurality of memory cells, wherein the plurality of memory cells are divided into a plurality of pages, and an operation circuit suitable for outputting operating voltages to local lines of the memory blocks to perform a program loop, an erase loop and a read operation on the plurality of memory cells, wherein the operation circuit is suitable for applying a dummy pulse having a positive potential to the local lines after the program loop or the erase loop is completed.. . ... Sk Hynix Inc

05/19/16 / #20160141037

Semiconductor memory system and method of operating the same

A method of operating a semiconductor memory system includes: programming lsb data into a memory cell of a selected word line included in a memory block; storing msb data to be programmed into the memory cell of the selected word line, from a controller into a page buffer; reading the programmed lsb data from the memory cell of the selected word line; performing an ecc operation on the read lsb data when a difference between a reference amount and an amount of bit line current, which flows through bit lines included in the memory block, does not fall in a predetermined range from a first current amount to a second current amount; and programming the msb data stored in the page buffer into the memory cell of the selected word line based on the ecc-corrected lsb data.. . ... Sk Hynix Inc

05/19/16 / #20160141035

Semiconductor memory device and method of operating the same

A semiconductor memory device and a method of operating the same are provided. The device may include a memory cell array including a plurality of memory blocks and a peripheral circuit configured for selecting one of the plurality of memory blocks and performing a program operation on selected memory cells of the selected memory block when the program operation is performed. ... Sk Hynix Inc

05/19/16 / #20160141027

Resistance variable memory apparatus, read circuit unit and operation method therefor

A resistance variable memory apparatus may include: a memory cell array; and a read circuit unit configured to receive a cell current, generate a digital code by repeating a cyclic analog-to-digital conversion (adc) process a designated number of times, generate read data from the digital code, and output the generated read data during a normal read mode for the memory cell array, and to generate test data corresponding to the cell current and output the generated test data during a test read mode for the memory cell to array.. . ... Sk Hynix Inc

05/19/16 / #20160141026

Memory system and method of operating the same

A memory system includes a memory device including memory blocks, each of the memory blocks including pages, each of the pages including memory cells that are electrically coupled to word lines, wherein the memory cells store data that is requested from a host; and a controller suitable for reading first data corresponding to a read command received from the host, from a page of a first memory block among the memory blocks, storing the first data in a buffer, providing the first data stored in the buffer, to the host, and writing and storing the first data stored in the buffer, in a page of a second memory block among the memory blocks.. . ... Sk Hynix Inc

05/19/16 / #20160141014

Semiconductor integrated circuit

A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a ddr (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.. . ... Sk Hynix Inc

05/19/16 / #20160141011

Semiconductor device and operating method thereof

Provided is a semiconductor device and an operating method thereof. The operating method of the semiconductor device includes performing an erase operation on a memory block including bottom dummy cells, a plurality of memory cells, top dummy cells and selection transistors arranged in a vertical direction with respect to a pipe gate, increasing threshold voltages of the top and bottom dummy cells at substantially a same time by applying a first soft program voltage to a bottom dummy word line coupled to the bottom dummy cells and a second soft program voltage greater than the first soft program voltage to the top dummy word line coupled to the top dummy cells, verifying the top and bottom dummy cells, and repeatedly performing the erase operation and increasing the threshold voltages by gradually increasing the first and second soft program voltages until the verifying of the top and bottom dummy cells passes.. ... Sk Hynix Inc

05/19/16 / #20160141010

Semiconductor memory apparatus and system including the same

A semiconductor memory apparatus includes a dbi calculation block, an inversion latch block, an inverted data selective output block, and a pipe latch block. The dbi calculation block performs a dbi calculation and outputs a dbi result signal based on a result of the dbi calculation. ... Sk Hynix Inc

05/19/16 / #20160141009

Semiconductor apparatus and operating method thereof

A semiconductor apparatus including a register input selection block configured to serially receive input data and output the input data in parallel as first and second data sets, or receive register selection output signals and output the register selection output signals as the first and second data sets, in response to a shift control signal and a capture control signal; a first data register configured to receive and store the first data set and output stored data as first register output signals; a second data register configured to receive and store the first and second data sets and output stored data as second register output signals; a register output selection block configured to output ones of the first and second register output signals as the register selection output signals; and a data output selection block configured to serially output one of the first and second data sets as output data.. . ... Sk Hynix Inc

05/19/16 / #20160141005

Semiconductor integrated circuit and method of driving the same

Provided is a semiconductor integrated circuit including a plurality of memory chips stacked therein, each of the memory chips may include: a pumping enable signal control unit suitable for generating a pumping enable signal in response to a power-up signal or a trigger signal received from a first adjacent memory chip, delaying the pumping enable signal by a given time, and outputting the delayed pumping enable signal to a second adjacent memory chip; and a pumping unit suitable for generating a pumping voltage by performing a pumping operation in response to the pumping enable signal.. . ... Sk Hynix Inc

05/19/16 / #20160139987

Generating soft read values using multiple reads and/or bins

A starting read threshold is received. A first offset and a second offset is determined. ... Sk Hynix Inc

05/19/16 / #20160139984

Data storage device and operating method thereof

A data storage device may include a memory device suitable for storing data and reading stored data as read data, and a bit distribution check unit suitable for performing a first error detection operation on the read data, based on a bit distribution of the read data.. . ... Sk Hynix Inc

05/19/16 / #20160139817

Deduplication using a master and a slave

A write instruction includes a logical address and write data to be stored. An address mapping master is used to determine if the logical address is stored in an address table. ... Sk Hynix Inc

05/19/16 / #20160139812

Hot-cold data separation method in flash translation layer

A method of data separation includes receiving a host write command operation identifying temperature of data contained in memory blocks during the host write command operation, selecting a victim block of the memory blocks based on the identified temperature, moving data from the victim block to a destination block, and assigning a sequence number to the destination block when the destination block is full.. . ... Sk Hynix Inc

05/19/16 / #20160139203

Test setting circuit, semiconductor device, and test setting method

A test setting circuit includes a first detection unit suitable for detecting whether a first code is sequentially inputted based on a first sequence, at each of first to nth steps, where n is a natural number; a second detection unit suitable for sequentially receiving a second code through the first to nth steps, and detecting whether the second code that is sequentially inputted through the first to nth steps has a value corresponding to a second sequence; and a test setting unit suitable for setting a test mode when it is detected that the first code and the second code are inputted to satisfy the first sequence and the second sequence.. . ... Sk Hynix Inc

05/12/16 / #20160133731

Lateral bipolar junction transistors having high current-driving capability

A bipolar junction transistor includes a common base region, a plurality of emitter regions disposed in the common base region and arrayed to be spaced apart from each other in a first diagonal direction, and a plurality of collector regions disposed in the common base region and arrayed to be spaced apart from each other in the first diagonal direction. The plurality of emitter regions and the plurality of collector regions are alternately arrayed in a second diagonal direction.. ... Sk Hynix Inc

05/12/16 / #20160133642

Semiconductor device and method of fabricating the same

A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes: a memory cell structure formed over a semiconductor substrate; a channel portion formed in the semiconductor substrate; a through-hole formed to pass through the memory cell structure; a first channel region formed over sidewalls of the through-hole; and a second channel region formed at a center part of the through-hole, and spaced apart from the first channel region, wherein each of the first channel region and the second channel region is coupled to the channel portion.. ... Sk Hynix Inc

05/12/16 / #20160133607

Semiconductor system

A semiconductor system may include first semiconductor device including a first pad, a second pad and a first test input pad, and suitable for storing data inputted in series through the first test input pad and outputting the stored data in parallel through the first pad and the second pad; a second semiconductor device including a third pad, a fourth pad and a second test output pad, and suitable for storing data inputted in parallel through the third pad and the fourth pad, a first through via connecting the first pad and the third pad so that the stored data outputted in parallel through the first pad is inputted in parallel through the third pad; and a second through via connecting the second pad and the fourth pad so that the stored data outputted in parallel through the second pad is inputted in parallel through the fourth pad.. . ... Sk Hynix Inc

05/12/16 / #20160133564

Semiconductor device with damascene bit line and method for fabricating the same

A semiconductor device includes a substrate having a plurality of contact surfaces, an interlayer dielectric layer formed over the substrate and having a first open portion which exposes a part of the contact surfaces and a second open portion which exposes the other contact surfaces, a storage node contact (snc) plug filling the first open portion, and a damascene structure filing the second open portion and including a bit line, a spacer formed on both sidewalls of the bit line, a capping layer formed over the bit line and the spacer, and an air gap formed between the bit line and the spacer. The bit line includes a conductive material of which the volume is contracted by a heat treatment to form the air gap.. ... Sk Hynix Inc

05/12/16 / #20160133511

Semiconductor device and method of manufacturing the same

A semiconductor device includes an interlayer insulating layer having openings, contact plugs formed in lower parts of the openings, wherein the contact plugs include a first conductive layer, and bit lines formed in upper parts of the openings and coupled to the contact plugs, wherein the bit lines include a second conductive layer.. . ... Sk Hynix Inc

05/12/16 / #20160133344

Repair circuit, semiconductor memory device and method of operating the same

A repair circuit includes a column repair signal generation block suitable for comparing an input address with respective first and second repair addresses in response to a mode control signal, and generating first and second column repair signals; a normal decoder suitable for accessing any one of a first normal column line corresponding to the input address and a second normal column line corresponding to an address that is different in terms of a most significant bit from the input address, in response to the first and second column repair signals; and a redundancy decoder suitable for decoding the first repair address in response to the first and second column repair signals, wherein the second repair address is generated by inverting a most significant bit of the first repair signal.. . ... Sk Hynix Inc

05/12/16 / #20160133343

Electronic device and method for operating electronic device

An electronic device comprising a semiconductor memory unit that may include a plurality of data transfer lines; a plurality of columns including a plurality of memory cells; at least one redundancy column including a plurality of redundancy memory cells and configured to replace at least one column among the plurality of columns; a repair select information generation unit configured to store a column address of the at least one column to be replaced among the plurality of columns and generate a plurality of repair select information in response to the stored column address; and a plurality of repair selection units connected with data transfer lines corresponding to them among the plurality of data transfer lines, columns corresponding to them among the plurality of columns and the at least one redundancy column, and each configured to electrically connect a column selected among a column corresponding to it and the at least one redundancy column, to a data transfer line corresponding to it, in response to repair select information corresponding to it among the plurality of repair select information.. . ... Sk Hynix Inc

05/12/16 / #20160133339

Test apparatus, test system and operating method of test apparatus

A test system may include: a vector storage unit suitable for storing a first test vector corresponding to a first test operation; a test target suitable for performing a test operation corresponding to the test vector stored in a vector storage unit; a comparison unit suitable for comparing a first test result to an expected value to output a first test result value, wherein the first test result is transferred from the test target as a result of the first test operation based on the first test vector; and a vector control unit suitable for modifying the first test vector to generate a second test vector corresponding to a second test operation.. . ... Sk Hynix Inc

05/12/16 / #20160133336

Shift register circuit and memory device including the same

A shift register circuit may include a first latch capable of latching an input signal in synchronization with a first clock, a first flip-flop capable of latching the output signal of the first latch in synchronization with a second dock having the same skew as the first clock, a second latch capable of latching the output signal of the first flip-flop in synchronization with a third clock having a different skew from the second clock, and a second flip-flop capable of latching the output signal of the second latch circuit in synchronization with a fourth clock having the same skew as the third clock.. . ... Sk Hynix Inc

05/12/16 / #20160133334

Read-threshold calibration in a solid state storage system

A read-threshold calibration method in a solid state storage system including measuring a threshold voltage distribution of solid state storage elements; determining a threshold voltage; decoding data according to the determined threshold voltage; filtering the threshold voltage distribution of solid state storage elements with a predetermined filter length when the decoding fails; changing the filter length; and repeating the determining, decoding, filtering, and changing steps with the changed filter length until the decoding is successful.. . ... Sk Hynix Inc

05/12/16 / #20160133333

Optimal read threshold estimation

An optimal read threshold estimation method includes determining a flip difference corresponding to an optimal step size Δopt, estimating a first slope m1 at a first read point and a second slope m2 at a second read point, and obtaining an optimal read threshold (xlpopt) as the intersection of a first line with the first slope m1 and a second line with the second slope m2.. . ... Sk Hynix Inc

05/12/16 / #20160133328

Semiconductor device and method of operating the same

A method of operating the semiconductor device includes performing an erase operation on a plurality of memory cells, performing a back-tunneling operation by injecting electrons into a storage node from a gate electrode of a memory cell, selected among the plurality of memory cells, and performing a program operation by injecting electrons into the storage node from a channel layer of the selected memory cell.. . ... Sk Hynix Inc

05/12/16 / #20160133313

Semiconductor memory and method for operating the same

A semiconductor memory may include: a storage unit suitable for storing a minimum operation interval between row command operations, a detection unit suitable for detecting whether row command signals inputted for the row command operations are activated at the minimum operation interval, a latching unit suitable for generating flag signals by latching the row command signals, and a shifting unit suitable for shifting the flag signals based on the minimum operation interval in response to an output signal of the detection unit, and generating an internal row command signals.. . ... Sk Hynix Inc

05/12/16 / #20160133311

Semiconductor device and method of driving the same

A semiconductor device may include a common coupling block suitable for coupling a plurality of first data lines to a plurality of second data lines in response to a common control signal, which is activated regardless of a data bandwidth option mode, a first coupling block suitable for coupling a part of the plurality of second data lines to a part of a plurality of third data lines in response to a first operation control signal, a second coupling block suitable for coupling the other part of the plurality of second data lines to the other part of the plurality of third data lines in response to a second operation control signal, and a control block suitable for activating one or more of the first and second operation control signals based on the data bandwidth option mode, during a data input/output operation.. . ... Sk Hynix Inc

05/12/16 / #20160133302

Nonvolatile memory device and method of operating the same

A nonvolatile memory device may include a power-on reset signal generation unit suitable for receiving a power supply voltage, and generating a power-on reset signal that changes based on the power supply voltage, and a discharging signal generation unit suitable for generating a discharging signal for discharging a word line to be activated earlier than an activation timing of the power-on reset signal when the power supply voltage decreases.. . ... Sk Hynix Inc

05/12/16 / #20160132406

Data storage device and operating method thereof

A data storage device includes memory devices including respective main regions and respective virtual regions, and a processor suitable for forming a super page by selecting main pages from the respective main regions, wherein when a main page of a main region in a memory device is a bad region, the processor forms a virtual super page by selecting a virtual page from a virtual region in the memory device instead of the main page.. . ... Sk Hynix Inc

05/12/16 / #20160131710

Test system for semiconductor apparatus and test method using the same

A test system for a semiconductor apparatus that includes a calibration board having first skew information therein and outputting a plurality of test signals, and a main board configured to perform first skew correction for correcting skews of the test signals based on the first skew information and perform secondary skew correction for correcting an i/o skew thereof using the plurality of test signals. . ... Sk Hynix Inc

05/12/16 / #20160131697

Built-in test circuit of semiconductor apparatus

A semiconductor apparatus includes a clock buffer and a reference voltage generation unit. The clock buffer generates an internal clock signal, based on first and second clock signals, in a first operation mode, and generates the internal clock signal, based on the first clock signal and a reference voltage, when a normal operation test is performed in a second operation mode. ... Sk Hynix Inc

05/05/16 / #20160126277

Image sensor and method for fabricating the same

An image sensor includes a substrate including two or more photoelectric conversion regions corresponding to two or more pixels, respectively, two or more color filters formed on the substrate corresponding to the photoelectric conversion regions, an interlayer insulation layer including an interconnection line and formed on the substrate, two or more condensing patterns each having a plurality of high refractive index regions and a plurality of low refractive index regions, which are alternately disposed, wherein line widths of the high and low refractive index regions are different in the respective condensing patterns depending on the pixels.. . ... Sk Hynix Inc

05/05/16 / #20160126272

Curved image sensor, method for fabricating the same, and electronic device having the same

The curved image sensor may include: a first substrate including a plurality of photoelectric conversion elements and having a curved first surface; a bonding pattern formed over a second surface opposite to the first surface of the first substrate, formed along an edge of the first substrate, and having an opening; a second substrate bonded to the second surface of the first substrate by the bonding pattern; and a sealing material filling the opening so that a cavity defined by the first substrate, the second substrate, and the bonding pattern is sealed by the sealing material.. . ... Sk Hynix Inc

05/05/16 / #20160126247

Nonvolatile memory devices having single-layered gates

A nonvolatile memory device includes an active region extending in a first direction, a first single-layered gate intersecting the active region and extending in a second direction, a second single-layered gate intersecting the active region and extending in the second direction, and a selection gate intersecting the active region. The selection gate includes a first selection gate main line and a second selection gate main line that intersect the active region to be parallel with the first and second single-layered gates, a selection gate interconnection line that connects a first end of the first selection gate main line to a first end of the second selection gate main line, and a selection gate extension that extends from a portion of the selection gate interconnection line to be disposed between first ends of the first and second single-layered gates.. ... Sk Hynix Inc

05/05/16 / #20160125949

Semiconductor device and operating method thereof

An operating method of a semiconductor device includes applying a read voltage to a selected word line of a selected memory block, among a plurality of memory blocks including cell strings coupled between bit lines and a source line, detecting a voltage of the source line by forming a channel in cell strings of the selected memory block, comparing the voltage of the source line with a reference voltage corresponding to the selected memory block, and performing a least significant bit (lsb) read operation on memory cells coupled to the selected word line when the voltage of the source line is greater than the reference voltage, as a result of the comparing, and performing a most significant bit (msb) read operation on the memory cells when the voltage of the source line is less than the reference voltage, as the result of the comparing.. . ... Sk Hynix Inc

05/05/16 / #20160125946

Semiconductor device and operating method thereof

A semiconductor device includes a memory array including memory blocks, and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the operation circuit performs the program loop on the selection transistors so that a difference occurs between threshold voltages of the selection transistors and a target threshold voltage based on a difference between a cell current value of the selected memory block and a reference cell current value.. . ... Sk Hynix Inc

05/05/16 / #20160125944

Semiconductor device

A semiconductor device according to an embodiment may include a memory string including a drain selection transistor, memory cells and a source selection transistor all coupled between a bit line and a common source line, and the drain selection transistor, the memory cells and the source selection transistor configured to operate, respectively, in response to voltages applied to a drain selection line, word lines and a source selection line. The semiconductor device may include an operation circuit configured for performing a program operation. ... Sk Hynix Inc

05/05/16 / #20160125940

Semiconductor integrated circuit device including a leakage current sensing unit and method of operating the same

A semiconductor integrated circuit device and a system including the same, configured for sensing a pure leakage current of a cell array and improving a read error is disclosed. The system a controller and a memory configured to interface with the controller. ... Sk Hynix Inc

05/05/16 / #20160125937

Semiconductor integrated circuit device including a leakage current sensing unit and method of operating the same

A semiconductor integrated circuit device configured for sensing a pure leakage current of a cell array and improving a read error is disclosed. The semiconductor integrated circuit device may include a leakage current sensing unit configured for sensing a pure leakage current of a cell array, and a determination circuit unit configured for comparing a voltage level of the input node with a reference voltage and for determining a state of read data while in a read mode. ... Sk Hynix Inc

05/05/16 / #20160125935

Semiconductor device and method of operating the same

A semiconductor device and a method of operating the same are provided. The method includes performing a program operation on a memory cell so that a threshold voltage of the memory cell is greater than a main verifying voltage, and while the program operation is performed, a bit line voltage applied to a bit line connected to the memory cell gradually increases based on the threshold voltage of the memory cell and the number of times a program voltage is applied to a word line connected to the memory cell.. ... Sk Hynix Inc

05/05/16 / #20160125119

Semiconductor integrated circuit having differential amplifier and method of arranging the same

A semiconductor integrated circuit comprises: a transistor region having a center line; a first block arranged in one side of the center line of the transistor region, and comprising a plurality of first and second groups each having a plurality of first and second segment transistors constituting first and second transistors of a differential amplifier; and a second block arranged in the other side of the center line, and having an arrangement corresponding to the arrangement of the first and second groups of the first block.. . ... Sk Hynix Inc

05/05/16 / #20160124848

Memory system and memory management method thereof

A memory system include a memory device including a plurality of blocks, each of the blocks having a plurality of pages, and a controller suitable for determining valid pages from among the plurality of pages based on data temperature, and performing a garbage collection process based on a number of valid pages and data temperature of the valid pages.. . ... Sk Hynix Inc

05/05/16 / #20160124805

Nonvolatile memory system and data recovery method thereof

A nonvolatile memory system includes a nonvolatile memory device including a plurality of memory cells; and a memory controller suitable for recovering normal data based on a recovery read level interval when an error occurs in the normal data read from the memory cells by using a reference read level, wherein the memory controller generates n distribution measurement values by measuring distribution values of threshold voltage levels of the memory cells at n respective distribution read levels, which have a preset read level interval with the reference read level serving as a center, and determines the recovery read level interval through calculating variations of the n distribution measurement values by using a linear equation, where ‘n’ is a natural number equal to or larger than 2.. . ... Sk Hynix Inc

05/05/16 / #20160124804

Nonvolatile memory system and data recovery method thereof

A nonvolatile memory system includes a nonvolatile memory device including a distribution table suitable for storing recovery read level intervals that are set by being changed through multiple stages according to a distribution value of threshold voltage levels of a plurality of memory cells, measured at a reference read level, is changed through the multiple stages; and a memory controller suitable for reading measurement data from the memory cells by additionally using a measurement read level, searching for a difference value between the normal data and the measurement data from the multiple stages of distribution values stored in the distribution table, and recovering the normal data based on a recovery read level interval corresponding to a searched distribution value, when an error occurs in normal data read from the memory cells by using the reference read level.. . ... Sk Hynix Inc

05/05/16 / #20160124640

Memory system and method of operating the same

A memory system includes a first control circuit part configured to communicate with a host through a first host channel, a second control circuit part configured to communicate with the host through a second host channel, a first chip group configured to communicate with the first control circuit part through a first internal channel, and a second chip group configured to communicate with the second control circuit part through a second internal channel, wherein the first control circuit part and the second control circuit part alternately receive a plurality of data inputted through one of the first and second host channels, which is selected during a single channel operation, and transmit the data to the first chip group and the second chip group.. . ... Sk Hynix Inc

04/28/16 / #20160118984

Calibration device and memory system having the same

A calibration device for use in a memory system includes a bias circuit providing bias current, and a calibration unit generating a control signal for calibration. The bias circuit includes an internal resistor and measures a second bias current generated by mirroring a first bias current through the internal resistor, and adjusts the second bias current to generate the second bias current in a predetermined range as a third bias current. ... Sk Hynix Inc

04/28/16 / #20160118983

Calibration circuit and calibration apparatus including the same

A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.. . ... Sk Hynix Inc

04/28/16 / #20160118978

Reference voltage generator having noise cancelling function and cmos image sensor using the same

The reference voltage generator may include a reference current generation unit suitable for generating a reference current based on a first power supply voltage and a first ground voltage, a current amount adjustment unit suitable for adjusting a current amount of the reference current generated by the reference current generation unit based on a second power supply voltage and a second ground voltage, and a reference voltage generation unit suitable for generating a reference voltage corresponding to the reference current, of which the current amount is adjusted by the current amount adjustment unit, based on the first power supply voltage and the first ground voltage.. . ... Sk Hynix Inc

04/28/16 / #20160118969

Delay adjusting apparatus and operating apparatus including the same

A delay adjusting apparatus may include at least one selective delay element electrically coupled to an electrical path between an input terminal and an output terminal of the electrical path, and the at least one selective delay element configured to add a delay factor to the electrical path in response to an enable signal. The delay adjusting apparatus may include at least one fuse circuit configured to control electrical coupling of an e-fuse, in response to a program signal, and program the enable signal.. ... Sk Hynix Inc

04/28/16 / #20160118963

Latch circuit and latch circuit array including the same

A latch circuit may include: first to nth storage nodes where n is an even number equal to or more than four; first to nth pairs of transistors each including a pmos transistor and an nmos transistor which are coupled in series through a corresponding storage node among the first to nth storage nodes, wherein each of the first to nth storage nodes is coupled to a gate of the nmos transistor of the transistor pair at the previous stage and a gate of the pmos transistor of the transistor pair at the next stage; first to nth pmos transistors suitable for driving corresponding storage nodes among the first to nth storage nodes to a high level; and first to nth nmos transistors suitable for driving corresponding storage nodes among the first to nth storage nodes to a low level.. . ... Sk Hynix Inc

04/28/16 / #20160118575

Electronic devices having semiconductor magnetic memory units

A semiconductor device includes a resistance variable element including a free magnetic layer, a tunnel barrier layer and a pinned magnetic layer; and a magnetic correction layer disposed over the resistance variable element to be separated from the resistance variable element, and having a magnetization direction which is opposite to a magnetization direction of the pinned magnetic layer.. . ... Sk Hynix Inc

04/28/16 / #20160118474

Semiconductor device and method for forming the same

A semiconductor device includes a semiconductor substrate including a trench, a gate insulation film located over a bottom and sidewall of the trench, a first gate formed over the gate insulation film and in a lower portion of the trench, a second gate formed over the first gate and in an upper portion of the trench, a multi-layered structure provided between the gate insulation film and the second gate.. . ... Sk Hynix Inc

04/28/16 / #20160118442

Electronic device and method for fabricating the same

Provided is an electronic device including a switching element, wherein the switching element may include a first electrode, a second electrode, a switching layer interposed between the first and second electrodes, and a first amorphous semiconductor layer interposed between the first electrode and the switching layer.. . ... Sk Hynix Inc

04/28/16 / #20160118403

Semiconductor device and method of manufacturing the same

A semiconductor device includes a channel layer including a sidewall having protrusions and depressions alternating with each other in a direction in which the channel layer extends, a tunnel insulating layer surrounding the channel layer, first charge storage patterns surrounding the tunnel insulating layer formed in the depressions, blocking insulation patterns surrounding the first charge patterns formed in the depressions, wherein the blocking insulating patterns include connecting portions coupled to the tunnel insulating layer, and second charge storage patterns surrounding the tunnel insulating layer formed in the protrusions.. . ... Sk Hynix Inc

04/28/16 / #20160118395

Semiconductor device and method of fabricating the same

A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a pipe gate, a multi-layered word line formed over the pipe gate, a first channel including a first pipe channel buried in the pipe gate and a first side channel coupled to both sides of the first pipe channel to pass through the word line, a second channel including a second pipe channel buried in the pipe gate and disposed over the first pipe channel and a second side channel coupled to both sides of the second pipe channel to pass through the word line, and an insulation pattern disposed between the first pipe channel and the second pipe channel.. ... Sk Hynix Inc

04/28/16 / #20160118376

Semiconductor integrated circuit

A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a first clamping unit configured to be connected to the first power line, a second clamping unit configured to be connected between the first clamping unit and the second power line, and a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit are included.. . ... Sk Hynix Inc

04/28/16 / #20160118375

Semiconductor integrated circuit

A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a first clamping unit configured to be connected to the first power line, a second clamping unit configured to be connected between the first clamping unit and the second power line, and a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit are included.. . ... Sk Hynix Inc

04/28/16 / #20160118337

Embedded packages, methods of fabricating the same, electronic systems including the same, and memory cards including the same

An embedded package includes a chip having a top surface on which a connection member is disposed, a first insulation layer surrounding a portion of the chip, a second insulation layer disposed on the first insulation layer to cover the chip, circuit patterns disposed on a bottom surface of the first insulation layer, a third insulation layer disposed on the bottom surface of the first insulation layer to cover the circuit patterns, an external connection terminal penetrating the third insulation layer to contact any one of the circuit patterns, a metal layer disposed on a top surface of the second insulation layer, a first via penetrating the first insulation layer to electrically couple the connection member to any one of the circuit patterns, and a second via penetrating the first and second insulation layers to electrically couple the metal layer to any one of the circuit patterns.. . ... Sk Hynix Inc

04/28/16 / #20160118306

Semiconductor device with buried metal layer

A semiconductor device includes: a first active region defined by a recess contained in a device isolation film of a semiconductor substrate belonging to a first region and a second region, in a peripheral region including the first region, the second region, and a third region; a second active region defined by the device isolation film contained in the semiconductor substrate of the third region; a buried metal layer buried in the recess; a first conductive layer formed over the semiconductor substrate of the first region; and a second conductive layer formed over the semiconductor substrate of the second region, wherein the first conductive layer or the second conductive layer is formed over the semiconductor substrate of the third region. A three-dimensional dual gate is formed in a peripheral region, such that performance or throughput of transistors is maximized even in the peripheral region.. ... Sk Hynix Inc

04/28/16 / #20160118139

Semiconductor devices

A semiconductor device may include a fuse controller and a fuse array. The fuse controller may be configured to generate internal address signals according to a level combination of repair data and may generate first and second voltage control signals in response to a rupture control signal that is enabled to rupture a predetermined fuse set for selecting a failed redundancy word line, in a test mode. ... Sk Hynix Inc

04/28/16 / #20160118109

Semiconductor memory device

A semiconductor memory device includes a cell string including dummy memory cells and a plurality of memory cells in which n bit data is stored, and a peripherial circuit configured to store the n bit data in first memory cells, among the memory cells, store n−1 bit data in the rest of second memory cells, and store data which is not stored in the second memory cells in at least one of the dummy memory cells, among the dummy memory cells.. . ... Sk Hynix Inc

04/28/16 / #20160118094

Semiconductor apparatus capable of self-tunning a timing margin

A semiconductor apparatus may include a delay-locked loop configured to generate a delay-locked clock signal through a delay locking operation of an internal clock signal and an external clock signal, and delay an internal read command by a delay time tuned in the delay locking operation and generate a delay-locked internal command. The semiconductor apparatus may include a tuning control block configured to generate the internal read command in response to a self-tuning enable signal generated by determining a delay locking completion time of the delay-locked loop. ... Sk Hynix Inc

04/28/16 / #20160118092

Driving apparatus and selection of a dead zone of an internal voltage

A driving apparatus includes a control circuit configured to generate a voltage region control signal enabled for a predetermined time according to a command signal; and a driving circuit configured to provide an internal voltage by selecting a dead zone of the internal voltage according to the voltage region control signal.. . ... Sk Hynix Inc

04/28/16 / #20160116972

Memory system and operating method thereof

A memory system includes a memory device including a plurality of blocks and a plurality of page buffers which respectively correspond to the blocks, wherein each of the blocks includes a plurality of pages in which data is stored, and a controller suitable for backing up data, which is stored in a memory included in the controller, in the page buffers when an operation mode is about to change to a power save mode.. . ... Sk Hynix Inc

04/28/16 / #20160116926

Integrated circuit

An integrated circuit may include a receiver suitable for comparing voltage levels of an external signal and a reference voltage with each other, and generating an internal signal, an adjustment code generation unit suitable for detecting a duty of the internal signal and generating an adjustment code of one or more bits, and a voltage adjustment unit suitable for adjusting the voltage level of the reference voltage in response to the adjustment code.. . ... Sk Hynix Inc

04/07/16 / #20160099706

Resistance element generator and output driver using the same

A resistance element generator includes a reference current generation unit suitable for receiving a source reference current to generate first and second reference currents, a first resistance generation unit suitable for generating a first resistance value by using a first reference voltage and the first reference current, and outputting a first voltage corresponding to the formed first resistance value, and a second resistance generation unit suitable for generating a second resistance value by using a third reference voltage and the second reference current, and outputting a second voltage corresponding to the formed second resistance value.. . ... Sk Hynix Inc

04/07/16 / #20160099230

Multi-chip package, test system and method of operating the same

A multi-chip package includes: a plurality of semiconductor chips that are coupled with each other through normal through silicon vias and repair through silicon vias; a state detection device suitable for detecting connection states of the normal through silicon vias and the repair through silicon vias; and a repair control device suitable for comparing the connection state of the normal through silicon vias with the connection state of the repair through silicon vias, and controlling whether to perform a repair operation.. . ... Sk Hynix Inc

04/07/16 / #20160099229

Semiconductor devices having through electrodes, semiconductor packages including the same, methods of manufacturing the same, electronic systems including the same, and memory cards including the same

A semiconductor device includes a substrate having a first surface and a second surface that are opposite to each other, a plurality of through electrodes penetrating the substrate and extending from the first surface to the second surface, front-side bumps disposed on the first surface and connected to odd-numbered through electrodes among the plurality of through electrodes, and backside bumps disposed on the second surface and connected to even-numbered through electrodes among the plurality of through electrodes. Related semiconductor packages, fabrication methods, electronic systems and memory cards are also provided.. ... Sk Hynix Inc

04/07/16 / #20160099203

Semiconductor stack packages

A semiconductor stack package includes a printed circuit board (pcb), a first semiconductor chip, and a second semiconductor chip. The first and second semiconductor chips are disposed side-by-side on a first surface of the pcb to be spaced apart from each other. ... Sk Hynix Inc

04/07/16 / #20160099152

Semiconductor device and method for fabricating the same

A method for fabricating a semiconductor device includes: implanting a first species into a substrate at a cold temperature to form a first region; and implanting a second species into the substrate at a hot temperature to form a second region that is adjacent to the first region.. . ... Sk Hynix Inc

04/07/16 / #20160099079

Repair circuit and semiconductor apparatus using the same

A repair circuit includes a fuse set latch array including a plurality of fuse set latches, and configured to store fuse informations in target fuse latches selected among the plurality of fuse set latches in response to fuse latch select signals; a fuse information control unit configured to generate the fuse latch select signals by using boot-up source signals generated by differently combining boot-up mode region select informations according to a region determination signal; and a repair processing unit configured to compare an address inputted from an exterior and the fuse informations, and access a normal memory cell corresponding to the external address or a redundant memory cell.. . ... Sk Hynix Inc

04/07/16 / #20160099076

Semiconductor memory device

A semiconductor memory device includes a memory bank divided into a plurality of test areas which provide test data for a data compression test operation, a data compressing unit suitable for generating compressed data based on the test data, a data converting unit suitable for converting the compressed data into analog data to generate a final compressed data, and an output unit suitable for outputting the final compressed data during a read operation for the data compression test operation.. . ... Sk Hynix Inc

04/07/16 / #20160099075

Fuse array circuit and semiconductor system including the same

A fuse array circuit includes a power generation block suitable for generating a driving power to be level-shifted at least once in a read operation period, a word line driving block suitable for driving a word line by using the driving power, and a fuse array suitable for outputting information programmed in a fuse that is activated by the driven word line through a bit line.. . ... Sk Hynix Inc

04/07/16 / #20160099074

Fuse circuit and semiconductor apparatus including the same

A fuse circuit includes an e-fuse array including a plurality of e-fuse elements configured to store fuse data; a latch block including a plurality of latch groups configured to latch the fuse data read from the e-fuse array; and a control block configured to output latch reset signals corresponding to the plurality of latch groups in response to an apparatus reset signal and a clock signal, wherein the control block sequentially enables the latch reset signals.. . ... Sk Hynix Inc

04/07/16 / #20160099063

Semiconductor device

A semiconductor device includes memory strings each including a drain select transistor, memory cells and a source select transistor, which are connected between a bit line and a common source line and suitable for operating based on voltages applied to a drain select line, word lines and a source select line, respectively, and an operation circuit suitable for performing a pre-program operation, an erase operation and a post-program operation on the memory strings. The operation circuit sequentially performs erase operations on the drain select transistors included in the memory strings.. ... Sk Hynix Inc

04/07/16 / #20160099060

Semiconductor memory device including a dummy memory cell and method of programming the same

A semiconductor memory and a method of programming the same are provided. A semiconductor memory device may include a memory cell array including a plurality of normal memory cells, a select transistor, and a dummy memory cell. ... Sk Hynix Inc

04/07/16 / #20160099055

Eprom cell array, method of operating the same, and memory device including the same

A memory cell array includes local blocks disposed in parallel with rows and arrayed along a direction parallel with columns, first selection lines being parallel with the rows and including a couple of first selection lines connected to each of the local blocks, second selection lines disposed in parallel with the columns, and local block selectors disposed between the plurality of local blocks. Each of the local block selectors is disposed between a qth wherein, “q” is an odd number local block and a (q+1)th local block among the local blocks to electrically connect unit cells disposed in any one of the qt local block and the (q+1)th local block to the second selection lines. ... Sk Hynix Inc

04/07/16 / #20160099030

Strobe signal interval detection circuit and memory system including the same

A strobe signal interval detection circuit may include an oscillator configured to generate a periodic signal at a preset cycle determined through a delay time of a delay circuit. The delay time of the delay circuit may be configured by modeling a path traveled by a strobe signal being transmitted to a data latch. ... Sk Hynix Inc

04/07/16 / #20160098350

Sizing a cache while taking into account a total bytes written requirement

A total bytes written (tbw) requirement associated with solid state storage is obtained. A size of a cache associated with the solid state storage is determined based at least in part on the tbw requirement. ... Sk Hynix Inc

04/07/16 / #20160098280

Semiconductor device and semiconductor system including the same

A semiconductor device includes a boot-up signal generator suitable for generating a boot-up signal based on an external reset signal and a specific mode signal; and an internal circuit suitable for performing a boot-up operation based on the boot-up signals. . ... Sk Hynix Inc

04/07/16 / #20160098214

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory apparatus suitable for accessing a target region corresponding to an access command, and a processor suitable for calculating a first hash value corresponding to the target region based on a first hash function, and updating an access count that is indexed by the first hash value.. . ... Sk Hynix Inc

04/07/16 / #20160098201

Data storage device and operating method thereof

A data storage device includes a controller configured to update an access request count and an access count corresponding to a target region based on an access request for the target region, and initialize the access count each time the access request count reaches a first threshold, and a nonvolatile memory apparatus including the target region, and configured to access the target region based on a control of the controller.. . ... Sk Hynix Inc

04/07/16 / #20160097812

Semiconductor package

A semiconductor package may include a probe circuit unit configured to be driven by buffering a signal received from a probe pad during probe testing, a bump circuit unit configured to buffer a signal received from a bump pad, and a power-source selection unit configured to change a level of an internal power-supply voltage applied to the probe circuit unit in response to a test-mode signal.. . ... Sk Hynix Inc

04/07/16 / #20160097809

Semiconductor device and multi-semiconductor package including the same

A semiconductor device includes a built-in self-test controller suitable for generating a test command and test data, and generating a test result signal in response to test result data, in a built-in self-test mode, an internal circuit suitable for performing a test operation in response to the test command and the test data and generating the test result data as a result of the test operation, and a signal transfer controller suitable for outputting the test command, the test data, and the test result signal through a set probe pad and a set bump pad in the built-in self-test mode.. . ... Sk Hynix Inc

03/31/16 / #20160093717

Dual work function buried gate type transistor and method for fabricating the same

A transistor includes a substrate having an active region defined by an isolation layer; a first trench defined in the active region and a second trench defined in the isolation layer; a fin region formed under the first trench; and a buried gate electrode covering sidewalls of the fin region and filling the first and second trenches. The buried gate electrode includes a first work function layer formed on the sidewalls of the fin region; a second work function layer formed on sidewalls of the first trench and the second trench; a third work function layer positioned over the fin region and contacting the second work function layer; and a low resistance layer contacting the third work function layer and partially filling the first and second trenches.. ... Sk Hynix Inc

03/31/16 / #20160093710

Semiconductor device and method for forming the same

A semiconductor device includes a junction region on both sides of a trench in a semiconductor substrate, a first gate electrode with a first workfunction buried in the trench, and a second gate electrode formed of a polycide layer having a second workfunction overlapping with the junction region at an upper part of the first gate electrode.. . ... Sk Hynix Inc

03/31/16 / #20160093654

Image sensor and method for operating the same

An image sensor includes a photoelectric conversion element suitable for generating photocharges corresponding to incident light, a transfer transistor suitable for transferring the generated photocharges to a floating diffusion node based on a transfer signal, and a reset transistor suitable for resetting the floating diffusion node based on a reset signal and including a memory gate.. . ... Sk Hynix Inc

03/31/16 / #20160093581

Semiconductor device with a through electrode

A semiconductor device includes a through electrode penetrating a substrate such that a first end portion of the through electrode protrudes from a first surface of the substrate, a passivation layer covering the first surface of the substrate and a sidewall of the first end portion of the through electrode, a bump having a lower portion penetrating the passivation layer and coupled to the first end portion of the through electrode, and a lower metal layer disposed between the bump and the first end portion of the through electrode. The lower metal layer extends onto a sidewall of the bump and has a concave shape.. ... Sk Hynix Inc

03/31/16 / #20160093527

Method for fabricating semiconductor device including silicon-containing layer and metal-containing layer, and conductive structure of the same

A method for fabricating a semiconductor device includes forming a silicon-containing layer; forming a metal-containing layer over the silicon-containing layer; forming an undercut prevention layer between the silicon containing layer and the metal containing layer; etching the metal-containing layer; and forming a conductive structure by etching the undercut prevention layer and the silicon-containing layer.. . ... Sk Hynix Inc

03/31/16 / #20160093509

Semiconductor device and method for forming the same

A semiconductor device in which a gettering layer is formed in a semiconductor substrate, and a method for forming the same are disclosed, resulting in increased reliability of the semiconductor substrate including the gettering layer. The semiconductor device includes a semiconductor substrate; a gettering layer formed of a first-type impurity and a second-type impurity in the semiconductor substrate so as to perform gettering of metal ion; and a deep-well region formed over the gettering layer in the semiconductor substrate.. ... Sk Hynix Inc

03/31/16 / #20160093391

Semiconductor device

A semiconductor device may include a memory string coupled between a bit line and a common source line and configured to include a drain select transistor, memory cells, and a source select transistor. The drain select transistor may be configured to operate based on a voltage applied to a drain select line. ... Sk Hynix Inc

03/31/16 / #20160093381

Method of manufacturing semiconductor device

Provided is a method of manufacturing a semiconductor device. The method includes forming memory cells which share a data storage layer; performing a first strong program operation on first memory cells, arranged in a checker board pattern among the memory cells; performing a first annealing process after the first strong program operation; performing a second strong program operation on second memory cells arranged in a reverse checker board pattern among the memory cells, and performing a slight program operation on the first memory cells; and performing a second annealing process after the second strong program operation and the slight program operation.. ... Sk Hynix Inc

03/31/16 / #20160093378

Semiconductor memory device

A semiconductor memory device may include a plurality of memory chips stacked upon one another, and electrically coupled to one another through a plurality of first tsvs. The semiconductor memory device may include a plurality of second memory chips stacked separately from the first memory chips, and the plurality of second memory chips electrically coupled to one another through a plurality of second tsvs. ... Sk Hynix Inc

03/31/16 / #20160092114

Techniques for selecting amounts of over-provisioning

A cost function is obtained where an amount of over-provisioning associated with solid state storage is an input of the cost function and a cost for a given amount of over-provisioning is an output of the cost function. An amount of over-provisioning is determined using the cost function and the amount of over-provisioning for the solid state storage is set to be the determined amount.. ... Sk Hynix Inc

03/31/16 / #20160091911

Semiconductor apparatus

A semiconductor apparatus includes a control block that generates a first control signal, a second control signal, and a heating enable signal in response to an enable signal and a heating control signal, a temperature measurement block that generates a temperature code corresponding to temperature in response to the first and second control signals, a heater that generates heat while the heating enable signal is being enabled, a code latch block that stores the temperature code in response to the first and second control signals, and outputs a first code and a second code, a control code generation circuit that generates a signal by performing an operation on the first and second codes, and generates a control code by comparing the signal with a preset code, and a reference voltage generation circuit configured to change a voltage level of a reference voltage in response to the control code.. . ... Sk Hynix Inc

03/24/16 / #20160087428

Semiconductor apparatus and test system including the same

A semiconductor apparatus includes an input/output pad configured to exchange signals with an external device; a control pad configured to be inputted with a discharge signal from the external device; and a first electrostatic protection unit configured to form an electrostatic discharge path from the input/output pad to a first voltage supply line according to the discharge signal.. . ... Sk Hynix Inc

03/24/16 / #20160087072

Dummy bit line mos capacitor and device using the same

A mos capacitor, a method of fabricating the same, and a semiconductor device using the same are provided. The mos capacitor is arranged in an outermost cell block of the semiconductor device employing an open bit line structure. ... Sk Hynix Inc

03/24/16 / #20160087011

Electronic device and method for fabricating the same

A semiconductor memory includes a substrate configured to include a plurality of active regions which are defined by isolation layers extending in a first direction and word lines extending in a second direction intersecting the first direction; source line contacts configured to be alternately disposed over the active regions arranged in the first and second directions and disposed over each of the active regions arranged in a third direction intersecting the first and second directions; source lines configured to extend in the third direction while being coupled to the source line contacts; contacts configured to be disposed over each of the active regions over which the source line contacts are not disposed; variable resistance elements configured to be disposed over each of the contacts; bit line contacts configured to be disposed over each of the variable resistance elements; and bit lines configured to extend in a fourth direction intersecting the first to third directions while being coupled to the bit line contacts.. . ... Sk Hynix Inc

03/24/16 / #20160087006

3-dimensional stack memory device

A 3-dimensional stack memory device includes a semiconductor substrate, a stacked active pattern configured so that a plurality of stripe shape active regions and insulation layers are stacked alternatively over the semiconductor substrate, a gate electrode formed in the stacked active pattern, a source and drain formed at both sides of the gate electrode in each of the plurality of active regions, a bit line formed on one side of the drain to be connected to the drain, a resistive device layer formed on one side of the source to be connected to the source, and a source line connected to the resistive device layer. The source is configured of an impurity region having a first conductivity type, and the drain is configured of an impurity region having a second conductivity type different from the first conductivity type.. ... Sk Hynix Inc

03/24/16 / #20160086957

Semiconductor device with buried bit line and method for fabricating the same

A method for fabricating a semiconductor device includes etching semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines.. . ... Sk Hynix Inc

03/24/16 / #20160086920

Semiconductor devices and semiconductor systems including the same

A semiconductor device may include a first input/output (i/o) unit and a second i/o unit. The first i/o unit may include a first input path that receives a signal through a first pad and a first output path and a first i/o controller that output a signal to the first pad. ... Sk Hynix Inc

03/24/16 / #20160086919

Multi-chip package

A multi-chip package includes first and second semiconductor chips that are sequentially stacked, each of the first and second semiconductor chips including an operation block for an internal operation, third and fourth semiconductor chips that are sequentially stacked over the second semiconductor chip and rotated 180 degrees in a horizontal direction with respect to the first and second semiconductor chips, each of the third and fourth semiconductor chips including an operation block, and through chip vias for transmitting predetermined signals between the operation blocks of the first to fourth semiconductor chips.. . ... Sk Hynix Inc

03/24/16 / #20160086888

Semiconductor device and method for forming the same

A semiconductor device includes an active region tilted at an angle with respect to a buried bit line. The buried bit line includes a metal silicide pattern and a metal pattern. ... Sk Hynix Inc

03/24/16 / #20160086679

Electronic device

An electronic device including a semiconductor memory unit that includes: a first access line coupled to a first memory cell; a second access line coupled to a second memory cell for replacing the first memory cell when the first memory cell is a failure memory cell; a first driving block coupled to one of the first access line and the second access line, and suitable for driving said one of the first access line and the second access line with a first voltage when the first memory cell is accessed; and a first repair coupling block suitable for selectively coupling the first access line and the second access line based on whether the first memory cell is a failure memory cell or not when the first memory cell is accessed.. . ... Sk Hynix Inc

03/24/16 / #20160086669

Nonvolatile memory device with improved voltage drop and method of driving the same

A nonvolatile memory device includes a block switching unit which transmits an operation signal to a memory cell array, and a voltage sustaining block which provides a voltage to sustain the operation signal to an arbitrary interconnection overlapping the block switching unit.. . ... Sk Hynix Inc

03/24/16 / #20160086667

System having a semiconductor integrated circuit device

A semiconductor memory apparatus including a latch unit configured to be driven in response to activation of a reset selection signal and resetting a first node and a second node; and an auxiliary driving unit configured to support a driving force of the latch unit in response to the reset selection signal and a voltage logic level of the first node or the second node, wherein the first node and the second node have substantially opposite voltage logic levels.. . ... Sk Hynix Inc

03/24/16 / #20160086663

Semiconductor system including semiconductor memory apparatus and temperature control method thereof

A semiconductor memory apparatus and a temperature control method thereof are provided. The semiconductor memory apparatus includes a temperature adjustment unit suitable for adjusting a temperature of a memory cell, and a temperature control unit suitable for sensing a temperature of the temperature adjustment unit, comparing a sensed temperature with a reference temperature range, and controlling the temperature adjustment unit to adjust the temperature thereof within the reference temperature range based on a comparison result.. ... Sk Hynix Inc

03/24/16 / #20160086653

Semiconductor device having transistor and semiconductor memory device using the same

Semiconductor device capable of preventing off-leakage of the transistor may include a pulse voltage generator configured to generate a pulse voltage, and a transistor configured to have a gate provided with the pulse voltage. The transistor is in an off state in response to the pulse voltage.. ... Sk Hynix Inc

03/24/16 / #20160086651

Semiconductor memory device and semiconductor memory system including the same

A semiconductor memory device includes: a memory cell array including a plurality of word lines; a word line driving unit suitable for activating a first word line among the plurality of word lines corresponding to an input address signal; an activation time detection unit suitable for enabling a detection signal by detecting an activation time of the first word line; an address latch unit suitable for latching an address information for a second word line corresponding to the first word line in response to the detection signal; and an address output unit suitable for providing the word line driving unit with the latched address information for the second word line during a refresh operation.. . ... Sk Hynix Inc

03/24/16 / #20160086650

Semiconductor memory device and memory system including the same

A semiconductor memory device includes: a command generator suitable for generating an internal active command signal corresponding to an active command signal, wherein, when an active section of the active command signal lasts for a predetermined time or longer, the internal active command signal is additionally activated; an address storage suitable for storing an address signal based on an activation number of the internal active command signal; and a refresh operation driver suitable for performing a refresh operation on a word line corresponding to the stored address signal.. . ... Sk Hynix Inc

03/24/16 / #20160086649

Smart refresh device

A smart refresh device includes an address control block configured to determine whether a specific row address is a row hammer address, and invert a first row hammer address and perform an addition/subtraction of an address; a repair control block configured to determine whether the row hammer address is a repaired address and output a stored repair address as a second repair control signal; a repair address storage block configured to store an output address of the address control block and output a stored address as a latch address; a fuse block configured to output a repair signal representing information on a repair address to the repair control block, and output a decoding signal according to the latch address; and an operator configured to add and subtract the decoding signal according to an addition signal and a subtraction signal.. . ... Sk Hynix Inc

03/24/16 / #20160086644

Semiconductor device

A semiconductor device includes a clock shifter configured to shift an active control signal by a predetermined number of clocks and output a shift signal according to a test signal; a command selection block configured to select any one of the active control signal and the shift signal according to the test signal, and output an active command signal; an active control block configured to control an active state of a bank active signal according to the active command signal; and an address latch block configured to latch an internal address according to the active command signal and the active control signal, and output a row address to a core region.. . ... Sk Hynix Inc

03/24/16 / #20160085249

Voltage conversion circuit, semiconductor memory apparatus having the same, and operating method

A voltage conversion circuit may include a first reference voltage generation block configured to be provided with an external voltage, and generate a first reference voltage; a second reference voltage generation block configured to be provided with the external voltage and generate a second reference voltage according to a standby trim code; a trim code generation block configured to generate the standby trim code according to levels of the first reference voltage and the second reference voltage; and an internal voltage generation block configured to select the first reference voltage or the second reference voltage as a determined reference voltage according to an operation mode of a semiconductor memory apparatus, and to generate an internal voltage from the external voltage.. . ... Sk Hynix Inc

03/17/16 / #20160080139

Receivers and semiconductor systems including the same

The receiver includes a first buffer configured to buffer a data to generate a first internal data, a first delay unit configured to retard the first internal clock signal by a first delay period to generate a first delayed internal clock signal, and a second buffer configured to buffer the first internal data to generate a first input data.. . ... Sk Hynix Inc

03/17/16 / #20160079525

Semiconductor apparatus and method for fabricating the same

A method for fabricating a semiconductor apparatus includes forming a variable resistor region, and forming a spacer having a top linewidth and a bottom linewidth substantially equal to each other in the variable resistor region. The forming of the spacer includes forming a first insulating layer in the variable resistor region through a first method, forming a second insulating layer along a surface of the first insulating layer in the variable resistor region through a second method for providing step coverage superior to the first method, and etching the first and second insulating layers.. ... Sk Hynix Inc

03/17/16 / #20160079524

Electronic device and method for fabricating the same

An electronic device includes a semiconductor memory that includes: a variable resistance element formed over a substrate; and a carbon-containing aluminum nitride layer formed on sidewalls and in an upper portion of the variable resistance element.. . ... Sk Hynix Inc

03/17/16 / #20160079398

Semiconductor device having fin gate, resistive memory device including the same, and method of manufacturing the same

A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same. The semiconductor device includes an active pillar formed on a semiconductor substrate, the active pillar including an inner region and an outer region surrounding the inner region, and a fin gate overlapping an upper surface and a lateral surface of the active pillar. ... Sk Hynix Inc

03/17/16 / #20160079390

Semiconductor integrated circuit apparatus and method of manufacturing the same

A semiconductor integrated circuit apparatus and a method of manufacturing the same are provided. The semiconductor integrated circuit apparatus includes a semiconductor substrate having an active island, a gate buried in a predetermined portion of the active island, a source and a drain formed at both sides of the gate, and a current blocking layer formed in the active island corresponding to a lower portion of the drain. ... Sk Hynix Inc

03/17/16 / #20160079363

Transistor, electronic device having the transistor, and method for fabricating the same

An electronic device includes a semiconductor memory unit that includes: a gate including at least a portion buried in a substrate; a junction portion formed in the substrate on both sides of the gate; and a memory element coupled with the junction portion on one side of the gate, wherein the junction portion includes: a recess having a bottom surface protruded in a pyramid shape; an impurity region formed in the substrate and under the recess; and a contact pad formed in the recess.. . ... Sk Hynix Inc

03/17/16 / #20160079275

Three-dimensional (3d) semiconductor device

A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.. . ... Sk Hynix Inc

03/17/16 / #20160079273

Semiconductor device

Provided is a semiconductor device including a plurality of pillar columns, each of the plurality of pillar columns including a plurality of pillars arranged in one direction to be offset from each other, wherein an mth pillar and an (m+1)th pillar, among the plurality of pillars included in each pillar column, are aligned with each other (m is an integer of 0 or more).. . ... Sk Hynix Inc

03/17/16 / #20160079272

Double-source semiconductor device

A semiconductor device may include a first source layer, a first insulating layer located over the first source layer, and a first stacked structure located over the first insulating layer. The semiconductor device may include first channel layers passing through the first stacked structure and the first insulating layer. ... Sk Hynix Inc

03/17/16 / #20160079210

Semiconductor packages including through electrodes and methods of manufacturing the same

A semiconductor package includes a substrate and a plurality of semiconductor chips stacked on the substrate. Each of the semiconductor chips has a front surface, a rear surface opposite to the front surface, a sidewall surface connecting the front surface to the rear surface, a vertical through electrode extending from the front surface toward the rear surface with a predetermined depth, and a horizontal through electrode laterally extending from the sidewall surface to be connected to the vertical through electrode. ... Sk Hynix Inc

03/17/16 / #20160078968

Memory device and memory system including the same

A memory device includes: a non-volatile memory circuit suitable for storing hard repair data; a data bus suitable for transmitting the hard repair data during a boot-up operation, and transmitting soft repair data during a soft repair mode; a plurality of registers suitable for storing repair data transmitted through the data bus and activated when the transmitted repair data is stored; a control circuit suitable for selecting a register to store the transmitted repair data among the plurality of the registers, and during the soft repair mode, deactivating a register that stores the same data as the transmitted repair data; and a memory bank suitable for performing a repair operation based on the data stored in a register that is activated among the plurality of the registers.. . ... Sk Hynix Inc

03/17/16 / #20160078962

Anti-fuse type one-time programmable memory cell and anti-fuse type one-time programmable memory cell arrays

An anti-fuse type otp memory cell includes a first anti-fuse transistor having a first channel width, a first selection transistor sharing a first active region with the first anti-fuse transistor and having a second channel width that is greater than the first channel width, a second anti-fuse transistor sharing a program gate with the first anti-fuse transistor and having a third channel width, and a second selection transistor sharing a second active region with the second anti-fuse transistor and having a fourth channel width that is greater than the third channel width.. . ... Sk Hynix Inc

03/17/16 / #20160078950

Semiconductor device and operating method thereof

An operating method of a semiconductor device includes repeating an erase loop operable to lower threshold voltages of memory cells in a selected memory block by applying an erase voltage to the selected memory block and performing an erase verification to determine whether the threshold voltages of the memory cells in the selected memory block are less than or equal to a target level, wherein an erase voltage is increased by a voltage difference wherein the voltage difference is increased between successive applications of two or more of the erase loops, and repeating a program loop including applying a program voltage to a selected word line to increase threshold voltages of memory cells electrically coupled to the selected word line and performing a program verification to determine whether the threshold voltages are greater than or equal to a target level, wherein a program voltage is increased by a voltage difference wherein the voltage difference is increased between successive applications of two or more program voltages.. . ... Sk Hynix Inc

03/17/16 / #20160078946

Memory system and operation method thereof

A memory system includes a memory device having a plurality of memory blocks, each including a plurality of pages, each page including a plurality of memory cells, wherein data provided from a host device is written on the plurality of pages and the plurality of memory cells coupled to a plurality of word lines; and a controller suitable for setting word line zones by grouping the plurality of word lines by a predetermined number, and performing a bad management for the memory blocks in each of the word line zones.. . ... Sk Hynix Inc

03/17/16 / #20160078942

Operating characteristics of a semiconductor device

Provided is a semiconductor device. The semiconductor device includes memory blocks including select transistors electrically coupled to local select lines and memory cells electrically coupled to local word lines, a first connection circuit configured to electrically couple the local select lines of a selected memory block and global select lines according to a block select signal, and formed in a first well region of a substrate, and a second connection circuit configured to electrically couple the local word lines of the selected memory block and global word lines according to the block selection signal, and formed in a second well region of the substrate.. ... Sk Hynix Inc

03/17/16 / #20160078918

Memory device and memory system including the same

A memory device includes: a plurality of memory blocks; an address counting block suitable for generating a counting address that is changed when all the memory blocks are refreshed; a target address generation block suitable for generating a target address, which is an address of a word line requiring an additional refresh operation, in the memory blocks; and a refresh control block suitable for controlling a 1st number of the memory blocks to be refreshed to when a refresh command is inputted a 1st number of times and controlling a 2nd number of the memory blocks to be refreshed when the refresh command is inputted a 2nd number of times, wherein the refresh control block controls a word line corresponding to the counting address to be refreshed and controls a word line corresponding to the target address to be refreshed during a target refresh operation.. . ... Sk Hynix Inc

03/17/16 / #20160078908

Semiconductor memory apparatus and operation method using the same

A semiconductor memory apparatus includes a command processing block configured to generate a voltage generation start signal, a first write control signal, a second write control signal, a read signal, and an operation signal in response to a first control signal and a second control signal in a write operation, and a memory control block configured to electrically couple a memory block, which stores data, to a sense amplifier or apply a predetermined voltage to the memory block in response to the voltage generation start signal, the first write control signal, the second write control signal, the read signal, and the operation signal.. . ... Sk Hynix Inc

03/17/16 / #20160077435

Methods of forming patterns

A method of forming patterns includes: forming guide patterns on an underlying layer, forming a self-assembling block copolymer (bcp) layer on the guide patterns and the underlying layer, annealing the self-assembling bcp layer to form first polymer block domains and second polymer block domains which are alternately and repeatedly arrayed, and selectively removing the first polymer block domains. The guide patterns are formed of a developable antireflective material. ... Sk Hynix Inc

03/10/16 / #20160073065

Image sensor, method of manufacturing the image sensor, and electronic device including the image sensor

Provided are an image sensor, a method of manufacturing the image sensor, and an electronic device including the image sensor. An image sensor according to an embodiment may include a photoelectric conversion element, a pixel lens formed over the photoelectric conversion element and comprising a plurality of light condensing layers, wherein an upper layer of plurality of light condensing layers has a smaller area than a lower layer, and the pixel lens comprises a color filter substance.. ... Sk Hynix Inc

03/10/16 / #20160072493

Current comparator and electronic device including the same

A current comparator may include a current comparison block configured to compare current flowing through first and second input terminals; a first current control unit configured to control current flowing through the first input terminal in response to a voltage of a first node; a second current control unit configured to control current flowing through the second input terminal in response to a voltage of a second node; a first driving unit configured to drive the first node with a first voltage higher than a read voltage in a non-comparison period, and drive the first node with the read voltage in a comparison period; and a second driving unit configured to drive the second node with a second voltage higher than a reference voltage in the non-comparison period, and drive the second node with the reference voltage in the comparison period.. . ... Sk Hynix Inc

03/10/16 / #20160072487

Buffer circuit and system having the same

A buffer circuit includes a power supply voltage detection block which may detect a voltage level of a power supply voltage, a bias generation block which may generate a constant bias signal and a plurality of enable bias signals based on the detection result of the power supply voltage, and an input buffer which may amplify an input signal in response to the constant bias signal and the plurality of enable bias signals.. . ... Sk Hynix Inc

03/10/16 / #20160072479

Semiconductor apparatus

A semiconductor apparatus includes a command decoding unit configured to decode an internal command, an internal clock and an internal clock enable signal, and generate an internal control signal; a clock enable signal control unit configured to receive a pre-clock enable signal and output one of the pre-clock enable signal and an enabled internal clock enable signal as the internal clock enable signal in response to a first test signal; an enable signal selection unit configured to output one of the pre-clock enable signal and a second to test signal as a counting enable signal in response to the first test signal; and a counting unit configured to perform a counting operation during an enable period of the counting enable signal, and output a counting code.. . ... Sk Hynix Inc

03/10/16 / #20160072059

Phase-change memory device having phase-change region divided into multi layers and operating method thereof

A phase-change memory device including a phase-change region divided into multi layers and an operation method thereof are provided. The device includes a first phase-change layer to which a current is provided from a heating electrode, and a second phase-change layer formed with continuity to the first phase-change layer and having a different width from the first phase-change layer, and to which a current is provided from the heating electrode. ... Sk Hynix Inc

03/10/16 / #20160071955

Semiconductor integrated circuit apparatus and method of manufacturing the same

A semiconductor integrated circuit apparatus and a method of manufacturing the same are provided. The semiconductor integrated circuit apparatus includes a semiconductor substrate having an active island, a gate buried in a predetermined portion of the active island, a source and a drain formed at both sides of the gate, and a current blocking layer formed in the active island corresponding to a lower portion of the drain. ... Sk Hynix Inc

03/10/16 / #20160071909

Electronic device having flash memory array formed in at different level than variable resistance memory cells

An electronic device includes a memory. The memory includes a first cell array including a plurality of flash memory cells, a first peripheral circuit suitable for controlling the first cell array, a second cell array including a plurality of variable resistance memory cells, and a second peripheral circuit suitable for controlling the second cell array. ... Sk Hynix Inc

03/10/16 / #20160071905

Electronic device and method for fabricating the same

An electronic device including a semiconductor memory that includes: a selection element; a first plug and a second plug that are coupled with two different sides of the selection element, respectively; a variable resistance element formed over the first plug and configured to store data; and a dummy variable resistance element formed over the second plug and configured to include a conductive path coupled with the second plug.. . ... Sk Hynix Inc

03/10/16 / #20160071895

Image sensor and electronic device including the same

This technology provides an image sensor and an electronic device including the same, in an image sensor including a pixel array including a plurality of unit pixels, each of the plurality of unit pixels may include a photoelectric conversion element and a pixel lens over the photoelectric conversion element and comprising a plurality of light condensing layers in which a lower layer has a larger area than an upper layer, wherein the pixel lens has a shape changing based on a position of a corresponding unit pixel from a center of the pixel array to an edge of the pixel array.. . ... Sk Hynix Inc

03/10/16 / #20160071894

Image sensor and electronic device including the same

Disclosed are an image sensor including a light collection member having a multi-layer step shape and an electronic device including the same. This technology can improve light condensing efficiency in a unit pixel since a corresponding pixel lens is included. ... Sk Hynix Inc

03/10/16 / #20160071881

Double-source semiconductor device

A semiconductor device may include a first source layer, a first insulating layer located over the first source layer, and a first stacked structure located over the first insulating layer. The semiconductor device may include first channel layers passing through the first stacked structure and the first insulating layer. ... Sk Hynix Inc

03/10/16 / #20160071869

Semiconductor memory device and method of manufacturing the same

The semiconductor memory device includes a stacked structure including conductive patterns and interlayer insulating patterns which are alternately stacked, a through-hole configured to pass through the stacked structure; a channel pattern formed inside the through-hole, a first capping conductive pattern formed on the channel pattern, a second capping conductive pattern formed on a sidewall of the first capping conductive pattern and surrounding the first capping conductive pattern, and a contact plug formed on the first capping conductive pattern and the second capping conductive pattern.. . ... Sk Hynix Inc

03/10/16 / #20160071823

Stack package and system-in-package including the same

A system-in-package includes first and second semiconductor chips disposed in a first region over a substrate, and a controller disposed in a second region over the substrate and selectively supplying a power supply voltage to the first or second semiconductor chip based on a data output operation of the first and second semiconductor chips, wherein each of the first and second semiconductor chips includes a first power supply region coupled with the controller through a first line and receiving the power supply voltage from the controller in common during an input/output operation of the first and second semiconductor chips, an output driver suitable for outputting data, and a second power supply region independently coupled with the controller through one of a second line and a third line and independently receiving the power supply voltage for an operation of the output driver from the controller during the data output operation.. . ... Sk Hynix Inc

03/10/16 / #20160071620

Semiconductor memory apparatus and data processing system with main memory blocks and redundant memory blocks sharing a common global data line

A semiconductor memory apparatus includes: a memory area including a plurality of memory banks having main memory areas configured to transmit and receive data to and from the outside through a plurality of global data lines, respectively, and one or more redundancy memory areas configured to use any one of the global data lines as a common global data line; and a controller configured to control data to be transmitted and received through the common global data line, as a redundancy program mode, a redundancy read mode, or a redundancy erase mode is enabled.. . ... Sk Hynix Inc

03/10/16 / #20160071616

Impedance calibration circuit, and semiconductor memory and memory system using the same

An embodiment may include a first replica driver group configured for replicating an output driver of a physical area. A second replica driver group configured for replicating an output driver of a test electrode area for direct access of a memory, and an impedance calibration unit configured to independently perform an impedance matching operation of the first replica driver group and the second replica driver group.. ... Sk Hynix Inc

03/10/16 / #20160071615

Semiconductor memory apparatus

A semiconductor memory apparatus includes an internal data generation block configured to generate test data in response to test signals, and output ones of normal data inputted from data input/output pads and the test data as internal data according to a test flag signal; a data storage region configured to receive and store the internal data, and output stored data as cell storage data; a latch block configured to receive and store the cell storage data in response to a data output enable signal, and output stored data as latch data; and a data comparison block configured to compare the test data and the latch data, and generate a test result signal.. . ... Sk Hynix Inc

03/10/16 / #20160071613

Semiconductor integrated circuit device including fuse block

A semiconductor integrated circuit device includes a plurality of column repair address lines configured to cross and a plurality of mat select lines; a fuse set unit including a plurality of latch units electrically coupled with the plurality of column repair address lines and the plurality of mat select lines; a fuse driving unit configured to provide fuse data to the latch units through the plurality of column repair address lines; and an equalizer configured to equalize the fuse data to a same level in response to a select signal of the fuse set unit and a boot-up signal of the fuse set unit.. . ... Sk Hynix Inc

03/10/16 / #20160071596

Semiconductor memory device including a 3-dimensional memory cell array and a method of operating the same

A semiconductor memory device may include a plurality of cell strings. Each of the cell strings may include at least one source selection transistor connected to a common source line, a plurality of memory cells connected to the common source line through the at least one source selection transistor. ... Sk Hynix Inc

03/10/16 / #20160071570

Refresh control circuit and semiconductor apparatus using the same

A semiconductor apparatus may include a plurality of slices electrically coupled through through electrodes. Any one slice of the plurality of slices may be configured to generate a refresh cycle signal in response to a refresh command, and transmit the refresh cycle signal to the other slices through the through electrodes. ... Sk Hynix Inc

03/10/16 / #20160071564

Semiconductor memory device

A semiconductor memory device includes a first signal generation unit configured to sequentially generate first and second delay signals in response to a first column control signal, the first and second delay signals having reflected a delay time and a multiplied delay time selected from a plurality of delay times in correspondence with an arrangement location of a unit memory region, through data is input/output, respectively, and a second signal generation unit configured to generate a second column control signal delayed by the selected delay time as compared with the first column control signal, to determine an activation time point of the second column control signal in response to the first delay signal, and to determine a deactivation time point of the second column control signal in response to the second delay signal.. . ... Sk Hynix Inc

03/10/16 / #20160071563

Output timing control circuit of semiconductor apparatus and method thereof

An output timing control circuit of a semiconductor apparatus may include a strobe signal generation path configured to control a latency and a delay time of an internal signal, and generate a strobe signal. The output timing control circuit may include a first detection block configured to detect a phase difference of the strobe signal and a clock signal, and control the delay time according to the detected phase difference. ... Sk Hynix Inc

03/10/16 / #20160071562

Stack type semiconductor apparatus

The invention may include a semiconductor apparatus comprising: a first die configured to latch and output external input data according to a strobe signal, to detect a valid pulse from among pulses of the strobe signal, and to generate a valid signal; and a second die configured to write data transmitted from the first die in response to the valid signal.. . ... Sk Hynix Inc

03/10/16 / #20160071560

Semiconductor apparatus

A semiconductor apparatus includes a control block configured to control a pulse width of a column select signal in response to a precharge command from an external; and a coupling block configured to electrically couple bit lines and data lines according to the column select signal. A semiconductor apparatus includes a control block configured to generate a drive signal in response to a write command and generate an overdrive signal in response to a precharge command; and a driver configured to drive data lines with a first voltage in response to the drive signal and overdrive the data lines with a second voltage higher than the first voltage in response to the overdrive signal.. ... Sk Hynix Inc

03/10/16 / #20160069959

Semiconductor apparatus and test device therefor

A semiconductor apparatus includes a clock enable signal buffer unit configured to receive an input clock enable signal, and generate an output clock enable signal; a buffer control unit configured to generate a buffer enable signal in response to the output clock enable signal and a test enable signal; an input/output buffer unit configured to receive input patterns and generate output patterns; and a compression test unit configured to test the output patterns and the output clock enable signal according to the test enable signal.. . ... Sk Hynix Inc

03/10/16 / #20160069956

Channel control circuit and semiconductor device having the same

A channel control circuit having a plurality of channels according to an embodiment of the present invention includes: a channel control signal generating block configured to generate a channel control signal capable of selectively controlling an activated state of a channel in response to a combination of a first test mode signal and a second test mode signal; a scan buffer control signal generating block configured to generate a scan buffer control signal in response to the first test mode signal and a scan signal; a clock to buffer control signal generating block configured to generate a clock buffer control signal in response to the channel control signal and the scan buffer control signal; and a clock input buffer configured to generate a clock output signal, which is used as an internal clock of a semiconductor device, in response to the clock buffer control signal.. . ... Sk Hynix Inc

03/10/16 / #20160069954

Semiconductor apparatus

A semiconductor apparatus may include a first normal circuit configured to generate a normal signal while operating in a normal operation, and a test signal generation unit configured to generate a test signal in response to a test control signal. The semiconductor apparatus may include a signal transfer unit configured to transfer one of either the normal signal or the test signal, as an internal signal, to a signal line, and a second normal circuit configured to perform the normal operation in response to receiving the internal signal from the signal line. ... Sk Hynix Inc

03/03/16 / #20160065870

Image sensor having depth detection pixels and method for generating depth data with the image sensor

An image sensor includes: a plurality of pixels that include a plurality of color detection pixels and a plurality of depth detection pixels, wherein the plurality of pixels are arranged in two dimensions; and a photoelectric conversion layer formed to correspond to the plurality of the pixels, wherein each of the plurality of the color detection pixels comprises: a first light condensing layer disposed over the photoelectric conversion layer; and a band pass filter layer interposed between the photoelectric conversion layer and the first light condensing layer, and wherein each of the plurality of the depth detection pixels comprises: a second light condensing layer disposed over the photoelectric conversion layer and having a greater size than a size of the first light condensing layer.. . ... Sk Hynix Inc

03/03/16 / #20160065240

Data storage device and operating method thereof

A data encoding method may include receiving n bits of first data, and converting the first data into m bits of second data, wherein the proportion of a first value in the second data is higher than the proportion of a second value.. . ... Sk Hynix Inc

03/03/16 / #20160065200

Input apparatus and input system

An input apparatus may include a pulse width control circuit, a reception circuit, and a latch circuit. The pulse width control circuit may be configured to generate a pulse width control signal by performing a logical operation on a pulse width detection signal and a clock signal. ... Sk Hynix Inc

03/03/16 / #20160065181

Semiconductor device and semiconductor system including the same

A semiconductor system includes a first semiconductor device including an offset signal generation circuit configured to compare at least one sensing code and a temperature code and generate an input offset signal, and a second semiconductor device including a temperature code generation circuit configured to be inputted with the input offset signal, compare a reference voltage controlled according to the input offset signal and a temperature signal, and generate the temperature code.. . ... Sk Hynix Inc

03/03/16 / #20160064659

Electronic device

An electronic device includes a semiconductor memory. The semiconductor memory includes a selection element layer; a material layer directly coupled to a first surface of the selection element layer and including a conductive filament; and a variable resistance layer coupled to a second surface of the selection element layer opposite to the first surface.. ... Sk Hynix Inc

03/03/16 / #20160064487

Power integrated devices, electronic devices and electronic systems including the same

A power integrated device includes a drift region disposed in a substrate, a source region disposed in the substrate spaced apart from the drift region, a drain region disposed in the drift region, a gate insulation layer and a gate electrode sequentially stacked on the substrate between the source region and the drift region, a trench isolation layer disposed in the drift region adjacent to a side of the drain region, and a deep trench field insulation layer disposed in the drift region adjacent to another side of the drain region, wherein a vertical height of the deep trench field insulation layer is greater than a width of the deep trench field insulation layer.. . ... Sk Hynix Inc

03/03/16 / #20160064454

3d variable resistance memory device having junction fet and driving method thereof

A 3d variable resistance memory device having a junction fet and a driving method thereof are provided. The variable resistance memory device includes a semiconductor substrate and a string selection switch formed on the semiconductor substrate. ... Sk Hynix Inc

03/03/16 / #20160064360

Semiconductor package and method for fabricating the same

A semiconductor package includes a package substrate on which a substrate pad is disposed, a structure disposed over the package substrate, a semiconductor chip disposed over the structure using an adhesive member having a magnetic material layer disposed therein, a chip pad disposed on a top surface of the semiconductor chip, and a bonding wire coupling the substrate pad and the chip pad.. . ... Sk Hynix Inc

03/03/16 / #20160064359

Stack packages and methods of fabricating the same

Stack packages are provided. The stack package includes a first chip configured to include a first chip body having a top surface and a bottom surface, first through electrodes penetrating the first chip body, and an insulation layer disposed on the bottom surface of the first chip body, and first bumps disposed on the top surface of the first chip body, and a second chip configured to include a second chip body having a top surface and a bottom surface, and second bumps disposed on the top surface of the second chip body. ... Sk Hynix Inc

03/03/16 / #20160064279

Semiconductor device having stable structure and method of manufacturing the same

The semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked; semiconductor patterns configured to pass through the stacked structure; and contact plugs electrically coupled to the conductive layers, respectively, wherein each of the conductive layers includes a first region which has a first thickness, and a second region electrically coupled to the first region and a second thickness greater than the first thickness, and a second region of a lower conductive layer located under a second region of an upper conductive layer.. . ... Sk Hynix Inc

03/03/16 / #20160064101

Semiconductor device and semiconductor system including the same

A semiconductor system may include a first semiconductor device including a first pad group. The semiconductor system may include a second semiconductor device including a second pad group which is configured for input and output of signals from and to a third semiconductor device. ... Sk Hynix Inc

03/03/16 / #20160064081

Semiconductor memory device, operating method thereof, and data storage device including the same

A semiconductor memory device includes a setting information area suitable for storing setting information necessary for driving of memory cells, a control logic suitable for loading the setting information stored in the setting information area on a content-addressable memory (cam) block, a cam state information storage block suitable for storing information on whether the setting information loaded on the cam block is changed, wherein when a reloading operation of the setting information stored in the setting information area on the cam block is requested, the control logic selectively performs the reloading operation based on the information stored in the cam state information storage block.. . ... Sk Hynix Inc

03/03/16 / #20160064072

3d variable resistance memory device having junction fet and driving method thereof

A 3d variable resistance memory device having a junction fet and a driving method thereof are provided. The variable resistance memory device includes a semiconductor substrate and a string selection switch formed on the semiconductor substrate. ... Sk Hynix Inc

03/03/16 / #20160064062

Semiconductor memory device and refresh operating method

A semiconductor memory device includes a plurality of normal memory mats, one or more of which includes a redundancy word line, a dummy memory mat suitable for performing an operation with an edge memory mat as a pair during an active operation, wherein the edge memory mat is one among the plurality of normal memory mats disposed at an edge, and a refresh control section suitable for controlling refresh operations for the plurality of normal memory mats and the dummy memory mat, and restricting activation of the redundancy word line during a refresh operation for the edge memory mat.. . ... Sk Hynix Inc

03/03/16 / #20160064051

Semiconductor memory apparatus

A semiconductor memory apparatus may include a write driver, a data sensing section, and a programming control section. The write driver may write an input data into a memory cell in response to a write signal. ... Sk Hynix Inc

03/03/16 / #20160064049

Semiconductor devices and semiconductor systems including the same

A semiconductor device includes a first data input/output unit storing first internal input data in a first cell block in response to a first shift data strobe signal generated by shifting a first data strobe signal in a test mode, a second data input/output unit storing second internal input data in a second cell block in response to a second shift data strobe signal generated by shifting a second data strobe signal in the test mode, and a connector electrically coupling the first data input/output unit to the second data input/output unit in the test mode.. . ... Sk Hynix Inc

03/03/16 / #20160062884

Data storage device and method for operating the same

An operating method of a data storage device includes receiving a write request, determining whether it is possible to perform a first write operation of simultaneously writing a plurality of bits in each of memory cells coupled to one word line of a nonvolatile memory apparatus, and performing a garbage collection operation for the nonvolatile memory apparatus, according to a determination result, and generating first merged data.. . ... Sk Hynix Inc

03/03/16 / #20160062883

Data storage device and operating method thereof

A data storage device may include: a nonvolatile memory device; and a controller suitable for generating a mapping table based on one or more of write logical addresses for access to the nonvolatile memory device. The mapping table may include information of: correspondence between a physical address for access to the nonvolatile memory device and one of the write logical addresses; and a number of successive physical addresses corresponding to successive logical addresses starting from the write logical addresses corresponding to the correspondence information.. ... Sk Hynix Inc

03/03/16 / #20160062690

Data storage device, data processing system including the same, and operating method thereof

A data processing system includes a host device including a first memory, and a data storage device including a second memory and a third memory, and suitable for storing data to be accessed by the host device, wherein the host device requests the data storage device to upload data stored in the second memory.. . ... Sk Hynix Inc

03/03/16 / #20160062686

Semiconductor device and method of operating the same

A semiconductor device and a method of operating the same are provided. A plurality of memory blocks are erased. ... Sk Hynix Inc

03/03/16 / #20160061886

Integrated circuit

An integrated circuit may include a first semiconductor device including a first through-silicon via configured for electrically coupling a first bump pad to a second bump pad, and may be configured to buffer a first internal test signal generated by a test signal inputted through the first bump pad and generate a first detection signal. The integrated circuit may include a second semiconductor device including a second through-silicon via configured for electrically coupling a third bump pad to a fourth bump pad, and may be configured to buffer a second internal test signal generated by the test signal inputted through the third bump pad and generate a second detection signal. ... Sk Hynix Inc

02/25/16 / #20160056796

Integrated circuits

An integrated circuit may include a first semiconductor device and a second semiconductor device. The first semiconductor device may compare a first internal voltage signal with a reference voltage signal received from outside the first semiconductor device to control a drive of the first internal voltage signal. ... Sk Hynix Inc

02/25/16 / #20160056716

Apparatus and system for adjusting internal voltage

An apparatus for adjusting an internal voltage includes a device characteristic detection circuit which detects a device characteristic, compares the device characteristic with an external clock, and generates a comparison signal, and an internal voltage adjustment circuit which receives an adjustment code generated based on the comparison signal, adjusts a level of an internal voltage, and generates a level-adjusted internal voltage.. . ... Sk Hynix Inc

02/25/16 / #20160056302

Three-dimensional semiconductor device

A three-dimensional (3d) semiconductor device includes first interlayer dielectric layers and word lines that are alternately stacked on a substrate; select lines formed on the first interlayer dielectric layers and the word lines; etch stop patterns formed on the select lines to contact the select lines; channel holes formed to pass through the select lines, the first interlayer dielectric layers, and the word lines; channel layers formed on surfaces of the channel holes; insulating layers formed in the channel holes, the insulating layers having an upper surface that is lower than upper surfaces of the etch stop patterns; impurity-doped layers formed in channel holes on upper surface of the insulating layers; and a second interlayer dielectric layer formed over the etch stop patterns and the impurity-doped layers.. . ... Sk Hynix Inc

02/25/16 / #20160056258

Semiconductor devices having polysilicon gate patterns and methods of fabricating the same

A semiconductor device including a gate insulation pattern on a substrate, and a semiconductor gate pattern including an amorphous silicon pattern and a polycrystalline silicon pattern stacked on a side of the gate insulation pattern opposite to the substrate. The amorphous silicon pattern includes anti-diffusion impurities that suppress diffusion of impurity ions in the semiconductor gate pattern.. ... Sk Hynix Inc

02/25/16 / #20160056246

Electronic device

An electronic device includes a transistor. The transistor includes a body including a metal oxide; a gate electrode; and a gate insulating layer interposed between the body and the gate electrode, wherein the transistor is turned on or turned off by movement of oxygen vacancies in the body according to voltages applied to the gate electrode and the body.. ... Sk Hynix Inc

02/25/16 / #20160056229

Method of fabricating semiconductor device

The method includes forming a metal interconnection layer and a first interlayer insulating layer on a semiconductor substrate, forming a reservoir capacitor region by etching the first interlayer insulating layer to expose the metal interconnection layer, forming a barrier metal layer on the reservoir capacitor region, forming a sacrificial insulating layer on the barrier metal layer in a lower portion of the reservoir capacitor region, performing a pre-cleaning process to remove the barrier metal layer on a sidewall of the reservoir capacitor region, and removing the sacrificial insulating layer.. . ... Sk Hynix Inc

02/25/16 / #20160056211

Electronic device including memory cells having variable resistance characteristics

An electronic device includes a semiconductor memory. The semiconductor memory includes a stack structure including a first electrode, a second electrode, a third electrode, an insulating layer interposed between the first electrode and the second electrode, and a variable resistance layer interposed between the second electrode and the third electrode; and a selection element layer disposed over at least a part of a sidewall of the stack structure.. ... Sk Hynix Inc

02/25/16 / #20160056209

Three-dimensional semiconductor device and a system having the same

A 3d semiconductor device and a system having the same are provided. The 3d semiconductor device includes a semiconductor substrate, a common source region formed on the semiconductor substrate and extending in a line shape, an active region formed on the common source region and including a lateral channel region, which is substantially in parallel to a surface of the semiconductor substrate, and source and drain regions that are branched from the lateral channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, and a gate formed in a space between the source region and the drain region.. ... Sk Hynix Inc

02/25/16 / #20160056195

Image sensor and electronic device having the same

An image sensor may include: a substrate including a substrate comprising a photoelectric conversion element; a pixel lens formed over the substrate and comprising a plurality of light condensing layers in which a lower layer has a larger area than an upper layer; a color filter layer covering the pixel lens; and an anti-reflection structure formed over the color filter layer.. . ... Sk Hynix Inc

02/25/16 / #20160056160

Semiconductor device having passing gate and method for fabricating the same

A semiconductor device that has a passing gate with a single gate electrode and a main gate with lower and upper gate electrodes mitigates gate induced drain leakage (gidl). Additional elements that help mitigate gidl include the upper gate electrode having a lower work function than the lower gate electrode, and the lower gate electrode being disposed below a storage node junction region while the upper gate electrode is disposed at a same level as the storage node junction region.. ... Sk Hynix Inc

02/25/16 / #20160056130

Semiconductor integrated circuit including power tsvs

A semiconductor device including power tsvs for stably supplying a power source is described. A semiconductor device includes a chip power pad placed in a first region of a chip, power through silicon vias (tsvs) connected to the chip power pad and placed in the second region of each of the chips, and metal lines configured to couple the chip power pad and the power tsvs.. ... Sk Hynix Inc

02/25/16 / #20160056122

Semiconductor package having overhang portion

A semiconductor package may include a substrate, and a structural body disposed over the substrate. The semiconductor package may include a semiconductor chip stacked over the structural body, and having an overhang portion projecting over a side surface of the structural body and overhanging out over the side surface of the structural body. ... Sk Hynix Inc

02/25/16 / #20160055913

Semiconductor memory device and operating method thereof

An operating method of a semiconductor device is provided. The operating method of the semiconductor memory device includes programming a second source select transistor electrically coupled to a common source line through a first source select transistor; reprogramming the second source select transistor when a threshold voltage of the second source select transistor is less than a target voltage, and ending a program for the second source select transistor when the threshold voltage of the second source select transistor is greater than or equal to the target voltage. ... Sk Hynix Inc

02/25/16 / #20160055912

Flash memory device

A flash memory device is configured to reduce loading of a word line without increasing the size of a region. The flash memory device includes a cell array region including a word line structure; an x-decoder region disposed at one side of the cell array region, and including a pass transistor composed of a gate electrode, a source region, and a drain region; and a metal line coupled not only to the drain region of the pass transistor, but also to one side and the other side of the word line structure.. ... Sk Hynix Inc

02/25/16 / #20160055896

Memory device and memory system including the same

A memory device includes a plurality of memory blocks; an address counter suitable for generating a counted address which is used for a normal refresh operation and changed when all the memory blocks are refreshed; a target address generator suitable for generating a target address used for a target refresh operation, wherein the target address corresponds to an address of a word line to be additionally refreshed in the memory blocks; and a refresh controller suitable for controlling the memory blocks to be refreshed at different times during a first normal refresh operation, controlling a memory block among the memory blocks, which is first refreshed in the first normal refresh operation, to be refreshed through the target refresh operation, and controlling the memory block, which is first refreshed in the first normal refresh operation, to be refreshed last during a second normal refresh operation, based on the refresh command.. . ... Sk Hynix Inc

02/25/16 / #20160055008

Operating method of data storage device

An operating method of a data storage device includes determining whether the data storage device is in a main boot mode or a sub boot mode, based on data stored in a boot mode register; executing a main boot code stored in a rom, when the data storage device is determined to be in the main boot mode; and executing a sub boot code loaded on a working memory, when the data storage device is determined to be in the sub boot mode, and then, executing the main boot code.. . ... Sk Hynix Inc

02/25/16 / #20160054361

Electronic apparatus

An electronic apparatus includes a first voltage detection circuit which detects when a voltage, becomes higher than a first level after the voltage starts to be supplied to a peripheral circuit, and detects when the voltage becomes lower than a second level after a supply of the voltage to the peripheral circuit starts to be interrupted, and a second voltage detection circuit which detects when the voltage becomes lower than a reference level while the peripheral circuit operates. The second level is lower than the reference level.. ... Sk Hynix Inc

02/18/16 / #20160049938

Semiconductor device

A semiconductor device includes a first block coupled between a first latch node and a second latch node, a second block suitable for generating common-mode noise between the first latch node and the second latch node, wherein the second block includes a first mos transistor having a gate coupled with the first latch node, and one between a source and a drain of the first mos transistor is coupled with the second latch node while the other between the source and the drain is floating.. . ... Sk Hynix Inc

02/18/16 / #20160049582

Memory device having a tunnel barrier layer in a memory cell, and electronic device including the same

An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction crossing the first direction, a resistance variable layer interposed between the first lines and the second lines, a tunnel barrier layer interposed between the resistance variable layer and the first lines, and an intermediate electrode layer interposed between the resistance variable layer and the tunnel barrier layer. ... Sk Hynix Inc

02/18/16 / #20160049446

Transistor, resistance variable memory device including the same, and manufacturing method thereof

A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (ldd) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the ldd region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first work function.. . ... Sk Hynix Inc

02/18/16 / #20160049409

Semiconductor device with air gap and method for fabricating the same

A semiconductor device includes a plurality of first conductive structures formed over a substrate, second conductive structures each formed between neighboring first conductive structures of the first conductive structures, air gaps each formed between the second conductive structures and the neighboring first conductive structures thereof, third conductive structures each capping a portion of the air gaps, and capping structures each capping the other portion of the air gaps.. . ... Sk Hynix Inc

02/18/16 / #20160049408

Semiconductor devices having bit line structures disposed in trenches

Semiconductor devices are provided. The semiconductor device includes a bit line contact plug and a storage node contact plug electrically connected to an active region of a substrate. ... Sk Hynix Inc

02/18/16 / #20160049200

Semiconductor memory device and operating method thereof

A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.. . ... Sk Hynix Inc

02/18/16 / #20160047854

Semiconductor device with test mode circuit

A semiconductor device includes a plurality of test entry selection units configured to selectively activate a plurality of test entry signals in response to a test entry code, and a plurality of test operation blocks, corresponding to the respective test entry signals, each configured to be reset in response to activation of the corresponding test entry signal to perform a set test operation corresponding to a test selection code.. . ... Sk Hynix Inc

02/11/16 / #20160043727

Period measuring circuit and semiconductor device including the same

A semiconductor device includes: a counting detection block suitable for generating a counting value of a clock signal transmitted through a first transmission path and a counting value of a target signal transmitted through a second transmission path during a counter enable section, and blocking the first transmission path and the second transmission path based on a comparison result obtained by comparing a predetermined code value with the counting value of the clock signal; and an output block suitable for outputting the counting value of the target signal corresponding to when the first and second transmission paths to a predetermined pad are blocked, based on a test mode signal.. . ... Sk Hynix Inc

02/11/16 / #20160043726

Test circuit and test method of semiconductor apparatus

A test circuit of a semiconductor apparatus may include a period signal counting block configured to count a period signal by a predetermined number of times, and enable an overflow signal. The test circuit of the semiconductor apparatus may include a clock signal counting block configured to count an internal clock signal until the overflow signal is enabled, and may output clock counting codes. ... Sk Hynix Inc

02/11/16 / #20160043725

Double data rate counter, and analog-to-digital converter and cmos image sensor using the same

A double data rate (ddr) counter includes an input clock control portion suitable for generating a first clock corresponding to a state of a input clock based on a counter enable signal, and an lsb control portion suitable for holding a least significant bit based on the counter enable signal and successively performing a counting operation on the first clock in multiple sections.. . ... Sk Hynix Inc

02/11/16 / #20160043723

Semiconductor apparatus

A semiconductor apparatus may include an operation signal input selection block configured to output one of either a first operation signal or a second operation signal, as a select signal, in response to an operation select signal. The semiconductor apparatus may include a target code selection block configured to output one of either a first target code or a second target code, as a select code, in response to the operation select signal. ... Sk Hynix Inc

02/11/16 / #20160043313

Electronic device and method for fabricating the same

An electronic device includes a semiconductor memory. The semiconductor memory includes first lines extending in a first direction; second lines extending in a second direction crossing the first direction; insulating patterns interposed between the first and second lines at first intersections of the first and second lines; and variable resistance patterns interposed between the first and the second lines at second intersections of the first and second lines. ... Sk Hynix Inc

02/11/16 / #20160043172

Semiconductor device including a wall oxide film and method for forming the same

A semiconductor device includes an oxide film structure having different thicknesses depending on where the oxide film structure is formed. In the semiconductor device, a wall oxide film is formed to have different thicknesses depending on locations of sidewalls of an active region. ... Sk Hynix Inc

02/11/16 / #20160043139

Transistor, resistance variable memory device including the same, and manufacturing method thereof

A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (ldd) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the ldd region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first work function.. . ... Sk Hynix Inc

02/11/16 / #20160043138

Semiconductor device and method for fabricating the same

A semiconductor device includes a memory block including a transistor region and a memory region. A variable resistance layer of the memory region acts as a gate insulating layer in the transistor region.. ... Sk Hynix Inc

02/11/16 / #20160043059

Multi-chip semiconductor apparatus

A multi-chip semiconductor apparatus includes a plurality of semiconductor chips stacked and packaged therein, wherein each of the semiconductor chips includes: a through-silicon via (tsv) formed through the semiconductor chip; a probe pad exposed to an outside of the semiconductor chip so as to enable a probing test; a bump pad exposed to the outside of the semiconductor chip and electrically connected to the tsv; and a conductive layer electrically connecting the probe pad and the bump pad inside the semiconductor chip.. . ... Sk Hynix Inc

02/11/16 / #20160042972

Electronic devices having semiconductor memory units and method for fabricating the same

The disclosed technology provides an electronic device and a fabrication method thereof. An electronic device according to an implementation of the disclosed technology may include: a first interlayer insulating layer formed over a substrate; first and second contact plugs passing through the first interlayer insulating layer to contact the substrate and alternately arranged to cross each other; a variable resistance element formed over the first interlayer insulating layer and coupled to the first contact plug; a second interlayer insulating layer formed over an entire structure including the first interlayer insulating layer; a third contact plug passing through the second interlayer insulating layer so as to be coupled to the variable resistance element, and a fourth contact plug passing through the second interlayer insulating layer so as to be contacted to the second contact plug; and conductive lines coupled to the third contact plug and the fourth contact plug, respectively.. ... Sk Hynix Inc

02/11/16 / #20160042960

3d semiconductor integrated circuit device and method of manufacturing the same

A 3d semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and an interlayer insulating layer is formed so that the active pillar is buried in the interlayer insulating layer. ... Sk Hynix Inc

02/11/16 / #20160042813

Semiconductor memory device and method for testing redundancy word line

A semiconductor memory device includes a plurality of redundancy cells suitable for repairing a defective cell of a plurality of normal cells, a defective redundancy cell information storing circuit block suitable for detecting whether the redundancy cells are defective and storing information on a redundancy cell that is detected to be defective, and a defective redundancy cell rupture circuit block suitable for performing a disable rupture operation on the redundancy cell that is detected to be defective.. . ... Sk Hynix Inc

02/11/16 / #20160042808

Semiconductor test device

A semiconductor test device performs a test using a high-speed internal clock. The semiconductor test device includes a clock generator suitable for generating an internal clock in response to a test mode signal during a test mode, a data generator suitable for generating internal data in response to the internal clock, and a data latch circuit suitable for latching the internal data in response to the internal clock, and outputting the latched data to an internal logic circuit.. ... Sk Hynix Inc

02/11/16 / #20160042805

Semiconductor memory device and method for operating the same

A semiconductor memory device includes a fuse portion including a first fuse set having a plurality of first fuses assigned for a first mode and a second fuse set having a plurality of second fuses assigned for a second mode, and a program portion suitable for programming an available fuse among the first fuses included in the first fuse set or programming the second fuses included in the second fuse set in response to a repair control signal in the second mode.. . ... Sk Hynix Inc

02/11/16 / #20160042788

Write driver, resistance variable memory apparatus including the same, and operation method

A write driver is configured to determine a magnitude and an application time of a pre-emphasis current pulse in response to control codes generated according to parasitic components on a path from a write driver to a program target cell and a resistance value of the program target cell, and supply a preset program current to a memory circuit block by adding a pre-emphasis current to the preset program current in a program mode.. . ... Sk Hynix Inc

02/11/16 / #20160042776

Semiconductor apparatus capable of compensating for data output time and method for controlling the same

A semiconductor apparatus may include a base die and a plurality of core dies stacked above the base die. Each of the core dies may be configured to output a strobe signal in response to a read command, and the base die may be configured to make remaining data output times correspond to any one data output time among respective data output times of the plurality of core dies, in response to the read command and the strobe signal.. ... Sk Hynix Inc

02/11/16 / #20160042775

Semiconductor memory device for conducting monitoring operation to verify read and write operations

A semiconductor memory device includes, in part, a first data i/o block and a second data i/o block. During a write operation, the first data i/o block transmits input data supplied through a first pad to a first global i/o line, and further generates a write internal signal. ... Sk Hynix Inc

02/11/16 / #20160042774

Semiconductor memory device for conducting monitoring operation to verify read and write operations

A semiconductor memory device includes, in part, a first data i/o block and a second data i/o block. During a write operation, the first data i/o block transmits input data supplied through a first pad to a first global i/o line, and further generates a write internal signal. ... Sk Hynix Inc

02/11/16 / #20160042772

Semiconductor devices

A semiconductor device may include a first input/output unit and a second input/output unit. The first input/output unit may operate in synchronization with an internal clock signal to output a first data as a first output data in response to a control signal or to output a transfer data generated from a second data as the first output data in response to the control signal. ... Sk Hynix Inc

02/11/16 / #20160042770

Semiconductor memory apparatus

A semiconductor memory apparatus includes a first memory cell electrically coupled to a word line and a bit line; a second memory cell electrically coupled to the word line and a bit line bar; a sense amplifier electrically coupled to the bit line and the bit line bar; and a switching unit configured to electrically couple the bit line and the bit line bar to an input/output line and an input/output line bar in response to a column select signal.. . ... Sk Hynix Inc

02/11/16 / #20160041872

Semiconductor memory device

A semiconductor memory device includes: a core block suitable for storing write data as normal data or a part of combined data according to a data masking signal, and masking information indicating data masking of the combined data; and an error correcting code (ecc) block suitable for performing an ecc decoding operation on the normal data, and bypassing the ecc decoding operation on the combined data according to the masking information, wherein the combined data further includes masked data.. . ... Sk Hynix Inc

02/04/16 / #20160036448

Electronic device and electronic system including the same

An electronic device includes a control logic portion suitable for generating a hold control signal based on a count enable signal, and a counting portion suitable for performing a counting operation while a latch operation stops during a counting section and performing the latch operation while the counting operation stops during a holding section based on the hold control signal and a counting clock signal.. . ... Sk Hynix Inc

02/04/16 / #20160036425

Buffer control circuit and multi-chip package including the same

A buffer control circuit includes: an activation control block suitable for generating a buffer activation control signal by detecting a first input of a repeatedly provided chip select signal; and a buffer suitable for buffering the chip select signal in response to the buffer activation control signal after the generation of the buffer activation control signal.. . ... Sk Hynix Inc

02/04/16 / #20160035972

Electronic device comprising semiconductor memory using metal electrode and metal compound layer surrounding sidewall of the metal electrode

This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a lower electrode, a variable resistance element over the lower electrode, an upper electrode disposed over the variable resistance element and including metal, and a metal compound layer configured to surround a side of the upper electrode. ... Sk Hynix Inc

02/04/16 / #20160035732

Three-dimensional non-volatile memory device

A semiconductor device includes at least one first conductive layer stacked on a substrate where a cell region and a contact region are defined; at least one first slit passing through the first conductive layer, second conductive layers stacked on the first conductive layer; a second slit passing through the first and second conductive layers and connected with one side of the first slit, and a third slit passing through the first and second conductive layers and connected with the other side of the first slit.. . ... Sk Hynix Inc

02/04/16 / #20160035708

Stack packages and methods of manufacturing the same

A stack package includes a substrate having connection terminals and a first chip on the substrate. The first chip has first connectors on edges thereof. ... Sk Hynix Inc

02/04/16 / #20160035669

Routing paths and semiconductor devices including the same

A semiconductor device may include a global line coupled to a source, and a plurality of local lines coupled to a plurality of targets, respectively, and coupled to the global line. The local lines may be configured to have cross-sectional areas. ... Sk Hynix Inc

02/04/16 / #20160035649

Semiconductor devices with optical through via structures, memory cards including the same, and electronic systems including the same

A semiconductor device is provided. The semiconductor device may include a substrate and a through via structure penetrating the substrate. ... Sk Hynix Inc

02/04/16 / #20160035438

Memory device and memory system including the same

A memory device includes a non-volatile memory circuit suitable for storing system hard repair data, a temporary memory circuit suitable for storing system soft repair data, a system register circuit suitable for receiving and storing the system hard repair data or the system soft repair data during a boot-up operation, and a memory bank suitable for performing a repair operation based on first data stored in the system register circuit.. . ... Sk Hynix Inc

02/04/16 / #20160035410

Memory and memory system including the same

A memory includes a first cell array including a plurality of first memory cells connected to a plurality of word lines, a bit line selection unit configured to select one or more bit lines among a plurality of bit lines based on repair information, a second cell array including a plurality of second memory cells connected to the plurality of word lines and the plurality of bit lines, wherein a group of the plurality of second memory cells connected to a corresponding word line stores the number of activations of the corresponding word line when the one or more connected bit lines are selected and an activation number update unit configured to update a value stored in the second memory cells, which are connected to the one or more selected bit lines and the activated word line among the plurality of word lines.. . ... Sk Hynix Inc

02/04/16 / #20160035400

Bank control circuit and semiconductor memory device including the same

A bank control circuit includes an implicit signal generation unit suitable for activating an implicit signal when a first active signal corresponding to a bank which is in an activated state bank, among a plurality of banks; and a delay unit suitable for delaying the implicit signal by a predetermined time, wherein the bank corresponding to the first active signal is precharged based on the implicit signal and activated again based on the delayed implicit signal.. . ... Sk Hynix Inc

02/04/16 / #20160034389

Data storage device and method for operating the same

A data storage device includes a memory including a plurality of memory blocks each of which includes a plurality of pages suitable for storing data transmitted from a host, and a controller suitable for storing data storage information on the data stored in the memory, wherein the data storage information is updated based on valid pages where the data are stored among the plurality of the pages.. . ... Sk Hynix Inc

02/04/16 / #20160034192

Data storage device and operation method thereof

A data storage device includes a memory including a plurality of memory blocks each of which includes a plurality of pages to write a data transmitted from a host therein, and a controller suitable for storing page information on the pages of each of the memory blocks, wherein the page information is updated based on a data update performed in a page where the data is written among the pages of each of the memory blocks.. . ... Sk Hynix Inc

01/28/16 / #20160028975

Device and method for compressing/decompressing lens shading compensation coefficient

A lens shading compensation coefficient compression device includes: a first differential block suitable for calculating a lens shading compensation coefficient between color channels and removing redundancy between the color channels; a second differential block suitable for calculating a lens shading compensation coefficient within color channels and removing redundancy within the color channels; and an entropy coding block suitable for performing entropy coding on remaining lens shading compensation coefficients and compressing the lens shading compensation coefficients.. . ... Sk Hynix Inc

01/28/16 / #20160028407

Semiconductor apparatus and system including plurality of channels

A semiconductor apparatus includes a direct access section, an interface section, and a through-silicon via region. The direct access section receives a normal clock, a first clock, and a control signal through a direct access pad. ... Sk Hynix Inc

01/28/16 / #20160028011

Semiconductor device and method for fabricating the same, and microprocessor, processor, system, data storage system and memory system including the semiconductor device

A semiconductor device includes first lines extending in a first direction; second lines extending in a second direction crossing with the first direction; and first resistance variable elements defined between the first lines and the second lines and each including a first substance layer and a second substance layer, wherein the first substance layer extends in the first direction and the second substance layer extends in the second direction.. . ... Sk Hynix Inc

01/28/16 / #20160028010

3d variable resistance memory device and method of manufacturing the same

A variable resistance memory device includes a plurality of cell gate electrodes extending in a first direction, wherein the plurality of cell gate electrodes are stacked in a second direction that is substantially perpendicular to the first direction. A gate insulating layer surrounds each cell gate electrode of the plurality of cell gate electrodes and a cell drain region is formed on two sides of the each cell gate electrode of the plurality of cell gate electrodes a channel layer extends in the second direction along the stack of the plurality of cell gate electrodes, and a variable resistance layer contacting the channel layer.. ... Sk Hynix Inc

01/28/16 / #20160028006

3d variable resistance memory device and method of manufacturing the same

A variable resistance memory device includes a plurality of cell gate electrodes extending in a first direction, wherein the plurality of cell gate electrodes are stacked in a second direction that is substantially perpendicular to the first direction, a gate insulating layer surrounds each cell gate electrode of the plurality of cell gate electrodes and a cell drain region is formed on two sides of the each cell gate electrode of the plurality of cell gate electrodes a channel layer extends in the second direction along the stack of the plurality of cell gate electrodes, and a variable resistance layer contacting the channel layer.. . ... Sk Hynix Inc

01/28/16 / #20160027915

Semiconductor device including a gate electrode

A semiconductor device includes a plurality of first gate electrodes buried in a semiconductor substrate including an active region and a device isolation film, a plurality of junction regions including storage node junction regions and a bit line junction region disposed between the storage node junction regions, a plurality of storage node contact plugs respectively disposed over and coupled to the storage node junction regions, a plurality of storage nodes respectively disposed over and coupled to the storage node contact plugs, and a second gate electrode disposed over a sidewall of a corresponding one of the storage node contact plugs. A vertical transistor includes the second gate electrode and the corresponding storage node contact plug and stores charges leaked from a corresponding one of the storage nodes.. ... Sk Hynix Inc

01/28/16 / #20160027741

Semiconductor packages having emi shielding layers, methods of fabricating the same, electronic systems including the same, and memory cards including the same

Semiconductor packages are provided. In some embodiments, the semiconductor package includes a substrate, a first ground line including a first internal ground line disposed along edges of the substrate and a plurality of first extended ground lines between the first internal ground line and sidewalls of the substrate, a chip on the substrate, a molding member disposed on the substrate to cover the chip, and an electromagnetic interference (emi) shielding layer covering the molding member, the emi shielding layer extending along the sidewalls of the substrate and contacting the end portions of the plurality of first extended ground lines. ... Sk Hynix Inc

01/28/16 / #20160027730

Interconnection structure, semiconductor device, and method of manufacturing the same

An interconnection structure may include insulating layers stacked stepwise and dielectric layers interposed between the insulating layers. The interconnection structure may include conductive layers interposed between the insulating layers and surrounding sidewalls of the dielectric layers, respectively. ... Sk Hynix Inc

01/28/16 / #20160027727

Semiconductor device with air gaps and method for fabricating the same

A semiconductor device includes: a first plug; a bit line which is in contact with the first plug and over the first plug and extended in one direction; a second plug including a first part adjacent to the bit line and a second part adjacent to the first plug; a double air gap which is disposed between the first part of the second plug and the bit line and includes a first air gap surrounding the first part of the second plug and a second air gap parallel to sidewalls of the bit line; and a capping layer suitable for capping the first and second air gaps.. . ... Sk Hynix Inc

01/28/16 / #20160027532

Memory device

A memory device includes a plurality of redundancy word lines each of which is coupled with a plurality of redundancy memory cells, and a redundancy refresh circuit suitable for sequentially refreshing first redundancy word lines that are selected as target word lines for an additional refresh operation among the plurality of the redundancy word lines.. . ... Sk Hynix Inc

01/28/16 / #20160027530

Semiconductor memory apparatus

A semiconductor memory apparatus may include a first data storage region configured to output a first data, a second data storage region configured to output a second data, a third data storage region configured to output a third data, and a fourth data storage region configured to output a fourth data. The apparatus may include a first comparison block configured to compare the first data with the second data, and generate a first comparison signal. ... Sk Hynix Inc

01/28/16 / #20160027524

Data storage device and operating method thereof

An operating method of a data storage device includes performing a first static read fail solving operation in which the memory cell is read by applying read fail solving voltages included in a first group to the memory cell; and performing a second static read fail solving operation in which the memory cell is read by applying read fail solving voltages included in a second group to the memory cell after the first static read fail solving operation fails, wherein read success numbers of the respective read fail solving voltages included in the first group are larger than read success numbers of the respective read fail solving voltages included in the second group.. . ... Sk Hynix Inc

01/28/16 / #20160027520

Semiconductor memory device including three-dimensional memory cell array structure and operating method thereof

An operating method includes biasing channel regions of unselected cell strings among the cell strings to an initial voltage while applying a first pass voltage to the plurality of word lines; floating the channel regions of the unselected cell strings; increasing the first pass voltage to a second pass voltage during the floating of the channel regions; and reading data from selected memory cells of selected cell strings among the cell strings.. . ... Sk Hynix Inc

01/28/16 / #20160027505

3d variable resistance memory device and method of manufacturing the same

A variable resistance memory device includes a plurality of cell gate electrodes extending in a first direction, wherein the plurality of cell gate electrodes are stacked in a second direction that is substantially perpendicular to the first direction, a gate insulating layer surrounds each cell gate electrode of the plurality of cell gate electrodes and a cell drain region is formed on two sides of the each cell gate electrode of the plurality of cell gate electrodes a channel layer extends in the second direction along the stack of the plurality of cell gate electrodes, and a variable resistance layer contacting the channel layer.. . ... Sk Hynix Inc

01/28/16 / #20160027491

Refresh circuit

A refresh circuit is configured to perform a first refresh operation for a plurality of memory banks. The first refresh operation may be performed within a first time period determined according to a first parameter. ... Sk Hynix Inc

01/28/16 / #20160027487

Semiconductor memory apparatus

A semiconductor memory apparatus includes a bank; a temperature sensor configured to generate a temperature voltage of which voltage level is changed according to a temperature variation of the bank; and a timing control block configured to control a timing of a signal to be inputted to the bank, according to the voltage level of the temperature voltage.. . ... Sk Hynix Inc

01/28/16 / #20160027483

Semiconductor integrated circuit

A semiconductor integrated circuit may include: a memory block partitioned into a first region and a second region; a data latch unit configured to latch data outputted from the memory block in response to a control signal; and a control circuit configured to generate a source signal separated into an odd order and an even order in response to a column access signal consecutively inputted to access the first region or the second region, and to generate the control signal in response to the source signal.. . ... Sk Hynix Inc

01/28/16 / #20160027478

Stack bank type semiconductor memory apparatus capable of improving alignment margin

A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks.. ... Sk Hynix Inc

01/28/16 / #20160026526

Encoder by-pass with scrambler

A first physical location is read to obtain read data. Error correction decoding is performed on the read data to obtain error-corrected data where the error-corrected data includes first error-corrected metadata. ... Sk Hynix Inc

01/28/16 / #20160026471

Semiconductor device and method of operating the same

A semiconductor device includes one or more internal circuits; a nonvolatile memory circuit including a first region suitable for storing first data for the nonvolatile memory circuit and a second region suitable for storing second data for the internal circuits; a first register suitable for temporarily storing the first data; one or more second registers suitable for temporarily storing the second data; and a control circuit suitable for controlling the nonvolatile memory circuit to transmit the first data and the second data to the first register and to the second registers, respectively, when a boot-up operation is performed.. . ... Sk Hynix Inc

01/28/16 / #20160026396

Semiconductor memory apparatus and electronic system having the same

A semiconductor memory apparatus includes a memory circuit unit, a radio frequency (rf) signal unit which wirelessly transmits and receives signals, and a control circuit unit which accesses the memory circuit unit in response to a signal received through the rf signal unit and provides data of the memory circuit unit to the rf signal unit. At least one of the rf signal unit and the control circuit unit has a one-chip structure with the memory circuit unit.. ... Sk Hynix Inc

01/21/16 / #20160021320

Image sensor

An image sensor includes: a plurality of pixels arranged in two dimensions, wherein at least one pixel among the pixels includes: a photoelectric conversion layer formed in a substrate; a color filter layer formed over the photoelectric conversion layer; a first shading layer formed in the same plane as the color filter layer and defining a first light transmitting region; and a second shading layer formed between the photoelectric conversion layer and the first shading layer and defining a second light transmitting region.. . ... Sk Hynix Inc

01/21/16 / #20160020754

Integrated circuit

An integrated circuit includes a latch block suitable for storing a signal through four or more even-numbered coupling lines inverted and driven alternately with each other, wherein the coupling lines are divided into two or more coupling line groups each including coupling lines inverted and driven to the same logic level, and a charge buffer block coupled between two or more coupling lines included in one of the coupling line groups and suitable for slowing down a charge movement speed therebetween.. . ... Sk Hynix Inc

01/21/16 / #20160020292

Unit cells of nonvolatile memory devices, cell arrays of nonvolatile memory devices, and methods of fabricating the same

Unit cells including a substrate having an active region, a first charge trap pattern disposed on the substrate to intersect the active region, a second charge trap pattern disposed on the substrate to intersect the active region and spaced apart from the first charge trap pattern, a first junction region disposed in the active region between the first and second charge trap patterns, a second junction region disposed in the active region adjacent to one side of the first charge trap pattern opposite to the second charge trap pattern, and a third junction region disposed in the active region adjacent to one side of the second charge trap pattern opposite to the first charge trap pattern.. . ... Sk Hynix Inc

01/21/16 / #20160020270

Metal-insulator-metal capacitor, electronic device including the same, and method of fabricating the same

A metal-insulator-metal (mim) capacitor that includes an insulation pattern on an underlying structure having a capacitor region and a peripheral region surrounding the capacitor region, the insulation pattern having a plurality contact holes that expose portions of the underlying structure in the capacitor region; a lower metal pattern in the capacitor region to cover a top surface of the insulation pattern, sidewalls of the insulation pattern corresponding to sidewalls of the contact holes, and the portions of the underlying structure exposed by the contact holes; a dielectric pattern that covers the lower metal pattern in the capacitor region and a top surface of the insulation pattern in the peripheral region; and an upper metal pattern on the dielectric pattern in the capacitor region and the peripheral region.. . ... Sk Hynix Inc

01/21/16 / #20160020254

Semiconductor memory device and method of manufacturing the same

A semiconductor memory device comprising a bit line extending in a first direction, a vertical gate cell including a gate oxide layer and a gate metal layer that are formed in a pillar shape, a lower electrode and a data storage material layer formed on the vertical gate cell, and an interconnection layer formed on the data storage material layer.. . ... Sk Hynix Inc

01/21/16 / #20160020252

Variable resistance memory device

A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a first insulating layer formed on a semiconductor substrate, the first insulating layer having a first hole formed therein. ... Sk Hynix Inc

01/21/16 / #20160020221

Three-dimensional (3d) non-volatile memory device

A three-dimensional (3d) non-volatile semiconductor memory device including a u-shaped channel structure is disclosed. The 3d non-volatile semiconductor memory device includes a pipe gate, an upper pipe channel disposed in the pipe gate at a first depth, a first lower pipe channel disposed in the pipe gate at a second depth different from the first depth, and neighboring the upper pipe channel in a first direction, and a second lower pipe channel disposed in the pipe gate at the second depth, and neighboring the upper pipe channel in a second direction perpendicular to the first direction, wherein the upper pipe channel and the lower pipe channels have the same length.. ... Sk Hynix Inc

01/21/16 / #20160020217

Semiconductor device

A semiconductor device includes a first vertical memory string connected to a common source line, a second vertical memory string connected to a bit line, a pipe transistor suitable for selectively connecting the first and second vertical memory strings based on a block selection signal, and a plurality of transistors suitable for selectively connecting local lines of the first and second vertical memory strings to corresponding global lines based on the block selection signal.. . ... Sk Hynix Inc

01/21/16 / #20160020184

Semiconductor devices having through electrodes, methods of fabricating the same, electronic systems including the same, and memory cards including same

A semiconductor device includes a chip body having an uneven surface including at least two regions at different levels from one another, a through electrode penetrating the chip body and having an end which is exposed by the uneven surface of the chip body, a passivation layer disposed on the uneven surface of the chip body, and a bump disposed on the passivation layer and the exposed end of the through electrode and overlapping with the uneven surface of the chip body.. . ... Sk Hynix Inc

01/21/16 / #20160019980

Electronic device

An electronic device comprising a semiconductor memory unit that may include a variable resistance element configured to be changed in a resistance value thereof in response to current flowing through both ends thereof, a toggle data generation unit configured to generate toggle data of which logic value toggles with a predetermined cycle, in a first mode for testing reliability of the variable resistance element, a data transfer line configured to transfer data inputted from an outside, and a driving unit configured to flow current which is changed in its direction with the predetermined cycle, through the variable resistance element in response to the toggle data in the first mode, and flow current through the variable resistance element in a direction determined in response to the data of the data transfer line, in a second mode in writing date into or reading data from the variable resistance element.. . ... Sk Hynix Inc

01/21/16 / #20160019969

Semiconductor memory device and operating method thereof

A semiconductor memory device according to an embodiment of the present invention includes a first cell string and a second cell string coupled to a first word line group and a second word line group, respectively. An operating method of the semiconductor memory device may include forming a channel in the second cell string by applying a pass voltage to the second word line group, reflecting data of a selected memory cell coupled to a selected word line of the first word line group, among memory cells of the first cell string, on the channel of the second cell string through the bit line, and determining the data of the selected memory cell by sensing a quantity of electric charge of the second cell string through the bit line.. ... Sk Hynix Inc

01/21/16 / #20160019968

Flash memory device

A flash memory device includes a first page buffer, a second page buffer neighboring the first page buffer, a source-pick-up region disposed between the first page buffer and the second page buffer, and a source line extending in a direction. The source line includes a first portion that corresponds to the first page buffer and a second portion that corresponds to the second page buffer. ... Sk Hynix Inc

01/21/16 / #20160019966

Semiconductor memory device and method of operating the same

A semiconductor memory device is operated by, inter alia, performing least significant bit programs for pages in a first page group, performing least significant bit programs for pages in a second page group, and performing most significant bit programs for the pages in the first page group. The distance between the second page group and the common source line is greater than that between the first page group and the common source line.. ... Sk Hynix Inc

01/21/16 / #20160019956

Electronic device

This patent document relates to memory circuits or devices and their applications in electronic devices or systems. The disclosed technology in this patent document includes memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device in which an electronic device capable of reducing an area, improving device characteristics due to a reduction in the resistance of a switching transistor, simplifying the process, and reducing a cost is provided. ... Sk Hynix Inc

01/21/16 / #20160019944

Address generation circuit and memory device including the same

An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.. . ... Sk Hynix Inc

01/21/16 / #20160019940

Memory device

A memory device includes a plurality of normal word lines arranged at a first distance from each other, a redundant word line arranged at a second distance, which is greater than the first distance from a normal word line adjacent to the redundant word line, among the normal word lines, and a word line control unit suitable for selectively activating the normal word lines, and replacing a frequently activated word line with the redundant word line when the frequently activated word line is detected.. . ... Sk Hynix Inc

01/21/16 / #20160019938

Latch circuit and semiconductor device including the same

A latch circuit includes: first to nth storage nodes where n is an even number equal to or more than four; and first to nth pairs of transistors, each of which comprises a pmos transistor and an nmos transistor coupled in series with each other through a corresponding node among the first to nth storage nodes. The pmos transistor is coupled to one of the storage nodes included in previous one of the pairs of transistors at a gate of the pmos transistor. ... Sk Hynix Inc

01/21/16 / #20160018445

Test circuit and semiconductor apparatus including the same

A test circuit includes a through via test unit configured to be set to a first resistance value in response to a first test control signal and to a second resistance value in response to the first test control signal and a second test control signal, and form a current path including a through via that electrically connects a first chip and a second chip; and a test measurement unit configured to supply a test voltage to the through via and measure a current flowing through the through via.. . ... Sk Hynix Inc

01/14/16 / #20160013796

Semiconductor device

A semiconductor device may include a delay line including a first group of unit delay cells and a second group of unit delay cells. The first group of unit delay cells and the second group of unit delay cells may be configured for delaying a phase of a clock by a unit cycle of a reference frequency. ... Sk Hynix Inc

01/14/16 / #20160013793

Electronic device

An electronic device including an inverter includes a pull-up driving unit configured to drive an output node with a high voltage in response to an input signal; a path switching unit coupled in a path between the pull-up driving unit and the output node according to a direction of a first current flowing between the pull-up driving unit and the output node and operable to selectively switch on or off the path; a pull-down driving unit coupled to the output node to supply a low voltage in response to the input signal; a path blocking unit coupled in a path between the pull-down driving unit and the output node to block the path; and a bypass unit coupled to form a bypass path between the pull-down driving unit and the output node.. . ... Sk Hynix Inc

01/14/16 / #20160013783

Semiconductor apparatus and system including plurality of channels

A semiconductor apparatus includes a direct access section, an interface section, and a through-via region. The direct access section receives first and second groups of input signals through a direct access pad, and generates first and second groups of control signals based on the first and second groups of input signals. ... Sk Hynix Inc

01/14/16 / #20160013408

Semiconductor apparatus and method for fabricating the same

A method for fabricating a semiconductor apparatus includes providing a semiconductor substrate, stacking a conductive layer, a variable resistance layer, and a sacrificial layer on the semiconductor substrate, etching the conductive layer, the variable resistance layer, and the sacrificial layer to form a pillar structure including a lower electrode, a variable resistor device, and a sacrificial layer pattern, removing the sacrificial layer pattern, and forming an upper electrode over the variable resistor device in a hole which is formed by removing the sacrificial layer pattern.. . ... Sk Hynix Inc

01/14/16 / #20160013405

Electronic device including a semiconductor memory and method for fabricating the same

The disclosed technology provides semiconductor memory devices and applications in electronic devices. In one implementation, an electronic device includes a semiconductor memory that includes a first contact plug over a substrate; an interlayer dielectric layer located over the first contact plug and having a hole which exposes at least a portion of the first contact plug; a first electrode layer formed along a sidewall and a bottom surface of the hole to be in contact with the first contact plug; a variable resistance layer over the first electrode layer and structured to include (1) a first portion that extends along the sidewall of the hole in a direction perpendicular to the substrate and exhibits a variable resistance and (2) a second portion that is parallel to the bottom surface of the hole and does not exhibit a variable resistance, and a second electrode layer formed over the variable resistance layer.. ... Sk Hynix Inc

01/14/16 / #20160013315

Transistor including a stressed channel, a method for fabricating the same, and an electronic device including the same

A semiconductor device includes a first channel, a second channel, a first strained gate electrode including a first lattice-mismatched layer for applying a first stress to the first channel, and a second strained gate electrode including a second lattice-mismatched layer for applying a second stress to the second channel.. . ... Sk Hynix Inc

01/14/16 / #20160013292

Semiconductor integrated circuit device having vertical channel and method of manufacturing the same

A semiconductor integrated circuit device having a vertical channel and a method of manufacturing the same are provided. A plurality of active lines are formed in a semiconductor substrate. ... Sk Hynix Inc

01/14/16 / #20160013203

Semiconductor device

A semiconductor device may include a first insulating pillar having a substantially y-shaped cross-sectional structure to define first through third regions, channel pillars formed in the first through third regions, respectively, and second insulating pillars disposed opposite one another across the first through third regions. The semiconductor device may also include third insulating pillars disposed between the second insulating pillars and disposed opposite one another across the first through third regions. ... Sk Hynix Inc

01/14/16 / #20160013161

Semiconductor package

A semiconductor package includes: a plurality of lead members disposed with a space therebetween over a surface of a substrate, a first semiconductor chip disposed in a face-up manner over the first surface of the substrate between at least two of the plurality of lead members; a second semiconductor chip disposed in a face-up manner over the first semiconductor chip and the at least two lead members, and a connection member for connecting the substrate, the at least two lead members, the first semiconductor chip and the second semiconductor chip with one another.. . ... Sk Hynix Inc

01/14/16 / #20160013157

Semiconductor apparatus including a plurality of channels and through-vias

A semiconductor apparatus includes a plurality of stacked chips. Each of the plurality of stacked chips may include a plurality of through-vias, each formed at a corresponding location in the plurality of through-vias, and each of the plurality of through-vias is electrically coupled with a through-via in a neighboring stacked chip in a diagonal direction. ... Sk Hynix Inc

01/14/16 / #20160013094

Semiconductor device and method for forming the same

A semiconductor device and a method for forming the same can block a moving path of electrons between neighbor buried gates. A semiconductor device includes a device isolation film formed to define an active region over a semiconductor substrate. ... Sk Hynix Inc

01/14/16 / #20160013077

Substrate including a dam for semiconductor package, semiconductor package using the same, and manufacturing method thereof

A substrate for a semiconductor package includes a substrate body having a first surface and a second surface which faces away from the first surface, and formed with at least one bump land on the first surface, and a dam formed and projected over an edge of the first surface of the substrate body, and having an underfill member discharge unit.. . ... Sk Hynix Inc

01/14/16 / #20160012917

Method for testing array fuse of semiconductor apparatus

Provided is a method for testing an array fuse of a semiconductor apparatus. The method may perform a series of operations for testing an array fuse block of the semiconductor apparatus as a test program is executed. ... Sk Hynix Inc

01/14/16 / #20160012909

Data storage circuit and system including the same

A data storage circuit includes a first antifuse which is programmed in response to a first access signal, and provide data indicating whether the first antifuse is programmed to a data node, an initialization section which controls a voltage level of the data node in response to an initialization flag, and a second antifuse which is programmed in response to the first access signal, and provide the initialization flag indicating whether the second antifuse is programmed to the initialization section.. . ... Sk Hynix Inc

01/14/16 / #20160012908

E-fuse array circuit and semiconductor memory apparatus having the same

An e-fuse array circuit includes a driving block arranged in a predetermined portion of a semiconductor substrate, a normal fuse array configured to one side of the driving block, and an auxiliary circuit part arranged in an other side of the driving block to a direction facing an arrangement direction of the normal fuse array.. . ... Sk Hynix Inc

01/14/16 / #20160012895

Semiconductor memory device, memory system having the same, and method of operating the same

By programming the memory cells mc0, mc1, mcn, mcn-1 adjacent to the source and drain select transistors sst and dst using different program methods, a total number of data bits of the memory cells mc0, mc1 adjacent to the source side dummy memory cell spmc may be three. The tlc program method may have eight threshold voltage distributions pv0-pv7 to store the three-bit data. ... Sk Hynix Inc

01/14/16 / #20160012893

Semiconductor memory device including three-dimensional array structure

A semiconductor memory device may include source selection transistors coupled to a common source line, source side dummy memory cells coupled between the source selection transistors and the normal memory cells, and drain selection transistors coupled to a bit line. The semiconductor memory device may include drain side dummy memory cells coupled between the drain selection transistors and the normal memory cells. ... Sk Hynix Inc

01/14/16 / #20160012877

Semiconductor memory apparatus

A semiconductor memory apparatus may include a row address control block configured to output an address as a row address or output a counted signal as the row address in response to a refresh signal and the address, and generate an auto-precharge signal and a pre-bank active signal in response to the refresh signal and a bank active signal. The semiconductor memory apparatus may include a bank control block configured to generate the bank active signal in response to an active signal, a precharge signal, a bank address signal, the auto-precharge signal and the pre-bank active signal.. ... Sk Hynix Inc

01/14/16 / #20160012873

Semiconductor device

A semiconductor device includes: a first block, which is initialized during an initialization mode; and a second block, which is initialized while the first block latches first signals during a boot-up mode. Herein, the second block may latch second signals after being initialized during the boot-up mode.. ... Sk Hynix Inc

01/14/16 / #20160012872

Integrated circuit for storing information

An integrated circuit includes a variable resistance unit including at least one transistor that receives a control signal and changes a resistance through the transistor in response to the control signal in a programming operation mode and an information detection unit configured to detect programming information in response to an output voltage of the variable resistance unit in a normal operation mode.. . ... Sk Hynix Inc

01/14/16 / #20160012871

Integrated circuit for storing information

An integrated circuit includes a variable resistance unit including at least one transistor that receives a control signal and changes a resistance through the transistor in response to the control signal in a programming operation mode and an information detection unit configured to detect programming information in response to an output voltage of the variable resistance unit in a normal operation mode.. . ... Sk Hynix Inc

01/14/16 / #20160012866

Semiconductor memory apparatus

A semiconductor memory apparatus includes an effective region which is a portion of the memory region and functions as a data storage space, a residual region which is another portion of the memory region, and a capacity control circuit which restricts supply of power and signals to the residual region.. . ... Sk Hynix Inc

01/14/16 / #20160012864

Stacked semiconductor package

A stacked semiconductor package includes a package substrate, an interposer mounted on the package substrate, a plurality of semiconductor chips stacked on the interposer, and a control unit provided in the interposer, that stores in advance data to be written in the plurality of semiconductor chips, and that outputs the data stored in advance according a test mode signal.. . ... Sk Hynix Inc

01/14/16 / #20160011620

Semiconductor integrated circuit device having bulk bias control function and method of driving the same

A semiconductor integrated circuit device having a bulk bias control function is provided. The semiconductor integrated circuit device may be configured to output the first external voltage as a bulk voltage of a transistor in a power-up period, and to output a second external voltage having a higher level than the first external voltage as the bulk voltage of the transistor in a power-down mode.. ... Sk Hynix Inc

01/14/16 / #20160011265

Semiconductor apparatus and test method thereof

A semiconductor apparatus includes first and second chips sharing first and second data channels. The first chip compresses first test data of the first chip and outputs the compressed first test data through the first data channel in a first test mode, and the second chip compresses second test data of the second chip and outputs the compressed second test data through the second data channel in the first test mode.. ... Sk Hynix Inc

01/14/16 / #20160011263

Semiconductor apparatus

A semiconductor apparatus includes a test entry control block configured to generate a plurality of trigger signals and a reset signal according to a test setting command and addresses; and a test entry signal generation block configured to enable a test entry signal when the plurality of trigger signals are sequentially enabled.. . ... Sk Hynix Inc

01/07/16 / #20160006432

Semiconductor device and operating method thereof

A semiconductor device includes a plurality of impedance providing sections suitable for providing an input/output node with a first impedance corresponding to a signal transmission, and a second impedance corresponding to a signal reception, and an impedance control section suitable for adjusting the first impedance by adjusting the number of enabled impedance providing sections among the plurality of impedance providing sections during the signal transmission, and adjusting the second impedance by changing impedance of one or more impedance providing sections among the plurality of impedance providing sections during the signal reception.. . ... Sk Hynix Inc

01/07/16 / #20160006419

Electronic systems

An electronic system may include a first circuit driven by a first power voltage signal and a first ground voltage signal, and a second circuit driven by a second power voltage signal and a second ground voltage signal. The electronic system may also include a stabilizer coupled between a first ground terminal and a second ground terminal and suitable for blocking a current flowing from the second ground terminal toward the first ground terminal.. ... Sk Hynix Inc

01/07/16 / #20160006418

Receiver circuit of semiconductor apparatus

A receiver circuit of a semiconductor apparatus may include, a latch comprising differential input terminals and differential output terminals. The receiver circuit may also include a control unit configured to selectively reset first and second intermediate nodes coupled between the differential input terminals and the differential output terminals according to previous data.. ... Sk Hynix Inc

01/07/16 / #20160005963

Electronic device and method for fabricating the same

An electronic device includes a semiconductor memory that includes: an inter-layer dielectric layer including a hole over a substrate; a first nitride layer disposed on sidewalls of the hole; a selector disposed in a bottom portion of the hole and over the first nitride layer on the sidewalls of the hole; a stacked structure including a variable resistance pattern disposed over a lower structure including the selector; and a second nitride layer disposed in an upper portion and on sidewalls of the stacked structure.. . ... Sk Hynix Inc

01/07/16 / #20160005953

Electronic device including a semiconductor memory

This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a contact plug; a first stack structure disposed over the contact plug and coupled to the contact plug, wherein the first stack structure includes a pinning layer controlling a magnetization of a pinned layer; and a second stack structure disposed over the first stack structure and coupled to the first stack structure, wherein the second stack structure includes a mtj (magnetic tunnel junction) structure which includes the pinned layer having a pinned magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer interposed between the pinned layer and the free layer, wherein a width of the first stack structure is larger than a width of the contact plug and a width of the second stack structure.. ... Sk Hynix Inc

01/07/16 / #20160005859

Three dimensional semiconductor integrated circuit having gate pick-up line and method of manufacturing the same

A 3d semiconductor integrated circuit having a gate pick-up line and a method of manufacturing the same, wherein the semiconductor integrated circuit includes a plurality of active pillars formed in a gate pick-up region, buffer layers formed on the respective active pillars in the gate pick-up region, gates each surrounding an outer circumference of the corresponding active pillar and the corresponding buffer layer, and a gate pick-up line electrically coupled to the gates.. . ... Sk Hynix Inc

01/07/16 / #20160005794

Three dimensional semiconductor integrated circuit having gate pick-up line and method of manufacturing the same

A 3d semiconductor integrated circuit having a gate pick-up line and a method of manufacturing the same, wherein the semiconductor integrated circuit includes a plurality of active pillars formed in a gate pick-up region, buffer layers formed on the respective active pillars in the gate pick-up region, gates each surrounding an outer circumference of the corresponding active pillar and the corresponding buffer layer, and a gate pick-up line electrically coupled to the gates.. . ... Sk Hynix Inc

01/07/16 / #20160005754

Nonvolatile memory device and method for fabricating the same

A nonvolatile memory device having a plurality of unit cells, each of the plurality of unit cells includes a first transistor suitable for having a fixed threshold voltage, and a second transistor suitable for coupling to the first transistor in parallel and having a variable threshold voltage.. . ... Sk Hynix Inc

01/07/16 / #20160005747

Three dimensional semiconductor device

A semiconductor device includes alternately stacked conductive layers and the insulating layers, an opening passing through the conductive layers and insulating layers, a first semiconductor layer formed in the opening, a second semiconductor layer formed in the first semiconductor layer, a capping layer formed in the opening and disposed over the first semiconductor layer and the second semiconductor layer, and a liner layer interposed between the first semiconductor layer and the second semiconductor layer and protruding through the capping layer relative to the first semiconductor layer and the second semiconductor layer.. . ... Sk Hynix Inc

01/07/16 / #20160005745

Semiconductor device and method of manufacturing the same

A semiconductor device includes a substrate having a cell region, wherein a contact region, page buffer regions, and a scribe lane region are defined around the cell region; a cell structure located in the cell region, including first conductive layers and first insulating layers which are alternately stacked, and having a non-stepped shape; a contact structure located in the contact region, including second conductive layers and second insulating layers which are alternately stacked, and having a stepped shape; a first dummy structure located in the page buffer region, including first sacrificial layers and third insulating layers which are alternately stacked, and having the non-stepped shape; and a second dummy structure located in the scribe lane region, including second sacrificial layers and fourth insulating layers which are alternately stacked, and having the stepped shape.. . ... Sk Hynix Inc

01/07/16 / #20160005743

Semiconductor device with air gap and method for fabricating the same

A semiconductor device includes a first conductive structure including a first conductive pattern that is formed over a substrate, a second conductive structure formed adjacent to a sidewall of the first conductive structure, and an insulation structure including an air gap that is formed between the first conductive structure and the second conductive structure, wherein the second conductive structure includes a second conductive pattern, an ohmic contact layer that is to formed over the second conductive pattern, and a third conductive pattern that is formed over the ohmic contact layer and is separated from the first conductive pattern through the air gap.. . ... Sk Hynix Inc

01/07/16 / #20160005706

Semiconductor devices having through electrodes, methods of manufacturing the same, and semiconductor packages including the same

A semiconductor device includes a semiconductor layer having a first surface and a second surface, a through electrode penetrating the semiconductor layer and having a protruding portion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed on the first surface of the semiconductor layer and electrically coupled to the through electrode, a passivation pattern including a first insulation pattern that surrounds a sidewall of the protruding portion of the through electrode and extends onto the second surface of the semiconductor layer and a second insulation pattern that covers the first insulation pattern and has an etch selectivity with respect to the first insulation pattern, and a back-side bump covering an end surface of the protruding portion of the through electrode and extending onto the passivation pattern.. . ... Sk Hynix Inc

01/07/16 / #20160005496

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a memory cell array including a plurality of word lines; a repair fuse section programmed with one or more repair-target addresses and fuse enable information; an address generation section suitable for generating test addresses during a test operation, corresponding to the word lines based on the repair-target addresses and the fuse enable information; and a word line control section suitable for selectively activating the word lines based on the test addresses.. . ... Sk Hynix Inc

01/07/16 / #20160005476

Semiconductor memory device and method of operating the same

A semiconductor memory device includes a memory string and a peripheral circuit. The memory string has a pipe cell, a plurality of memory cells, and at least one channel layer having a three-dimensional u-shaped structure. ... Sk Hynix Inc

01/07/16 / #20160005472

Semiconductor device

A semiconductor device includes a memory block including memory cells connected to a word line, and an operation circuit suitable for consecutively applying a main program pulse and a sub program pulse to the word line to perform a program operation of the memory cells, and suitable for performing a program verification operation of the memory cells, wherein the sub program pulse has a lower voltage level than the main program pulse.. . ... Sk Hynix Inc

01/07/16 / #20160005466

Semiconductor device

A semiconductor device includes a first memory string and a second memory string. The first memory string includes a plurality of first main memory cells formed on a pipe transistor of a semiconductor substrate and a plurality of first dummy memory cells connected between the first main memory cells and a common source line. ... Sk Hynix Inc

01/07/16 / #20160005462

Electronic device

An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction intersecting the first direction, and a plurality of variable resistance patterns that is positioned at intersections of the first lines and the second lines and disposed between the first lines and the second lines in a vertical direction. ... Sk Hynix Inc

01/07/16 / #20160005456

Semiconductor memory apparatus

A semiconductor memory apparatus may include a refresh mode control circuit configured to enable a row address increase signal when all banks capable of being designated by a bank address in a refresh operation are all designated. The semiconductor memory apparatus may also include and a row address generation circuit configured to increase a value of a row address when the row address increase signal is enabled.. ... Sk Hynix Inc

01/07/16 / #20160005453

Semiconductor device

A semiconductor device may include pad blocks configured for receiving and outputting data. The semiconductor device may also include input/output driving blocks configured to transfer data received from global input/output lines to the pad blocks in response to a read operation, and transfer data from the pad blocks to the global input/output lines in response to a write operation. ... Sk Hynix Inc

01/07/16 / #20160005445

Semiconductor memory device and method of testing the same

A semiconductor memory device includes a row input section suitable for receiving a first row signal including a first row command and a first row address, corresponding to an active command, during a test operation of the active command, a column input section suitable for receiving a second row signal including a second row address corresponding to the active command during the test operation of the active command, and a signal control section suitable for generating an internal row signal for an operation of the active command by transforming the first row signal and the second row signal outputted from the row input section and the column input section.. . ... Sk Hynix Inc

01/07/16 / #20160005444

Data storage device

A data storage device includes a first memory device suitable for performing an internal operation in response to a first internal operation command; and a state checking block suitable for performing a state read operation by transmitting a state read command one or more times to the first memory device during one of an initial mode and a repeat mode which is set based on a type of the internal operation.. . ... Sk Hynix Inc

01/07/16 / #20160005443

Memory and memory system

A memory may include first to nth cell arrays configured to include a plurality of memory cells and one or more first to nth data input/output pads respectively corresponding to the first to nth cell arrays, wherein the one or more first to nth data input/output pads are configured to input/output data to/from the first to nth cell arrays.. . ... Sk Hynix Inc

01/07/16 / #20160004660

Memory system and data storage device

A memory system includes a first memory device and a second memory device suitable for outputting and receiving signals through first and second sub input/output lines, respectively, a controller suitable for outputting and receiving signals to and from the first memory device and the second memory device, through a main input/output line and a selection unit suitable for electrically coupling the main input/output line with one of the first and the second sub input/output lines, through which an activated one of the first memory and the second memory devices outputs and receives signals.. . ... Sk Hynix Inc

01/07/16 / #20160004649

Data input circuit of semiconductor apparatus

A data input circuit of a semiconductor apparatus may include a plurality of parallelizing units corresponding to a plurality of input/output pads in a one-to-one manner, and a data control block configured to transmit serial test data, which may be input through less than all of the plurality of input/output pads, to the plurality of parallelizing units in response to first and second control signals.. . ... Sk Hynix Inc








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