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Sk Hynix Inc patents (2017 archive)


Recent patent applications related to Sk Hynix Inc. Sk Hynix Inc is listed as an Agent/Assignee. Note: Sk Hynix Inc may have other listings under different names/spellings. We're not affiliated with Sk Hynix Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Sk Hynix Inc-related inventors


Group selection circuit, and column readout device and method thereof

A group selection circuit includes an input block suitable for receiving a last column select signal of a previous column switch group and a last column select signal of a current column switch group; and a group selection block suitable for generating a group select signal that is activated from a first edge of the last column select signal of the previous column switch group to a first edge of the last column select signal of the current column switch group, in response to an output signal of the input block.. . ... Sk Hynix Inc

Data dependency mitigation in parallel decoders for flash storage

A memory device can include a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform parallel decoding of codewords. ... Sk Hynix Inc

Image sensor including transfer gates in deep trenches

An image sensor is described. The image sensor includes a photodiode that is formed in a substrate, a floating diffusion region that vertically overlaps with a first portion of the photodiode, a shallow trench isolation (sti) region that vertically overlaps with a second portion of the photodiode and has an elbow shape, and a transfer gate that is adjacent to at least two sides of the photodiode and has an elbow shape.. ... Sk Hynix Inc

Semiconductor device and method of manufacturing the same

A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and one or more openings. The pad structure may be disposed between the first cell structure and the second cell structure, and may be electrically coupled to the first and second cell structures. ... Sk Hynix Inc

Method of manufacturing wafer level package and wafer level package manufactured thereby

Provided are a wafer level package and a manufacturing method thereof. A reconfigured substrate may be formed by disposing a first semiconductor die on a dummy wafer, and forming a molding layer and a mold covering layer. ... Sk Hynix Inc

Package-on-package type semiconductor device including fan-out memory package

A semiconductor device may include a bottom package embedded with a first semiconductor chip. The semiconductor device may include a middle package stacked over the bottom package, and embedded with at least two second semiconductor chips in a fan-out structure. ... Sk Hynix Inc

Automated testing system and operating method thereof

A system and an operating method thereof include at least a system under test (sut) having collection of flash storages including hardware of array of flash storages, collection of partitions including logical volumes, a kernel subsystem including operating system, and an application layer including services, applications, systems, or a combination thereof; test drivers configured to drive tests, wherein the tests are configured for testing the sut, test fixtures configured to generate test data sets corresponding to the test drivers, observers configured to track test results of test cases created in accordance with the test drivers and the test data sets, wherein the test results include metrics, and archives configured to store historical data of the test cases.. . ... Sk Hynix Inc

Semiconductor devices

A semiconductor device may include a syndrome generation circuit and a failure detection circuit. The syndrome generation circuit may generate a syndrome signal corresponding to a pattern of an output data signal. ... Sk Hynix Inc

Test apparatus, memory test system, and test method

A memory test system may include a memory apparatus and a test apparatus. The test apparatus may be configured to generate a code distribution of noble cells. ... Sk Hynix Inc

Semiconductor memory device and operating method thereof

The present disclosure relate a method of operating a semiconductor memory device including at least two memory blocks sharing one block word line. The method including applying an erase voltage to a source line commonly coupled to the memory blocks, one of which is a selected memory block and applying a first voltage to the block word line and a third voltage to a global word line of an unselected memory block of the memory blocks when the erase voltage is applied to the source line, wherein the first voltage is higher than a turn-on voltage to turn on a pass transistor coupled to the block word line, and wherein the third voltage floats a local word line included in the unselected memory block according to a level of the first voltage.. ... Sk Hynix Inc

Resistance change memory device and method of sensing the same

A method of sensing a resistance change memory device includes preparing a memory cell including a variable resistance element storing different data on the basis of a variable resistance, and a switching element connected to the variable resistance element and performing a threshold switching operation, measuring a first cell current by applying a first read voltage to the memory cell, the first read voltage being selected in a threshold-sensing range of a current-voltage characteristic curve of the memory cell, measuring a second cell current by applying a second read voltage to the memory cell, the second read voltage being selected in a resistance-sensing range of the current-voltage characteristic curve, and when at least one of the first cell current and the second cell current is greater than a corresponding reference current, outputting a data signal having a first logic value as data stored in the memory cell.. . ... Sk Hynix Inc

Semiconductor memory device and method for operating the same

A semiconductor memory device includes: a high frequency signal control unit for receiving an external command address signal, removing noise and glitch from the external command address signal and outputting a first command address signal; a pulse width control unit for controlling a pulse width of the first command address signal or maintaining the pulse width of the first command address signal and outputting a second command address signal with a predetermined pulse width; a refresh operation control unit for generating a row address for a refresh operation in response to the second command address signal; and a memory cell array for performing the a refresh operation in response to the row address.. . ... Sk Hynix Inc

Semiconductor memory device and operating method thereof

A semiconductor memory device including a weak cell storage circuit suitable for programming therein weak cell information, and outputting the weak cell information in an initialization operation; a cell array region including a first cell region which stores the weak cell information received from the weak cell storage circuit, in the initialization operation; a refresh address generation block suitable for generating a refresh address by counting a refresh signal, and outputting a weak cell address corresponding to the weak cell information outputted from the first cell region, as the refresh address, with a predetermined cycle; and a refresh circuit suitable for performing a refresh operation for a word line corresponding to the refresh address, among a plurality of word lines.. . ... Sk Hynix Inc

Semiconductor devices

A semiconductor device includes a first rank and a second rank. The first rank operates in synchronization with a clock signal in response to a first rank selection signal, and the second rank operates in synchronization with the clock signal in response to a second rank selection signal. ... Sk Hynix Inc

12/28/17 / #20170372759

Active control circuit, internal voltage generation circuit, memory apparatus and system using the same

A memory apparatus may include an active control circuit and an internal voltage generation circuit. The active signal generation circuit may enable an internal active signal after a level of a second external power supply voltage is stabilized even when a normal active signal is enabled. ... Sk Hynix Inc

12/28/17 / #20170371834

Memory system and method for accelerating boot time

A memory system includes a plurality of memory channels, each of the plurality of memory channels includes a plurality of memory dies and a die processor, each of the plurality of memory dies includes a plurality of memory blocks; and a memory controller including a monarch processor, coupled to the plurality of memory channels, wherein the die processor on each of the plurality of memory channels is configured in parallel to process to find last written data within at least a predetermined block of the plurality of memory dies; and provide information regarding the last written data to the monarch processor, the monarch processor determines which boot record to be used to identify firmware images based on the information.. . ... Sk Hynix Inc

12/28/17 / #20170371817

Interface circuit relating to variable delay, and semiconductor apparatus and system including the same

A semiconductor apparatus may include an interface circuit. The interface circuit may sense level variations of a first signal and a second signal. ... Sk Hynix Inc

12/28/17 / #20170371800

Memory system, and address mapping method and access method thereof

Provided is a method for mapping a logical address to a physical address, including: identifying whether a logical address is identical to a round value; mapping the logical address to a first physical address identical to an interval value when the logical address is identical to the round value; mapping the logical address to a second physical address corresponding to a value obtained by subtracting the round value from the logical address when the logical address is different from the round value; and adjusting a mapping value of the logical address to the second physical address to a value obtained by subtracting one from the second physical address when the second physical address is less than or equal to the interval value.. . ... Sk Hynix Inc

12/28/17 / #20170371746

Methods of correcting data errors and semiconductor devices used therein

A semiconductor device correcting data errors using a hamming code is provided. The hamming code is realized by an error check matrix, and the error check matrix includes a first sub- matrix and a second sub-matrix. ... Sk Hynix Inc

12/28/17 / #20170371745

Semiconductor device and semiconductor system

A semiconductor device may include an operation control circuit configured to generate a detection signal based on an internal temperature of the semiconductor device. The semiconductor device may include an error correction circuit configured to output read data as output data with or without performing an error correction operation and with or without performing a scrub operation based on the detection signal.. ... Sk Hynix Inc

12/28/17 / #20170371575

Memory system and method of operating the same

Provided herein are a memory system and method of operating the memory system, which have improved reliability. A method of operating a controller for controlling a semiconductor memory device including a plurality of memory blocks, the method comprising generating a program command and a program address for performing a program operation on at least one page included in an open block, among the plurality of memory blocks, reading data from the at least one page corresponding to the program address and transmitting the program command and the program address to the semiconductor memory device when the number of fail bits included in data read from the at least one page is equal to or less than a first reference value.. ... Sk Hynix Inc

12/28/17 / #20170371548

Memory system and operating method of memory system

A memory system may include: a memory system may include: a memory device suitable for storing user data and corresponding metadata; and a controller including a memory, the controller being suitable for storing user data and corresponding metadata in the memory and for controlling the memory device for storing therein the user data and the metadata of the memory when sizes of the user data and metadata of the memory reach first and second thresholds, respectively.. . ... Sk Hynix Inc

12/21/17 / #20170366169

Impedance calibration circuit

An impedance calibration circuit is disclosed, which relates to a technology for improving precision of pad resistance. The impedance calibration circuit includes: a first on die termination (odt) circuit selected by a first selection signal, configured to tune its own resistance using a first code signal, and output a first resistance value to an output terminal; and a second odt circuit selected by a second selection signal, configured to tune its own resistance using a second code signal, and output a second resistance value to the output terminal.. ... Sk Hynix Inc

12/21/17 / #20170366003

Device for protecting semiconductor circuit

A semiconductor circuit protection device for protecting an input/output circuit include an ultra-low electrostatic discharging block suitable for discharging ultra-low electrostatic charges before migrating to the input/output circuit.. . ... Sk Hynix Inc

12/21/17 / #20170365640

Switch and method for fabricating the same, and resistive memory cell and electronic device, including the same

A switch includes a first electrode layer, a second electrode layer disposed over the first electrode layer, and a selecting element layer interposed between the first electrode layer and the second electrode layer. The selecting element layer includes a gas region in which a current flows or does not flow according to a voltage applied to the switch. ... Sk Hynix Inc

12/21/17 / #20170365635

Image sensor including phase difference detectors

An image sensor may include a main photodiode formed in a substrate, a first inter-layer dielectric layer formed over a lower surface of the substrate, and phase difference detectors formed over the first inter-layer dielectric layer. The phase difference detectors include a left phase difference detector that is vertically overlapping and aligned with a left side region of the main photodiode, and a right phase difference detector that is vertically overlapping and aligned with a right side region of the main photodiode.. ... Sk Hynix Inc

12/21/17 / #20170365630

Image sensor having nano voids and method for fabricating the same

An image sensor includes a plurality of photodiodes formed in a substrate; nano void regions formed in the substrate adjacent to sides of each photodiode of the plurality of photodiodes; and a plurality of nano voids formed in each nano void region of the nano void regions.. . ... Sk Hynix Inc

12/21/17 / #20170365363

Rupture control device and semiconductor device to improve yield

A rupture control device may include an address control circuit configured to generate a rupture address in response to a first rupture command signal, a rupture mask signal and an external address, wherein the rupture address is generated according to whether the rupture mask signal is activated, and wherein an address and fuse data are compared, and a rupture mask signal indicating whether a fuse is ruptured is determined. Further, a fuse array configured to perform a rupture operation in response to the rupture address when a rupture enable signal is activated, and output the fuse data in response to a read enable signal.. ... Sk Hynix Inc

12/21/17 / #20170365312

Semiconductor integrated circuit

A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a ddr (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.. . ... Sk Hynix Inc

12/21/17 / #20170365311

Semiconductor device and semiconductor system

A semiconductor device may include a division control circuit and a latch circuit. The division control circuit may be configured to divide an external clock to generate a first preliminary divided clock and a second preliminary divided clock. ... Sk Hynix Inc

12/21/17 / #20170365307

Data storage device and operating method thereof

A method for operating a data storage device includes determining appropriateness of a first read bias for adjacent target threshold voltage distributions among threshold voltage distributions for a plurality of memory cells; and if it is determined that the first read bias is inappropriate, determining a second read bias.. . ... Sk Hynix Inc

12/21/17 / #20170365303

Methods, semiconductor devices, and semiconductor systems

A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.. ... Sk Hynix Inc

12/21/17 / #20170364445

System of multiple configurations and operating method thereof

A system and an operating method thereof include a system on chip (soc) flash controller having at least one soc channel; at least one memory device coupled with the at least one soc channel; a printed circuit board (pcb), wherein the soc flash controller and the at least one memory device are mounted thereon; a flash address translation (ftl) address translator automatically managing the at least one memory device in accordance with a pcb board configuration file of the pcb board and a drive configuration file of the at least one memory device; and a fuse storing an open data plane (odp) fuse setting generated in accordance with at least in part with data of the pcb board configuration file and the drive configuration file.. . ... Sk Hynix Inc

12/21/17 / #20170364306

Electronic device and method for fabricating the same

A method for fabricating an electronic device including a semiconductor memory includes: forming a memory layer over a substrate; forming a memory element by selectively etching the memory layer, wherein forming the memory element includes forming an etching residue on a sidewall of the memory element, the etching residue including a first metal; and forming a spacer by implanting oxygen and a second metal into the etching residue, the spacer including a compound of the first metal-oxygen-the second metal, the second metal being different from the first metal.. . ... Sk Hynix Inc

12/21/17 / #20170364286

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device; a control unit configured to generate a descriptor in which works for controlling the nonvolatile memory device are written; a memory control unit configured to provide control signals and write data to the nonvolatile memory device based on the descriptor; and a voltage detector configured to provide a voltage drop signal to the memory control unit in the case where a first operating voltage provided to the memory control unit or a second operating voltage provided to the nonvolatile memory device drops.. . ... Sk Hynix Inc

12/21/17 / #20170364108

Circuits for setting reference voltages and semiconductor devices including the same

A circuit for setting a reference voltage is provided. The circuit includes a reference voltage information storage unit and a reference voltage input/output (i/o) control unit. ... Sk Hynix Inc

12/14/17 / #20170359543

Circuit for reading-out voltage variation of floating diffusion area, method thereof and cmos image sensor using the same

A circuit for reading-out a voltage variation of a floating diffusion area includes a reference capacitor suitable for causing a voltage variation of the floating diffusion area based on a charge transfer signal and a read-out block including the floating diffusion area, and suitable for initializing the floating diffusion area, performing a read-out on an initial voltage of the floating diffusion area and performing a read-out on a varied voltage of the floating diffusion area caused by the reference capacitor.. . ... Sk Hynix Inc

12/14/17 / #20170359521

Pixel signal transfer device and method thereof and cmos image sensor including the same

A pixel signal transfer device includes a transfer block suitable for transferring a pixel output voltage according to an amount of a charge generated from a pixel; a correction block suitable for correcting the pixel output voltage using a threshold voltage of an amplification transistor; and a conversion gain adjusting block including the amplification transistor, the conversion gain adjusting block being suitable for adjusting a conversion gain of the corrected pixel output voltage outputted from the correction block.. . ... Sk Hynix Inc

12/14/17 / #20170359084

Semiconductor devices and semiconductor systems

A semiconductor system may be provided. The semiconductor system may include a first semiconductor device and a second semiconductor device. ... Sk Hynix Inc

12/14/17 / #20170358743

Resistive random access memory device

A resistive random access memory device is provided. The resistive random access memory device includes a first electrode, a second electrode, and an electrolyte layer disposed between the first electrode and the second electrode. ... Sk Hynix Inc

12/14/17 / #20170358739

Electronic device and method for fabricating the same

A method for fabricating an electronic device including a semiconductor memory includes: forming a variable resistance element including material layers over a substrate; forming a hard mask layer including a metal over the material layers; selectively etching the hard mask layer to form an etched hard mask layer; etching the material layers by using the etched hard mask layer as an etch barrier, the etching of the material layers providing an etch byproduct formed on sidewalls of the etched material layers and the etch byproduct including a material that is more readily oxidized than the metal of the hard mask layer; and performing a treatment using a gas or plasma to suppresses oxidation of the hard mask layer and facilitate oxidation of the etch byproducts.. . ... Sk Hynix Inc

12/14/17 / #20170358591

Semiconductor integrated circuit device relating to resistance characteristics and method of manufacturing the same

A semiconductor integrated circuit device may include a structure, a first capping layer, a channel layer and a second capping layer. The structure may have an opening formed in the structure. ... Sk Hynix Inc

12/14/17 / #20170358362

Semiconductor device and method of manufacturing the same

A semiconductor device may include an insulating layer, a bulk pattern, a stack structure, and a channel pattern. A first trench may be formed in the insulating layer. ... Sk Hynix Inc

12/14/17 / #20170358356

Semiconductor device and method of manufacturing the same

A semiconductor device may be provided. The semiconductor device may include a sub-channel layer located over a conductive layer. ... Sk Hynix Inc

12/14/17 / #20170358351

Memory apparatus and reference voltage setting method thereof

A memory apparatus includes a write driver, a sense amplifier and a reference voltage setting circuit. The write driver programs a set data or a reset data into a memory cell. ... Sk Hynix Inc

12/14/17 / #20170358350

Memory device, operation method of the same, and operation method of memory controller

A method for operating a memory device comprising a plurality of memory cells, the method may include: performing a first refresh operation comprising sequentially applying a recovery pulse to each of the plurality of memory cells and repeating the sequential application of the recovery pulse to each of the plurality of memory cells for a predetermined number of times; and performing a second refresh operation comprising sequentially re-writing data of each of the plurality of memory cells once after the first refresh operation is performed for the predetermined number of times.. . ... Sk Hynix Inc

12/14/17 / #20170358346

Read threshold optimization in flash memories

A memory device includes a plurality of memory blocks, each block with multiple memory cells. Each memory block has an address and a block read threshold. ... Sk Hynix Inc

12/14/17 / #20170358342

Semiconductor device having input/output line drive circuit and semiconductor system including the same

A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a command/address signal. ... Sk Hynix Inc

12/14/17 / #20170358341

Semiconductor device having input/output line drive circuit and semiconductor system including the same

A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a command/address signal. ... Sk Hynix Inc

12/14/17 / #20170358337

Comparison circuits and semiconductor devices employing the same

A comparison circuit may be provided. The comparison circuit may include a number of first logic circuits and a number of second logic circuits. ... Sk Hynix Inc

12/14/17 / #20170358335

Page buffer and memory device including the same

Provided herein are a page buffer and a memory device having the same. The page buffer may include: a latch circuit comprising a first node configured to be set to a first level in response to a sense amplifier strobe signal when an operation of setting up a bit line is performed during a program operation of a semiconductor memory device; a current control circuit configured to supply an internal power to a current sensing node depending on a value of the first level of the first node; and a page buffer sensing circuit configured to couple the bit line to the current sensing node in response to a page buffer sensing signal and control a potential level of the bit line depending on a potential level of the page buffer sensing signal.. ... Sk Hynix Inc

12/14/17 / #20170357466

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device; and a controller configured to generate a read command based on information on a memory region of the nonvolatile memory device corresponding to a read request and at least one memory region of the nonvolatile memory device corresponding to at least one stand-by read request, wherein the nonvolatile memory device simultaneously reads data stored in the memory region and data stored in the at least one memory region, in response to the read command.. . ... Sk Hynix Inc

12/14/17 / #20170357461

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device; and a controller suitable for controlling the nonvolatile memory device. The controller includes a status storage unit suitable for storing a status information on the nonvolatile memory device; and a reset unit suitable for selectively performing a reset operation for the nonvolatile memory device, based on the status information, when performing a booting operation.. ... Sk Hynix Inc

12/14/17 / #20170357458

Memory system and operating method thereof

A memory system may include: a memory device comprising a plurality of memory blocks, each memory block comprising a plurality of pages; a controller suitable for performing a command operation on the memory blocks, the command operation including checking one or more parameters of each of the memory blocks, selecting at least one source memory block from the memory blocks according to the checked one or more parameters, and storing data stored in the at least one source memory block in a target memory block among the memory blocks.. . ... Sk Hynix Inc

12/14/17 / #20170357447

Memory system and operation method thereof

An operation method for a memory system may include: an accessing a plurality of memory devices, each including a plurality of dies, in an interleaving manner, and performing program operations; and performing at least one internal read operation to read data from the plurality of dies accessed in the interleaving manner, during the program operations, wherein one or more internal read operations which are performed during any one program operation of the program operations are determined according to a maximum internal read operation number and a minimum internal read operation waiting number.. . ... Sk Hynix Inc

12/07/17 / #20170353677

Analog-digital converting device and method, and image sensor including the same

An analog-digital converting device includes a comparison block generating at least one first comparison signal by comparing pixel signals with each other, and for generating second comparison signals by comparing each of the plurality of pixel signals with a ramp signal through a single ramping operation; a feedback control unit determining a data conversion sequence according to the at least one first comparison signal received from the comparison block, and outputting a control signal according to the determined data conversion sequence; a selection block selecting two of the plurality of the pixel signals or at least one of the plurality of the pixel signals and the ramp signal to be applied to the comparison block according to the control signal received from the feedback control unit; and a data conversion unit performing a data conversion on the plurality of pixel signals based on the second comparison signal.. . ... Sk Hynix Inc

12/07/17 / #20170352807

Method of fabricating switching element and method of manufacturing resistive memory device

A method of manufacturing a switching element includes forming a first electrode layer over a substrate, forming a switching structure on the first electrode layer, and forming a second electrode layer on the switching structure. The switching structure includes a plurality of unit switching layers that includes a first unit switching layer and a second unit switching layer. ... Sk Hynix Inc

12/07/17 / #20170352805

Electronic device and method for fabricating the same

An electronic device including a semiconductor memory is provided. The semiconductor memory includes an interlayer dielectric layer disposed over a substrate, and having a recess which exposes a portion of the substrate; a bottom contact partially filling the recess; and a resistance variable element including a bottom layer which fills at least a remaining space of the recess over the bottom contact, and a remaining layer which is disposed over the bottom layer and protrudes out of the interlayer dielectric layer.. ... Sk Hynix Inc

12/07/17 / #20170352683

Semiconductor device with high integration

The present disclosure may provide a semiconductor device having a stable structure and a low manufacturing degree of the difficulty. The device may include conductive layers and insulating layers which are alternately stacked; a plurality of pillars passing through the conductive layers and the insulating layers; and a plurality of deposit inhibiting patterns, each deposit inhibiting pattern being formed along a portion of an interface between a side-wall of each of the pillars and each of the conductive layers and along a portion of an interface between each of the insulating layers and each of the conductive layers.. ... Sk Hynix Inc

12/07/17 / #20170352682

Semiconductor device with high integration

The present disclosure may provide a semiconductor device having a stable structure and a low manufacturing degree of the difficulty. The device may include conductive layers and insulating layers which are alternately stacked; a plurality of pillars passing through the conductive layers and the insulating layers; and a plurality of deposit inhibiting patterns, each deposit inhibiting pattern being formed along a portion of an interface between a side-wall of each of the pillars and each of the conductive layers and along a portion of an interface between each of the insulating layers and each of the conductive layers.. ... Sk Hynix Inc

12/07/17 / #20170352673

Semiconductor device and manufacturing method thereof

A semiconductor device includes a second channel layer in a first column and a second channel layer in a second column disposed biased to one side of a first channel layer in a first column and a first channel layer in a second column, respectively. The one side of the first channel layer in the first column and the one side of the first channel layer in the second column face directions opposite to each other.. ... Sk Hynix Inc

12/07/17 / #20170352667

Pattern forming method and semiconductor device manufacturing method using the same

A method for forming patterns includes forming an etch target layer; etching the etch target layer to form a pre-pattern having a line forming portion and a plurality of pad portions; forming a plurality of spacers which extend across the pad portions and the line forming portion; forming, over the spacers, a blocking layer having an opening which blocks the pad portions and exposes the line forming portion; and etching the line forming portion by using the blocking layer and the spacers as a barrier, to form a plurality of line portions.. . ... Sk Hynix Inc

12/07/17 / #20170352642

Apparatus for bonding a semiconductor chip and method of forming a semiconductor device

An apparatus for bonding a semiconductor chip to a package substrate, the apparatus comprising: a die-bonding unit configured to attach the semiconductor chip to the package substrate; a load-measuring unit installed at the die-bonding unit, the load-measuring unit including a panel having a plurality of regions and a plurality of load-measuring members with at least one load-measuring member arranged in each of the regions of the panel to measure load values applied to each of the regions; and a controller configured to determine a load and a flatness of the semiconductor chip based on the load values measured by the load-measuring members.. . ... Sk Hynix Inc

12/07/17 / #20170352612

Semiconductor packages including heat spreaders and methods of manufacturing the same

There may be provided a method of manufacturing a semiconductor package. The method may include disposing a first semiconductor device and through mold ball connectors (tmbcs) on a first surface of an interconnection structure layer, forming a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the tmbcs, attaching outer connectors to the exposed portions of the tmbcs, mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer, and attaching a heat spreader to the second surface of the interconnection structure layer to overlap with a portion of the first semiconductor device.. ... Sk Hynix Inc

12/07/17 / #20170352552

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device may include forming a first stack structure by alternately stacking first material layers and second material layers, forming first holes penetrating the first stack structure and a first slit located between the first holes, forming channel patterns in the first holes and a dummy channel pattern in the first slit, selectively removing the dummy channel pattern from the first slit, and replacing the first material layers with third material layers through the first slit.. . ... Sk Hynix Inc

12/07/17 / #20170352405

Semiconductor device and semiconductor system

A semiconductor system includes a semiconductor device suitable for not performing an internal refresh operation when entering a self-refresh mode in response to a self-refresh command, and cutting off input of an auto-refresh command when exiting the self-refresh mode.. . ... Sk Hynix Inc

12/07/17 / #20170352404

Refresh control device, and memory device including the same

A refresh control device, and a memory device may be provided. The latch controller may include a first oscillator configured to generate a first oscillation signal, and a second oscillator configured to generate a second oscillation signal. ... Sk Hynix Inc

12/07/17 / #20170352400

Semiconductor memory device and refresh method of semiconductor memory device

A semiconductor memory device may include a row address generating circuit, a row active pulse generating circuit and a word line activating circuit. The row address generating circuit may generate a row address in response to a refresh command, a row active pulse, and a normal address. ... Sk Hynix Inc

12/07/17 / #20170351460

Memory apparatus relating to on die termination

A memory apparatus may include a plurality of ranks commonly coupled to an input/output (i/o) terminal. Non-target ranks other than a target rank among the plurality of ranks may be configured to perform an on die termination operation based on a read operation of the target rank.. ... Sk Hynix Inc

12/07/17 / #20170351449

Memory system

A memory system includes a memory apparatus including a write driver and a memory controller configured to control the memory apparatuses. The memory controller includes a command comparison circuit configured to compare word line addresses, bit line addresses, and pieces of write data of a first write command and a second write command and output a simultaneous write control signal having a first level when the bit line addresses and the pieces of write data are the same as each other and most significant bits (msbs) of the word line addresses are different from each other and a processor configured to transfer a simultaneous write command for simultaneously operating the first write command and the second write command to the memory apparatus when the simultaneous write control signal having the first level is output from the command comparison circuit.. ... Sk Hynix Inc

12/07/17 / #20170351290

Reference voltage generation circuit and method for driving the same

A reference voltage generation circuit includes a loading block suitable for generating a reference current and first and second mirroring currents obtained by mirroring the reference current based on a power source voltage, a biasing block suitable for generating a first bias voltage controlled corresponding to variations in the power source voltage and a second bias voltage controlled corresponding to variations in temperature based on the first mirroring current, a compensation block suitable for compensating for the reference current based on the first and second bias voltages, and an output load block suitable for generating a reference voltage which corresponds to the reference current based on the second mirroring current.. . ... Sk Hynix Inc

11/30/17 / #20170347048

Amplification circuit

An amplification circuit includes a first amplification block suitable for primarily amplifying a voltage difference between a first voltage and a second voltage corresponding to a first input current and a second input current, respectively, and a second amplification block suitable for secondarily amplifying the voltage difference between the first and second voltages to generate an amplification signal.. . ... Sk Hynix Inc

11/30/17 / #20170345861

Wafer level curved image sensors and method of fabricating the same

A wafer level curved image sensor may include a substrate having a central region, a peripheral region, and an edge region, the peripheral region being formed between the central region and the edge region, supporting patterns formed over the substrate, first fixed patterns formed between the supporting patterns, and an image sensing chip formed over the supporting patterns. The supporting patterns and the first fixed patterns, in combination, form a planar lower surface and a concavely-curved upper surface. ... Sk Hynix Inc

11/30/17 / #20170345854

Three-layer stacked image sensor

An image sensor may include a lower device that includes logic transistors, an intermediate device that is formed over the lower device and includes a correlated double sampling (cds) circuit and a capacitor, and an upper device that is formed over the intermediate device and includes a photodiode, a floating diffusion region, and a transfer gate electrode.. . ... Sk Hynix Inc

11/30/17 / #20170345844

Semiconductor device and method of manufacturing the same

Provided herein is a semiconductor device including n stacked groups (where n is a natural number greater than or equal to two) sequentially stacked over a substrate, each stacked group including interlayer insulating films and conductive patterns alternately stacked, and n concave portions each having stepped sidewalls formed in the interlayer insulating films and the conductive patterns of the stacked groups, the n concave portions each having stepped sidewalls being aligned in a first direction.. . ... Sk Hynix Inc

11/30/17 / #20170345839

Semiconductor device and manufacturing method thereof

A semiconductor device includes channel layers arranged in a first direction and a second direction intersecting the first direction; stacked insulating layers surrounding sidewalls of the channel layers; stacked gate electrodes interposed between the insulating layers, the gate electrodes respectively surrounding the channel layers; and stacked gate lines interposed between the insulating layers, the gate lines electrically connecting the gate electrodes to each other.. . ... Sk Hynix Inc

11/30/17 / #20170345823

Electronic device and method for fabricating the same

An electronic device includes a semiconductor memory. The semiconductor memory may include a semiconductor substrate having an isolation trench in a first region and a capacitor trench in a second region, an isolation layer filling the isolation trench, an insulation layer pattern disposed along the capacitor trench, and a conductive layer pattern filling the capacitor trench over the insulation layer pattern. ... Sk Hynix Inc

11/30/17 / #20170345751

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first line pattern and a second line pattern formed in parallel on a semiconductor substrate, third line patterns formed in parallel between the first line pattern and the second line pattern, fourth line patterns formed in parallel between the first line pattern and the second line pattern, a first connection structure configured to couple a first of the third line patterns with a first of the fourth lines patterns, which are adjacent to the first line pattern, and a second connection structure configured to couple a second of the first lines patterns with a second of the fourth lines patterns, which are adjacent to the second line pattern.. . ... Sk Hynix Inc

11/30/17 / #20170345474

Transmission circuit, and semiconductor apparatus and system using the same

A transmission circuit may be provided. The transmission circuit may include a strobe control circuit and an output driver. ... Sk Hynix Inc

11/30/17 / #20170345471

Semiconductor integrated circuit

A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a ddr (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.. . ... Sk Hynix Inc

11/30/17 / #20170345466

Resistance variable memory apparatus and operating method thereof

A resistance variable memory apparatus may include a memory cell array and a controller. The memory cell array may include a plurality of resistance variable memory cells. ... Sk Hynix Inc

11/30/17 / #20170344476

Electronic device and method for fabricating the same

An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.. . ... Sk Hynix Inc

11/30/17 / #20170344422

Semiconductor devices and semiconductor systems

A semiconductor device may be provided. The semiconductor device may include an error correction circuit and a verification operation control circuit. ... Sk Hynix Inc

11/30/17 / #20170344278

Memory controllers, memory systems, and methods relating to wear-leveling

A memory controller may be provided. The memory controller may include a wear-leveler may be configured to determine whether execution of a swapping operation is required based on reception of a write command for a stack region.. ... Sk Hynix Inc

11/30/17 / #20170344263

Memory system and operating method thereof

A memory system includes: a memory device comprising a plurality of dies each die comprising a plurality of planes, each plane comprising a plurality of blocks, each block comprising a plurality of pages; a controller suitable for inputting a plurality of commands received from a host to the memory device through command queuing, wherein a first memory die among the plurality of memory dies processes the plurality of commands as a burst command, and performs command operations in one or more pages in one or more first memory blocks included in the first memory die, and data corresponding to the command operations are stored in a plurality of latches corresponding to the one or more first memory blocks.. . ... Sk Hynix Inc

11/30/17 / #20170344262

Data processing system and method for operating the same

A data processing system includes: a host suitable for processing a plurality of tasks in parallel through a plurality of processors included therein, detecting write tasks that generate write data among the plurality of the tasks, and generating write process data which represent which one of the processors processes the respective write tasks; and a memory system suitable for storing the write data, which are processed by same one of the processors, into a plurality of memory devices thereof according to an interleaving scheme. The memory system determines based on the write process data whether the write data are processed by the same processor.. ... Sk Hynix Inc

11/30/17 / #20170344260

Electronic device and operating method thereof

An electronic device includes a first memory suitable for storing a plurality of segment codes each associated with at least one operation; a second memory; and a processor suitable for loading a first segment code among the plurality of segment codes from the first memory to the second memory, and performing an operation associated with the first segment code by executing the first segment code loaded into the second memory.. . ... Sk Hynix Inc

11/23/17 / #20170339359

Analog-to-digital converter and operating method thereof

An analog-to-digital conversion method may include: generating an initial comparison signal by comparing a pixel signal of a comparison column to a pixel signal of an adjacent column; generating a control signal for selecting a ramp signal according to the generated initial comparison signal; and performing data conversion by comparing the ramp signal selected according to the generated control signal to a difference between adjacent first and second pixel signals.. . ... Sk Hynix Inc

11/23/17 / #20170339356

Image sensing device and method for driving the same

An image sensing device includes: a pixel array suitable for generating a plurality of pixel signals corresponding to incident light; a comparison block suitable for comparing the pixel signals with a ramp signal to generate a plurality of comparison signals; a logic block suitable for adjusting slew rates of the respective comparison signals to generate a plurality of logic signals; a global count block suitable for generating a global count signal; and a storing block suitable for storing counted values of the global count signal based on the logic signals received from the logic block.. . ... Sk Hynix Inc

11/23/17 / #20170338409

Switching element, resistive memory device including switching element, and methods of manufacturing the same

A method of manufacturing a switching element includes forming a pillar-shaped structure over a substrate, performing a dopant injection process to form a first doping region in an insulation layer. The method further includes performing the dopant injection process to form a second doping region in a first electrode, to form a third doping region in a second electrode, or both. ... Sk Hynix Inc

11/23/17 / #20170338317

Semiconductor device having air gap and method for manufacturing the same, memory cell having the same and electronic device having the same

A semiconductor device including a semiconductor substrate including a plurality of active regions and a device isolation region for isolating the plurality of active regions; and a buried bit line and a buried gate electrode which are formed in the semiconductor substrate. The device isolation region includes a first device isolation region extending in a first direction and a second device isolation region extending in a second direction crossing with the first direction and having a shield pillar formed therein.. ... Sk Hynix Inc

11/23/17 / #20170338264

Image sensor

An image sensor may include a photoelectric conversion element, a transfer transistor formed over the photoelectric conversion element, and a reset transistor formed over the photoelectric conversion element, formed substantially at the same level as the transfer transistor, and spaced apart from the transfer transistor by a gap, wherein the transfer transistor and the reset transistor are configured symmetrical to each other with respect to the gap.. . ... Sk Hynix Inc

11/23/17 / #20170338241

Semiconductor device and manufacturing method thereof

A semiconductor device includes a first structure, a dummy buffer stack structure, a peripheral contact hole, and a peripheral contact plug. The first structure may include a substrate and a peripheral circuit disposed on the substrate. ... Sk Hynix Inc

11/23/17 / #20170338219

Semiconductor integrated circuit device including an electrostatic discharge protection circuit

A semiconductor integrated circuit device having a first clamping circuit, a second clamping circuit, a third clamping circuit, a first path-changing line and a second path-changing line. The first clamping circuit may be connected between an input/output pad and a power pad. ... Sk Hynix Inc

11/23/17 / #20170338205

Semiconductor packages including through mold ball connectors and methods of manufacturing the same

There is provided a structure and a method of manufacturing a semiconductor package. The method includes disposing a first semiconductor device and through mold ball connectors (tmbcs) on a first surface of an interconnection structure layer, recessing a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the tmbcs, attaching outer connectors to the exposed portions of the tmbcs, and mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.. ... Sk Hynix Inc

11/23/17 / #20170337986

Semiconductor memory device and weak cell detection method thereof

A semiconductor memory device includes: a plurality of memory blocks; a plurality of bit-line sense amplifiers shared by neighboring memory blocks among the plurality of the memory blocks, and suitable for sensing and amplifying data read from memory cells coupled to activated word lines through bit lines, and outputting the amplified data through a plurality of segment data lines; a word line driver suitable for activating word lines of memory blocks that do not share the bit-line sense amplifiers during a test mode; and a weak cell detection circuit suitable for compressing the amplified data transferred through the plurality of the segment data lines for generating compressed data and detecting a weak cell based on the compressed data during the test mode.. . ... Sk Hynix Inc

11/23/17 / #20170337975

Low voltage detection circuit, nonvolatile memory apparatus including the same, and operating method thereof

A low voltage detection circuit includes a first detection block configured to detect a level of an external voltage according to a reference voltage, and output a pre-detection signal; and a second detection block configured to generate a low voltage detection signal of a beginning level regardless of a variation in a level of the pre-detection signal when the level of the pre-detection signal is detected as the beginning level.. . ... Sk Hynix Inc

11/23/17 / #20170337973

Semiconductor memory device and operating method thereof

There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a peripheral circuit for performing a program operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit to perform the program operation. ... Sk Hynix Inc

11/23/17 / #20170337972

Memory system and operating method thereof

A memory system may include a memory device including a plurality of memory blocks each memory block including a plurality of pages; and a controller suitable for non-sequentially selecting some pages among a plurality of pages included in an open block among the plurality of blocks, checking a program state or an erase state of each of the selected pages, and searching for a boundary page between the program state pages and the erase state pages among the plurality of pages.. . ... Sk Hynix Inc

11/23/17 / #20170337970

Electrically programmable read only memory devices having uniform program characteristic and methods of progamming the same

An eprom device includes bit lines branching from a supply voltage line, a first group of enablement signal lines intersecting the bit lines, unit cells respectively located at cross points of the bit lines and the first group of enablement signal lines, pass transistors, load transistors, comparators, and enablement signal generators. One of the pass transistors and one of the load transistors are coupled in series between the supply voltage line and each of the bit lines. ... Sk Hynix Inc

11/23/17 / #20170337961

Electronic device

An electronic device may include a semiconductor memory. The semiconductor memory may include a global line pair including a global bit line and a global source line; a plurality of cell matrices coupled between the global bit line and the global source line, each cell matrix including a plurality of local line pairs and a plurality of storage cells that are coupled to the plurality of local line pairs, wherein each storage cell is operable to store data and is coupled between local lines of a corresponding local line pair; and a plurality of isolation switch pairs that couple the plurality of cell matrices to the global bit line and the global source line of the global line pair, one isolation switch pair per cell matrix.. ... Sk Hynix Inc

11/23/17 / #20170337956

Nonvolatile memory device, semiconductor device, and method for operating semiconductor device

A nonvolatile memory device may include a plurality of cell strings including a plurality of memory cells serially coupled to one another; a plurality of bit lines coupled to a corresponding cell string of the plurality of cell strings; a plurality of page buffers each including a plurality of latches and coupled to a corresponding bit line of the plurality of bit lines; a first control circuit suitable for controlling the plurality of latches to perform an operation corresponding to an activated command signal of a plurality of command signals in an access operation; and a second control circuit suitable for activating one or more of the plurality of command signals, while controlling operations of the plurality of cell strings and the plurality of bit lines in the access operation.. . ... Sk Hynix Inc

11/23/17 / #20170337950

Semiconductor memory apparatus and operating method

A semiconductor memory apparatus, including a first mat which includes a first bit line and a first word line and a second mat which includes a second bit line and a second word line, includes a first bit line driving circuit configured to enable the first bit line in response to a first bit line select signal and a first machine bit line select signal; a second bit line driving circuit configured to enable the second bit line in response to a second bit line select signal and a second machine bit line select signal; a column-related decoding circuit configured to selectively enable the first and second bit line select signals in response to a column address; and a state machine configured to selectively enable the first and second machine bit line select signals in response to the column address.. . ... Sk Hynix Inc

11/23/17 / #20170337130

Memory device including page buffer and method of arranging page buffer

A memory device includes a memory cell array, a plurality of bit lines, and a plurality of page buffers including a plurality of cache latches, exchanging data with the memory cell array through the plurality of bit lines, wherein the plurality of cache latches are arranged in a column direction in parallel with the plurality of bit lines and a row direction perpendicular to the plurality of bit lines, and have a two-dimensional arrangement of m stages in the column direction, where m is a positive integer not corresponding to 2l and l is zero or a natural number.. . ... Sk Hynix Inc

11/23/17 / #20170337105

Semiconductor devices

A semiconductor device may include a data storage region, a parity storage region and an error correction circuit. The data storage region may be configured to store first data and second data. ... Sk Hynix Inc

11/23/17 / #20170337001

Memory system and operating method of memory system

A memory system includes: a memory device including a plurality of memory blocks; and a controller including a memory, the controller being suitable for: selecting a source memory block and a target memory block among the plurality of memory blocks; loading map segments of map data for the source memory block on the memory; determining valid pages, among a plurality of pages included in the source memory block, through the map segments; loading valid data stored in the valid pages on the memory; updating map data for the valid data; and storing the valid data and the updated map data in a plurality of pages included in the target memory block.. . ... Sk Hynix Inc

11/23/17 / #20170336985

Memory system and write and read operation method for the same

A method for operating a memory system includes detecting a size of a data requested by a host, generating a first data that represents the size of the requested data and a second data that represents a remaining empty space other than a space for the requested data in a first region having a unit size of data storage in a memory device when the size of the requested data is smaller than the first region and the request is to write the requested data into the memory device, and storing the first data and the second data in the memory device along with the requested data.. . ... Sk Hynix Inc

11/23/17 / #20170336974

Self error-handling flash memory device

A flash memory device includes a flash memory configured to store a plurality of pages and a control circuit coupled to the flash memory. The control circuit is configured to retrieve data from a page of the flash memory, determine a number of zeroes or ones of the retrieved data, determine whether the number is between a first value and a second value, and determine that the retrieved data has one or more errors based on determining that the number is not between the first value and the second value.. ... Sk Hynix Inc

11/23/17 / #20170336471

Semiconductor devices

A semiconductor device may include an inversion control signal generation circuit, a pattern control signal generation circuit, and a data input/output (i/o) circuit. The inversion control signal generation circuit may generate an inversion control signal according to a logic level combination of bit patterns included in at least one of a first address and a second address. ... Sk Hynix Inc

11/16/17 / #20170331500

System and method for parallel decoding of codewords sharing common data

A memory device can include a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform parallel decoding of codewords. ... Sk Hynix Inc

11/16/17 / #20170331462

Buffer, and multiphase clock generator, semiconductor apparatus and system using the same

A buffer includes an amplification circuit, an amplification current generation circuit, and a latch. The amplification circuit may change voltage levels of a first output node and a second output node based on a clock signal and a pair of input signals. ... Sk Hynix Inc

11/16/17 / #20170330907

Image sensor

An image sensor may include: a substrate including a photoelectric conversion element; a first interlayer dielectric layer formed over the photoelectric conversion element; a channel layer including a first region and a second region, the first region being formed in an opening passing through the first interlayer dielectric layer, with a portion of the first region contacting the photoelectric conversion element, and the second region being formed over the first interlayer dielectric layer; a transfer transistor formed over the first region of the channel layer, the transfer transistor including a transfer gate which gapfills the opening; and a reset transistor including a reset gate formed over the second region of the channel layer.. . ... Sk Hynix Inc

11/16/17 / #20170330886

Semiconductor device and voltage transfer unit

A semiconductor device may include a first active region including a first main region and a first protruding part. The semiconductor device may include a second active region including a second main region and a second protruding part. ... Sk Hynix Inc

11/16/17 / #20170330752

Method of manufacturing memory device

Provided herein is a method of manufacturing a memory device. The method of manufacturing the memory device includes: forming a compensation layer over the channel layer, wherein an incubation time used for a nucleation of the compensation layer is shorter than an incubation time of the channel layer; and performing a heat treatment process for crystallizing the channel layer.. ... Sk Hynix Inc

11/16/17 / #20170330634

Test mode circuit with serialized i/o and semiconductor memory device including the same

A semiconductor system may include a controller and a semiconductor device. The controller may output command/address signals. ... Sk Hynix Inc

11/16/17 / #20170330628

Nonvolatile memory device including sub common sources

A nonvolatile memory device includes a memory block including a plurality of cell strings each of which includes memory cells electrically coupled with word lines stacked over a substrate; a plurality of sub common sources electrically coupled to one ends of the cell strings; and a plurality of bit lines electrically coupled to the other ends of the cell strings, wherein the memory block includes sub blocks respectively corresponding to the sub common sources, and cell strings electrically coupled to the same bit line among the cell strings are included in the same sub block.. . ... Sk Hynix Inc

11/16/17 / #20170330625

Block decoder and semiconductor memory device having the same

There are provided a block decoder including a control signal generating circuit suitable for generating a control signal in response to address signals, a potential level switch circuit suitable for outputting an internal voltage having an internal power potential level or a negative potential level in response to the control signal, and a voltage apply circuit suitable for outputting a block selecting signal having a high potential level higher than the internal power potential level in response to the control signal and the internal voltage having the internal power potential level, or outputting the internal voltage having the negative potential level as the block selecting signal in response to the control signal.. . ... Sk Hynix Inc

11/16/17 / #20170330607

Memory system having optimal threshold voltage and operating method thereof

A semiconductor memory system and an operating method thereof include a memory device; and a memory controller including a sequence generator, a sequence analyzer, and a processor coupled to the memory device and containing instructions executed by the processor, and configured to generate a sequence by the sequence generator, wherein the sequence comprises a sequence of digital data, write the sequence associated with a user data to the memory device, read out a read data including the sequence and the associated user data, analyze the sequence to understand characters of the read data and create analysis result by the sequence analyzer, identify an optimal threshold voltage in accordance with the analysis result, and provide the optimal threshold voltage to an ecc engine.. . ... Sk Hynix Inc

11/16/17 / #20170330606

Three-dimensional semiconductor device with top dummy cells, bottom dummy cells and operating method thereof

Provided is a semiconductor device and an operating method thereof. The operating method of the semiconductor device includes performing a soft program operation on a top dummy cell and a bottom dummy cell, among dummy cells stacked in a vertical direction, by applying a first soft program voltage to a bottom dummy word line coupled to the bottom dummy cell and a second soft program voltage greater than the first soft program voltage to a top dummy word line coupled to the top dummy cell formed above the bottom dummy cell.. ... Sk Hynix Inc

11/16/17 / #20170329726

Memory system and operation method of the same

A memory system includes: a plurality of memory devices, one of which includes an unrepaired defective memory cell; a control bus that is shared by the plurality of the memory devices; a plurality of data buses assigned to each of the plurality of the memory devices; and a memory controller that communicates with the plurality of the memory devices through the control bus and the plurality of the data buses, a control latency of the memory device including unrepaired defective memory cells is set differently from a control latency of the other memory devices, where the control latency is used for recognizing control signals of the control bus.. . ... Sk Hynix Inc

11/16/17 / #20170329716

Mapped region table

Techniques and systems for first determining if a non-volatile memory configured to store physical data pages is being initialized, and a volatile memory configured to store (a) plurality of physical data page addresses, each physical data page address corresponding to a physical data page and accessed via a corresponding logical address (b) first bitmap including plurality of first set of bits with each bit configured to indicate a validity state of a different first plurality of logical addresses, and (c) a second bitmap including a plurality of second set of bits, each bit in second set of bits configured to indicate a validity state of (i) different second plurality of logical addresses, and (ii) different first set of bits in first bitmap; accessing second bitmap based on first determining; and second determining of invalid state of at least one of selected logical address(es) based on a bit in second bitmap.. . ... Sk Hynix Inc

11/16/17 / #20170329709

Memory system having multiple cache pages and operating method thereof

A semiconductor memory system and an operating method thereof include a controller; and a memory device including a memory page manager, nand pages, and multiple cache pages, wherein the nand pages include current nand pages and next nand pages, wherein the current nand pages is corresponding to a read command received from the controller, the memory page manager is configured to manage correlation of the nand pages and the multiple cache pages, predict next nand pages in accordance at least in part with the read command, the current nand pages, or a combination thereof, and send the nand pages to the controller, and the multiple cache pages contain pages loaded from the nand pages.. . ... Sk Hynix Inc

11/16/17 / #20170329703

Self-management memory system and operating method thereof

A semiconductor memory system and an operating method thereof include a controller configured to perform macro management; and a memory device including nand pages, counters, a self-management component, and devoted memories, wherein the memory device is coupled and controlled by the controller, the nand pages contains data corresponding to commands received from the controller, the counters are configured to track operation information corresponding to the nand pages in accordance with the commands, the devoted memories are configured to record recovery information, and the self-management component configured to perform micro management in accordance at least in part with the operation information or the recovery information.. . ... Sk Hynix Inc

11/16/17 / #20170329547

Bank interleaving controller and semiconductor device including the same

A bank interleaving controller may include a power calculator and a write driver. The power calculator may calculate a total power consumption by adding a power consumption of one or more memory banks that are performing write operations and an amount of power that is expected to be additionally consumed to write input data. ... Sk Hynix Inc

11/16/17 / #20170329540

Semiconductor device and semiconductor system

A semiconductor device, semiconductor system, and or method relating to a refresh operation may be provided. The semiconductor device may include an operation control signal generation circuit configured for generating an operation control signal for a target word line. ... Sk Hynix Inc

11/16/17 / #20170329518

Electronic devices having semiconductor memory with interface enhancement layer

This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an interface enhancement layer interposed between the tunnel barrier layer and the pinned layer, wherein the interface enhancement layer may include an fe-rich first layer; a co-rich second layer formed over the first layer; and a metal layer formed over the second layer.. ... Sk Hynix Inc

11/16/17 / #20170329389

Memory module, system including the same

In an embodiment of the present disclosure, a memory module may be provided. In an embodiment of the present disclosure, a system may be provided. ... Sk Hynix Inc

11/09/17 / #20170324593

Equalization circuit, semiconductor apparatus and semiconductor system using the same

An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. ... Sk Hynix Inc

11/09/17 / #20170324592

Equalization circuit, semiconductor apparatus and semiconductor system using the same

An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. ... Sk Hynix Inc

11/09/17 / #20170324540

Serializer, and semiconductor apparatus and system including the same

A serializer may be provided. The serializer may include a first data output circuit and a second data output circuit. ... Sk Hynix Inc

11/09/17 / #20170323899

3d semiconductor memory device and manufacturing method thereof

Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer.. . ... Sk Hynix Inc

11/09/17 / #20170323898

Semiconductor memory device including 3-dimensional structure and method for manufacturing the same

A semiconductor memory device includes a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.. . ... Sk Hynix Inc

11/09/17 / #20170323897

Manufacturing method of semiconductor device

A semiconductor device includes a substrate having a memory array region and a peripheral region, isolation layers formed in the peripheral region to define an active region, offset insulating layers separated from each other and formed in the active region, and a gate electrode having edges overlapping with the offset insulating layers and arranged in the active region between the offset insulating layers.. . ... Sk Hynix Inc

11/09/17 / #20170323685

Semiconductor memory device

Provided herein is a semiconductor memory device. The semiconductor memory device may include: a memory cell array including a plurality of pages; a voltage supply unit configured to provide operating voltages to the plurality of pages; a plurality of page buffers coupled to a plurality of bit lines of the memory cell array and configured to control and sense currents flowing through the plurality of bit lines in response to a page buffer sensing signal; and a control logic configured to control the voltage supply unit and the plurality of page buffers such that the plurality of pages are successively programmed, and to control a potential level of the page buffer sensing signal depending on a program sequence of the plurality of pages during a program verify operation of a program operation.. ... Sk Hynix Inc

11/09/17 / #20170323678

Data output circuit and semiconductor memory device including the same

A data output circuit includes: a first data latch unit enabled in response to a first bank selection signal including clock information, for storing first lower bank data and first upper bank data in response to a first input control signal, and outputting lower preliminary output data and upper preliminary output data in response to an output control signal; a second data latch unit enabled in response to a second bank selection signal including clock information, for storing second lower bank data and second upper bank data in response to a second input control signal, and outputting the lower preliminary output data and the upper preliminary output data in response to the output control signal; and a data output unit for driving the lower preliminary output data to send rising output data, and synchronizing the upper preliminary output data with the clock to send falling output data.. . ... Sk Hynix Inc

11/09/17 / #20170323674

Data input/output circuit and semiconductor memory device having the same

Provided herein are a data input/output circuit and a semiconductor memory system having the same. The data input/output circuit may be coupled to an input/output line. ... Sk Hynix Inc

11/09/17 / #20170323671

Control circuit and memory device having the same

In an embodiment, a control circuit may include a command interface, a clock selection signal output circuit, and a clock generating circuit. The command interface may output a selection enable signal in response to a command. ... Sk Hynix Inc

11/09/17 / #20170322849

Memory system and operating method thereof

A memory system may include a memory device including a plurality of pages which include a plurality of memory cells coupled with a plurality of word lines and are stored with data, a plurality of memory blocks in which the pages are included, a plurality of planes which include the memory blocks, and a plurality of memory dies in which the planes are included; and a controller suitable for performing a program operation corresponding to a write command received from a host, at a first point of time, for first memory blocks among the memory blocks, checking program information for the program operation at the first point of time, predicting erase information on the memory blocks in correspondence to the program information, performing an erase operation for second memory blocks among the memory blocks, at a second point of time after the first point of time, in correspondence to the erase information, and performing the program operation for the second memory blocks at a third point of time after the second point of time.. . ... Sk Hynix Inc

11/09/17 / #20170322741

Memory system and operating method thereof

A memory system may include: a memory device comprising: a plurality of pages each having a plurality of memory cells coupled to a plurality of word lines and suitable for storing data; a plurality of memory blocks each having the pages; a plurality of planes each having the memory blocks; and a plurality of memory dies each having the planes, and a controller suitable for transmitting a request command for acquiring setting information on the memory device to the memory device, receiving an acknowledgement signal corresponding to the request command from the memory device, acquiring the setting information through the acknowledgement signal, and checking the setting information to perform a command operation based on a command received from a host on the memory device.. . ... Sk Hynix Inc

11/09/17 / #20170322738

Data processing system and operating method thereof

A data processing system may include: a plurality of memory systems each comprising a memory device and a controller for the memory device; and a host system suitable for performing processes corresponding to workloads which are processed in the plurality of memory systems, wherein at a first time, the host system performs a first process corresponding to a first workload among the workloads and transmits a command corresponding to the first workload to the memory systems, and at a second time, the host system receives an acknowledgement signal of the command from the memory systems, checks an end time of a command operation corresponding to the command through the acknowledgement signal, and prepares the first process in advance according to the end time.. . ... Sk Hynix Inc

11/09/17 / #20170322731

Memory system and operating method thereof

A memory system includes a memory device including a plurality of memory blocks; and a controller suitable for; storing user data corresponding to a write command received from a host, in the memory blocks, storing map data in response to storing of the user data, in the memory blocks, sorting map segments included in the map data, according to logical information of the user data, determining correlations for the memory blocks, through the map segments, and selecting source memory blocks among the memory blocks based on the determined correlations.. . ... Sk Hynix Inc

11/09/17 / #20170322728

Grouped trim bitmap

Techniques and systems are provided for tracking commands. Such methods and systems can include receiving a data access request in a controller coupled to (a) a non-volatile memory configured to store a set of physical data pages, and (b) a volatile memory configured to store a plurality of physical data page addresses, wherein each physical data page address corresponding to a physical data page in the set of physical data pages, and each physical data page address is accessed via a corresponding logical address in a set of logical addresses; accessing, by the controller based on the received data access request, a bitmap stored on the volatile memory, the bitmap including a set of bits, each bit configured to indicate a validity state of a different plurality of logical addresses in a set of logical addresses; and determining, via the controller, an invalid state of at least one of a selected (a) logical address, or (b) plurality of logical addresses, based on a bit in the bitmap.. ... Sk Hynix Inc

10/26/17 / #20170310859

Image sensor having outer and inner address markers

Provided is an image sensor having a pixel region including a plurality of pixel blocks disposed in a matrix form, outer address markers around the pixel region, interspaces between the plurality of pixel blocks, and inner address markers disposed in the interspaces.. . ... Sk Hynix Inc

10/26/17 / #20170310342

Early selection decoding and automatic tuning

Techniques are described for codeword decoding. In an example, a system computes a checksum for a codeword based on the codeword and a parity check matrix. ... Sk Hynix Inc

10/26/17 / #20170310341

Efficient data path architecture for flash devices

Efficient data path architecture for flash devices requiring multi-pass programming utilizes an external memory as an intermediate buffer to store the encoded data used for a first pass programming of the flash device. The stored encoded data can be read from the external memory for subsequent passes programming instead of fetching the data from an on-chip memory, which stores the data received from a host system. ... Sk Hynix Inc

10/26/17 / #20170310316

Efficient digital duty cycle adjusters

The embodiments of the present invention provide an apparatus of an efficient digital duty cycle adjuster and the method of operation thereof. The method includes: providing an input clock having an input clock duty cycle; inserting at least one programmable delay of a programmable delay line to the input clock, the input clock has a first delay inserted for a delayed rise edge, and a second delay inserted for a delayed fall edge, wherein the first delay, the second delay, or the combination thereof, includes the programmable delay; and adjusting an output clock duty cycle of an output clock by configuring the programmable delay, the output clock is generated by a selecting circuit, the selecting circuit includes a select signal, and the select signal is determined in accordance with the first delay and the second delay.. ... Sk Hynix Inc

10/26/17 / #20170309815

Electronic device and method for fabricating the same

An electronic device includes a semiconductor memory that includes: a first conductive pattern disposed over a substrate; a first selection element layer disposed over the first conductive pattern and having one or more first grooves therein, the first grooves overlapping the first conductive pattern; a first variable resistance layer whose sidewalls and bottom are surrounded by the first selection element layer, the first variable resistance layer being buried in the first groove; and a second conductive pattern that overlaps the first variable resistance layer and is disposed over the first variable resistance layer. . ... Sk Hynix Inc

10/26/17 / #20170309636

Manufacturing method of memory device

A method of manufacturing a memory device includes providing a semiconductor substrate including a first region and a second region. The method includes forming a lower structure including interconnect lines and an etch stop layer in the second region. ... Sk Hynix Inc

10/26/17 / #20170309600

Semiconductor packages

A planar dual die package includes a package substrate and first and second semiconductor dice disposed side by side on a first surface of the package substrate. Outer connectors are disposed on a second surface of the package substrate, and the second surface of the package substrate includes a command/address ball region and a data ball region. ... Sk Hynix Inc

10/26/17 / #20170309567

Fuse structure and semiconductor device including the same

A fuse structure includes a fusing line including a first portion, a second portion, and a central portion between the first portion and the second portion; and a dummy fuse neighboring the fusing line, the dummy fuse may include: a first air dummy fuse including a plurality of first air gaps extending in a first direction parallel to the fusing line; and a second air dummy fuse including a second air gap extending in a second direction crossing the fusing line.. . ... Sk Hynix Inc

10/26/17 / #20170309343

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device and a controller configured to control an operation of the nonvolatile memory device. The controller includes an ram in which a category table that categories with respect to lbas are defined and a read voltage table that read voltages with respect to the categories are set are stored and a controller configured to, when a read request and an lba to be read are received from a host apparatus, determine a category corresponding to the lba with reference to the category table and perform a read operation on a read-requested memory cell of the nonvolatile memory device by applying a read voltage corresponding to the determined category to the memory cell with reference to the read voltage table.. ... Sk Hynix Inc

10/26/17 / #20170309317

Reception circuit and electronic apparatus including the same

Provided is a reception circuit provided in a chip, the reception circuit including a controller that generates a reception control signal which is activated for a preset time on a basis of a first control signal individually provided to a plurality of chips, a buffer that receives a second control signal commonly provided to the plurality of chips, and a delay circuit that receives the second control signal from the buffer in response to the reception control signal and provides the second control signal to other elements in the chip.. . ... Sk Hynix Inc

10/12/17 / #20170295335

Unit pixel and operating method thereof and cmos image sensor using the same

This technology relates a unit pixel and an operating method thereof and a cmos image sensor using the same. The unit pixel may include a photo sensitive device; a reset transistor; a selection transistor including a gate terminal, a first terminal and a second terminal, suitable for operating in response to a selection control signal applied to the gate terminal and outputting a voltage applied to the first terminal to a first terminal of the reset transistor through the second terminal; and a drive transistor including a first terminal coupled to the second terminal of the selection transistor, a second terminal and a gate terminal, suitable for generating an electrical signal corresponding to charges accumulated in a floating diffusion node coupled to the gate terminal, and outputting the electrical signal as a pixel signal through the second terminal.. ... Sk Hynix Inc

10/12/17 / #20170294923

Optimization of low density parity-check code encoder based on a search for an independent set of nodes

Techniques are described for optimizing a parity-check matrix for a low density parity check (ldpc) encoder. In an example, a first parity-check matrix is accessed. ... Sk Hynix Inc

10/12/17 / #20170294899

Periodic signal generation circuit and semiconductor system including the same

A semiconductor system may include a first semiconductor device configured to output a command and receive data. The semiconductor system may include a second semiconductor device configured to generate a period signal, the period signals periodically toggled in response to the command, output the data in response to the period signal, and discharge the charges of an internal node if the period signal is not toggled during a predetermined section.. ... Sk Hynix Inc

10/12/17 / #20170294581

Semiconductor device including an etching stop layer and method of manufacturing the same

A method of semiconductor device fabrication that includes sequentially forming an interfacial conductive layer and an etch stop layer on a resistive memory layer; forming a main conductive layer on the etch stop layer; exposing a portion of the etch stop layer by patterning the main conductive layer; exposing a portion of the interfacial conductive layer by patterning the portion of the etch stop layer; forming an upper electrode structure by patterning the portion of the interfacial conductive layer; cleaning a surface of the upper electrode structure and an exposed surface of the resistive memory layer; and patterning the resistive memory layer using the upper electrode structure as an etch mask.. . ... Sk Hynix Inc

10/12/17 / #20170294484

Electronic device including metal-insulator-semiconductor structure and method for fabricating the same

A method for fabricating an electronic device that includes a metal-insulator-semiconductor (m-i-s) structure includes: providing a semiconductor layer; forming a primary insulation layer of a first thickness over the semiconductor layer; forming a reactive metal layer of a second thickness over the primary insulation layer, where the second thickness is greater than the first thickness; forming a primary capping layer of a third thickness over the reactive metal layer, where the third thickness is greater than the second thickness; and performing a thermal treatment.. . ... Sk Hynix Inc

10/12/17 / #20170294468

Image sensor and method for fabricating the same

An image sensor may include: a photoelectric conversion element suitable for generating a photo charge in response to incident light; and a transfer transistor suitable for transferring the photo charge generated by the photoelectric conversion element to a floating diffusion in response to a transfer signal, the transfer transistor comprising a first transfer gate formed over the photoelectric conversion element; an opening formed in the first transfer gate and exposing the photoelectric conversion element; a second transfer gate formed in the opening; and a channel layer interposed between the first and second transfer gates and between the photoelectric conversion element and the second transfer gate.. . ... Sk Hynix Inc

10/12/17 / #20170294411

Semiconductor packages including chip enablement pads

A semiconductor package includes a package substrate and semiconductor chips stacked on the package substrate. The package substrate may include at least one first chip enablement finger, at least one second chip enablement finger, and a chip enablement pad selection finger. ... Sk Hynix Inc

10/12/17 / #20170294237

Detect developed bad blocks in non-volatile memory devices

Systems and methods are provided to detect a developed bad word-line of a flash memory. Embodiments provide an improved background media scan (bgms) process that can predict at the end of a block read if a word-line will potentially become bad with the use of the flash memory. ... Sk Hynix Inc

10/12/17 / #20170294232

Nonvolatile memory device for suppressing read disturbances

A nonvolatile memory device includes a nonvolatile memory cell, a sensing circuit coupled between a sensing input line coupled to a bit line of the nonvolatile memory cell and a sensing output line, a sensing output grounding portion fixing an output signal of the sensing circuit at a low level if the output signal of the sensing circuit has a low level, and a bit line grounding portion fixing a bit line voltage at a ground voltage if the output signal of the sensing circuit is fixed at a low level.. . ... Sk Hynix Inc

10/12/17 / #20170294231

Nonvolatile memory cells having lateral coupling structures and nonvolatile memory cell arrays including the same

A nonvolatile memory (nvm) cell includes a selection transistor configured to have a selection gate terminal coupled to a word line and a source terminal coupled to a source line, a cell transistor configured to have a floating gate electrically isolated, a drain terminal coupled to a bit line and sharing a junction terminal with the selection transistor, a first coupling capacitor disposed in a first connection line coupled between the word line and the floating gate, and a p-n diode and a second coupling capacitor disposed in series in a second connection line coupled between the word line and the floating gate. An anode and a cathode of the p-n diode are coupled to the second coupling capacitor and the word line, respectively. ... Sk Hynix Inc

10/12/17 / #20170294226

Electronic device

An electronic device including a semiconductor memory. The semiconductor memory may include a cell array including a plurality of resistive storage cells; a current code generation block suitable for generating a current code which has a value corresponding to an average value of current amounts of test currents respectively flowing through at least two first resistive storage cells among the plurality of resistive storage cells, in a test operation; and a sensing block suitable for comparing a read current flowing through a second resistive storage cell selected among the plurality of resistive storage cells with a reference current, and thereby sensing data of the second resistive storage cell, wherein the semiconductor memory is operable to adjust a current amount of at least one current flowing through the sensing block based on the value of the current code.. ... Sk Hynix Inc

10/12/17 / #20170293524

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device including a plurality of memory cells; and a controller suitable for reading target data from a target page corresponding to the plurality of memory cells, estimating error bits of the target data based on reference data read from at least one reference page corresponding to the plurality of memory cells of the target data, and performing an error correction operation to the target data based on a result of the estimation.. . ... Sk Hynix Inc

10/12/17 / #20170293446

Erase page indicator

A flash memory device includes a flash memory comprising a plurality of pages for storing data, a control circuit configured to select a page of the plurality of pages in response to a received command, an accumulator configured to obtain a signal value of the selected page, and a comparator configured to compare the signal value with a predetermined value. The control circuit generates an indication signal indicative of a state of the selected page based on a comparison result.. ... Sk Hynix Inc

10/12/17 / #20170293437

Last written page indicator

A flash memory device includes a flash memory having a plurality of blocks, each block having a plurality of pages, and a control circuit configured to receive a command, decode the received command to determine whether the command is a last written page command, upon determining that the command is the last written page command, select a block of the plurality of blocks, and perform a number of iterations. Each of the iterations includes obtain a measurement of a signal level of a page in the selected block, compare the signal level with a predetermined threshold value, determine whether the page is an erased page based on a comparison result, upon determining that the page is an erased page, save an address associated with the erased page and output the address of the erased page, and upon determining that the page is not an erase page, perform a next iteration.. ... Sk Hynix Inc

10/12/17 / #20170293435

Memory device and operating method thereof

The present disclosure relates to a memory device and an operating method thereof. A memory device includes an enable signal generation unit generating an enable signal in response to a command; a storage unit storing product information of the memory device; an information generation unit generating variable information of the memory device; and an output unit combining the product information from the storage unit with the variable information from the information generation unit and outputting the combined information in response to the enable signal.. ... Sk Hynix Inc

10/12/17 / #20170293430

Data processing system and operating method of data processing system

A data processing system may include: a first memory system including a first memory device, and a first controller of the first memory device; and a second memory system including a second memory device, and a second controller of the second memory device, the first memory system may receive a command from a host, and then checks time information included in the command and performs a first update operation for the first memory device for a first time corresponding to the time information, and the second memory system may perform a second update operation for the second memory device for the first time for which the first update operation is performed.. . ... Sk Hynix Inc

10/12/17 / #20170293429

Memory device and operating method thereof

There are provided a memory device and an operating method thereof. A memory device may include a memory block, peripheral circuits, and a control logic. ... Sk Hynix Inc

10/12/17 / #20170293427

Memory module and memory system including the same

A memory module may include a first memory device configured to be controlled by a host memory controller, to transmit/receive data to/from the host memory controller in a first mode, and to transmit/receive data to/from a module memory controller in a second mode, a second memory device configured to be controlled by the module memory controller and to transmit/receive data to/from the module memory controller in the second mode, and the module memory controller configured to monitor control of the first memory device by the host memory controller, to exchange data such that the data is transmitted/received between the first memory device and the second memory device in the second mode, and to control the second memory device.. . ... Sk Hynix Inc

10/05/17 / #20170288669

Calibration circuit and calibration apparatus including the same

A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.. . ... Sk Hynix Inc

10/05/17 / #20170288012

Analog capacitor

An analog capacitor is disclosed. The analog capacitor may include a main analog capacitor, an interlayer insulating layer, and a plurality of stacked sub analog capacitors. ... Sk Hynix Inc

10/05/17 / #20170287959

Image sensor

An image sensor may include: a photoelectric conversion element including a second conductive layer formed over a first conductive layer; an insulating layer and a third conductive layer which are sequentially formed over the second conductive layer; an opening exposing the second conductive layer through the third conductive layer and the insulating layer; a channel layer formed along the surface of the opening, and including first and second channel layers which are coupled to each other while having different conductivity types; and a transfer gate formed over the channel layer to fill the opening, and partially formed over the third conductive layer.. . ... Sk Hynix Inc

10/05/17 / #20170287932

Semiconductor device

Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device includes source select lines, word lines, drain select lines, and a bit line stacked on a substrate in which a first cell string region and a second cell string region are defined; channel layers and memory layers vertically passing through the source select lines, the word lines, and the drain select lines in each of the first cell string region and the second cell string region; and a common source line vertically passing through the source select lines, the word lines, and the drain select lines at centers of the first cell string region and the second cell string region, and extended to a lower side of the source select lines.. ... Sk Hynix Inc

10/05/17 / #20170287927

Manufacturing method of semiconductor device including barrier pattern

The invention is related to a method for manufacturing a semiconductor device having a barrier pattern. The method includes alternately forming first sacrificial layers and insulating layers forming channel patterns penetrating the first sacrificial layers and the insulating layers, and forming a slit penetrating the first sacrificial layers and the insulating layers. ... Sk Hynix Inc

10/05/17 / #20170287879

Thin stack packages

The stack package includes a substrate body layer having a top surface and a bottom surface, first circuit patterns disposed on the bottom surface of the substrate body layer, second circuit patterns disposed on the top surface of the substrate body layer, a first semiconductor chip including first bumps, and a second semiconductor chip including second bumps. The first bumps extend through the substrate body layer to be electrically coupled to the first circuit patterns, and the second bumps extend past sidewalls of the first semiconductor chip to be electrically coupled to the second circuit patterns. ... Sk Hynix Inc

10/05/17 / #20170287734

Semiconductor packages including interposer and methods of manufacturing the same

A semiconductor package may include a semiconductor die mounted on a first surface of an interposer die so that a die connection portion of the semiconductor die faces to the first surface of the interposer die, a protection portion may be disposed on the first surface of the interposer die to cover the semiconductor die, and an interconnection structure disposed in and on the interposer die. The interconnection structure may include an external connection portion that is located on a second surface of the interposer die opposite to the semiconductor die, a through electrode portion that penetrates the interposer die to have an end portion combined with the die connection portion, and an extension portion that connects the through electrode portion to the external connection portion. ... Sk Hynix Inc

10/05/17 / #20170287711

Method of manufacturing semiconductor device

In accordance with an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include forming an opening passing-through a multi-layer stack, forming a channel layer on and along a sidewall of the opening, forming a conductive layer on and along a sidewall of the channel layer, and applying a laser to the conductive layer to transfer a heat from the conductive layer to the channel layer to heat-treat the channel layer using the heat.. . ... Sk Hynix Inc

10/05/17 / #20170287702

Nano-scale structures

A nanoscale structure includes an array of pillars over an underlying layer, a separation wall layer including first separation walls formed over sidewalls of the pillars, and a block co-polymer (bcp) layer formed over the separation wall layer and filling gaps between the pillars. The bcp layer is phase-separated to include first domains that provide second separation walls formed over the first separation walls and second domains that are separated from each other by the first domains.. ... Sk Hynix Inc

10/05/17 / #20170287564

Memory system and operating method thereof

The present disclosure relates to a memory system and an operating method thereof. A memory system may include a semiconductor memory device including a cam block and a normal memory block, and a controller suitable for setting an initial setting read voltage according to an option parameter stored in the cam block and controlling the semiconductor memory device to perform a first read operation to the normal memory block according to the initial setting read voltage.. ... Sk Hynix Inc

10/05/17 / #20170287563

High voltage switch circuit for switching high voltage without potential drop and semiconductor memory device including the same

There are provided a high voltage switch circuit and a semiconductor memory device including the same. A high voltage switch circuit may include a switching circuit including a first depletion transistor and a first high voltage transistor, which are coupled in series between an input terminal and an output terminal, and a control signal generator for applying, to the first depletion transistor, a control signal having the same potential level as an input voltage applied to the input terminal, in response to a first enable signal and a second enable signal.. ... Sk Hynix Inc

10/05/17 / #20170287562

High voltage switch circuit for switching high voltage without potential drop and semiconductor memory device including the same

There are provided a high voltage switch circuit and a semiconductor memory device including the same. A high voltage switch circuit may include a switching circuit including a first depletion transistor and a first high voltage transistor, which are coupled in series between an input terminal and an output terminal, and a control signal generator for applying, to the first depletion transistor, a control signal having the same potential level as an input voltage applied to the input terminal, in response to a first enable signal and a second enable signal.. ... Sk Hynix Inc

10/05/17 / #20170287560

Semiconductor memory device and operating method thereof with a connection control transistor operation voltage adjusted

There is provided a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a memory cell array including a plurality of pages; a peripheral circuit suitable for performing a program operation by applying a program voltage, a pass voltage, and a pipe transistor operation voltage, to the memory cell array; and a control logic suitable for controlling the peripheral circuit to perform the program operation, wherein the control logic adjusts a potential level of the pipe transistor operation voltage according to an address of a selected page among the plurality of pages.. ... Sk Hynix Inc

10/05/17 / #20170286655

Wearable device, system including the same, and operation methods thereof

A semiconductor device and a system may be provided. The semiconductor device may include a plurality of memory cell groups. A wearable device may include: an authentication unit suitable for authenticating a user by verifying user identification information of the user; a sensor suitable for detecting contact between the authenticated user and the wearable device; a wireless communication unit suitable for wirelessly provide link success information to an electronic device requiring user authentication; and a control unit suitable for controlling the wireless communication unit to provide the link success information to the electronic device during the contact after success of the authentication of the authentication unit.. . ... Sk Hynix Inc

10/05/17 / #20170286219

Data storage device and operating method thereof

A method for operating a data storage device includes reading out a data chunk from a nonvolatile memory device; arranging first codes and second codes of the read-out data chunk in the form of a matrix; and determining the total number of corrected error bits for the data chunk by decoding the respective first codes and the respective second codes, and summing the numbers of corrected error bits of the respective decoded first codes and the respective decoded second codes.. . ... Sk Hynix Inc

10/05/17 / #20170286218

Semiconductor devices, and semiconductor systems

A write parity signal generation circuit, semiconductor device and semiconductor system may be provided. The write parity signal generation circuit may be configured to generate a pre-parity signal from a write data signal and a read data signal, and generate a write parity signal from the pre-parity signal and a syndrome signal.. ... Sk Hynix Inc

10/05/17 / #20170285950

Semiconductor memory device and operating method thereof

Provided herein is a semiconductor memory device and an operating method thereof. The semiconductor memory device may include a memory cell array, a peripheral circuit, and a control logic. ... Sk Hynix Inc

10/05/17 / #20170285945

Throttling for a memory system and operating method thereof

A semiconductor memory system and an operating method thereof include: a memory device; and a memory controller including a processor, coupled to the memory device, containing instructions executed by the processor, and configured to provide sets of throttling numbers, select a throttling mode, calculate a garbage collection (gc)/host ratio based on at least a part of invalid count of garbage collection (gc) blocks and valid count of bgc blocks, and adjust throttling parameters of commands in accordance with the gc/host ratio and a number of erased blocks.. . ... Sk Hynix Inc

10/05/17 / #20170285942

Memory system including memory controller and operation method thereof

A memory system may include a memory device suitable for storing data requested from a host, and a controller suitable for generating information on the data and transmitting/receiving the data and the information to/from the memory device through first and second data buses, respectively, during a first operation mode, or for transmitting/receiving the data to/from the memory device through one of the first and second data buses based on the data size, during a second operation mode.. . ... Sk Hynix Inc

09/28/17 / #20170280085

Pixel output level control device and cmos image sensor using the same

A pixel output level control device may include: a pixel output level control unit suitable for controlling a pixel output level of a pixel signal of a pixel for reducing the time required for settling the pixel signal during a specific period; and a pixel output level retention unit suitable for maintaining the pixel output level of the pixel signal during the specific period to a fixed value, according to control of the pixel output level control unit.. . ... Sk Hynix Inc

09/28/17 / #20170280077

Comparison device and cmos image sensor using the same

Provided are a comparison device capable of achieving a small area by using one small sampling capacitor for an input terminal and improving linearity by using a fixed reference voltage and a cmos image sensor using the same. The comparison device may include a comparator configured to compare a pixel signal inputted through a positive input terminal with a ramp signal, a first sampling capacitor configured to be provided between an input terminal of the ramp signal and the positive input terminal of the comparator, a sampling switch configured to be provided between an output terminal of the comparator and a negative input terminal of the comparator, and a second sampling capacitor configured to be provided between a ground terminal and the negative input terminal of the comparator.. ... Sk Hynix Inc

09/28/17 / #20170279468

Soft decoder for generalized product codes

A memory device includes a memory array, a processor, and a decoding apparatus. The processor is coupled to the memory array and configured to read encoded data from the memory array. ... Sk Hynix Inc

09/28/17 / #20170279467

Performance optimization in soft decoding of error correcting codes

Techniques are described for decoding a codeword. In one example, the techniques include obtaining a first message comprising reliability information corresponding to each bit in the first codeword, determining a plurality of least reliable bits in the first codeword, and generating a plurality of flipped messages by flipping one or more of the plurality of least reliable bits in the first codeword. ... Sk Hynix Inc

09/28/17 / #20170279466

Hybrid soft decoding algorithm for multiple-dimension tpc codes

An apparatus for decoding a tpc codeword is disclosed. The apparatus includes a memory and a processor coupled to the memory. ... Sk Hynix Inc

09/28/17 / #20170279465

Soft decoder parameter optimization for product codes

In one embodiment, an apparatus for decoding is disclosed. The apparatus includes a memory and at least one processor coupled to the memory. ... Sk Hynix Inc

09/28/17 / #20170279463

Techniques for low-latency chase decoding of turbo product codes with soft information

Techniques are described for decoding a first message. In one example, the techniques include obtaining a second message comprising reliability information corresponding to each bit in the first message, performing a soft decision decoding procedure on the second message to generate a decoded codeword, wherein the soft decision decoding procedure comprises a joint decoding and miscorrection avoidance procedure, and outputting the decoded codeword.. ... Sk Hynix Inc

09/28/17 / #20170278884

Image sensor and method for fabricating the same

This technology relates to an image sensor. The image sensor may include a substrate including a photoelectric conversion element; a pillar formed over the photoelectric conversion element and having a concave-convex sidewall; a channel film formed along a surface of the pillar and for having at least one end coupled to the photoelectric conversion element; and a transfer gate formed over the channel film.. ... Sk Hynix Inc

09/28/17 / #20170278883

Transistor and image sensor having the same

An image sensor includes: a light receiving section suitable for generating photocharges in response to incident light; and a driving section including a source follower transistor suitable for generating an output voltage corresponding to a reference voltage in response to the photocharges. The source follower transistor includes: a stack structure formed by sequentially stacking a first conductive layer, an insulating layer and a second conductive layer; an open portion to formed through the second conductive layer and the insulating layer so as to expose the first conductive layer; a channel layer formed along the surface of the open portion so as to be connected to the first conductive layer and the second conductive layer; and a gate is connected to the light receiving section and which is formed over the channel layer so as to overlap the second conductive layer.. ... Sk Hynix Inc

09/28/17 / #20170278882

Image sensor and method for fabricating the same

A method for fabricating an image sensor in accordance with an embodiment of the inventive concepts may include forming first and second photodiodes within a substrate, forming first and second gate electrodes over the substrate, the first gate electrode vertically partially overlapping the first photodiode and the second gate electrode vertically partially overlapping the second photodiode, forming an impurity injection region comprising first and second type impurities between the first and the second gate electrodes, and performing an annealing process to form a floating diffusion region comprising the first type impurities and a channel region comprising the second type impurities. The channel region surrounds lateral surfaces and a bottom surface of the floating diffusion region.. ... Sk Hynix Inc

09/28/17 / #20170278833

Semiconductor package

A semiconductor package may include a dram chip mounted on a substrate; an interposer stacked over the dram chip and including redistribution structures; a nonvolatile memory chip stacked over the interposer; a memory controller chip mounted on the substrate, and including a control circuit for controlling the nonvolatile memory chip and first pads and second pads electrically coupled to the control circuit; first conductive coupling members configured to electrically couple bonding pads of the nonvolatile memory chip to the redistribution structures; second conductive coupling members configured to electrically couple the redistribution structures to the first pads; and third conductive coupling members configured to electrically couple the second pads to the substrate.. . ... Sk Hynix Inc

09/28/17 / #20170278574

Semiconductor device and operating method thereof

The present disclosure relates to a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a peripheral circuit: suitable for performing an erase operation and a program operation to the memory cell array, and a control logic suitable for controlling the peripheral circuit to erase all of the plurality of memory blocks and then to program the plurality of memory blocks with dummy data during the erase operation.. ... Sk Hynix Inc

09/28/17 / #20170277606

Semiconductor system including replacement storage unit

A semiconductor system includes one or more core chips including a plurality of memory banks; one or more replacement storage units; and a base chip suitable for: first detecting a memory bank having an access frequency that satisfies a first condition, second detecting whether an utilization rate of the first detected memory bank satisfies a second condition, and replacing the second detected memory bank with one among the replacement storage units.. . ... Sk Hynix Inc

09/28/17 / #20170277594

Nonvolatile dual in-line memory module and method for operating the same

A nonvolatile memory module includes a plurality of volatile memory devices sharing a data bus through which data is transmitted and a control bus through which a command and an address are transmitted; at least one nonvolatile memory device; and a controller including a backup logic which backs up data stored in the plurality of volatile memory devices when a fail in power of the host is detected or a backup operation is instructed from the memory controller of the host, wherein the backup logic sets a command address latency (cal) of one among the plurality of volatile memory devices to a first value, and sets a command address latency of remaining volatile memory devices to a second value different from the first value.. . ... Sk Hynix Inc

09/28/17 / #20170277593

Power-down interrupt of nonvolatile dual in-line memory system

A nonvolatile memory module includes volatile memory devices; a nonvolatile memory device; and a controller suitable for backing up data stored in the volatile memory devices or restoring data backed up in the nonvolatile memory device, according to a fail/recovery of power of the host, the controller including a power-down interrupt logic which interrupts a backup operation when the power of the host is recovered while performing the backup operation, the power-down interrupt logic including: a logic which determines whether sufficient erased blocks exist in the nonvolatile memory device; a logic which erases a new block when the sufficient erased bocks do not exist; and an interrupt backup logic which backs up a volatile memory device having data corresponding to the erased block, when a fail in the power of the host is detected or a backup operation is instructed from the host.. . ... Sk Hynix Inc

09/28/17 / #20170277588

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device; a randomizing unit configured to randomize data to be stored in the nonvolatile memory device and derandomize data read from the nonvolatile memory device, by using seed values; and a control unit configured to, in the case where return is made from a power failure state to a normal state, detect a page of the nonvolatile memory device in which a power problem has occurred, and randomize data of the page in which the power problem has occurred, by using a seed value that is different from a seed value corresponding to the page in which the power problem has occurred, through the randomizing unit.. . ... Sk Hynix Inc

09/28/17 / #20170277476

Memory system and operating method of memory system

A memory system may include: a memory device comprising a plurality of pages, which include a plurality of memory cells coupled to a plurality of word lines, and in which data is stored, and a plurality of memory blocks in which the pages are included; and a controller configured to divide the memory blocks into a first group and a second group, perform a command operation corresponding to a command received from a host, and respectively store segments of user data and meta data for the command operation in memory blocks included in the first group or memory blocks included in the second group, in accordance with type information of the user data included in the command.. . ... Sk Hynix Inc

09/28/17 / #20170277474

Data processing system including data storage device

A data processing system includes a data storage device; and a host device configured to transmit a write request to the data storage device to store data in the data storage device, wherein the host device transmits the write request including a request purpose meaning what a cause that results in the write request is, and wherein the data storage device processes the write request based on the request purpose.. . ... Sk Hynix Inc

09/28/17 / #20170277473

Data processing system and operating method thereof

A data processing system includes a host device including a first volatile memory which includes an exclusive region and a shared region, and a first control unit; and a data storage device including a second control unit, and configured to store data to be accessed by the host device, wherein the first control unit adds a header information including an identification information and a state information, to data to be stored in the data storage device, and stores the data added with the header information, in the shared region, according to a request of the second control unit. . ... Sk Hynix Inc

09/28/17 / #20170277464

Nonvolatile memory module and operating method for the same

A nonvolatile memory module includes volatile memory devices sharing a data bus and a control bus; at least one nonvolatile memory device; and a controller for backing up data stored in the volatile memory devices into the nonvolatile memory device at a power failure of a host, and restoring data backed up in the nonvolatile memory device to the volatile memory devices at recovery of the power failure, the controller including: a command/address snooping logic for snooping on a command and an address inputted from a memory controller of the host, and analyzing amounts of stored data in the respective volatile memory devices; and a command/address control logic for selecting one of the volatile memory devices in order of the amounts of stored data based on analysis results of the command/address snooping logic, and backing up data of the selected volatile memory device in the nonvolatile memory device.. . ... Sk Hynix Inc

09/28/17 / #20170277463

Nonvolatile memory module and operating method for the same

A nonvolatile memory module includes volatile memory devices sharing a data bus and a control bus through which a command and an address are transmitted; at least one nonvolatile memory device; and a controller for backing up data stored in the volatile memory devices into the nonvolatile memory device at a power failure of a host, and restoring data backed up in the nonvolatile memory device to the volatile memory devices at recovery of the power failure, the controller including: a command/address snooping logic for snooping on a command and an address inputted from a memory controller of the host, and analyzing valid areas of data stored in the respective volatile memory devices; and a command/address control logic for selecting the volatile memory device having the valid area of data based on analysis results of the command/address snooping logic, and backing up selected volatile memory into the nonvolatile memory device.. . ... Sk Hynix Inc

09/28/17 / #20170277454

Memory device and operating method thereof

Provided herein are a memory device and an operating method thereof. The memory device includes: a memory device comprising: a memory cell array including a plurality of pages; a peripheral circuit suitable for successively receiving a plurality of logical page data, and performing a program operation with the received logical page data to a selected page; and a control logic suitable for controlling the peripheral circuit to perform, in parallel, the program operation to the selected page with reception-completed logical page data among the plurality of logical page data while receiving other logical page data.. ... Sk Hynix Inc

09/28/17 / #20170277445

Data storage device, operating method thereof, and data processing system including the same

A data storage device includes a nonvolatile memory device including first and second memory regions; and a controller suitable for performing a pattern identification operation for write requests, based on a pattern information for one or more patterns, and storing data corresponding to the write requests in one of the first and second memory regions according to a result of the pattern identification operation.. . ... Sk Hynix Inc

09/28/17 / #20170277434

Data storage device and operating method thereof

A data storage device includes: a plurality of nonvolatile memory devices; and a controller suitable for receiving a command and executing the command for the plurality of nonvolatile memory devices. The controller includes: a first queue suitable for storing the command; and a command manager suitable for managing the command in the first queue, based on a first attribute of the command and queue information of the first queue.. ... Sk Hynix Inc

09/28/17 / #20170276719

Semiconductor apparatus and characteristic measurement circuit therefor

A semiconductor apparatus may include a unit chip and a characteristic measurement circuit configured to include a plurality of unit elements for test and to output electrical characteristic information of the plurality of unit elements for test.. . ... Sk Hynix Inc

09/21/17 / #20170272673

Image sensing device

An image sensing device includes: a pixel array including a plurality of pixels arranged at each cross point of rows and columns, wherein the pixel array comprises a plurality of pixel blocks, each including n pixels, n being a natural number equal to or greater than 2, wherein the pixel blocks sequentially output a plurality of pixel signals having pixel information on the same color n times during one or more single row times; a plurality of column lines suitable for sequentially transferring the plurality of pixel signals from the pixel blocks, each column line being shared by two adjacent columns and coupled to at least one of the pixel blocks; a plurality of averaging blocks suitable for grouping the pixel signals to overlap each other, into a plurality of pixel signal groups, and averaging the pixel signal groups to output a plurality of averaged pixel signals, wherein the number of the averaging blocks is smaller than the number of the column lines; and a plurality of conversion blocks suitable for converting the averaged pixel signals into a plurality of digital signals.. . ... Sk Hynix Inc

09/21/17 / #20170272076

Semiconductor integrated circuit device

A semiconductor integrated circuit device may include a main inverter and a negative bias temperature instability (nbti) compensating circuit. The main inverter may be configured to receive an input signal. ... Sk Hynix Inc

09/21/17 / #20170272064

Integrated circuits relating to transmission data

An integrated circuit may be provided. The integrated circuit may include a transmitter and a receiver. ... Sk Hynix Inc

09/21/17 / #20170272063

Delay circuit

A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled n times, where n is an integer equal to or greater than 0.. . ... Sk Hynix Inc

09/21/17 / #20170271464

Semiconductor structure having buried gate structure, method for manufacturing the same, and memory cell having the same

A method for forming a semiconductor structure includes forming a trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the trench; forming a work function layer over the gate dielectric layer; recessing the work function layer, and forming a gate electrode which is positioned in the trench; and exposing the gate electrode to a thermal process, and forming a dipole induction layer between the gate electrode and the gate dielectric layer.. . ... Sk Hynix Inc

09/21/17 / #20170271354

Semiconductor device

Provided herein is a semiconductor device. The semiconductor device includes: a lower conductive pattern; a lower memory string conductive pattern disposed over the lower conductive pattern; a stack of upper memory string conductive patterns, wherein the stack is disposed over the lower memory string conductive pattern; a lower pad pattern extending from the lower memory string conductive pattern; upper pad patterns respectively extending from the upper memory string conductive patterns; a floating conductive pattern disposed under below the lower pad pattern, the floating conductive pattern overlapping the lower pad pattern; and a contact plug coming into contact with the lower pad pattern and overlapping the floating conductive pattern.. ... Sk Hynix Inc

09/21/17 / #20170271353

Semiconductor device

Provided herein is a semiconductor device. The semiconductor device may include a substrate, conductive patterns, and a pipe gate. ... Sk Hynix Inc

09/21/17 / #20170271346

Anti-fuse nonvolatile memory devices employing lateral bipolar junction transistors as selection transistors

An anti-fuse nonvolatile memory device includes an anti-fuse memory cell and a bipolar junction transistor. The anti-fuse, memory cell has a first terminal and a second terminal. ... Sk Hynix Inc

09/21/17 / #20170271308

Stack chip package and method of manufacturing the same

A stack chip package may include a plurality of stacked semiconductor chips. Each of the semiconductor chips may have a first node, a second node, a third node and a fourth node corresponding to corners of the semiconductor chip. ... Sk Hynix Inc

09/21/17 / #20170271149

Methods of forming fine patterns

A method of forming fine patterns includes forming pillars arrayed in rows and columns on an underlying layer and forming a spacer layer on the underlying layer to cover the pillars. Portions of the spacer layer respectively covering the pillars arrayed in each row or in each column are in contact with each other to provide first interstitial s paces disposed between the pillars arrayed in a diagonal direction between a row direction and a column direction as well as to provide cleavages at corners of each of the first interstitial spaces in a plan view. ... Sk Hynix Inc

09/21/17 / #20170271026

Memory and system including the same

There may be provided a memory or memory system. A memory may include an active cell array comprising a plurality of unit cells coupled to a word line and configured to store an active count of the word line. ... Sk Hynix Inc

09/21/17 / #20170271024

Data storage device and operating method thereof

A data storage device includes a controller configured to control data to be written in a first page; and a nonvolatile memory device configured to perform a write operation for writing the data, according to whether the first page is written or not, wherein the nonvolatile memory device provides a state information including an overwrite information meaning whether the write operation has caused an overwrite, to the controller.. . ... Sk Hynix Inc

09/21/17 / #20170271019

Non-volatile memory device and method for operating non-volatile memory device

A non-volatile memory device includes: a plurality of cache latches; a pair of input/output lines; a plurality of switches, each couples a corresponding cache latch to the pair of the input/output lines, when the corresponding cache latch is selected among the plurality of cache latches; a pre-charger suitable for pre-charging the pair of the input/output lines; and a sense-amplifier suitable for sensing and amplifying the data of the pair of the input/output lines, wherein the sense-amplifier operates with a first power source voltage, and the plurality of the cache latches, the plurality of the switches, and the pre-charger operate with a second power source voltage having a voltage level that is higher than the voltage level of the first power source voltage.. . ... Sk Hynix Inc

09/21/17 / #20170271012

Semiconductor memory device and operating method thereof

Provided herein are a semiconductor memory device and an operating method thereof. The semiconductor memory device may include a memory cell array, peripheral circuits, and a control logic. ... Sk Hynix Inc

09/21/17 / #20170270997

Semiconductor devices relating to a refreshing operation

A semiconductor device may be provided. The semiconductor device may include an address input circuit and a target address generation circuit. ... Sk Hynix Inc

09/21/17 / #20170270982

Semiconductor system and operating method thereof

This technology relates to a semiconductor system. The semiconductor system may include a first semiconductor device capable of outputting a clock signal, a data strobe signal, and data; and a second semiconductor device capable of generating a division enable signal and a data input clock signal in response to the clock signal when performing a write operation, generating an internal strobe signal by dividing the data strobe signal in response to the division enable signal, and aligning the data in response to the internal strobe signal, wherein the first semiconductor device receives the division enable signal from the second semiconductor device and trains the data strobe signal so that the data strobe signal is output in a predetermined section.. ... Sk Hynix Inc

09/21/17 / #20170270981

Precharge circuitry for semiconductor memory device

A semiconductor memory apparatus may include a memory cell circuit, a data latch circuit, and a first stage amplification circuit. The data latch circuit may be electrically coupled to the memory cell circuit by a bit line. ... Sk Hynix Inc

09/21/17 / #20170270050

Memory system including memory device and operation method thereof

A memory system includes first and second memory devices having at least one different characteristic from each other and a controller suitable for configuring an address map of data stored in the first and the second memory devices, checking access frequency of the stored data, and updating the address map based on a result of the checking.. . ... Sk Hynix Inc

09/21/17 / #20170270045

Hybrid memory device and operating method thereof

A memory device may include: a data determination unit for receiving page data from a main memory device, and distinguishing between first and second data based on tag information of the page data; an index management unit for storing an index of the first data; a first cache for storing the second data, and writing back first victim data to the main memory device, the first victim data being selected when the first cache is full; and a second cache for storing the first victim data transferred from the first cache when a write count of the first victim data is smaller than a first threshold value, updating tag information of second victim data to a value indicating the first data, the second victim data being selected when the second cache is full, and storing the second victim data in the main memory device.. . ... Sk Hynix Inc

09/21/17 / #20170270040

Memory system and operating method thereof

There are provided a memory system having improved operation speed and an operating method thereof. A method of operating a controller for controlling a memory block including a plurality of pages includes determining whether the memory block is in an open state or a closed state, if the memory block is in the open state, reading merged metadata included in the plurality of pages, and rebuilding logical to physical (l2p) mapping data of a plurality of logical pages included in each of the plurality of pages based on the merged metadata.. ... Sk Hynix Inc

09/21/17 / #20170269989

Semiconductor device

A semiconductor device may include normal memory cells, redundancy memory cells, a fuse array, and a controller. The normal memory cells may be coupled to a plurality of word lines and bit lines. ... Sk Hynix Inc

09/21/17 / #20170269875

Memory system and operating method thereof

A memory system includes a first memory device suitable for inputting and outputting data through a serial interface, a second memory device suitable for inputting and outputting the data through a parallel interface, and a controller suitable for detecting an access pattern of the data, selecting one of the first and the second memory devices based on the detected access pattern, and controlling the selected memory device to store the data.. . ... Sk Hynix Inc

09/21/17 / #20170269874

Controller of semiconductor memory device and operating method thereof

There are provided a controller of a semiconductor memory device, which stores data for debug processing, and an operating method of the controller. A controller for controlling a semiconductor memory device includes an event occurrence detection unit configured to detect whether an event occurs, an event information generation unit configured to generate event information in response to the detecting result from the event occurrence detection unit, and a command generation unit configured to generate a command for storing the event information in the semiconductor memory device.. ... Sk Hynix Inc

09/21/17 / #20170269833

Data storage device

A data storage device includes a first nonvolatile memory device including a target memory region, and a controller suitable for performing a first data input operation to transmit first data, which is to be stored in the target memory region, to the first nonvolatile memory device, regardless of whether a size of the first data corresponds to the target memory region.. . ... Sk Hynix Inc

09/21/17 / #20170269628

Latency control device and semiconductor device including the same

A latency control device and a semiconductor device including the same may be provided. The latency control device may include a first delay controller configured to delay a command signal based on a first internal clock having a first phase and a control signal. ... Sk Hynix Inc

09/21/17 / #20170269626

Reference voltage generator and voltage generating system having the same

A reference voltage generator includes a constant voltage generator suitable for using a high voltage as a first power supply voltage and for generating a constant voltage, and a first reference voltage generating unit suitable for using the constant voltage as a second power supply voltage and for generating a first reference voltage.. . ... Sk Hynix Inc

09/14/17 / #20170264320

Code reconstruction scheme for multiple code rate tpc decoder

An apparatus for decoding is disclosed. The apparatus includes a memory and a processor coupled to the memory. ... Sk Hynix Inc

09/14/17 / #20170264191

Charge pump circuit and internal voltage generation circuit including the same

A charge pump circuit may include a charge pump unit suitable for performing a charge pump operation until an output voltage reaches a target voltage; and a multi-stage charge sharing unit comprising first to nth capacitors coupled in parallel between the charge pump unit and a load circuit, the multi-stage charge sharing unit being suitable for sequentially performing first to nth charge sharing operations between the first to nth capacitors, respectively, and the load circuit after the charge sharing operation, wherein the first to nth charge sharing operations are mutually and exclusively performed, and n is a natural number equal to or greater than 2.. . ... Sk Hynix Inc

09/14/17 / #20170263680

Magnetoresistive memory device and manufacturing method of the same

According to one embodiment, a magnetoresistive memory device includes an electrode, a first layer which is provided on the electrode and includes an amorphous portion in at least a part of an electrode side, and a magnetoresisive element provided on the first layer.. . ... Sk Hynix Inc

09/14/17 / #20170263620

Memory device and manufacturing method thereof

There are provided a memory device and a manufacturing method thereof. A method of manufacturing a memory device may include forming, on a substrate, a conductive layer, a sacrificial layer, and a stack structure. ... Sk Hynix Inc

09/14/17 / #20170263335

Semiconductor test system during burn-in process

A command generation circuit, test control circuit, semiconductor device, semiconductor system, and or a test method may be provided. The semiconductor device may be configured to enter test modes and to generate internal commands during a clock cycle.. ... Sk Hynix Inc

09/14/17 / #20170263327

Semiconductor memory device and operating method thereof

The present technique relates to an electronic device, and more particularly, to a semiconductor memory device and an operating method thereof. A semiconductor memory device having improved reliability includes an address decoder applying a program voltage to a selected word line coupled to selected memory cells, among the plurality of memory cells, and a read and write circuit applying a program permission voltage or a program inhibition voltage to bit lines coupled to the selected memory cells, and a control logic controlling the read and write circuit to sequentially apply the program permission voltage and the program inhibition voltage to the bit lines coupled to the selected memory cells when the program voltage is applied.. ... Sk Hynix Inc

09/14/17 / #20170263321

Nonvolatile memory device and data storage device including the same

A data storage device includes a nonvolatile memory device; and a controller suitable for providing a normal erase command or a fine erase command to the nonvolatile memory device, wherein the nonvolatile memory device performs a first normal erase loop in which a first normal erase voltage and an erase verify voltage are applied to erase target memory cells, according to the normal erase command, and performs a first fine erase loop in which a first fine erase voltage and the erase verify voltage are applied to the erase target memory cells, according to the fine erase command.. . ... Sk Hynix Inc

09/14/17 / #20170263317

Electronic device including variable resistance element and method for operating the same

A method for operating an electronic device including a variable resistance element comprises performing a reset operation on the variable resistance element. The variable resistance element is fully reset by a first reset voltage applied thereto. ... Sk Hynix Inc

09/14/17 / #20170263293

Semiconductor memory device and operating method thereof

In an embodiment, a semiconductor memory device may include a memory cell array, a plurality of page buffers, and a control logic. The memory cell array may include a plurality of memory cells. ... Sk Hynix Inc

09/14/17 / #20170262173

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device including a main map table, the main map table including a plurality of map segments; and a controller comprising a sub map table including only some of the plurality of map segments of the main map table, the controller is suitable for updating access frequencies for the respective map segments of the main map table; and for determining whether to erase a map segment of the sub map table based on the updated access frequencies for the respective map segments.. . ... Sk Hynix Inc

09/14/17 / #20170262171

Nonvolatile memory apparatus and verification write method thereof

A non-volatile memory apparatus may include a program current generation circuit, a clamping circuit and a voltage generation circuit. The program current generation circuit may increase a program current based on a memory cell current flowing through a memory cell. ... Sk Hynix Inc

09/07/17 / #20170257083

Integrated circuit

An integrated circuit includes: a latch unit suitable for inverting a voltage level of a first node and driving a second node with the inverted voltage level of the first node, and inverting a voltage level of the second node and driving the first node with the inverted voltage level of the second node; and a sink unit coupled with one or more among the first and second nodes, and suitable for sinking a charge of the coupled node.. . ... Sk Hynix Inc

09/07/17 / #20170256630

Method of manufacturing a semiconductor device

Disclosed is a method of manufacturing a semiconductor device. The semiconductor device may be manufactured by forming a trench extended in a first direction within a first pipe gate, forming a trench filled structure including a first sacrificial layer along a surface of the trench, a second pipe gate along a surface of the first sacrificial layer, and a second sacrificial layer filled in a center area of the trench opened by the second pipe gate inside the trench, and forming a partition pipe gate disposed within the trench in a second direction crossing the first direction to divide the first sacrificial layer into first sacrificial patterns and to divide the second sacrificial layer into second sacrificial patterns.. ... Sk Hynix Inc

09/07/17 / #20170256589

Switching element, switching element array, and resistive random access memory including switching element, and methods of manufacturing the same

A first electrode and an insulation material layer are sequentially formed over a substrate. A doping mask pattern is formed over the insulation material layer. ... Sk Hynix Inc

09/07/17 / #20170256561

Semiconductor device and method of manufacturing the same

Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a lower layer and an etch catalyst layer which are sequentially stacked on a semiconductor substrate; a plurality of interlayer insulating layers and a plurality of conductive patterns, which are alternately stacked on the etch catalyst layer; and a channel plug passing through the plurality of interlayer insulating layers, the plurality of conductive patterns, and the etch catalyst layer, wherein inclination of a lower lateral wall of the channel plug is different from an inclination of an upper lateral wall of the channel plug.. ... Sk Hynix Inc

09/07/17 / #20170256559

Semiconductor device and manufacturing method for the same

A semiconductor device includes interlayer insulating layers and conductive patterns alternately stacked over a pipe gate, a first slit and a second slit penetrating the interlayer insulating layers and the conductive patterns and crossing each other, an etch stop pad groove overlapping an intersection of the first slit and the second slit, arranged in the pipe gate, and connected to the first slit or the second slit, and slit insulating layers filling the first slit, the second slit and the etch stop pad groove.. . ... Sk Hynix Inc

09/07/17 / #20170256556

Nonvolatile memory device and method for fabricating the same

A nonvolatile memory device includes cell strings, each including a plurality of memory cells over a substrate, extending in a direction, channel layers, connected with one sides and the other sides of the cell strings, extending in another direction perpendicular to the substrate, select gate electrodes, located over the cell strings, surrounding side surfaces of the channel layers with a gate dielectric layer interposed therebetween, and conductive lines connected with upper ends of the channel layers.. . ... Sk Hynix Inc

09/07/17 / #20170256326

Semiconductor memory device

A semiconductor memory device includes: a plurality of memory cell arrays each memory cell array including a first region, a second region, and a third region in the second region; and a repair controller suitable for storing a first repair address information, generating a first mode enable signal for accessing the third region by comparing the first repair address information with a row address during a first mode for a repair operation, and disabling the first mode enable signal in response to a refresh command regardless of a result of the comparing the first repair address information with the row address.. . ... Sk Hynix Inc

09/07/17 / #20170256294

Semiconductor device

A semiconductor device may be provided. The semiconductor device may include a first chip and a second chip. ... Sk Hynix Inc

09/07/17 / #20170256293

Sensing buffer, peripheral circuit, and/or memory device

A sensing buffer, or peripheral circuit or memory device may be provided. The sensing buffer may be configured to maintain a predetermined current according to a first current regardless of an external power supply and/or a temperature.. ... Sk Hynix Inc

09/07/17 / #20170255586

Data processing system and method for operating the same

A data processing system includes: a first memory system including a first memory device and a first controller for controlling the first memory device; a second memory system including a second memory device; a first connector suitable for supporting the first memory system to be coupled with the second memory system through a first connection method; a second connector suitable for supporting the second memory system to be coupled with the first memory system through a second connection method; and a third connector that couples the first memory system and the second memory system with each other.. . ... Sk Hynix Inc

09/07/17 / #20170255550

Data storage device and the operating method thereof

A method for operating a data storage device includes determining a valid page distribution characteristic of used memory blocks; and performing a garbage collection operation based on the valid page distribution characteristic of used memory blocks.. . ... Sk Hynix Inc

09/07/17 / #20170255413

Memory controller and method for managing memory

A method for managing a memory includes: receiving a write request from a host; selecting an internal storage region among a plurality of internal storage regions of the memory based on data characterization information of a data received from a host according to the write request from a host; generating a metadata including the data characterization information of the data according to the write request; and storing the metadata along with the data in the selected internal storage region.. . ... Sk Hynix Inc

09/07/17 / #20170254707

Temperature sensors

The temperature sensor includes a voltage generator and a temperature code generator. The voltage generator includes a first temperature element having a first resistance value and a second temperature element having a second resistance value and utilizes the first and second temperature elements to generate a temperature voltage signal having a voltage level that varies according to a variation in temperature. ... Sk Hynix Inc

08/31/17 / #20170250714

Error correction circuit and error correction method

An error correction method includes performing a first error correction operation, the first error correction operation including performing a syndrome check operation by calculating a syndrome matrix corresponding to a codeword based on a parity check matrix, performing a decoding operation for the codeword according to a result of the syndrome check operation, and iterating the decoding operation until the syndrome check operation is passed for a codeword acquired as the decoding operation is performed or an iteration count of the decoding operation reaches a threshold count; accumulating syndrome matrixes, which are calculated as the decoding operation is iterated, to an accumulation matrix; and performing a second error correction operation for a last codeword acquired through the iterating of the decoding operation for the codeword, based on the accumulation matrix, when the iteration count reaches the threshold count.. . ... Sk Hynix Inc

08/31/17 / #20170250696

Signal recovery circuit

A signal recovery circuit includes a clock code generation circuit configured to generate codes in response to an enable signal and a clock, and a pulse recovery circuit configured to generate an output pulse in response to an input pulse and the codes.. . ... Sk Hynix Inc

08/31/17 / #20170250694

Synchronization circuit and semiconductor apparatus including the same

A synchronization circuit may include: a delay line configured to delay a reference clock signal; a division circuit configured to generate a divided feedback clock signal by dividing a feedback clock signal at a division ratio which is set according to a division ratio control signal; a phase detection circuit configured to generate a phase detection signal by detecting the phase of the divided feedback clock signal based on the reference clock signal; and a delay line control circuit configured to control a delay time of the delay line according to the phase detection signal and the divided feedback clock signal.. . ... Sk Hynix Inc

08/31/17 / #20170250599

Internal voltage generation circuit and system including the same

An internal voltage generation circuit may be provided. The internal voltage generation circuit may include a first internal voltage generation circuit configured to provide a reference internal voltage to either an internal voltage control circuit or a node at which an output internal voltage is generated. ... Sk Hynix Inc

08/31/17 / #20170250337

Non-volatile memory device including ferroelectrics and method of manufacturing the same

A non-volatile memory device may include a semiconductor substrate, a ferroelectric layer, a source, a drain, a gate and a channel region. The semiconductor substrate may have a recess. ... Sk Hynix Inc

08/31/17 / #20170250196

Multi-level ferroelectric memory device and method of manufacturing the same

A ferroelectric memory device may include a semiconductor substrate, a plurality of ferroelectric layers, a source, a drain and a gate. The semiconductor substrate may have a recess. ... Sk Hynix Inc

08/31/17 / #20170249997

Test apparatus and semiconductor chip

A test apparatus may be provided. The test apparatus may include a delay compensator configured to generate delayed read data by delaying read data according to a difference between an external turnaround delay value provided externally from the test apparatus and a turnaround delay detection value detected within the test apparatus. ... Sk Hynix Inc

08/31/17 / #20170249980

Semiconductor apparatus including column selection signal generation circuit

A semiconductor apparatus may include a column select signal generation circuit and a control signal generation circuit. The column select signal generation circuit may generate a column select signal by driving an output node of the column select signal with a first drivability in response to a column decoding signal and adjust the first drivability according to a drivability control signal. ... Sk Hynix Inc

08/31/17 / #20170249977

Sense amplifier and input/output circuit of semiconductor apparatus including the same

A sense amplifier may be provided. The sense amplifier may include a first switch coupled between any one of a first signal line pair and a first power supply terminal. ... Sk Hynix Inc

08/31/17 / #20170249276

Integrated circuit system

An integrated circuit system includes a host device; and a memory module suitable for communicating with the host device according to a first protocol, the memory module comprising: at least one memory device suitable for storing data or outputting stored data, and executing communication according to a second protocol; and a protocol converter suitable for transferring information among the host device and the at least one memory device, wherein information to be inputted to the at least one memory device is transferred by being converted according to the second protocol and information to be outputted from the at least one memory device is transferred by being converted according to the first protocol.. . ... Sk Hynix Inc

08/31/17 / #20170249262

Semiconductor device, semiconductor system, and system

A semiconductor device, semiconductor system, and system may be provided. The semiconductor system may include one semiconductor device of a first semiconductor device and a second semiconductor device suitable for transmitting and receiving addresses and encrypted data. ... Sk Hynix Inc

08/31/17 / #20170249256

Memory controller and integrated circuit system

A memory controller includes a plurality of ports coupled with at least one host device; a plurality of channels coupled with at least one memory device; an arbiter suitable for receiving at least one first address received through the plurality of ports, and outputting the first address; a mapping table storage block including a plurality of address mapping tables, suitable for selecting an address mapping table corresponding to the first address among the plurality of address mapping tables and outputting the selected address mapping table as a variable address mapping table; an address mapping block suitable for mapping the first address to a second address according to the variable address mapping table and a fixed address mapping table; and a scheduler suitable for outputting the second address to the channels.. . ... Sk Hynix Inc

08/31/17 / #20170249209

Data storage device and operating method thereof

A data storage device includes at least one nonvolatile memory device; and a controller suitable for: generating parity data for data; performing a write operation for storing the data in at least one first memory region corresponding to at least one word line of the nonvolatile memory device; and selectively storing the parity data in at least one second memory region corresponding to the word line according to a size of the data, wherein the controller generates a plurality of parity data for the data according to respective types of the first memory region where the data are to be stored, and performs the write operation by storing parity data corresponding to respective types of the second memory region among the plurality of parity data, in the second memory region.. . ... Sk Hynix Inc

08/31/17 / #20170249208

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device including a target memory region; and a controller suitable for performing a read operation by reading a data chunk from the target memory region based on a read bias and performing an error correction operation for the data chunk, iterating the read operation according to a result of the error correction operation, and adjusting the read bias based on at least one read bias used in one or more previous read operations and at least one correction failure index corresponding to the at least one read bias.. . ... Sk Hynix Inc

08/31/17 / #20170249201

Controller of semiconductor memory device and method of operating the same

There are provided an electronic device, and more particularly, to a memory system capable of detecting transmission errors and a method of operating the same. The method of operating the controller configured to control the semiconductor memory device includes generating reception count information by counting a number of bits of a predetermined value of data received from the semiconductor memory device, requesting the semiconductor memory device to transmit transmission count information representing a number of bits of the predetermined value of the data transmitted by the semiconductor memory device and determining whether transmission errors are included in the received data based on the reception count information and the transmission count information.. ... Sk Hynix Inc

08/31/17 / #20170249104

Memory controller and request scheduling method using the same

A memory controller includes a plurality of request queues suitable for storing requests transmitted from corresponding host devices among a plurality of host devices; a token information generation unit suitable for generating informations on the numbers of first and second tokens corresponding to the plurality of respective host devices; and a request scheduler suitable for selecting repeatedly and sequentially the plurality of request queues, and outputting requests stored in a selected request queue, by using first and second tokens, wherein the request scheduler outputs one request per one first token and, when first tokens are consumed all, outputs one request per one second token.. . ... Sk Hynix Inc

08/31/17 / #20170248979

Semiconductor apparatus

A semiconductor apparatus includes a detection voltage generation circuit configured to generate a first detection voltage and a second detection voltage of which voltage levels are varied according to characteristics of a pmos transistor and an nmos transistor in response to a detection enable signal, a code generation circuit configured to generate a detection code in response to the voltage levels of the first and second detection voltages, a reference voltage generation circuit configured to generate a reference voltage in response to the detection code, an internal voltage generation circuit configured to generate an internal voltage in response to the reference voltage, and an internal circuit configured to operate by receiving the internal voltage.. . ... Sk Hynix Inc

08/24/17 / #20170244389

Input and output circuits and integrated circuits using the same

An input/output (i/o) circuit may be provided. The i/o circuit may include an input control circuit and an output control circuit. ... Sk Hynix Inc

08/24/17 / #20170243972

Semiconductor device including a pipe channel layer having a protruding portion

Disclosed is a semiconductor device, including: a first pipe gate; a second pipe gate on the first pipe gate; a stacked structure on the second pipe gate; a first channel layer including a first pipe channel layer positioned within the first pipe gate and first cell channel layers connected to the first pipe channel layer; a second channel layer including a second pipe channel layer positioned within the second pipe gate, and second cell channel layers connected to the second pipe channel layer; and a slit insulating layer passing through the stacked structure and positioned between the adjacent second cell channel layers, wherein the second pipe channel layer has a body portion and a protrusion portion extending below the body portion at a position below the slit insulating layer.. . ... Sk Hynix Inc

08/24/17 / #20170243881

Semiconductor device and method of manufacturing the same

Disclosed is a method of manufacturing a semiconductor device, including: forming a stacked structure including first material layers and second material layers alternately stacked on each other; forming a pillar passing through the stacked structure, the pillar including a protruding portion protruding above an uppermost surface of the stacked structure; forming a conductive layer surrounding the protruding portion of the pillar; and forming a conductive pattern in contact with the protruding portion of the pillar by oxidizing a surface of the conductive layer.. . ... Sk Hynix Inc

08/24/17 / #20170243871

Pattern forming method and semiconductor device manufacturing method using the same

A method for forming patterns includes forming an etch target layer; etching the etch target layer to form a pre-pattern having a line forming portion and a plurality of pad portions; forming a plurality of spacers which extend across the pad portions and the line forming portion; forming, over the spacers, a blocking layer having an opening which blocks the pad portions and exposes the line forming portion; and etching the line forming portion by using the blocking layer and the spacers as a barrier, to form a plurality of line portions.. . ... Sk Hynix Inc

08/24/17 / #20170243658

Semiconductor device and method of operating the same

A semiconductor device and a method of operating the same are provided. The method includes performing a program operation on a memory cell so that a threshold voltage of the memory cell is greater than a main verifying voltage, and while the program operation is performed, a bit line voltage applied to a bit line connected to the memory cell gradually increases based on the threshold voltage of the memory cell and the number of times a program voltage is applied to a word line connected to the memory cell.. ... Sk Hynix Inc

08/24/17 / #20170243653

Nand flash memory comprising current sensing page buffer

Disclosed herein is a nand flash memory comprising a bit-line and a page buffer, the page buffer comprising: a first switching circuit arranged between a first node and the bit-line; a third switching circuit arranged between the first node and a sensing node and configured to discharge the sensing node during an evaluation period, a pre-charging period preceding the evaluation period; and a fourth switching circuit configured to provide a first pre-charging path to the bit-line through the first node and the first switching circuit from a first voltage source during the pre-charging period, wherein the sensing node is configured to be charged through a second pre-charging path during the pre-charging period, and the second pre-charging path is separated from the first pre-charging path by the third switching circuit during the pre-charging period.. . ... Sk Hynix Inc

08/24/17 / #20170243651

Semiconductor device having sub-block stack structures

A semiconductor device includes sub-block stack structures respectively including source layers, where the sub-block stack structures are disposed to be spaced apart from each other along a first direction, a memory block stack structure including word lines stacked over the sub-block stack structures, the word lines being coupled to memory cells, the memory block stack structure extending along the first direction to overlap the sub-block stack structures, and channel layers respectively coupled to the source layers by penetrating the memory block stack structure.. . ... Sk Hynix Inc

08/24/17 / #20170243641

Resistive memory apparatus and voltage generating circuit therefor

A resistive memory apparatus may include a memory region including a plurality of resistive memory cells arranged in a plurality of memory cell pairs. The resistive memory apparatus may include a voltage generating circuit configured to generate a read voltage code based on a switching state of at least one memory cell pair. ... Sk Hynix Inc

08/24/17 / #20170243640

Nonvolatile memory devices having wide operation range

A nonvolatile memory device includes a nonvolatile memory cell and a variable resistive load portion. The variable resistive load portion is coupled between a bit line of the nonvolatile memory cell and a supply voltage line. ... Sk Hynix Inc

08/24/17 / #20170243639

Resistive memory device and method relating to a read voltage in accordance with variable situations

A resistive memory device and a method may be provided. The resistive memory device may include a reset voltage-detecting circuit, a set voltage-detecting circuit, a control circuit and a read voltage-generating circuit. ... Sk Hynix Inc

08/24/17 / #20170243632

Device for controlling a refresh operation to a plurality of banks in a semiconductor device

A refresh control device may include a plurality of latch circuits configured to receive an active signal, a refresh signal, an active control signal, and a refresh control signal, and output a word line enable signal for controlling a refresh operation to banks. The refresh control device may include a command decoder configured to decode a row address in correspondence to an external command signal and generate the active signal and the refresh signal. ... Sk Hynix Inc

08/24/17 / #20170242786

Memory system and operation method thereof

A memory system includes a memory device including a plurality of memory blocks and a controller suitable for selecting first memory blocks, the number of valid pages of which is equal to or less than a first threshold value, among the plurality of memory blocks, and performing a garbage collection operation on the first memory blocks based on error bit information of the first memory blocks.. . ... Sk Hynix Inc

08/24/17 / #20170242768

Controller of semiconductor memory device and method of operating the same

There are provided an electronic device, and more particularly, to a controller of a semiconductor memory device with an increased operation speed and a method of operating the same. The method of operating the controller configured to control the semiconductor memory device includes obtaining a recovery address in which recovered data stored in a page buffer of the semiconductor memory device in which the program fail is generated is to be stored, transmitting a recovery command requesting the semiconductor memory device to transmit the recovered data to the semiconductor memory device, and storing the recovered data in the recovery address. ... Sk Hynix Inc

08/24/17 / #20170242754

Semiconductor device

Semiconductor device including an input and output line control circuit may be provided. The input/output line control circuit may include a write connection circuit configured to transmit data of a write local line pair based on a write control signal. ... Sk Hynix Inc

08/24/17 / #20170242749

Semiconductor device and driving method thereof

A driving method of a semiconductor device and semiconductor device may be provided. The semiconductor device may include a cell array including a plurality of data areas. ... Sk Hynix Inc

08/24/17 / #20170242609

Memory system and operation method thereof

A memory system includes: a non-volatile memory device including a normal region in which most significant bits (msbs) and least significant bits (lsbs) stored in memory cells are accessed simultaneously, a hot region in which msbs stored in memory cells are accessed, and a cold region in which lsbs stored in memory cells are accessed; and a memory controller controlling the non-volatile memory device, herein, the memory controller includes: a read/write counter that counts the number of read operations and the number of write operations that are performed for each of logical cluster to thereby produce a counting result; and a region selector that maps each logical cluster to one among the normal region, the hot region and the cold region based on the counting result to thereby produce mapping data.. . ... Sk Hynix Inc

08/24/17 / #20170242600

Data storage device

A data storage device includes a host interface unit for generating a host request based on a request received from a host device; a control unit for generating a task based on the host request; and a memory control unit for controlling a nonvolatile memory device based on the task, wherein, when it is determined that an operation of the nonvolatile memory device has failed, the memory control unit transmits a fail information regarding the failed operation to the host interface unit.. . ... Sk Hynix Inc

08/24/17 / #20170242584

Method of dynamic table journaling

Embodiments of the disclosure are directed to a journaling scheme in a flash memory device. Advantageously, embodiments described can be used to keep the rebuild time of a flash translation layer (ftl) mapping table to a maximum upon restart from a sudden power-loss event.. ... Sk Hynix Inc

08/24/17 / #20170242332

Photomasks for reducing thermal stress generated by heat

A photomask includes a light transmission substrate having a transfer region and a frame region, a light-transmitting region exposing a portion of the light transmission substrate in the transfer region corresponding to a transfer pattern, a phase shift region surrounding the light-transmitting region in the transfer region. The phase shift region includes a first phase shift region surrounding the light-transmitting region and a second phase shift region surrounding the first phase shift region. ... Sk Hynix Inc

08/24/17 / #20170241917

Methods of defect inspection for photomasks

A method of defect inspection for a photomask is provided. According to the method, a light transmittance correction is performed to reduce a light transmittance of a calibration key pattern region of a photomask including a field region and the calibration key pattern region to the light transmittance of the field region. ... Sk Hynix Inc

08/17/17 / #20170237922

Image sensor and method for driving unit pixel of image sensor

A method of driving a unit pixel may include activating a transfer signal prior to an activation of a reset signal to boost a floating diffusion node of the unit pixel, during a first section of a photodiode reset period; and activating a reset signal using a hard reset, during a second section of the photodiode reset period.. . ... Sk Hynix Inc

08/17/17 / #20170237550

Clock data recovery circuit, integrated circuit including the same, and clock data recovery method

A clock data recovery circuit may include: a phase comparison unit suitable for comparing input data with a phase of a multi-phase clock, and for generating an up/down signal corresponding to the comparison result; a filtering unit suitable for counting the up/down signal based on an upper threshold value and a lower threshold value, for setting, when an overflow occurs, the lower threshold value to an initial value for the count of the up/down signal, or when a underflow occurs, the upper threshold value to the initial value for the count of the up/down signal, and for generating a control code corresponding to one of the underflow and the overflow; and a phase rotating unit suitable for adjusting the phase of the multi-phase clock in response to the control code outputted from the filtering unit.. . ... Sk Hynix Inc

08/17/17 / #20170237442

Clock generation circuit, interface circuit and semiconductor system using the same

A clock generation circuit may be provided. The clock generation circuit may include a master dll (delay locked loop) circuit, a code divider and a slave dll circuit. ... Sk Hynix Inc

08/17/17 / #20170237415

Buffer circuit

In an embodiment, a buffer circuit may includes a current source circuit, a self-bias generation circuit, a signal input circuit, and a first current sink circuit. The current source circuit may apply current to a first node and a second node in response to a self-bias voltage. ... Sk Hynix Inc

08/17/17 / #20170237342

Switched-capacitor dc-to-dc converters and methods of fabricating the same

A switched-capacitor dc-to-dc converter includes a logic cell and a capacitor cell vertically overlapping with the logic cell. The logic cell has a plurality of active elements disposed over a first substrate. ... Sk Hynix Inc

08/17/17 / #20170236999

Method for fabricating semiconductor device

A method for fabricating a semiconductor device includes: forming an inter-layer dielectric layer and a sacrificial layer over a substrate so that the sacrificial layer covers the inter-layer dielectric layer; forming a conductive pattern that is coupled with a portion of the substrate while penetrating through the inter-layer dielectric layer and the sacrificial layer; protruding a first portion of the conductive pattern by removing the sacrificial layer while maintaining a second portion of the conductive pattern inside the inter-layer dielectric layer; oxidizing the protruded first portion of the conductive pattern without oxidizing the second portion of the conductive pattern; removing the oxidized first portion of the conductive pattern to expose a top of the second portion of the conductive pattern; and forming a variable resistance element on top of the conductive pattern to couple a bottom of the variable resistance element with the top of the second portion of the conductive pattern.. . ... Sk Hynix Inc

08/17/17 / #20170236919

Electronic device including transistor and method for fabricating the same

A method for fabricating an electronic device is provided to include: forming a hard mask pattern over a substrate to expose a gate formation region; forming a gate trench by etching the substrate using the hard mask pattern; forming a gate insulating layer over an inner wall of the gate trench; forming a gate electrode filling a lower portion of the gate trench in which the gate insulating layer is formed; forming an insulating material covering a resultant structure in which the gate electrode is formed; forming a gate protective layer having a top surface lower than a bottom surface of the hard mask pattern; removing the hard mask pattern; recessing the substrate so that a top surface of the substrate is lower than the top surface of the gate protective layer; and forming a conductive pattern filling a space formed by the recessing of the substrate.. . ... Sk Hynix Inc

08/17/17 / #20170236831

Semiconductor device and method of manufacturing the same

A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first channel layers arranged in a first direction. ... Sk Hynix Inc

08/17/17 / #20170236829

Single-poly nonvolatile memory cells

A single-poly nonvolatile memory cell includes a coupling capacitor, a cell transistor and a selection transistor. The cell transistor has a floating gate, a first source, and a first drain. ... Sk Hynix Inc

08/17/17 / #20170236825

Semiconductor integrated circuit device with reservoir capacitors and method of manufacturing the same

A semiconductor integrated circuit device may include a semiconductor chip, a power line region and a reservoir capacitor. The semiconductor chip may include a cell region and a peripheral circuit region. ... Sk Hynix Inc

08/17/17 / #20170236598

Noise detection circuit and semiconductor system using the same

A noise detection circuit may include a divider configured to receive a clock signal and a clock bar signal, divide the clock signal and the clock bar signal, and generate a first divided signal and a second divided signal. The noise detection circuit may also include a noise detection reference block configured to reflect a power supply voltage level variation on the first divided signal and the second divided signal, and generate a first reference signal and a second reference signal, and a duty sensing unit configured to generate first duty information and second duty information of the clock signal in response to the first reference signal and the second reference signal. ... Sk Hynix Inc

08/17/17 / #20170236588

Memory chip and operating method thereof

There are provided a memory chip and an operating method thereof. A memory chip includes a main memory block including a plurality of sub-memory blocks, a peripheral circuit for programming memory cells included in the sub-memory blocks in units of pages, and a control circuit for controlling the peripheral circuit such that, after a program operation of a sub-memory block selected among the sub-memory blocks is completed, a program operation of a sub-memory block selected next among the sub-memory blocks is performed.. ... Sk Hynix Inc

08/17/17 / #20170236583

Semiconductor apparatus comprising a plurality of current sink units

A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.. . ... Sk Hynix Inc

08/17/17 / #20170236582

Semiconductor apparatus comprising a plurality of current sink units

A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.. . ... Sk Hynix Inc

08/17/17 / #20170236573

Semiconductor device including sense amplifier having power down

This technology relates to a semiconductor device. The semiconductor device may include a sense amplification unit suitable for sensing and amplifying data loaded onto a data line pair, and a voltage supply unit suitable for supplying a pull-down power line with a first voltage in response to a pull-down driving signal in an active mode, and for supplying the pull-down power line with a second voltage having a higher voltage level than the first voltage in response to the pull-down driving signal during an initial period of the active mode.. ... Sk Hynix Inc

08/17/17 / #20170236568

Electronic device

The semiconductor memory includes a plurality of word lines; and a plurality of columns including a plurality of resistive storage cells corresponding to the plurality of word lines, the plurality of columns being divided into a plurality of pages each having one or more columns; a memory circuit coupled to the semiconductor memory to sense data stored in the resistive storage cells; and a memory control circuit coupled to the semiconductor memory and the memory circuit to control sensing of the stored data by the memory circuit to, in a read operation, sense data of resistive storage cells included in a selected page by continuously active-precharging one or more word lines among the plurality of word lines in a period in which the selected page among the plurality of pages is activated.. . ... Sk Hynix Inc

08/17/17 / #20170235687

Data storage device and method thereof

A data storage device includes a nonvolatile memory device; a buffer memory for storing temporarily data to be transmitted from the nonvolatile memory device to a host device or data to be transmitted from the host device to the nonvolatile memory device; a memory control unit for performing a control operation for controlling the nonvolatile memory device; and a direct memory access (dma) unit for performing a data transmission operation associated with the buffer memory, according to control of the memory control unit, wherein the dma block transmits a first data from the nonvolatile memory device to the buffer memory, and wherein the dma unit transmits a second data from the nonvolatile memory device to the buffer memory, while the first data stored in the buffer memory is transmitted from the buffer memory to the host device.. . ... Sk Hynix Inc

08/17/17 / #20170235634

Semiconductor devices and semiconductor systems including the same

A semiconductor device may be provided. The semiconductor device may include an error correction control circuit and a signal storage circuit. ... Sk Hynix Inc

08/17/17 / #20170235488

Window based mapping

Window based mapping is used to reduce the usage of volatile memory for storing the mapping of logical to physical addresses for accesses to data in a flash drive. Two separate mapping tables for translation of logical addresses to physical addresses (l2p), e.g., an l2p front map and an l2p back map, are used where the l2p front map acts as a window to the l2p back map. ... Sk Hynix Inc

08/17/17 / #20170235487

Memory system and operation method thereof

A memory device includes: a memory including a plurality of blocks, each including a plurality of pages; and a control logic that controls a read operation and a copy-back operation on the memory based on a combination of a block read operation number and a page read operation number.. . ... Sk Hynix Inc

08/17/17 / #20170235324

Voltage generation circuit and integrated circuit including the same

A voltage generation circuit includes: a periodic wave generator that generates an on/off signal that is periodically enabled/disabled, where at least one between a period and a duty cycle of the on/off signal is controlled based on at least one information among temperature information, capacitance information, leakage current information, speed information, and voltage level information; and an internal voltage generator that is enabled/disabled in response to the on/off signal and generates an internal voltage.. . ... Sk Hynix Inc

08/10/17 / #20170230040

Duty correction circuit

A duty correction circuit may be provided. The duty correction circuit may include a control circuit configured to generate a duty correction control signal by detecting edges of first and second differential clock signals. ... Sk Hynix Inc

08/10/17 / #20170230039

Clock generating circuit and semiconductor apparatus including the same

A clock generation circuit may include a first clock generator, a second clock generator, and a common mode generator. The first clock generator may generate a multi-phase clock signal from a first clock signal. ... Sk Hynix Inc

08/10/17 / #20170230036

Phase and frequency control circuit and system including the same

A phase and frequency control circuit may be provided. The phase and frequency control circuit may include a division circuit configured to generate a plurality of divided signals by dividing an input signal. ... Sk Hynix Inc

08/10/17 / #20170230018

Receiver circuit and system using the same

A receiver circuit may be provided. The receiver circuit may include a first duty cycle adjuster configured to correct a duty cycle of a first output signal pair. ... Sk Hynix Inc

08/10/17 / #20170229477

Semiconductor device and method of manufacturing the same

A semiconductor device may include pipe channel layer, and a pipe gate surrounding the pipe channel layer. The semiconductor device may include an oxidization layer formed between the pipe gate and the pipe channel layer. ... Sk Hynix Inc

08/10/17 / #20170229471

Single poly nonvolatile memory cells, arrays thereof, and methods of operating the same

A single poly nvm cell includes a first n-type well region and a second n-type well region spaced apart from each other by a p-type semiconductor layer, a first active region and a second active region disposed in the first n-type well region and the second n-type well region, respectively, a p-channel floating gate transistor including a floating gate disposed in the first active region, a p-type drain region disposed in the first active region, and a p-type junction region disposed in the first active region, wherein the floating gate extends to over the second active region, a p-channel read selection transistor including a read selection gate electrode disposed in the first active region, the p-type junction region disposed in the first active region, and a p-type source region disposed in the first active region, and an interconnection line connecting the first n-type well region to the p-type source region of the p-channel read selection transistor.. . ... Sk Hynix Inc

08/10/17 / #20170229395

Fuse structure having multiple air dummy fuses

A fuse structure includes a fusing line including a first portion, a second portion, and a central portion between the first portion and the second portion; and a dummy fuse neighboring the fusing line, the dummy fuse may include: a first air dummy fuse including a plurality of first air gaps extending in a first direction parallel to the fusing line; and a second air dummy fuse including a second air gap extending in a second direction crossing the fusing line.. . ... Sk Hynix Inc

08/10/17 / #20170229189

Semiconductor memory device and operating method thereof

There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device may include a memory cell array, a peripheral circuit, a control logic, and one or more programs. ... Sk Hynix Inc

08/10/17 / #20170229185

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation or erase operation of the memory cell array, and a control logic controlling the peripheral circuit. The control logic controls the peripheral circuit such that a first program allowable voltage applied to bit lines of the memory cell array during a first program operation of the program operation and a second program allowable voltage applied during a second program operation of the program operation are different from each other.. ... Sk Hynix Inc

08/10/17 / #20170229168

Nonvolatile memory system and sequential reading and programming methods thereof

A nonvolatile memory device includes a multi-level cell which stores m-bit data at a time and m number of latches for respectively storing m-bit data on a single bit basis. A controller sequentially latches m-bit data of the multi-level cell into the m number of latches, respectively, during a first half read period, and sequentially outputs the latched m-bit data in the m number of latches during a second half read period.. ... Sk Hynix Inc

08/10/17 / #20170229164

Refresh verification circuit, semiconductor apparatus and semiconductor system

A refresh verification circuit may include a filtering circuit configured to receive a refresh pulse and to generate a filtering pulse in response to a duration of the enable period of the refresh pulse.. . ... Sk Hynix Inc

08/10/17 / #20170228176

Data storage device

A data storage device includes a first memory device including an operation information region for an original operation information, and suitable for performing a first initialization operation based on the original operation information and a controller suitable for performing a management operation to the original operation information, wherein the original operation information of the operation information region is prohibited from being changed until completion of the management operation.. . ... Sk Hynix Inc

08/10/17 / #20170227605

Stack type semiconductor apparatus and system including the stack type semiconductor apparatus

A stack type semiconductor apparatus may be provided. The stack type semiconductor apparatus may include a plurality of semiconductor chips stacked and configured for transferring signals through through-hole vias. ... Sk Hynix Inc

08/03/17 / #20170223295

Analog-digital converter and method, and image sensor including the same

An analog-digital converter may include a comparator suitable for comparing an input signal to a ramp signal to repetitively output a comparison signal a number of times corresponding to an analog gain for an analog-digital conversion; a counter receiving the repetitively outputted comparison signal from the comparator, the counter being suitable for performing a counting operation based on the repetitively outputted comparison signal; and a counting limiter suitable for limiting the counted number of bits by a maximum counted bit number of the counter.. . ... Sk Hynix Inc

08/03/17 / #20170223294

Image sensing device and method for driving the same

An image sensing device includes a plurality of pixel groups, each pixel group including two or more neighboring pixels, and a controller suitable for controlling the pixel groups on a basis of a frame unit, wherein a readout order of the pixels in each of the pixel groups is different between present and next frames.. . ... Sk Hynix Inc

08/03/17 / #20170223284

Image sensing device and method for driving the same

An image sensing device includes: a pixel suitable for generating a pixel signal based on a first driving voltage; a ramp signal generation block based on a variable resistance, the ramp signal generation block being suitable for generating a ramp signal whose slope is controlled by a resistance value varied according to an analog gain; a noise compensation block based on a fixed resistance suitable for sensing a noise component included in the first driving voltage to generate a noise signal and reflecting the noise signal in the ramp signal; and a digital processing block suitable for generating a digital signal based on the pixel signal and the ramp signal.. . ... Sk Hynix Inc

08/03/17 / #20170222662

Data dependency mitigation in decoder architecture for generalized product codes for flash storage

A memory device includes a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform coarse decoding and fine decoding. ... Sk Hynix Inc

08/03/17 / #20170221919

Semiconductor device

A semiconductor device includes a substrate including a cell region and a peripheral region adjacent to the cell region, a cell stack structure located in the cell region, the cell stack structure including vertical memory strings, a circuit located in the peripheral region, the circuit driving the vertical memory strings, and an interlayer insulating layer formed on the substrate to cover the cell stack structure and the circuit, and including air gaps located between the cell region and the peripheral region.. . ... Sk Hynix Inc

08/03/17 / #20170221868

Manufacturing methods semiconductor packages including through mold connectors

A semiconductor package structure and a method for manufacturing the same are provided. According to the method, a first mold layer is formed to cover a first semiconductor chip and a first bumps. ... Sk Hynix Inc

08/03/17 / #20170221585

Current sensing circuit and memory device having the same

There are provided a current sensing circuit and a memory device having the same. A current sensing circuit includes a current mirror unit suitable for outputting a first voltage and a second voltage; a chunk current controller suitable for generating the first voltage by generating a current through at least one page buffer; a fail bit counter suitable for adjusting a current at a first node where the first voltage is output in response to fail bits received from the page buffer; an allowed bit counter suitable for adjusting the current at the first node according to predetermined allowed bits; and a target range setting unit suitable for adjusting a current at a second node where the second voltage is output in response to a target code.. ... Sk Hynix Inc

08/03/17 / #20170221583

Data storage device and operating method thereof

A method for operating a data storage device includes obtaining test data from a target region of a memory block by applying a test bias simultaneously to all word lines of the memory block; and estimating a state of the memory block based on the test data.. . ... Sk Hynix Inc

08/03/17 / #20170221571

Semiconductor memory device and method of operating the same

There may be provided an electronic device, and more particularly, a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory cells. ... Sk Hynix Inc

08/03/17 / #20170221570

Nonvolatile memory device and operating method of data storage device including the same

A nonvolatile memory device includes a memory block including a plurality of memory cells which are coupled to a plurality of word lines; and a control unit configured to perform a read operation in response to a read command for target memory cells which are coupled to a target word line, wherein the control unit performs the read operation by applying a read bias voltage to the target word line, applying a first pass bias to a monitoring word line, applying a second pass bias to one or more adjacent word lines adjacent to the target word line, and applying a third pass bias to remaining word lines.. . ... Sk Hynix Inc

08/03/17 / #20170221557

Electronic device and method for fabricating the same

An electronic device comprising a semiconductor memory unit that includes a resistance variable element formed over a substrate, and including stacked therein a bottom electrode, a variable resistance layer and a top electrode, and a barrier layer formed over the resistance variable element, and including an amorphous silicon layer which is doped with at least one kind of impurity.. . ... Sk Hynix Inc

08/03/17 / #20170221545

Memory device and system including the same

A memory device may include: an active controller configured to output a row active signal in response to a refresh control signal and a row enable signal when an active signal is activated; a refresh controller configured to generate and store a flag bit for controlling a refresh operation in response to a refresh signal, a precharge signal, and a precharge stop signal, and output the row enable signal corresponding to the stored flag bit to the active controller; and a cell array circuit configured to perform a refresh operation in memory cell array areas in response to the row active signal.. . ... Sk Hynix Inc

08/03/17 / #20170221539

Electronic device

An electronic device including an inverter includes a pull-up driving unit configured to drive an output node with a high voltage in response to an input signal; a path switching unit coupled in a path between the pull-up driving unit and the output node according to a direction of a first current flowing between the pull-up driving unit and the output node and operable to selectively switch on or off the path; a pull-down driving unit coupled to the output node to supply a low voltage in response to the input signal; a path blocking unit coupled in a path between the pull-down driving unit and the output node to block the path; and a bypass unit coupled to form a bypass path between the pull-down driving unit and the output node.. . ... Sk Hynix Inc

08/03/17 / #20170220497

System and method for operating the same

A system includes a central processing unit (cpu); main and auxiliary storage devices coupled to a plurality of memory ports; a memory bus suitable for coupling the cpu and the plurality of memory ports; and a memory controller suitable for, when the cpu calls data stored in the auxiliary storage device, controlling the called data to be transferred from the auxiliary storage device to the main storage device and stored in the main storage device.. . ... Sk Hynix Inc

08/03/17 / #20170220472

Memory system and operation method thereof

A memory system may include a plurality of first and second memory devices each comprising m-bit multi-level cells (mlcs), m-bit multi-buffers, and transmission buffers, a cache memory suitable for caching data inputted to or outputted from the plurality of first and second memory devices, and a controller suitable for programming program data cached by the cache memory to a memory device selected among the first and second memory devices by transferring the program data to m-bit multi-buffers of the selected memory device whenever the program data are cached by m bits into the cache memory, and controlling the selected memory device to perform a necessary preparation operation, except for a secondary preparation operation, of a program preparation operation, until an input of the program data is ended or the m-bit multi-buffers of the selected memory device are full.. . ... Sk Hynix Inc

08/03/17 / #20170220465

Memory system and operating method thereof

A memory system supporting an interleaving operation including: a plurality of memory devices; and a controller suitable for detecting whether, among a plurality of logical address groups inputted to perform a read or write operation in the plurality of memory devices, first logical address groups having values related to each other are inputted, and for adjusting, when physical storage locations of data corresponding to logical addresses of the first logical address groups are inaccessible using interleaving, the physical storage locations of the data to locations that are accessible using interleaving and store the data in adjusted locations.. . ... Sk Hynix Inc

08/03/17 / #20170220413

Memory system, semiconductor memory device and operating method thereof

A semiconductor memory device may include: a memory cell array comprising: a content addressable memory (cam) cell block including cam cells storing option information including operation setting information for controlling an operation of the semiconductor memory device, and error check information for the operation setting information; and memory blocks including memory cells for storing data; an error detection unit suitable for reading out, in response to a cam read command, the operation setting information and the error check information stored in the cam cell block and outputting an error detection signal indicating whether there is an error; and a control logic suitable for determining and outputting a state of a ready/busy signal depending on the error detection signal.. . ... Sk Hynix Inc

08/03/17 / #20170220294

Memory system

A memory system includes a memory controller, a first memory module including first and second groups of first memory chips, a second memory module including first and second groups of second memory chips, and a channel including a first group of signal lines suitable for coupling the memory controller with the first memory module, and a second group of signal lines suitable for coupling the memory controller with the second memory module.. . ... Sk Hynix Inc

08/03/17 / #20170220274

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device including a memory block, to which a write operation is interrupted and not completed due to at least one time occurrence of sudden power-off (spo) of the data storage device, wherein the memory block includes at least one first valid page group including one or more valid pages caused before the interruption and at least one invalid page group having one or more invalid pages caused by the interruption; and a controller suitable for writing at least one physical address-to-logical address (p2l) list for the first valid page group into the invalid page group after power-on of the data storage device following the spo, and recovering an address mapping table for the memory block based on the p2l list after completion of the write operation to the memory block.. . ... Sk Hynix Inc

08/03/17 / #20170220251

Memory system and method of operating the same

A memory system in accordance with an embodiment may include a memory chip and a controller. The memory chip may store data in a plurality of logical pages by performing a sensing operation on a selected page in response to commands and performing an output operation of the data. ... Sk Hynix Inc

08/03/17 / #20170219643

Jitter detection circuit and semiconductor system using the same

A semiconductor system may include a first semiconductor device configured to output a clock, receive and output data, and detect a jitter of a transmission path according to a level combination of a plurality of monitoring signals. The semiconductor system may also include a second semiconductor device configured to generate the plurality of monitoring signals of which the level combination is changed according to phase differences between an internal clock generated through the transmission path for transmitting the clock and a plurality of divided clocks obtained by dividing the frequency of the clock.. ... Sk Hynix Inc

07/27/17 / #20170214868

Pixel biasing device for canceling ground noise of ramp signal and image sensor including the same

A pixel biasing device includes a ramp ground noise unit, a bias current generation unit, and a pixel biasing unit; the ramp ground noise unit being suitable for generating a ramp ground noise and for transferring the ramp ground noise to the bias current generation unit; the bias current generation unit being suitable for generating a bias current by combining an inputted reference current with the ramp ground noise received from the ramp ground noise unit; and the pixel biasing unit being suitable for performing a biasing operation on an inputted pixel signal based on the bias current.. . ... Sk Hynix Inc

07/27/17 / #20170213958

Switching device, method of fabricating the same, and resistive random access memory including the switching device as a selection device

A switching device includes a first electrode and a second electrode that are disposed over a substrate, and an electrolyte layer disposed between the first electrode and the second electrode and including a porous oxide. The switching device performs threshold switching operation on the basis of oxidation-reduction reactions of metal ions that are provided from the first electrode or the second electrode to the electrolyte layer.. ... Sk Hynix Inc

07/27/17 / #20170213846

Semiconductor device

The semiconductor device according to the embodiments of the present disclosure may include a contact line connecting a pair of channel pillars with a silt disposed therebetween. The contact line may extend in various directions, for example, a diagonal direction with respect to the slit. ... Sk Hynix Inc

07/27/17 / #20170213844

Semiconductor device and method of manufacturing the same

In an embodiment, the semiconductor device may include interlayer insulating layers, conductive patterns, a channel layer, cell blocking insulating layers, dummy blocking insulating layers, and a data storage layer. The interlayer insulating layers and conductive patterns may be alternately stacked. ... Sk Hynix Inc

07/27/17 / #20170213843

Semiconductor device and method of manufacturing the same

There is provided a semiconductor device. The semiconductor device includes a source layer, a well pickup layer formed on the source layer, a body structure formed on the well pickup layer and including a well region contacting the well pickup layer and first junctions formed on side walls of the body structure, channel pillars contacting the body structure and protruding from the body structure, and contact layers formed on the side walls of the body structure and electrically connecting the body structure and the well pickup layer.. ... Sk Hynix Inc

07/27/17 / #20170213789

Semiconductor device

A semiconductor device includes a signal transmission line extending in a first direction; an outer protective line extending in a substantially identical direction as the first direction and spaced apart from the signal transmission line by a predetermined distance along a second direction which is substantially perpendicular to the first direction; and an inner protective line, disposed between the outer protective line and the signal transmission line, and intermittently extending substantially in parallel with said signal transmission line and outer protective line.. . ... Sk Hynix Inc

07/27/17 / #20170213595

Nonvolatile memory cells having lateral coupling structures and nonvolatile memory cell arrays including the same

A nonvolatile memory (nvm) cell includes a selection transistor configured to have a selection gate terminal coupled to a word line and a source terminal coupled to a source line, a cell transistor configured to have a floating gate electrically isolated, a drain terminal coupled to a bit line and sharing a junction terminal with the selection transistor, a first coupling capacitor disposed in a first connection line coupled between the word line and the floating gate, and a p-n diode and a second coupling capacitor disposed in series in a second connection line coupled between the word line and the floating gate. An anode and a cathode of the p-n diode are coupled to the second coupling capacitor and the word line, respectively. ... Sk Hynix Inc

07/27/17 / #20170212816

Semiconductor memory device and data storage device including the same

A data storage device includes a semiconductor memory device including a memory cell array which includes a main cell area and a spare cell area; and a controller coupled with the semiconductor memory device through a plurality of main data lines and at least one spare data line, and configured to transmit main data to be stored in the main cell area, through the plurality of main data lines, and transmit spare data for managing the main data to be stored in the spare cell area, through the spare data line.. . ... Sk Hynix Inc

07/27/17 / #20170212709

Memory system and operation method for the same

A memory device includes a memory unit comprising one or more storage regions, and a control logic suitable for generating status information representing individualized states for the one or more storage regions.. . ... Sk Hynix Inc

07/20/17 / #20170208282

Image sensing device and method for driving the same

An image sensing device includes: a floating diffusion node; an initialization block suitable for initializing the floating diffusion node with a first voltage, based on an initialization control signal; a boosting block suitable for boosting the floating diffusion node with a second voltage, based on a boost control signal; a photodiode suitable for generating a photocharge based on incident light; a transmission block suitable for transmitting the photocharge to the floating diffusion node based on a transmission control signal; and a selection block suitable for generating a pixel signal corresponding to a voltage loaded on the floating diffusion node based on a selection control signal.. . ... Sk Hynix Inc

07/20/17 / #20170208281

Pixel, image sensing device including the pixel and method for driving the image sensing device

A pixel includes: a charge transmission node; an initialization block suitable for initializing the charge transmission node with a first voltage during a data initialization period; a photodiode suitable for generating a photocharge based on incident light during an exposure period; a transmission block suitable for transmitting the photocharge to the charge transmission node during a transmission period; a first accumulation block suitable for boosting the charge transmission node with a second voltage during a boosting period and accumulating the photocharge transmitted to the charge transmission node during the transmission period; and a selection block suitable for generating a pixel signal corresponding to a voltage loaded on the charge transmission node during a selection period.. . ... Sk Hynix Inc

07/20/17 / #20170208280

Pixel apparatus, operation method thereof and image sensor using the same

A pixel apparatus may include a pixel unit suitable for outputting a pixel signal corresponding to incident light, a voltage supply unit suitable for supplying a reset voltage for a floating diffusion (fd) node of the pixel unit, and a voltage switching unit suitable for transferring the reset voltage from the voltage supply unit to the pixel unit during a first period from an exposure start time to just before a readout time, in response to a control signal.. . ... Sk Hynix Inc

07/20/17 / #20170207235

Method of manufacturing semiconductor device

Disclosed is a method of manufacturing a semiconductor device, including: forming a multi-layered stack; forming a vertical hole in the stack; forming a plurality of material layers over a bottom and a sidewall of the vertical hole, wherein the plurality of material layers includes a first material layer and a second material layer, wherein the second material layer is provided under the first material layer; patterning the first material layer located over the bottom of the vertical hole to form a first opening, wherein the first opening exposes the second material layer; and patterning the second material layer exposed by the first opening using a difference in an etch rate between the first material layer and the second material layer.. . ... Sk Hynix Inc

07/20/17 / #20170207229

Voltage switching circuit and semiconductor apparatus including the same

A voltage switching circuit includes: a control signal generation block configured to include a high voltage switching block which controls an electric current flowing according to a high voltage in response to a voltage level of a low voltage control signal and generates complementary high voltage control signals; and a high voltage transfer block configured to be driven according to the complementary high voltage control signals, and generate a switching signal, the voltage level of which is raised based on the high voltage so that the switching signal has substantially the same level as the high voltage.. . ... Sk Hynix Inc

07/20/17 / #20170207226

Semiconductor device

A semiconductor device may include a source layer, a stack structure, a channel layer, a slit, and a source pick-up line. The source layer may include at least one groove in an upper surface thereof. ... Sk Hynix Inc

07/20/17 / #20170207119

Method of manufacturing semiconductor device

Disclosed is a method of manufacturing a semiconductor device, including: forming a stacked structure including a plurality of layers, the stacked structure including a cell region, and first and second contact regions; forming a first mask pattern covering the cell region and the second contact region of the stacked structure; forming steps of n layers at a boundary of the cell region and the first contact region, where n is a natural number greater than or equal to 1; forming a second mask pattern on the stacked structure, wherein the second mask pattern covers the cell region and the formed steps and is expanded to partially cover the first and second contact regions; and etching the stacked structure by k layers by using the second mask pattern as an etch barrier, where k is a natural number greater than or equal to 2.. . ... Sk Hynix Inc

07/20/17 / #20170207098

Semiconductor integrated circuit device with a surface and method of manufacturing the same

A semiconductor integrated circuit device and a method of manufacturing the same are disclosed. A semiconductor wafer having a surface step is prepared. ... Sk Hynix Inc

07/20/17 / #20170206966

Semiconductor memory device and operating method thereof

In an embodiment, a method of operating a semiconductor memory device may include performing a read operation on a selected memory block, and, during the read operation, enabling local select lines to float so that potential levels of local word lines coupled to unselected memory blocks is increased.. . ... Sk Hynix Inc

07/20/17 / #20170206961

Electronic device and method for driving the same

An electronic device including a semiconductor memory may be provided. The semiconductor memory may include a write circuit configured for generating a first current. ... Sk Hynix Inc

07/20/17 / #20170206944

Bitline senseamplifier and semiconductor memory apparatus using the same

A memory apparatus may include a bit line sense-amplifier coupled to first and second bit lines; a first precharge unit suitable for coupling the first and second bit lines in response to a bit line equalization signal; a sense-amplifier power control unit suitable for providing a plurality of powers to the bit line sense-amplifier in response to a power control signal; and a second precharge unit suitable for individually changing each voltage level of the first and second bit lines based on a precharge control signal.. . ... Sk Hynix Inc

07/20/17 / #20170206943

Bitline senseamplifier and semiconductor memory apparatus using the same

A memory apparatus may include a bit line sense-amplifier coupled to first and second bit lines; a first precharge unit suitable for coupling the first and second bit lines in response to a bit line equalization signal; a sense-amplifier power control unit suitable for providing a plurality of powers to the bit line sense-amplifier in response to a power control signal; and a second precharge unit suitable for individually changing each voltage level of the first and second bit lines based on a precharge control signal.. . ... Sk Hynix Inc

07/20/17 / #20170206940

Semiconductor device

A semiconductor device may be provided. The semiconductor device may include a first chip and a second chip. ... Sk Hynix Inc

07/20/17 / #20170206172

Tehcniques with os- and application- transparent memory compression

Memory systems may include a memory storage including a fast memory portion and a slow memory portion, a software page remapping kernel driver (sprkd) suitable for intercepting a memory management command generated by an operating system, at least one of compressing data to be written from the fast memory portion to the slow memory portion prior to execution of the operating system memory management command, and decompressing data to be written from the slow memory portion to the fast memory portion prior to execution of the operating system memory management command, and transferring either the compressed data to be written to the slow memory portion or the decompressed data to be written to the fast memory portion, and a controller suitable for executing the memory management command after the transferring by the sprkd such that the compressing or decompressing of data is performed transparent to the operating system.. . ... Sk Hynix Inc

07/20/17 / #20170206037

Memory device and method of operating the same

Disclosed herein is a memory system including: a plurality of memory chips coupled to a plurality of input/output lines included in a channel and output ready/busy signals to the input/output lines in response to a status check command; and a memory controller configured to transmit the status check command to the memory chips through the channel and simultaneously determine an operation status of the memory chips depending on the ready/busy signals received through the input/output lines.. . ... Sk Hynix Inc

07/20/17 / #20170206033

Mechanism enabling the use of slow memory to achieve byte addressability and near-dram performance with page remapping scheme

Memory systems may include a memory storage including a dynamic random access memory (dram) portion, a non-volatile memory (nvm) portion, and a virtual memory (vm), a software page remapping kernel driver (sprkd) suitable for intercepting a memory management command, the memory management command including an access to a virtual address location of the vm, and remapping the virtual address location from a physical address of the nvm portion mapped to the virtual address location to a physical address of the dram portion, and a controller suitable for executing the memory management command by accessing the physical address of the dram portion to which the virtual address location is remapped.. . ... Sk Hynix Inc

07/20/17 / #20170206032

Data storage device and operating method thereof

A method for operating a data storage device including a plurality of memory regions. The method includes performing a read operation for a first memory region, increasing a read count based on read sequences of the first memory region and a second memory region which has been read before the read operation for the first memory region, and performing a management operation for the plurality of memory regions based on the read count.. ... Sk Hynix Inc

07/20/17 / #20170206007

Memory system and operating method of memory system

This technology relates to a memory system for processing data into a memory device and an operating method of the memory system. The memory system may include a memory device; and a controller suitable for: performing a command operation to the memory device in response to a command, calculating a foreground operation workload corresponding to the command, calculating a memory available workload of the memory device for the command operation, and dynamically determining priority and workload for the command operation based on the foreground operation workload and the memory available workload.. ... Sk Hynix Inc

07/13/17 / #20170201238

Semiconductor device

A semiconductor device may include: a pre-driving unit suitable for transmitting input data to a first node in response to a first control signal; a main driving unit suitable for outputting the input data transmitted to the first node, using a first voltage as a driving voltage; and a bias control unit suitable for supplying a second voltage to the first node in response to a second control signal, the second voltage having a different level from the first voltage.. . ... Sk Hynix Inc

07/13/17 / #20170200888

Switching device and resistive random access memory including the same

A switching device includes a first electrode and a second electrode, and an electrolyte layer disposed between the first electrode and the second electrode. The electrolyte layer includes a first layer charged with negative charges and a second layer charged with positive charges.. ... Sk Hynix Inc

07/13/17 / #20170200883

Electronic device and method of fabricating the same

An electronic device includes a semiconductor memory, wherein the semiconductor memory includes a variable resistance element formed over a substrate, and a multi-layer passivation layer positioned over sidewalls of the variable resistance element and having two or more insulating layers formed over the sidewalls of the variable resistance element.. . ... Sk Hynix Inc

07/13/17 / #20170200761

Image sensor

The present invention provides an image sensor. An image sensor include a pixel array. ... Sk Hynix Inc

07/13/17 / #20170200733

Semiconductor device and manufacturing method thereof

A semiconductor device includes bit lines extending along a first direction, the bit lines being arranged along a second direction intersecting the first direction, a plurality of channel layers disposed under the bit lines, the plurality of channel layers extending in a third direction perpendicular to a plane extending along the first and second directions and spaced apart along the second direction, so that each channel layer is at least partially overlapped with at least two of the bit lines, and a contact plug extending, from the channel layer, toward one of the bit lines overlapped with the channel layer.. . ... Sk Hynix Inc

07/13/17 / #20170200688

Semiconductor package having a bump bonding structure

A semiconductor package may be provided. The semiconductor package may include a substrate having a first surface over which bond fingers are arranged, the other surface facing away from the first surface and over which ball lands are arranged, and terminals which are respectively formed over the bond fingers. ... Sk Hynix Inc

07/13/17 / #20170200611

Manufacturing method of memory device

A manufacturing method for a memory device includes forming a stack structure over a substrate, forming a mask pattern over the stack structure, forming a first vertical hole by patterning the stack structure using the mask pattern, implanting a dopant into a sidewall of the first vertical hole to form a first region, wherein the first region is exposed by the mask pattern; and removing the first region to form a second vertical hole.. . ... Sk Hynix Inc

07/13/17 / #20170200504

Semiconductor memory device and operating method thereof

Provided herein are a semiconductor memory device and an operating method thereof. The semiconductor memory device may include: drain select transistor coupled to a bit line; a source select transistor coupled to a source line; a plurality of memory cells coupled in series between the drain select transistor and the source select transistor; and a peripheral circuit configured to successively apply a discharge control voltage to memory cells in sequence from a memory cell adjacent to the source select transistor to a memory cell adjacent to the drain select transistor.. ... Sk Hynix Inc

07/13/17 / #20170200488

Semiconductor device and operating method thereof

A semiconductor memory device includes a plurality of memory cell blocks each including a plurality of word lines and suitable for being selectively activated based on an active command and a row address, wherein word lines are selected from the respective activated memory cell blocks based on the active command and the row address, and a column decoding block sequentially accessing the activated memory cell blocks to input/output data thereof by decoding a column address based on the row address.. . ... Sk Hynix Inc

07/13/17 / #20170200487

Electronic device

Disclosed are an electronic device comprising a semiconductor memory. The semiconductor memory includes a variable resistance element including a free layer having a variable magnetization direction; a pinned layer having a fixed magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer includes: a first free layer adjacent to the tunnel barrier layer and having a perpendicular magnetic anisotropy at an interface with the tunnel barrier layer; and a second free layer spaced apart from the tunnel barrier layer by the first free layer and having a saturation magnetization lower than a saturation magnetization of the first free layer.. ... Sk Hynix Inc

07/13/17 / #20170200485

Semiconductor devices and semiconductor systems including the same

A semiconductor device may include a strobe signal buffer, a strobe signal division circuit, and a drive control circuit. The strobe signal buffer may buffer a first data strobe signal and a second data strobe signal to generate a buffer output signal and an inverted buffer output signal. ... Sk Hynix Inc

07/13/17 / #20170200481

Semiconductor memory apparatus

A semiconductor memory apparatus includes an input/output pad, a first data input/output circuit, a first data transfer circuit, a second data transfer circuit, and a test data comparison circuit. The input/output pad may be coupled to an external equipment. ... Sk Hynix Inc

07/13/17 / #20170200480

Voltage regulator, memory system having the same and operating method thereof

Provided herein are a voltage regulator, a memory system having the same and an operation method thereof. The memory system includes a memory device configured to store data, a controller configured to control the memory device, and a voltage regulator configured to supply a pump-out voltage to the memory device or the controller so that the memory device or the controller is operated in the following manner: until a level of the pump-out voltage is increased to a second reference voltage lower than a first reference voltage, the pump-out voltage is output using a clock having a first frequency; when the pump-out voltage exceeds the second reference voltage and does not exceed the first reference voltage, the pump-out voltage is output using a clock having a second frequency lower than the first frequency; and when the pump-out voltage exceeds the first reference voltage, the pump-out voltage is output using the clock having the first frequency.. ... Sk Hynix Inc

07/13/17 / #20170199954

Apparatus for modeling resistive memory devices

An apparatus for modeling a resistive memory device may include a first model circuit and a second model circuit. The first model circuit may include a current-voltage characteristic-embodying circuit, a phase-expressing circuit, and a characteristic-expressing circuit. ... Sk Hynix Inc

07/13/17 / #20170199783

Data storage device and operating method thereof

A method for operating a data storage device includes reading a plurality of data chunks from a plurality of pages corresponding to target memory cells coupled to a target word line based on read biases; obtaining discrimination data corresponding to the target memory cells based on discrimination biases; determining an unreliable bit in a target data chunk among the plurality of data chunks based on the plurality of data chunks and the discrimination data; and determining whether the unreliable bit is an error bit.. . ... Sk Hynix Inc

07/13/17 / #20170199691

Memory module

A memory module may include a plurality of memory groups configured to include a plurality of memory packages, respectively, and input/output data through input/output pins. The memory module may include a control circuit configured to activate one or more of the plurality of memory groups on a basis of an address signal. ... Sk Hynix Inc

07/13/17 / #20170199685

Memory system and operating method of memory system

A memory system includes a memory device including a plurality of memory blocks each block including a plurality of pages; and a controller including a memory, and suitable for buffering segments of user data and metadata for a command operation into the memory, and storing the buffered segments into a super memory block including two or more of the plurality of memory blocks during the command operation in response to a command, wherein, when the total size of to-be-stored data among the buffered segments of the memory is smaller than an unit size of the one shot program, the controller stores dummy data as well as the to-be-stored data into the super memory block.. . ... Sk Hynix Inc

07/13/17 / #20170199676

Memory system and operating method thereof

There are provided a memory system including a semiconductor memory device and a controller and an operating method thereof. A memory system having an extended storage area includes a semiconductor memory device including a plurality of memory blocks, and a controller for controlling the semiconductor memory device. ... Sk Hynix Inc

07/13/17 / #20170199240

Semiconductor apparatus

A semiconductor apparatus includes a test entry control block configured to generate a plurality of trigger signals and a reset signal according to a test setting command and addresses; and a test entry signal generation block configured to enable a test entry signal when the plurality of trigger signals are sequentially enabled.. . ... Sk Hynix Inc

07/06/17 / #20170195601

Ramp signal generator, and cmos image sensor using the same

A ramp signal generator may include a reference current generation unit suitable for generating a reference current based on a gain; a ramp signal generation unit suitable for generating a ramp signal according to the reference current; a replica current supply unit suitable for supplying a replica current using the reference current generation unit; and an offset compensation unit suitable for compensating for an offset of the ramp signal generated by the ramp signal generation unit using the replica current.. . ... Sk Hynix Inc

07/06/17 / #20170194989

Techniques for miscorrection detection for constituent codewords in product codes

Techniques are described for protecting miscorrection in a codeword. In one example, the techniques include obtaining a first set of data to be encoded using a product code comprising one or more constituent codes, and generating a second set of data by performing a miscorrection avoidance procedure on the first set of data. ... Sk Hynix Inc

07/06/17 / #20170194946

Data output circuit

Provided is a data output circuit including: a control code generation unit suitable for generating a control code; and a driving unit suitable for driving an output pad with driving power determined by the control code in response to a data signal, wherein the control code generation unit generates an initial value of the control code in an initialization section, a calibration value of the control code in a calibration section, and a blocking value of the control code before the initialization section, wherein the calibration value is adjusted by a calibration operation in the calibration section, and wherein the driving unit is blocked by the blocking value.. . ... Sk Hynix Inc

07/06/17 / #20170194558

Electronic device

An electronic device in accordance with an implementation may include a semiconductor memory, and the semiconductor memory may include an interlayer dielectric layer having a hole; a conductive pattern filled in the hole; and a variable resistance element coupled with the conductive pattern over the conductive pattern and storing different data according to a resistance change, wherein the conductive pattern includes a carbon-containing conductive layer in a region adjacent to the variable resistance element.. . ... Sk Hynix Inc

07/06/17 / #20170194554

Electronic device

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a pinned layer having a pinned magnetization direction; a free layer having a changeable magnetization direction; a tunnel barrier layer interposed between the pinned layer and the free layer, and including a metal oxide; and a carbon-based compound patch positioned at one or more of between the pinned layer and the tunnel barrier layer, between the free layer and the tunnel barrier layer, and in the tunnel barrier layer.. ... Sk Hynix Inc

07/06/17 / #20170194489

Lateral power integrated devices having low on-resistance

A lateral power integrated device includes a source region and a drain region disposed in a semiconductor layer and spaced apart from each other in a first direction, a drift region disposed in the semiconductor layer and surrounding the drain region, a channel region arranged between the source region and the drift region in the first direction, a plurality of planar insulation field plates disposed over the drift region and spaced apart from each other in a second direction, a plurality of trench insulation field plates disposed in the drift region, a gate insulation layer formed over the channel region, and a gate electrode formed over the gate insulation layer. Each of the trench insulation field plates is disposed between the planar insulation field plates in the second direction.. ... Sk Hynix Inc

07/06/17 / #20170194446

Neuromorphic device including gating lines with different widths

A neuromorphic device includes a row line extending in a first direction; a column line disposed over the row line, the column line extending in a second direction perpendicular to the first direction; a plurality of gating lines disposed between the row line and the column line; and a synapse disposed between the row line and the column line, the synapse passing through the plurality of gating lines.. . ... Sk Hynix Inc

07/06/17 / #20170194378

Electronic device and method for fabricating the same

An electronic device may include a semiconductor memory. The semiconductor memory may include a trench formed in a substrate; a gate dielectric layer formed on a surface of the trench; a gate electrode which is formed on the gate dielectric layer, gap-fills a part of the trench, and contains dopants; a diffusion region which is formed to be in contact with the surface of the trench and to correspond to the gate electrode in the substrate; junction regions formed in the substrate at both sides of the trench; and a memory element coupled to a junction region in a side of the trench.. ... Sk Hynix Inc

07/06/17 / #20170194346

Semiconductor device and method of manufacturing the same

A semiconductor device includes memory blocks each configured to comprise a pair of channels, each channel including a pipe channel formed in a pipe gate of the memory block and a drain-side channel and a source-side channel coupled to the pipe channel; first slits placed between the memory blocks adjacent to other memory blocks; and a second slit placed between the source-side channel and the drain-side channel of each pair of channels.. . ... Sk Hynix Inc

07/06/17 / #20170194337

Neuromorphic device

A neuromorphic device may include: a plurality of row lines extending in a first direction; a plurality of additional row lines extending in the first direction; a plurality of column lines extending in a second direction that crosses the first direction; and a plurality of synapses positioned at intersections of the row lines, the additional row lines, and the column lines, wherein each of the synapses includes a transistor comprising a floating gate, a control gate insulated from the floating gate, a first junction, and a second junction, the control gate being coupled to a corresponding one of the plurality of row lines, the first junction being coupled to a corresponding one of the plurality of additional row lines, the second junction being coupled to a corresponding one of the plurality of column lines.. . ... Sk Hynix Inc

07/06/17 / #20170194322

Fin transistor, method for fabricating the same and electronic device including the same

An electronic device is provided. The electronic device comprises a fin transistor formed over a substrate which is structured to include a device isolation region and an active region, the fin transistor including: a layer formed over the substrate and having a trench crossing the device isolation region and the active region; a gate filled in the trench; a first fin formed over and overlapping the active region and protruding over the device isolation region; and second fins formed on both sidewalls of the first fin in a direction of the trench.. ... Sk Hynix Inc

07/06/17 / #20170194255

Electronic device and method for fabricating the same

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate; and a stepped structure including first interlayer dielectric layers and conductive layers which are alternately stacked over the substrate, wherein ends of the conductive layers are exposed along the profile of the stepped structure, and the stepped structure further includes a barrier layer formed on a sidewall of the conductive layer.. ... Sk Hynix Inc

07/06/17 / #20170194060

Semiconductor device, semiconductor system including the same and test method thereof

A semiconductor device includes a memory region suitable for providing a plurality of read data in parallel at every read operation cycle, an output path suitable for outputting the plurality of read data at a set time in response to an internal clock and one or more internal control signals at the every read operation cycle, and an output path control unit suitable for generating the internal control signal in response to a read command and generating the internal clock in response to a system clock, wherein a shifting time of a first edge of the internal clock is adjusted by a set level at the every read operation cycle during a test mode.. . ... Sk Hynix Inc

07/06/17 / #20170194051

Nonvolatile memory device and data storage device including the same

A data storage device includes a nonvolatile memory device; and a controller suitable for providing a normal erase command or a fine erase command to the nonvolatile memory device, wherein the nonvolatile memory device performs a first normal erase loop in which a first normal erase voltage and an erase verify voltage are applied to erase target memory cells, according to the normal erase command, and performs a first fine erase loop in which a first fine erase voltage and the erase verify voltage are applied to the erase target memory cells, according to the fine erase command.. . ... Sk Hynix Inc

07/06/17 / #20170194043

Circuit for generating periodic signal and memory device including same

Provided is a periodic signal generation circuit including: a clock generation unit suitable for generating first to nth clocks which have a basic period and have a phase increasing sequentially by a time interval obtained by dividing the basic period by “n”; a pulse generation unit suitable for generating first to nth periodic pulses having an equal pulse width and having a phase increasing sequentially by a time interval obtained by dividing the basic period by “n” by combining two or more clocks among the first to nth clocks; and a periodic signal generation unit suitable for generating a periodic signal by combining one or more periodic pulses among the first to nth periodic pulses depending on combination information.. . ... Sk Hynix Inc

07/06/17 / #20170194038

Latch circuit and semiconductor apparatus including the same

A latch circuit may be provided. The latch circuit may include a plurality of latches configured to store and output data through input/output signal lines according to input/output control signals. ... Sk Hynix Inc

07/06/17 / #20170193365

Synapse and neuromorphic device including the same

A neuromorphic device includes a synapse. The synapse, according to an embodiment, includes a first electrode, a second electrode spaced apart from the first electrode, an oxygen-containing layer disposed between the first electrode and the second electrode, the oxygen-containing layer including oxygen ions, and a reactive metal layer disposed between the oxygen-containing layer and the second electrode. ... Sk Hynix Inc

07/06/17 / #20170193364

Learning method for synapses of a neuromorphic device

A learning method for synapses of a neuromorphic device may include generating and inputting, by a pre-synaptic neuron, a first pre-synaptic pulse to a plurality of synapses at a first start time, the plurality of synapses being coupled to the pre-synaptic neuron; generating and inputting, by a first post-synaptic neuron, a first post-synaptic pulse to a first synapse of the plurality of synapses at a first delayed time that is delayed by a first delay amount from the first start time, the first synapse being coupled to the first post-synaptic neuron; and generating and inputting, by a second post-synaptic neuron, a second post-synaptic pulse to a second synapse of the plurality of synapses at a second delayed time that is delayed by a second delay amount from the first start time, the second synapse being coupled to the second post-synaptic neuron.. . ... Sk Hynix Inc

07/06/17 / #20170193363

Method for updating weights of synapses of a neuromorphic device

A method for updating a weight of a synapse of a neuromorphic device is provided. The synapse may include a transistor and a memristor. ... Sk Hynix Inc

07/06/17 / #20170193359

Neuromorphic device

A neuromorphic device includes a substrate; a first electrode and a second electrode that are disposed over the substrate, extend in a first direction, and are spaced apart in a second direction; a stack structure between the first electrode and the second electrode, which includes reactive metal layers alternately stacked with one or more insulating layers; an oxygen-containing layer between the first electrode and the stack structure, which includes oxygen ions; and an oxygen diffusion-retarding layer between the stack structure and the oxygen-containing layer. The first direction is perpendicular to a top surface of the substrate, and the second direction is parallel to the top surface of the substrate. ... Sk Hynix Inc

07/06/17 / #20170193358

Neuromorphic devices including post-synaptic neurons having at least one of integrators, amplifiers, or sampling elements

A neuromorphic device may include: a pre-synaptic neuron; a row line electrically coupled to the pre-synaptic neuron; a post-synaptic neuron; a column line electrically coupled to the post-synaptic neuron; and a synapse disposed at a cross point between the row line and the column line. The post-synaptic neuron may include: a first integrator electrically coupled to the synapse; a second integrator electrically coupled to the first integrator; and a comparator electrically coupled to the second integrator.. ... Sk Hynix Inc

07/06/17 / #20170193357

Neuromorphic device including synapses having carrier traps distributed at multiple energy levels

A neuromorphic device having synapses may include: a top electrode; a bottom electrode; and a variable resistive layer disposed between the top electrode and the bottom electrode. The variable resistive layer may include a plurality of carrier traps distributed at multiple energy levels.. ... Sk Hynix Inc

07/06/17 / #20170193356

Synapse and a neuromorphic device including the same

A neuromorphic device includes a synapse. The synapse includes a first electrode, a second electrode spaced apart from the first electrode, an oxygen-containing layer disposed between the first electrode and the second electrode, the oxygen-containing layer including oxygen ions, and a stack structure disposed between the oxygen-containing layer and the second electrode, the stack structure including a plurality of reactive metal layers alternately arranged with a plurality of oxygen diffusion-retarding layers. ... Sk Hynix Inc

07/06/17 / #20170193355

Method of reading data from synapses of a neuromorphic device

A method reads data from a synapse which includes a transistor and a variable resistor. The transistor has a gate electrode, a first electrode and a second electrode. ... Sk Hynix Inc

07/06/17 / #20170193354

Neuromorphic device and method of adjusting a resistance change ratio thereof

A neuromorphic device may include: a plurality of pre-synaptic neurons; row lines extending in a row direction from the plurality of pre-synaptic neurons; a plurality of post-synaptic neurons; column lines extended in a column direction from the plurality of post-synaptic neurons; a plurality of synapses arranged at intersections between the row lines and the column lines; a plurality of first control blocks; and first control lines extending from the control blocks. The first control lines may be electrically connected to the plurality of synapses.. ... Sk Hynix Inc

07/06/17 / #20170193353

Neuromorphic device including post-synaptic neurons having a comparator for deciding quasi-learned synapses

A neuromorphic device may include: a pre-synaptic neuron; a plurality of post-synaptic neurons; and a plurality of synapses electrically connected to the pre-synaptic neuron and electrically connected to the plurality of post-synaptic neurons. Each of the post-synaptic neurons may include: an integrator; a main comparator having a first input port connected to an output port of the integrator; and a first sub comparator having a first input port connected to the output port of the integrator.. ... Sk Hynix Inc

07/06/17 / #20170193352

Synapse and neuromorphic device including the same

A neuromorphic device includes a synapse. The synapse includes a first electrode, a second electrode spaced apart from the first electrode, an oxygen-containing layer disposed between the first electrode and the second electrode, a reactive metal layer disposed between the oxygen-containing layer and the second electrode, and an oxygen diffusion-retarding layer disposed between the reactive metal layer and the oxygen-containing layer. ... Sk Hynix Inc

07/06/17 / #20170192845

Semiconductor system

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output command/address signals. ... Sk Hynix Inc

07/06/17 / #20170192719

Controller coupled to semiconductor memory device and operating method thereof

There are provided a controller coupled to a semiconductor memory device and an operating method thereof. A controller having improved operation speed includes a command generation unit for generating commands to be performed by a semiconductor memory device, a command queue for storing the commands and providing at least one command among the stored commands to the semiconductor memory device, and a command removal unit for, if the semiconductor memory device fails in the performance of the at least one command output from the main command queue, removing the at least one command and related commands of the at least one command from the command queue.. ... Sk Hynix Inc

07/06/17 / #20170192678

Electronic device and method for fabricating the same

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an interlayer dielectric layer formed over a substrate and having a contact hole; a contact plug formed in a lower part of the contact hole; a contact pad formed in an upper part of the contact hole; an amorphous buffer layer interposed between the contact plug and the contact pad; and a variable resistance element formed over the contact pad.. ... Sk Hynix Inc

06/29/17 / #20170187517

Semiconductor apparatus

A semiconductor apparatus includes a pattern conversion circuit configured to generate conversion data in response to a monitoring enable signal, pattern select signals and parallel input data; a transmission circuit configured to output the conversion data as serial data in response to a plurality of clocks; a reception circuit configured to output the serial data as parallel output data in synchronization with the plurality of clocks; and a monitoring circuit configured to generate a result signal in response to the plurality of clocks, clock select signals and the serial data.. . ... Sk Hynix Inc

06/29/17 / #20170187397

Data storage device and operating method thereof

A method for operating a data storage device including a nonvolatile memory device and first and second type decoders includes: obtaining a plurality entry values of total power consumption value of the first and second type decoders respectively based on a plurality entry values of decoding performance information of the first type decoders; choosing a minimum value among the plurality entry values of total power consumption value; generating first and second decoding control information according to the minimum value in order to control the first and second type decoders; updating the decoding performance information at each of the decoding operations of the first and second type decoders; and repeating the obtaining of the total power consumption value, the choosing of the minimum value, and the generating of the first and second decoding control information based on the updated decoding performance information.. . ... Sk Hynix Inc

06/29/17 / #20170187370

Semiconductor apparatus

A semiconductor apparatus may include a noise determination circuit, a strobe signal control circuit, and a reception circuit. The noise determination circuit may sense and determine noise of a reference voltage, and generate an up control signal and a down control signal. ... Sk Hynix Inc

06/29/17 / #20170186948

Method for fabricating semiconductor device and method for operating the same

A method for fabricating a semiconductor device and a method for operating the semiconductor device are provided. The method for fabricating a semiconductor device includes forming a first electrode layer; forming a material layer, including conductive path components, over the first electrode layer; forming a second electrode layer over the material layer; performing a forming operation, which includes initially creating, in the material layer, a conductive path that electrically connects the first electrode layer to the second electrode layer by applying one of a predetermined voltage and a predetermined current between the first and second electrode layers, the conductive path including the conductive path components; and performing a first heat-treatment process at a predetermined temperature that removes some of the conductive path components from the conductive path, wherein a resistance state of the material layer changes based on the creation or dissolution of the conductive paths.. ... Sk Hynix Inc

06/29/17 / #20170186870

Semiconductor device and method for fabricating the same

A semiconductor device includes a substrate comprising a channel region and a recess, wherein the recess is located at both side of the channel region; a gate structure formed over the channel region; a first sip layer covering bottom corners of the gate structure and the recess; and a second sip layer formed over the first sip layer and in the recess, wherein the second sip layer has a phosphorus concentration higher than that of the first sip layer.. . ... Sk Hynix Inc

06/29/17 / #20170186844

Semiconductor device having buried gate structure, method for manufacturing the same, and memory cell having the same

A semiconductor device includes at least one trench extending into a semiconductor substrate and lined with a gate dielectric layer; a dipole inducing layer covering a lowermost portion of the lined trench; a gate electrode covering the dipole inducing layer and filled in the lined trench; and doping regions, in the semiconductor substrate, separated from each other by the lined trench and separated from the dipole inducing layer.. . ... Sk Hynix Inc

06/29/17 / #20170186813

Threshold switching device and electronic device including the same

A threshold switching device may include: a first electrode layer; a second electrode layer; an insulating layer interposed between the first and second electrode layers and containing a plurality of neutral defects; and an additional insulating layer interposed between the insulating layer and one or each of the first and second electrode layers, and being substantially free from neutral defects, and wherein the threshold switching device has an on or off state according to whether electrons are ejected from the plurality of neutral defects.. . ... Sk Hynix Inc

06/29/17 / #20170186812

Threshold switching device, method for fabricating the same and electronic device including the same

A threshold switching device may include: a first electrode layer; a second electrode layer; a first insulating layer interposed between the first and second electrode layers, and provided adjacent to the first electrode layer; and a second insulating layer interposed between the first and second electrode layers, and provided adjacent to the second electrode layer, wherein the first and second insulating layers contain a plurality of neutral defects, a concentration of the plurality of neutral defects being at a maximum along a first interface between the first insulating layer and the second insulating layer, and wherein the threshold switching device has an on or off state according to whether electrons are ejected from the plurality of neutral defects. . ... Sk Hynix Inc

06/29/17 / #20170186756

Anti-fuse type nonvolatile memory cells, arrays thereof, and methods of operating the same

An anti-fuse type nonvolatile memory cell includes a semiconductor layer having a first conductivity type, a junction region having a second conductivity type and a trench isolation layer disposed in an upper portion of the semiconductor layer spaced apart from each other by a channel region, an anti-fuse insulation pattern disposed on the channel region, a gate electrode disposed on the anti-fuse insulation pattern, a gate spacer disposed on sidewalls of the anti-fuse insulation pattern and the gate electrode, a word line connected to the gate electrode, and a bit line connected to the junction region. The anti-fuse insulation pattern is broken if a first bias voltage and a second bias voltage are applied to the word line and the bit line, respectively.. ... Sk Hynix Inc

06/29/17 / #20170186753

Semiconductor device having buried gate structure and method for manufacturing the same, memory cell having the same and electronic device having the same

A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer.. . ... Sk Hynix Inc

06/29/17 / #20170186734

Semiconductor package

A semiconductor package includes a first chip, a second chip stacked over the first chip and having a different size from the first chip, a first guard unit formed in an edge of a chip having a relatively small size of the first chip and the second chip, and a second guard unit formed in an edge of a chip having a relatively large size of the first chip and the second chip. The first guard unit includes an extension pad which expands the size of the chip having the relatively small size to the size of the chip having the relatively large size.. ... Sk Hynix Inc

06/29/17 / #20170186659

Semiconductor devices having through electrodes and methods of manufacturing the same

Semiconductor devices are provided. The semiconductor device includes a semiconductor layer having a first surface and a second surface that are opposite each other, a through electrode penetrating the semiconductor layer and having a protrusion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed over the first surface of the semiconductor layer and electrically coupled to the through electrode, a polymer pattern disposed over the second surface of the semiconductor layer to enclose a part of the protrusion of the through electrode, and a back-side bump covering an upper surface and a sidewall of a remaining part of the protrusion of the through electrode and extending over a portion of the polymer pattern.. ... Sk Hynix Inc

06/29/17 / #20170186642

Isolation structure and method for manufacturing the same

A method for manufacturing a semiconductor device includes forming a first trench and a second trench in a substrate, the first and the second trenches communicate with each other, the second trench may be formed wider than the first trench; forming a liner layer over an inner surface of the first trench and over an inner surface of the second the trench; forming a capping layer over the liner layer to form a merged overhang and a non-merged overhang, the merged overhang may be fill a top portion of the first trench, the non-merged overhang may be open a top portion of the second trench; and forming a gap-fill layer over the capping layer to fill a lower portion of the first trench and the second trench.. . ... Sk Hynix Inc

06/29/17 / #20170186501

Integrated circuit and memory device

An integrated circuit may include nonvolatile memory suitable for outputting stored data during the boot-up operation, one or more registers suitable for receiving the data output by the nonvolatile memory and storing the received data when the boot-up operation is performed, and one or more internal circuits suitable for operating using the data stored in the one or more registers. In no-update mode, although the boot-up operation is performed, a data update from the nonvolatile memory to the registers may not be performed.. ... Sk Hynix Inc

06/29/17 / #20170186496

Semiconductor memory devices and methods of testing open failures thereof

Semiconductor memory devices are provided. The semiconductor memory device includes an input/output (i/o) drive controller, a data i/o unit and a data transmitter. ... Sk Hynix Inc

06/29/17 / #20170186494

Memory system performing wear leveling using average erase count value and operating method thereof

A memory system may include a memory device including 0th to n-1th memory blocks, wherein n is a positive integer; and a controller having a first list and a second list, wherein the first list includes 0th to n-1th erase count values respectively for the 0th to n-1th memory blocks, wherein the second list includes 0th to n-1th difference values respectively for the 0th to n-1th memory blocks, wherein each of the 0th to n-1th difference values is a difference between an average value of the 0th to n-1th erase count values and each of the 0th to n-1th erase count values, wherein the controller selects a source block and a target block among the 0th to n-1th memory blocks depending on the 0th to n-th erase count values included in the first list and the 0th to n-1th difference values included in the second list to perform a wear leveling between the source block and the target block.. . ... Sk Hynix Inc

06/29/17 / #20170186485

Electronic device and method for driving the same

An electronic device includes a semiconductor memory that includes: a memory cell coupled between a first line and a second line; a first selection block configured to select the first line; a second selection block configured to select the second line; an alternate current supply block configured to supply, during a read operation, an alternate current corresponding to a resistance state of the memory cell; and a sensing block configured to sense, during the read operation, at least one of a cell current flowing through the memory cell and the alternate current.. . ... Sk Hynix Inc

06/29/17 / #20170186480

Semiconductor memory device for performing refresh operation and operating method therof

A semiconductor memory device may include: a memory bank comprising a plurality of word lines; a smart command generation unit suitable for generating a smart refresh command, which is enabled at a random cycle, in response to an active command; and a refresh operation control unit suitable for performing a refresh operation to at least one of adjacent word lines of a target word line among the plurality of word lines in response to the smart refresh command.. . ... Sk Hynix Inc

06/29/17 / #20170186477

Semiconductor memory device

A semiconductor memory device may include: a plurality of memory mats; and a plurality of sense amplifier arrays arranged alternately with the memory mats, each sense amplifier array being suitable for sensing and amplifying data of memory mats adjacent thereto, wherein during a data sensing operation to a memory mat among the plurality of memory mats, in addition to a sense amplifier for the memory mat and sense amplifiers positioned immediately above and below the sense amplifier for the memory mat, at least one additional sense amplifier closest to the sense amplifier for the memory mat is also activated for providing additional amplification.. . ... Sk Hynix Inc

06/29/17 / #20170186476

Address generation circuit and memory device including the same

An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.. . ... Sk Hynix Inc

06/29/17 / #20170186470

Signal shifting circuit, base chip, and semiconductor system including the same

A signal shifting circuit may include a bank selection signal generation unit suitable for generating a bank selection signal synchronized with a first clock in response to a bank address and an internal write signal; and a shifting device suitable for generating a shifted bank selection signal by shifting the bank selection signal by a number of times according to latency information and for advancing a phase of the shifted bank selection signal whenever shifting the bank selection signal once or more so that the shifted bank selection signal is synchronized with a second clock having a phase leading a phase of the first clock.. . ... Sk Hynix Inc

06/29/17 / #20170186469

Memory circuit and stack type memory system including the same

A memory circuit may be provided. The memory circuit may include a memory array. ... Sk Hynix Inc

06/29/17 / #20170185524

Memory system and operation method of memory system

A memory system includes: a memory device suitable for storing data; and a controller suitable for storing a first data which is provided from a host, in one of first and second regions of a cache corresponding to priority of the first data according to a type of the first data.. . ... Sk Hynix Inc

06/29/17 / #20170185480

Control circuit, memory device including the same, and method

A control circuit configured to associate a plurality of memory with an error correction scheme. The control circuit including an internal operation circuit configured to generate an internal command based on an access unit of the plurality of memory. ... Sk Hynix Inc

06/29/17 / #20170185463

Memory system and operating method thereof

An operating method of a memory system including a plurality of memory blocks may include grouping the pages of a selected memory block among the plurality of memory blocks based on a program time, sequentially performing a test read on the groups of the pages, detecting an error in the pages of the test-read groups, and reprogramming a page selected based on a result of the error detection.. . ... Sk Hynix Inc

06/29/17 / #20170185352

Memory device

A memory device may include one or more multi-channel memories and an interface unit suitable for interfacing the multi-channel memories. The interface unit may include a first data interface suitable for transferring data for the first channel of the multi-channel memories, a second data interface suitable for transferring data for the second channel of the multi-channel memories, and an extra data interface suitable for transferring data for a selected one of the first channel and the second channel so that the data is additionally transmitted.. ... Sk Hynix Inc

06/29/17 / #20170185349

Memory module and memory system including the memory module

A memory system may include a controller and a plurality of memory modules. Each of the plurality of memory modules may include a buffer chip and a plurality of memory chips coupled to the buffer chip through independent input and output (i/o) lines. ... Sk Hynix Inc

06/29/17 / #20170185348

Memory system and operating method of memory system

A memory system may include a memory device including a plurality of memory blocks, and a controller including a memory the controller being suitable for performing a command operation corresponding to a command received from a host, storing user data and metadata in the memory, and storing the user data and the metadata in at least one memory block among the memory blocks based on a command parameter included in the command.. . ... Sk Hynix Inc

06/29/17 / #20170185336

Memory system and operating method thereof

A memory system may include: a memory device comprising a plurality of pages and a plurality of word lines; and a controller suitable for: performing a program operation to at least one selected page coupled to a single word line; performing an erase operation to the at least one selected page when the memory system is powered on after a power off interrupted the performing of the program operation to the at least one selected page; and re-performing the interrupted program operation to the erased at least one selected page.. . ... Sk Hynix Inc

06/29/17 / #20170185329

Memory system and operation method thereof

A memory system may include: a data storage unit comprising a first memory device through which data are inputted/outputted through a first channel and a second memory device through which data are inputted/outputted through a second channel, wherein each of the first and second memory devices comprises a plurality of blocks each having multi-level cells (mlcs); and a controller suitable for selecting a first target block among the plurality of blocks of a channel which includes a first victim block and selecting a second target block among the plurality of blocks of a channel of which does not include the first victim block, and separating data of the mlcs included in the first victim block on a level basis and copying the separated data into the first and second target blocks, respectively, during a garbage collection operation.. . ... Sk Hynix Inc

06/29/17 / #20170185319

Memory system and operating method of the memory system

This technology relates to a memory system in which a plurality of memory devices operates in an interleaving manner and an operating method of the memory system. The memory system may include a plurality of memory devices, a host controller suitable for generating a plurality of internal read commands by splitting an external read command applied from a host in a minimum read size, and a memory controller suitable for checking information about internal read commands which belong to the plurality of internal read commands and which are sequentially late in a section in which a read operation is performed on the plurality of memory devices based on check values of information about internal read commands which belong to the plurality of internal read commands and which are sequentially ahead.. ... Sk Hynix Inc

06/29/17 / #20170185295

Memory system and operating method of memory system

The memory system, may include: a memory device comprising a plurality of memory blocks; and a controller suitable for performing a command operation to the memory blocks, updating update parameters and erase cycles (ecs) of the memory blocks, selecting at least one source memory block based on the update parameters, selecting at least one target memory block based on the ecs, and performing at least one swap operation between the selected at least one or more source memory block and the selected at least one target memory block.. . ... Sk Hynix Inc

06/29/17 / #20170185294

Memory system and operating method thereof

A memory system may include a memory device including n (n is an integer of 1 or more) physical banks and a memory controller suitable for communicating with a host using m (m is an integer greater than n) logical banks and for communicating with the memory device. The memory controller may include m row buffers corresponding to the respective m logical banks, for caching the data of the respective m logical banks and an address translator for performing an address translation between a logical address used for communication with the host and a physical addresses used for communication with the memory device.. ... Sk Hynix Inc

06/29/17 / #20170184673

Test mode control circuit

A test mode control circuit relating to a technology for controlling a vendor specific test mode is disclosed. The test mode control circuit includes a signal generation circuit configured to generate a plurality of set signals and a plurality of reset signals in response to a plurality of code signals and a predetermined mode register signal; and a plurality of serially-connected latch circuits configured to selectively operate in response to the plurality of set signals and the plurality of reset signals so as to control an entry signal of an output terminal.. ... Sk Hynix Inc

06/22/17 / #20170179980

Techniques for low complexity soft decoder for turbo product codes

Techniques are described for decoding a message. In one example, the techniques include obtaining a first message comprising a plurality of information bits and a plurality of parity bits, decoding the first message using an iterative decoding algorithm to generate a first bit sequence, generating a miscorrection metric based at least on the first bit sequence and one or more reliability values corresponding to one or more bits in the first message, determining whether a miscorrection happened in the decoder by comparing the miscorrection metric with a first threshold, and upon determining that a miscorrection did not happen, outputting the first bit sequence as a decoded message.. ... Sk Hynix Inc

06/22/17 / #20170179963

Clock generation circuit and semiconductor apparatus and electronic system using the same

A clock generation circuit may include a reference clock generator configured to generate a pair of first reference clocks in an offset code generation mode, a correction code generator configured to generate a reference correction code according to a duty detection signal based on a phase difference between the pair of first reference clocks, and an offset code generator configured to generate an offset code based on the reference correction code and a preset reference code.. . ... Sk Hynix Inc

06/22/17 / #20170179956

Duty cycle correction circuit and duty cycle correction method

A duty cycle correction circuit may include: a phase mixing section capable of mixing a first integrated signal generated by integrating a positive clock signal, with a first compensation signal generated by differentiating and integrating the positive clock signal and a negative clock signal, respectively, to generate a first phase-mixed signal, and mixing a second integrated signal generated by integrating the negative clock signal, with a second compensation signal generated by integrating and differentiating the positive clock signal and the negative clock signal, respectively, to generate a second phase-mixed signal; and a noise removal section capable of receiving and removing a common mode noise between the first phase-mixed signal and the second phase-mixed signal by adjusting a cross-point therebetween, and outputting first and second duty-corrected clock signals.. . ... Sk Hynix Inc

06/22/17 / #20170179951

Transmitter

A transmitter includes: a main pull-up driver suitable for pull-up driving an output node; and an auxiliary pull-up driver suitable for pull-up driving the output node based on a voltage of the output node, wherein the auxiliary pull-up driver compensates for non-linear driving current characteristics of the main pull-up driver.. . ... Sk Hynix Inc

06/22/17 / #20170179948

Signal transfer circuit and circuit for generating hit signal including the same

A signal transfer circuit may include a pass gate coupled between first and second nodes; and a control unit suitable for controlling the pass gate to prevent a current flowing from the second node to the first node during turn-on of the pass gate.. . ... Sk Hynix Inc

06/22/17 / #20170179938

Phase detection circuit

A phase detection circuit includes a sampling signal generation circuit configured to generate a plurality of sampling signals in response to a plurality of phase change clocks having different phases and data; a charging voltage generation circuit configured to compare the plurality of sampling signals, and change a voltage level of one charging voltage between a first charging voltage and a second charging voltage; and a comparison circuit configured to compare voltage levels of the first and second charging voltages, and generate a result signal.. . ... Sk Hynix Inc

06/22/17 / #20170179253

Semiconductor device and method for fabricating the same

A method for fabricating a semiconductor device may include: preparing a semiconductor substrate including a doping region; performing tilt implantation using a first additional dopant to form an amorphous region in the doping region; doping a second additional dopant in the amorphous region; forming a metal layer on the doped amorphous region; and reacting the doped amorphous region with the metal layer to form metal silicide. . ... Sk Hynix Inc

06/22/17 / #20170179180

Light field imaging device and method for fabricating the same

A light field imaging device includes an image sensor having a plurality of pixels arranged two-dimensionally therein; a microlens array formed over the image sensor, the microlens array having a plurality of microlenses arranged two-dimensionally therein; and a plurality of support structures formed between the image sensor and the microlens array for providing an air gap therebetween.. . ... Sk Hynix Inc

06/22/17 / #20170179174

Image sensor including vertical transfer gate

An image sensor includes a photoelectric conversion element, including a first impurity region and a second impurity region, wherein the first impurity region contacts a first surface of a substrate, wherein the second impurity region has conductivity complementary to the first impurity region and is formed in the substrate and below the first impurity region; a pillar formed over the photoelectric conversion element; a transfer gate formed over the photoelectric conversion element to surround the pillar; and a channel layer formed between the transfer gate and the pillar and contacting the photoelectric conversion element, wherein the channel layer contacts the first impurity region and has the same conductivity as the second impurity region.. . ... Sk Hynix Inc

06/22/17 / #20170179148

Manufacturing method for semiconductor device

A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure, forming a reflective metal pattern in the first hole, filling an etch stop layer in the first hole and over the reflective metal pattern, forming a second stacked structure over the first stacked structure, and forming a second hole penetrating the second stacked structure to expose the etch stop layer.. . ... Sk Hynix Inc

06/22/17 / #20170179144

Semiconductor device and manufacturing method thereof

A semiconductor device includes channel layers arranged in a first direction and a second direction intersecting the first direction; stacked insulating layers surrounding sidewalls of the channel layers; stacked gate electrodes interposed between the insulating layers, the gate electrodes respectively surrounding the channel layers; and stacked gate lines interposed between the insulating layers, the gate lines electrically connecting the gate electrodes to each other.. . ... Sk Hynix Inc

06/22/17 / #20170179110

Electro-static discharge protection devices having a low trigger voltage

An electro-static discharge (esd) protection device includes a first pn diode, a second pn diode and a silicon controlled rectifier (scr). The first pn diode and the second pn diode are coupled in series between a pad and a ground voltage to provide a first discharge current path. ... Sk Hynix Inc

06/22/17 / #20170179078

Semiconductor packages and methods of manufacturing the same

A semiconductor package and or method of fabricating the semiconductor package may be provided. The semiconductor package may include a first die, at least one second die electrically connected to the first die, and a plurality of first connectors disposed on the interconnection structure layer. ... Sk Hynix Inc

06/22/17 / #20170179003

Semiconductor package including a conductive fabric

A semiconductor package may be provided. The semiconductor package may include a substrate formed with one or more connection pads. ... Sk Hynix Inc

06/22/17 / #20170178977

Semiconductor device and method for manufacturing the same

A semiconductor device includes a first active region including at least one first recess; a second active region including at least one second recess; an isolation region including a diffusion barrier that laterally surrounds at least any one active region of the first active region and the second active region; a first recess gate filled in the first recess; and a second recess gate filled in the second recess, wherein the diffusion barrier contacts ends of at least any one of the first recess gate and the second recess gate.. . ... Sk Hynix Inc

06/22/17 / #20170178952

Method for manufacturing dual damascene structure

A method for manufacturing a semiconductor device include forming a dielectric layer over an underlying layer; forming an etch barrier over the dielectric layer, wherein a partial via opening is formed in the etch barrier and exposes a lower portion of the etch barrier; forming an assist-etch barrier over the etch barrier to fill the partial via opening; patterning the assist-etch barrier to form an initial trench opening in the assist-etch barrier, wherein the initial trench opening communicates with the partial via opening; patterning the lower portion of the etch barrier exposed by the partial via opening to form a final via opening in the etch barrier; patterning the dielectric layer exposed by the final via opening to form an initial via hole in the dielectric layer; patterning the etch barrier exposed by the initial trench opening to form a final trench opening in the etch barrier; patterning a lower portion of the dielectric layer exposed by the initial via hole to form a final via hole in the dielectric layer; and patterning a upper portion of the dielectric layer exposed by the final trench opening to form a trench, wherein the trench communicates the final via hole.. . ... Sk Hynix Inc

06/22/17 / #20170178936

Wafer processing system and wafer processing method using same

A system for processing a wafer may use a wafer identification (id) assigned by a wafer manufacturing company as an id code of the wafer in managing the wafer by a semiconductor manufacturing company.. . ... Sk Hynix Inc

06/22/17 / #20170178753

Nonvolatile memory circuit and memory device including same

A nonvolatile memory circuit may include: a cell array including a first region comprising a plurality of first cell groups and a second region comprising a plurality of second cell groups, each of the first and second cell groups having one or more nonvolatile memory cells; and a control unit suitable for controlling the cell array to sequentially output repair addresses of the plurality of cells groups included in a region which is not over used among the first and second regions when one of the first and second regions is over used.. . ... Sk Hynix Inc

06/22/17 / #20170178751

Semiconductor memory device and method for detecting weak cells

A semiconductor memory device may include: a memory cell array coupled between a plurality of word lines and a plurality of bit lines; a first source voltage supply unit suitable for providing a boosted voltage to a source voltage terminal when a cell mat signal is activated; a second source voltage supply unit suitable for providing a dropped voltage that is lower than the boosted voltage to the source voltage terminal; a word line driving circuit suitable for selecting one of the plurality of word lines in response to an address combination signal and driving the selected word line and unselected word lines, when the cell mat signal is activated; and a weak cell detection circuit suitable for detecting a weak cell by checking data values of memory cells coupled to a word line which is driven by the word line driving circuit during the test mode.. . ... Sk Hynix Inc

06/22/17 / #20170178715

Base chip and semiconductor package including the same

A base chip including first to nth delay units coupled in series, where n is a natural number equal to or larger than 2, wherein when the number of stacked chips over the base chip is 1, the base chip is suitable for delaying a refresh signal, and generating first to xth delayed refresh signals using the first to xth delay units among the first to nth delay units, where x is a natural number having a relation of n>x≧1, and when the number of stacked chips over the base chip is 2, the base chip is suitable for delaying the refresh signal, and generating first to yth delayed refresh signals using the first to yth delay units among the first to nth delay units, where y is a natural number having a relation of n≧y>x.. . ... Sk Hynix Inc

06/22/17 / #20170177515

Electronic device and method of driving the same

An electronic device may include a semiconductor memory. The semiconductor memory may include a write circuit, a first selection circuit, a memory cell, a coupling control circuit, and a coupling circuit. ... Sk Hynix Inc

06/22/17 / #20170177514

Electronic device

This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the pinned layer and the free layer, wherein the free layer may include a first magnetic layer; a second magnetic layer formed over the first magnetic layer; and a zirconium (zr)-containing material layer interposed between the first magnetic layer and the second magnetic layer.. ... Sk Hynix Inc

06/22/17 / #20170177494

Data processing system and operation method thereof

A data processing system may include: a host suitable for managing a plurality of data through a balance tree structure in which each node is set to a predetermined size, wherein each of the data includes information regarding the node in which the data is positioned, as node information; and a memory system having a plurality of physical storage areas each corresponding to the predetermined size, and suitable for gathering data included in two different new nodes based on the node information included in each of the data applied from the host, and storing the gathered data in one of the plurality of physical storage area.. . ... Sk Hynix Inc

06/22/17 / #20170177436

Operating method of memory system

An operating method of a memory system includes: reading a first data from a particular data group among a plurality of data groups included in a memory device; performing a first error correction code (ecc) decoding for the first data; when the first ecc decoding fails, reading a plurality of the remaining data other than the first data from the particular data group; performing a second ecc decoding for the plurality of the remaining data; when the second ecc decoding fails, identifying data, to the second ecc decoding fails among the plurality of the remaining data; obtaining first and second soft read values respectively corresponding to the first data, to which the first ecc decoding fails, and the second data, to which the second ecc decoding fails; determining reliability of the first and second data based on the first and second soft read values; and correcting the first data based on the reliability of the first and second data.. . ... Sk Hynix Inc

06/22/17 / #20170177242

Memory system and operation method for the same

A memory system may include: a plurality of memory devices; a cache memory suitable for caching request information applied from a host and data corresponding to the request information; and a controller suitable for backing up the request information and the corresponding data of the cache memory and state information of the cache memory in a backup space when a reset request is provided from the host, performing a reset operation on the plurality of memory devices, the cache memory, and the controller in response to the reset request, and restoring the request information and the corresponding data from the backup space to the cache memory by referring to the state information during a booting operation after the reset operation.. . ... Sk Hynix Inc

06/22/17 / #20170177226

Memory system and operating method of memory system

A memory system may include: a memory device including a plurality of pages each having a plurality of memory cells coupled to a plurality of word lines and suitable for storing data, and a plurality of memory blocks each having the pages; and a controller suitable for programming test data to a first memory block among the memory blocks before a first time point, and programming meta-data corresponding to the program of the test data to a second memory block among the memory blocks, in case where the memory system including the memory device is changed from a power-on state to a power-off state at the first time point.. . ... Sk Hynix Inc

06/22/17 / #20170176517

Semiconductor device and test system including the same

A semiconductor device may include a first node coupled to a first pad to which a first voltage having a first voltage level is inputted; a second node coupled to a second pad to which a second voltage having a second voltage level is inputted; an internal voltage generation unit suitable for shifting a voltage level of the first node to generate an internal voltage having the second voltage level, and outputting the internal voltage to third and fourth nodes; a first internal circuit suitable for operating by employing a voltage of the second node; and a node coupling unit that electrically couples the second node to the third node during a test operation, and electrically separates the second node and the third node during a normal operation.. . ... Sk Hynix Inc

06/15/17 / #20170170831

Inverter circuits

An inverter circuit includes a pull-up control circuit and a pull-up drive circuit. The pull-up control circuit generates a drive signal which is enabled during a first time period in response to an input signal and an output signal. ... Sk Hynix Inc

06/15/17 / #20170170235

Switching device, and resistive random access memory including the same as a selection device

A switching device includes a first electrode, a switching layer and a second electrode that are disposed over a substrate. The switching layer includes an oxide of a first atom or a nitride of the first atom, and a second atom is doped in the oxide or the nitride. ... Sk Hynix Inc

06/15/17 / #20170170193

Semiconductor device and method of manufacturing the same

A semiconductor device includes a cell structure; n first pad structures formed on one side of the cell structure and each configured to have a step form in which 2n layers form one stage; and n second pad structures formed on the other side of the cell structure each configured to have a step form in which 2n layers form one stage, wherein n is a natural number of 1 or higher, and the first pad structures and the second pad structures have asymmetrical step forms having different heights.. . ... Sk Hynix Inc

06/15/17 / #20170170192

Semiconductor device and method of manufacturing the same

The present disclosure may provide a semiconductor device with an enhanced integration. The device may include a lower pipe gate; an upper pipe gate including a first horizontal portion and first and second protrusions, the first horizontal portion being parallel to the lower pipe gate, the first and second protrusions extending from the first horizontal portion to the lower pipe gate and crossing each other so as to define a pipe channel region; a partition pipe gate disposed between the lower and upper pipe gates, the partition pipe gate dividing the pipe channel region into first and second pipe channel regions; and first and second pipe channel films disposed respectively in the first and second pipe channel regions.. ... Sk Hynix Inc

06/15/17 / #20170170127

Semiconductors, packages, wafer level packages, and methods of manufacturing the same

According to various embodiments, there may be provided packages, semiconductors, and wafer level packages, and there may be provided methods of manufacturing packages, semiconductors, and wafer level packages. A method of manufacturing a wafer level package may include forming alignment marks at a surface of a protection wafer, mounting semiconductor dice on the protection wafer using the alignment marks, forming a first dielectric layer covering the semiconductor dice, planarizing a top surface of the first photosensitive layer, exposuring and developing portions of the planarized first dielectric layer to form opening portions exposing portions of the semiconductor dice, and forming redistribution lines on the first photosensitive dielectric layer. ... Sk Hynix Inc

06/15/17 / #20170169901

Test mode setting circuit and semiconductor device including the same

A test mode setting circuit may include: a first test mode signal generation unit operated by a first supply voltage, the first test mode signal generation unit suitable for activating a first test mode signal at a first voltage level in a state where mode setting is completed, the first test mode signal corresponding to a test code among a plurality of first test mode signals; and a second test mode signal generation unit operated by a second supply voltage, the second test mode signal generation unit suitable for latching the first test mode signal at a second voltage level and generating the latched first test mode signal as a second test mode signal when a first supply voltage is reset.. . ... Sk Hynix Inc

06/15/17 / #20170169879

Semiconductor devices and semiconductor systems including the same

A semiconductor system includes a semiconductor device. The semiconductor device executes an active operation according to a combination of command/address signals to store location information of mats selectively activated. ... Sk Hynix Inc

06/15/17 / #20170169869

Nonvolatile random access memory including control circuit configured to receive commands at high and low edges of one clock cycle

A nonvolatile random access memory including a memory cell array including banks, each bank including rows; an address latch circuit; and a control circuit receiving a first set of signals including a precharge command and a first row address, and a second set of signals including an active command and a second row address. The control circuit executes a first operation in which one of the banks is deactivated when the first set of signals is loaded, executes a second operation in which the first row address is loaded when the first set of signals is loaded, and executes a third operation in which at least one of the rows in the bank is selected and activated based on the second row address when the second set of signals is loaded after the first set of signals.. ... Sk Hynix Inc

06/15/17 / #20170169866

Page buffer and memory device having the same

There are provided a page buffer and a memory device having the same. A page buffer includes a reference current generation unit for precharging a bit line by generating a reference current, a current sensing unit for changing or maintaining a voltage of a select node, based on a change in current of the bit line, a first data sensing unit for storing first data, based on a change in the voltage of the select node, and a second data sensing unit for, when the first data is stored in the first data sensing unit, consecutively storing second data, based on the change in the voltage of the select node.. ... Sk Hynix Inc

06/15/17 / #20170169865

Semiconductor devices and semiconductor systems including the same

A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a command and a mask command. ... Sk Hynix Inc

06/15/17 / #20170168894

Data storage device and operating method thereof

A data storage device includes a first decoder suitable for performing first ecc decoding operation; a second decoder suitable for performing second ecc decoding operation; and a control unit suitable for controlling the first decoder to perform the first ecc decoding operation to data chunks read from a memory region respectively according to read voltage sets, and performing one of prioritization, reservation and omission of the second ecc decoding operation to a current data chunk when the first ecc decoding operation to the current data chunk fails.. . ... Sk Hynix Inc

06/15/17 / #20170168892

Controller for semiconductor memory device and operating method thereof

A controller includes a command generation unit suitable for generating a first read command for at least one page selected from said plurality of pages, an error correction block suitable for performing a first error correction operation to one or more code words stored in said at least one selected page in response to the first read command, and a command mirroring unit suitable for generating a mirrored command by mirroring the first read command.. . ... Sk Hynix Inc

06/15/17 / #20170168754

Memory storage device and operating method thereof

Disclosed are a memory storage device and an operating method thereof. The operating method writes data to a plurality of memory devices of the memory storage device through a controller, and performs interleaving programming on the plurality of memory devices. ... Sk Hynix Inc

06/15/17 / #20170168740

Reducing read disturb in data storage

A memory controller includes a data modulator and a data demodulator. The data modulator is configured to translate original data into modified data according to a conversion operation and write the modified data to the array of memory locations. ... Sk Hynix Inc

06/15/17 / #20170168722

Memory system and operating method of memory system

A memory system includes a memory device including a plurality of memory blocks; and a controller suitable for selecting for a garbage collection operation one or more source memory blocks among closed memory blocks in the plurality of memory blocks according to at least one parameter of the closed memory blocks and parameter deviations of the closed memory blocks depending on the at least one parameter.. . ... Sk Hynix Inc

06/08/17 / #20170163916

Pixel power noise cancelling apparaus and method, and cmos image sensor including the same

A pixel power noise cancelling apparatus may include: a ramp signal generator suitable for generating a ramp signal according to control of a controller; a pixel power noise copy unit suitable for copying a pixel power noise of a pixel column of a pixel array to superimpose on the ramp signal fed from the ramp signal generator to the pixel column and output a ramp signal with added pixel power noise; and a comparator suitable for comparing a pixel signal output by the pixel column with the ramp signal with added pixel power noise from the pixel power noise copy unit.. . ... Sk Hynix Inc

06/08/17 / #20170162594

Manufacturing method of semiconductor device

A method of manufacturing a semiconductor device includes sequentially stacking a source sacrificial layer, an upper protective layer, and an etch stop layer, which are formed of different materials from each other, over a substrate, alternately stacking interlayer dielectric layers and gate sacrificial layers over the etch stop layer, forming a first slit which penetrates the interlayer dielectric layers and the gate sacrificial layers, wherein a bottom surface of the first slit is disposed in the etch stop layer, replacing the gate sacrificial layers with gate conductive patterns through the first slit, forming a second slit which extends from the first slit through the etch stop layer and the upper protective layer to the source sacrificial layer, and replacing the source sacrificial layer with a first source layer through the second slit.. . ... Sk Hynix Inc

06/08/17 / #20170162591

Semiconductor device and manufacturing method thereof

A semiconductor device includes a first source seed layer, a second source seed layer disposed over the first source seed layer while being spaced apart from the first source seed layer, a stacked structure formed on the second source seed layer, channel layers extending inside the first source seed layer by penetrating the stacked structure, and an interlayer source layer extending into a space between the first source seed layer and the second source seed layer while contacting each of the channel layers, the first source seed layer, and the second source seed layer.. . ... Sk Hynix Inc

06/08/17 / #20170162516

Semiconductor packages including side shielding parts

A method of fabricating a semiconductor package is provided. The method includes providing a package substrate strip including chip mounting regions, bridge regions connecting the chip mounting regions to each other, and through slits disposed between the chip mounting regions. ... Sk Hynix Inc

06/08/17 / #20170162515

Semiconductor packages including a shielding part and methods for manufacturing the same

A method for manufacturing a semiconductor package and the semiconductor package are provided. The method for manufacturing a semiconductor package may include arranging a conductive elastic plate over a package substrate including through slits disposed along edges of a chip mounting region and a conductive guard rails providing a concave trench shape, and bending the conductive elastic plate. ... Sk Hynix Inc

06/08/17 / #20170162273

Memory device and operating method thereof

A memory device includes a pass/fail check circuit configured to compare the number of memory cells, which are verified as being a program fail based on a result of verifying program operations of a first group of memory cells of a plurality of memory cells, with a first reference bit number, and to check whether the first group of memory cells is a pass or fail and a control circuit configured to control the pass/fail check circuit to recheck whether the first group of memory cells is the pass or fail based on a second reference bit number smaller than the first reference bit number when the first group of memory cells is found to be the pass based on a result of a pass/fail check operation of the pass/fail check circuit.. . ... Sk Hynix Inc

06/08/17 / #20170162262

Resistive memory device and operation method thereof

A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell includes a data storage material and a non-silicon-substrate-based type bidirectional access device coupled in series, a path setting circuit coupled between the bit line and the word line, suitable for providing a program pulse toward the bit line or the word line based on a path control signal, a forward write command, and a reverse write command, and a control unit suitable for providing a write path control signal, a forward program command, and a reverse program command based on an external command signal.. . ... Sk Hynix Inc

06/08/17 / #20170162259

Memory system and operating method thereof

A memory system includes a memory device including a plurality of memory blocks, each memory block including a plurality of word lines, each word line being coupled to a plurality of memory cells, and a controller suitable for grouping the word lines into a plurality of word line groups, wherein when receiving a read command for data stored in a first memory block, the controller performs a read operation for word lines of the first memory block, checks for read fail word lines in the word lines of the first memory block, checks for word line groups including the read fail word lines, and transmits a set command corresponding to the read fail word lines to the word line groups which contain read fail word lines.. . ... Sk Hynix Inc

06/08/17 / #20170162245

Semiconductor system

A semiconductor system may include a controller and a semiconductor memory device. The controller may provide an external command, an external address and a first external clock. ... Sk Hynix Inc

06/08/17 / #20170162237

Semiconductor apparatus having multiple ranks with noise elimination

A semiconductor apparatus includes a plurality of dies. Any one of the dies may be set to a first rank and another of the dies may be set to a second rank. ... Sk Hynix Inc

06/08/17 / #20170162231

Memory device

A memory device may be provided. The memory device may include a plurality of channel areas including a plurality of cell array areas. ... Sk Hynix Inc

06/01/17 / #20170155859

Counting apparatus, analog-to-digital converter and image sensor including the same

A counting apparatus may include: a count control unit suitable for controlling a counting operation of a common value and a differential value of two pixel signals according to two neighboring output signals of a comparator unit; a counting unit suitable for counting a clock during a period corresponding to the common value and the differential value, according to control of the count control unit; and a memory unit suitable for storing count information from the counting unit and operation information from the count control unit.. . ... Sk Hynix Inc

06/01/17 / #20170155407

Techniques for low complexity turbo product code decoding

Techniques are described for decoding a codeword, including, obtaining a first message comprising a plurality of information bits and a plurality of parity bits, wherein the message corresponds to a turbo product code (tpc) comprising two or more constituent codes, wherein each constituent code corresponds to a class of error correcting codes capable of correcting a pre-determined number of errors, performing an iterative tpc decoding using at least one of a first decoder corresponding to a first constituent code and a second decoder corresponding to a second constituent code on the first message to generate a second message, determining if the decoding was successful. Upon determining that the tpc decoding was not successful, determining one or more error locations in the second message based on a third constituent code using a third decoder. ... Sk Hynix Inc

06/01/17 / #20170155382

Semiconductor integrated circuit device having delay circuit

A semiconductor integrated circuit device may include a first circuit, a second circuit, and a delay circuit. The first circuit may include an output node. ... Sk Hynix Inc

06/01/17 / #20170155239

Protection circuit

A protection circuit may include a first power line and a second power line, a plurality of high voltage interconnections, a plurality of low voltage interconnections, first and second pickup active regions, a high voltage protection transistor, and a low voltage protection transistor. The first power line and the second power line extending in parallel to each other while facing each other, and a plurality of high voltage interconnections are coupled to the first power line and extend toward the second power line while being spaced apart from each other. ... Sk Hynix Inc

06/01/17 / #20170155040

Electronic device and method for fabricating the same

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a free layer comprising cofegeb alloy, and having a changeable magnetization direction that is perpendicular to the free layer; a tunnel barrier layer positioned over the free layer, and configured for enabling electron tunneling; a pinned layer positioned over the tunnel barrier layer, and having a pinned magnetization direction that is perpendicular to the pinned layer; and a bottom layer positioned under the free layer, and having a b2 structure to improve a perpendicular magnetic crystalline anisotropy of the free layer.. ... Sk Hynix Inc

06/01/17 / #20170155039

Electronic device

This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include a free layer including a plurality of magnetic layers each having a variable magnetization direction; a tunnel barrier layer formed over the free layer; and a pinned layer formed over the tunnel barrier layer and having a pinned magnetization direction; wherein the plurality of magnetic layers in the free layer includes a first magnetic layer in contact with the tunnel barrier layer and a second magnetic layer not in contact with the tunnel barrier layer and a sum of an exchange field between the first magnetic layer and the second magnetic layer and a stray field generated by the first magnetic layer is larger than or the same as a difference between a uniaxial anisotropy field of the second magnetic layer and a demagnetizing field due to a shape of the second magnetic layer.. ... Sk Hynix Inc

06/01/17 / #20170154892

Electronic device and method for fabricating the same

Provided is an electronic device including a semiconductor memory, the semiconductor memory may include: a first channel layer formed over a substrate and extending in a vertical direction; a first stacked structure comprising a plurality of first interlayer dielectric layers arid a plurality of first gate electrode layers which are alternately stacked along the first channel layer; a first memory layer interpose d between the first channel layer and the first gate electrode layers; a second channel layer formed over the first channel layer and extending in the vertical, direction; a second stacked structure comprising, a plurality of second interlayer dielectric layers and a plurality of second gate electrode layers which are alternately stacked along the second channel layer; a second memory layer interposed between the second channel layer and the second gate electrode layers; a first channel connection pattern formed between the first channel layer and the second channel layer and coupling the first and the second channel layers to each other; and a first etch stop pattern formed between the first and second stacked structures and at substantially the same level as the first channel connection pattern, wherein the first etch stop pattern includes the same material as the first channel connection pattern and is isolated from the first channel connection pattern,. . ... Sk Hynix Inc

06/01/17 / #20170154872

Semiconductor packages including molded stacked die with terrace-like edges

A semiconductor package may include a first semiconductor die, external connectors, second semiconductor dies, a mold layer, an outer packaging part, and a terrace-like edge. The external connectors may be disposed over a first surface of the first semiconductor die. ... Sk Hynix Inc

06/01/17 / #20170154869

Flexible packages including chips

A flexible package may be provided. The flexible package may include a flexible molding member including a top surface. ... Sk Hynix Inc

06/01/17 / #20170154868

Semiconductor packages

A semiconductor package includes a first die including first chip pads disposed in a first chip pad region, first connecting pads spaced apart from the first chip pad region a predetermined distance and gathered in a first connecting pad region, and first redistribution layer patterns connecting the first chip pads to the first connecting pads, a second die including second chip pads disposed in a second chip pad region on the chip, second connecting pads spaced apart from the second chip pad region a predetermined distance and disposed in a second connecting pad region, and second redistribution layer patterns connecting the second chip pads to the second connecting pads, and a first semiconductor chip disposed below the first die and the second die, and electrically connected to the first connecting pads and the second connecting pads. The second connecting pad region is disposed adjacent to the first connecting pad region.. ... Sk Hynix Inc

06/01/17 / #20170154844

Electronic device including switching element and semiconductor memory

An electronic device including a semiconductor memory is provided to include a mat region comprising a plurality of memory cells, each including a second transistor; a first switching region located at a side of the mat region and including first transistors; and a second switching region located at the other side of the mat region and including third transistors, wherein the second transistors comprise: a plurality of second active regions; and a plurality of second gate structures extending in the first direction to cross the second active regions, wherein each second active regions is divided into a first side portion, a middle portion and a second side portion that are arranged alternately and repeatedly in the first direction, wherein the first transistors and the third transistors include their active regions and gate structures which are arranged in the same manner as those of the second transistors.. . ... Sk Hynix Inc

06/01/17 / #20170154817

Electronic device and method for fabricating the same

A semiconductor device may include: a plurality of first contacts arranged at a predetermined distance in a first direction and a second direction crossing the first direction; a plurality of second contacts alternately arranged between the first contacts and arranged at a predetermined distance in the first direction and the second direction; a plurality of dog bone-type conductive lines connected to the second contacts arranged in the second direction, respectively, among the plurality of second contacts, and having concave parts and convex parts; and a plurality of etching prevention patterns formed over the plurality of conductive lines so as to overlap the conductive lines, respectively.. . ... Sk Hynix Inc

06/01/17 / #20170154809

Methods of forming fine patterns including pad portion and line portion

A method of forming fine patterns includes forming a partition on a base layer. The partition includes a partition block, a first open region provided to face the partition block, and first lines extending from the partition block to the first open region. ... Sk Hynix Inc

06/01/17 / #20170154688

Memory device and operating method thereof

A memory device may include a plurality of memory cells; one or more backup memory cells; a test circuit suitable for performing a backup operation and a test operation to a test target cell selected among the plurality of memory cells; and a control circuit suitable for accessing the backup memory cells instead of the test target cell during the performance of the test operation after completion of the backup operation for the selected test target cell, wherein, during the backup operation, the test circuit controls the control circuit to copy an original data of the test target cell to a corresponding backup memory cell selected among the backup memory cells, and wherein, during the test operation, the test circuit determines whether the test target cell is a as a pass or a fail.. . ... Sk Hynix Inc

06/01/17 / #20170154680

Semiconductor memory device and operating method thereof

A semiconductor memory device may include a memory cell array including a plurality of cell strings, a peripheral circuit unit configured to perform a program loop for alternately performing a program operation and a verification operation on the memory cell array, and a control logic configured to control the peripheral circuit unit to perform the program loop, wherein, in performing the program loop, a second pass voltage applied to unselected word lines adjacent to a selected word line among a plurality of word lines coupled to the memory cell array is lower than a first pass voltage applied to remaining unselected word lines during the program operation, wherein a potential level of the first pass voltage is adjusted in accordance with an arrangement position of each of the plurality of word lines and the plurality of word lines are defined as a plurality of groups, and the first pass voltages applied to the plurality of groups, respectively, are different from one another.. . ... Sk Hynix Inc

06/01/17 / #20170154675

Memory and electronic device including the same

A semiconductor memory includes a cell array including a plurality of resistive memory cells in which a plurality of columns and a plurality of rows are arranged, a read voltage application circuit configured to apply a read voltage to a selected memory cell of the plurality of resistive memory cells, a sensing circuit configured to detect an amount of a current flowing through the selected memory cell and sense data, and an overcurrent prevention circuit configured to reduce voltage levels at both ends of the selected memory cell when an overcurrent flows through the selected memory cell.. . ... Sk Hynix Inc

06/01/17 / #20170154670

Memory device, refresh method, and system including the same

A memory device may be provided. The memory device may include an active control section configured to output a row active signal in response to a refresh signal when an active signal is activated. ... Sk Hynix Inc

06/01/17 / #20170154662

Electronic device

This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include: an under layer including a plurality of material layers having a different crystal structures; a first magnetic layer formed over the under layer and having a variable magnetization direction; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer and having a pinned magnetization direction.. ... Sk Hynix Inc

06/01/17 / #20170154661

Electronic device

This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include free layer having a variable magnetization direction; a tunnel barrier layer formed over the free layer; a pinned layer formed over the tunnel barrier layer and having a pinned magnetization direction; an exchange coupling layer formed over the pinned layer; and a magnetic correction layer formed over the exchange coupling layer, wherein the magnetic correction layer comprises a first magnetic layer, a spacer layer and a second magnetic layer that are sequentially stacked, and the first magnetic layer has a saturation magnetization smaller than a saturation magnetization of the second magnetic layer.. ... Sk Hynix Inc

06/01/17 / #20170154659

Nonvolatile memory device, semiconductor device, and method for operating semiconductor device

A nonvolatile memory device may include a plurality of cell strings including a plurality of memory cells serially coupled to one another; a plurality of bit lines coupled to a corresponding cell string of the plurality of cell strings; a plurality of page buffers each including a plurality of latches and coupled to a corresponding bit line of the plurality of bit lines; a first control circuit suitable for controlling the plurality of latches to perform an operation corresponding to an activated command signal of a plurality of command signals in an access operation; and a second control circuit suitable for activating one or more of the plurality of command signals, while controlling operations of the plurality of cell strings and the plurality of bit lines in the access operation.. . ... Sk Hynix Inc

06/01/17 / #20170154657

Data storage device and operating method thereof

A data storage device includes a memory device including memory regions classified into a plurality of memory groups each corresponding to a plurality read bias voltage groups; and a controller suitable for: performing for a target memory region a read retry operation based on a first read bias voltage group corresponding to a memory group in which the target memory region is included, and performing an additional read retry operation based on at least one of remaining read bias voltage groups excluding the first read bias voltage group among the plurality of read bias voltage groups, according to a result of the read retry operation.. . ... Sk Hynix Inc

06/01/17 / #20170153995

Data transfer device

A data transfer device includes a shifter block that generates first and second input signals and first and second output signals, an input/output control block that selects the first input signal and the first output signal in correspondence to a mode signal and outputs an input control signal and an output control signal for controlling a data input/output operation, or selects the second input signal and the second output signal and outputs the input control signal and the output control signal, and a buffer block that latches first input data or second input data which have different data bit widths according to the input control signal, and outputs first output data or second output data which have different data bit widths according to the output control signal.. . ... Sk Hynix Inc

06/01/17 / #20170153844

Memory system and operation method thereof

A memory system may include a first memory having a first operating speed, and a second memory having a second operating speed which is different from the first operating speed. A compression device may compress data of the first memory, and may transfer the compressed data to the second memory. ... Sk Hynix Inc

06/01/17 / #20170153657

Integrated circuit and method for driving the same

An integrated circuit includes: a source current generation block suitable for generating a source current; a first mirroring block suitable for generating first and second mirroring currents corresponding to the source current; a second mirroring block suitable for generating a third mirroring current and a reference current corresponding to the first mirroring current; a first correction block suitable for correcting a current mismatch between the source current, the first mirroring current and the second mirroring current based on the third mirroring current; and a second correction block suitable for correcting a current mismatch between the first mirroring current, the third mirroring current and the reference current based on the second mirroring current.. . ... Sk Hynix Inc

05/18/17 / #20170142357

Image sensor

An image sensor may include a pixel array in which a plurality of pixel units are arranged in a matrix structure. Each of the pixel units may include a light receiver suitable for generating photocharge in response to incident light, a floating diffusion node electrically coupled to an end of the light receiver, and a reset transistor electrically isolated from the floating diffusion node, wherein a floating diffusion node of a first pixel unit among the plurality of pixel units is electrically coupled to a reset transistor of a second pixel unit adjacent to the first pixel unit among the plurality of pixel units.. ... Sk Hynix Inc

05/18/17 / #20170141770

Signal processing circuit

A signal processing circuit may be provided. The signal processing circuit may include a mask generation circuit configured to output a mask signal in response to an internal control signal and masking information; and a masking circuit configured to mask the internal control signal in response to the mask signal, and output a masked control signal, wherein the mask generation circuit resets the mask signal in response to an internal reset signal, regardless of a pause polarity of the internal control signal.. ... Sk Hynix Inc

05/18/17 / #20170141183

Semiconductor integrated circuit device having with a reservior capacitor

A semiconductor integrated circuit device may include a through silicon via (tsv), a keep out zone and a plurality of dummy patterns. The tsv may be arranged in a selection region of a semiconductor substrate. ... Sk Hynix Inc

05/18/17 / #20170141159

Electronic device and method for fabricating the same

Implementations of the disclosed technology provide an electronic device including a semiconductor memory and a method for fabricating the same, in which processes are easily performed and the characteristics of a variable resistance element are improved. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a substrate; a conductive contact plug formed over the first conductive layer and including a stack of a conductive low-resistance structure and a conductive planarizing layer; and a variable resistance pattern coupled to the contact plug, wherein the low-resistance structure comprises a diffusion barrier layer, a low-resistance material layer and a gap-fill layer.. ... Sk Hynix Inc

05/18/17 / #20170141034

Power line layout structure of semiconductor device and method for forming the same

A power line layout structure of a semiconductor device and a method for forming the same are disclosed. The power line layout structure of the semiconductor device includes a first block region including a plurality of first and second power lines, a second block region including a plurality of first and second power lines spaced apart from the first block region by a predetermined distance. ... Sk Hynix Inc

05/18/17 / #20170141032

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate including a cell area, a first contact area, and a second contact area; a lower stacked structure extending over the second contact area from the cell area; an upper stacked structure extending over the first contact area from the cell area, the upper stacked structure leaving the second contact area open; n (n is a natural number of 2 or more) first group of stepped grooves penetrating at least one portion of the upper stacked structure in the first contact area; and m (m is a natural number equal to or smaller than n) second group of stepped grooves penetrating at least one portion of the lower stacked structure in the second contact area.. . ... Sk Hynix Inc

05/18/17 / #20170141025

Semiconductor device and semiconductor package

A semiconductor device may include a first metal line; a second metal line; a first insulating layer formed between the first metal line and the second metal line; a first driving unit coupled to the first metal line, the first driving unit being suitable for driving the first metal line in response to first data; and a second driving unit coupled to the second metal line, the second driving unit being suitable for driving the second metal line in response to second data obtained by inverting and delaying the first data.. . ... Sk Hynix Inc

05/18/17 / #20170140834

Control signal generation circuit and non-volatile memory device including the same

A control signal generation circuit may include: a counting unit suitable for generating counting information; a first signal generation unit suitable for activating/deactivating a first signal based on the counting information, first rising information, and first falling information; a second signal generation unit suitable for activating/deactivating a second signal based on the counting information, second rising information, second falling information, and the first falling information; and a control signal driving unit suitable for driving a control signal in response to the first and second signals.. . ... Sk Hynix Inc

05/18/17 / #20170140823

Nand flash memory comprising a current sensing page buffer

Disclosed herein is a flash memory including a bit-line and a page buffer circuit. The page buffer circuit may include: a first node; a first switching circuit configured to pre-charge the bit-line based on a voltage provided to the first switching circuit; a sensing node; a second switching circuit configured to discharge the sensing node when the voltage value of the first node is lower than a voltage value associated with a voltage inputted to the second switching circuit during an evaluation period; a sense latch configured to latch a voltage being determined based on the voltage level of the sensing node, during a strobe period; and a third switching circuit configured to prevent the voltage value of the first node from being lower than a voltage value associated with a voltage inputted to the third switching circuit independently from the voltage at the sense latch.. ... Sk Hynix Inc

05/18/17 / #20170140813

Nonvolatile memory device havng connection unit for allowing precharging of bit lines in single step

A nonvolatile memory device may include a cell string comprising a plurality of memory cells coupled in series; a bit line coupled to the cell string; a page buffer suitable for driving a sensing node to a ground voltage, a middle voltage, and a core voltage during a normal program operation, a slow program operation and a program inhibition operation, respectively; and a connection unit suitable for coupling the bit line to the sensing node in response to a control signal of a first voltage during the slow program operation, and in response to the control signal of a second voltage higher than the first voltage during the normal program operation and the program inhibition operation.. . ... Sk Hynix Inc

05/18/17 / #20170140811

Refresh control circuit and memory device including same

A memory device may include: at least one memory bank; and a control circuit suitable for: refreshing the at least one memory bank through a first refresh operation in response to a refresh command; and refreshing the at least one memory bank through a second refresh operation when an active operation is performed between a current refresh command and a previous refresh command.. . ... Sk Hynix Inc

05/18/17 / #20170140803

Control signal generation circuit and non-volatile memory device including the same

A control signal generation circuit may include: a counting unit suitable for generating counting information; a first signal generation unit suitable for activating/deactivating a first signal based on the counting information, first rising information, and first falling information; a second signal generation unit suitable for activating/deactivating a second signal based on the counting information, second rising information, second falling information, and the first falling information; and a control signal driving unit suitable for driving a control signal in response to the first and second signals.. . ... Sk Hynix Inc

05/18/17 / #20170140802

Data storage device and operating method thereof

A data storage device includes a memory device including a plurality of memory cells; and a controller suitable for determining, based on data read from the plurality of memory cells, section cell numbers corresponding to threshold voltage sections, and for determining an average threshold voltage of a threshold voltage distribution selected among a plurality of threshold voltage distributions of the memory cells which are estimated based on the section cell numbers, based on a gaussian distribution function.. . ... Sk Hynix Inc

05/18/17 / #20170139646

Memory system and operating method thereof

A memory system may include a memory device comprising a plurality of memory blocks each having a plurality of pages; and a controller suitable for storing data in a first memory block among the memory blocks, storing map data of the data in a second memory block among the memory blocks, and scanning the map data by performing filtering on logical information of the data in response to a command.. . ... Sk Hynix Inc

05/18/17 / #20170139645

Memory system and operating method thereof

A memory system may include a memory device including a plurality of memory blocks each having a plurality of pages suitable for storing data requested from a host, and a controller including a memory, and suitable for storing write data corresponding to a write command received from the host in a first memory block of the memory blocks, storing first and second map data corresponding to the write data written to the first memory block in a second memory block of the memory blocks, and storing a segment list for first segments of the first map data in the memory.. . ... Sk Hynix Inc

05/18/17 / #20170139643

Memory system and operating method of memory system

The memory system may include a memory device including: a plurality of planes each including a plurality of memory blocks suitable for storing data, and a plurality of page buffers corresponding to the planes; and a controller including a memory, the controller being suitable for performing a read operation to the memory blocks of a first plane storing a first data corresponding to a read command among the planes by referring to a meta-data of the first data, and for providing the first data to a host; wherein the meta-data is stored in the memory or the page buffers.. . ... Sk Hynix Inc

05/18/17 / #20170139638

Memory system and operating method thereof

This technology relates to a memory system supporting a one-shot program and an operating method of the memory system the memory system may include: a first memory device comprising a first multi-level cell and a first multi-level buffer, a second memory device comprising a second multi-level cell and a second multi-level buffer, and a controller suitable for buffering input data in the first and the second multi-level buffers in an interleaving way, for rearranging and storing the buffered input data in a multi-level buffer selected from the first and second multi-level buffers if the input data have a size smaller than or equal to a preset size, wherein a one-shot program is performed on a memory device including the selected multi-level buffer.. . ... Sk Hynix Inc

05/18/17 / #20170139628

Electronic device

An electronic device includes semiconductor memory. The semiconductor memory includes a cell array comprising a plurality of resistive memory cells arranged in a plurality of columns and a plurality of rows; and an access circuit applying a first voltage or a second voltage to a first node of a selected memory cell of the plurality of resistive memory cells, and applying a third voltage to a second node of the selected memory cell, the third voltage having a magnitude that is substantially the same as that of the first voltage and having a polarity that is opposite to a polarity of the first voltage.. ... Sk Hynix Inc

05/18/17 / #20170139627

Memory system and operating method of memory system

A memory system may include a memory device comprising a plurality of memory blocks, each of the plurality of memory blocks comprising a plurality of pages having a plurality of memory cells coupled to a plurality of word lines, the memory device being suitable for storing read data and write data requested by a host in the plurality of pages, and a controller suitable for grouping the plurality of pages included in the memory blocks, dividing each of the memory blocks into a plurality of sub-memory blocks, programming data corresponding to a write command received from the host into a first memory block of the memory blocks, performing an update program on the data programmed into the first memory block into the memory blocks in response to a write command for the data programmed into the first memory block from the host, and storing a map list for the sub-memory blocks included in the first memory block in accordance with the update program.. . ... Sk Hynix Inc

05/18/17 / #20170139603

Memory system and operating method thereof

A memory system may include: a plurality of memory blocks each including a plurality of page zones each page zone including a plurality of pages suitable for storing data; and a controller suitable for updating one or more closed memory blocks, by storing data into another memory block among the memory blocks in response to a write command for the one or more closed memory blocks, and updating a map list indicating one or more invalid page zones each of which contains only invalid pages in the closed memory blocks, as a result of the updating of the closed memory blocks.. . ... Sk Hynix Inc

05/11/17 / #20170134014

Duty cycle detector

A duty cycle detector may include a rising clock detection unit enabled in response to a first control signal; a falling clock detection unit enabled in response to a second control signal with a different activation timing from the first control signal; and a comparison unit configured to compare an output signal of the rising clock detection unit to an output signal of the falling clock detection unit in response to a comparison enable signal, and output a duty cycle detection signal.. . ... Sk Hynix Inc

05/11/17 / #20170134006

Impedance calibration circuit

An impedance calibration circuit is disclosed, which relates to a technology for improving precision of pad resistance. The impedance calibration circuit includes: a first on die termination (odt) circuit selected by a first selection signal, configured to tune its own resistance using a first code signal, and output a first resistance value to an output terminal; and a second odt circuit selected by a second selection signal, configured to tune its own resistance using a second code signal, and output a second resistance value to the output terminal.. ... Sk Hynix Inc

05/11/17 / #20170133583

Platinum and cobalt/copper-based multilayer thin film having low saturation magnetization and fabrication method thereof

A multilayer thin film for magnetic random access memory that includes thin platinum layers and thin cobalt-copper layers, and more particularly, to a multilayer thin film having magnetic layers including non-magnetic material copper that replaces a portion of the magnetic material cobalt.. . ... Sk Hynix Inc

05/11/17 / #20170133418

Latch circuit, double data rate ring counter based on the latch circuit, hybrid counting device, analog-digital converting device, and cmos image sensor

Disclosed are a latch circuit receiving a negative output of a next stage latch circuit as a feedback input, a double data rate (ddr) ring counter based on the latch circuit to perform ddr counting of pulse periods and reduce the number of toggles, a hybrid counting device counting lower-bit portion by using the latch-based ddr ring counter and upper-bit portion by using a binary counter, and an analog-to-digital converting device and a cmos image sensor employing the hybrid counting device. A double data rate ring counter may include a plurality of latches coupled in a ring type. ... Sk Hynix Inc

05/11/17 / #20170133397

Three-dimensional semiconductor device and manufacturing method thereof

There are provided a 3-d semiconductor device and a manufacturing method thereof. The 3-d semiconductor device includes a substrate extending along a first plane defined by first and second x and y directions, the substrate having a pipe transistor formed therein, a plurality of word lines spaced apart at regular intervals along a third direction z perpendicular to the first and second x and y directions; a first vertical plug connected to a first end of the pipe transistor by passing vertically through the word lines; a second vertical plug, connected to a second end of the pipe transistor by passing vertically through the word lines; a bit line connected to a top surface of the first vertical plug; and a source line connected to a top surface of the second vertical plug, wherein the first and second vertical plugs have different size.. ... Sk Hynix Inc

05/11/17 / #20170133223

Method of manufacturing semiconductor device

In accordance with an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include forming an opening passing-through a multi-layer stack, forming a channel layer on and along a sidewall of the opening, forming a conductive layer on and along a sidewall of the channel layer, and applying a laser to the conductive layer to transfer a heat from the conductive layer to the channel layer to heat-treat the channel layer using the heat.. . ... Sk Hynix Inc

05/11/17 / #20170133109

Semiconductor apparatus and repair method thereof

A semiconductor apparatus includes a memory region; a fuse array including a plurality of fuse groups, each fuse group being configured to store a failed address of the memory region; a remaining-fuse information storage unit configured to store remaining-fuse information on a fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups; and a control unit configured to perform a control operation for updating the remaining-fuse information for the fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups and for storing the failed address when the failed address is detected.. . ... Sk Hynix Inc

05/11/17 / #20170133103

Stack type semiconductor memory and semiconductor system using the same

A stack type semiconductor memory includes a plurality of stacked dies configured to transmit signals through a plurality of through electrodes. Any one die of the plurality of stacked dies is configured to provide preliminary test mode signals to other dies through the plurality of through electrodes, and the other dies are configured to generate test mode signals according to the preliminary test mode signals transmitted through the plurality of through electrodes.. ... Sk Hynix Inc

05/11/17 / #20170133093

Semiconductor memory device and operating method thereof

Disclosed are a semiconductor memory device, and an operating method thereof. The semiconductor memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program pulse application operation and a verification operation on the memory cell array; a pass/fail check circuit configured to output a pass/fail signal according to a result of the verification operation; and a control logic configured to control the peripheral circuit to perform the program pulse application operation and the verification operation such that two or more program pulses are continuously applied during the program pulse application operation, and first and second verification operations are continuously performed during the verification operation.. ... Sk Hynix Inc

05/11/17 / #20170133086

Semiconductor device

A semiconductor device includes a decoded signal generation circuit suitable for executing a counting operation to generate a decoded signal in response to an oscillation signal during a refresh section, a refresh pulse generation circuit suitable for generating a refresh pulse for executing a refresh operation in response to the decoded signal and a temperature code, and a reset pulse generation circuit suitable for generating a reset pulse initializing the decoded signal in response to the refresh pulse.. . ... Sk Hynix Inc

05/11/17 / #20170133084

Semiconductor device and driving method thereof

A semiconductor device includes a sense amplification unit suitable for sensing and amplifying data loaded on a data line pair; a pull-up driving unit suitable for supplying a first voltage to a pull-up power line of the sense amplification unit as a pull-up driving voltage in an active mode, and supplying second voltage higher than the first voltage to the pull-up power line as the pull-up driving voltage during an initial period of a precharge mode; a pull-down driving unit suitable for supplying a third voltage to a pull-down power line of the sense amplification unit as a pull-down driving voltage during the active mode and the initial period of the precharge mode; and a post over-driving control unit suitable for adjusting the initial period of the precharge mode by detecting a voltage level of the pull-up power line.. . ... Sk Hynix Inc

05/11/17 / #20170133079

Semiconductor systems for fast sensing speed and correct amplification

A semiconductor device may include a power control signal generator and a sense amplifier circuit. The power control signal generator may generate a first power control signal, an enablement moment of the first power control signal controlled according to a logic level combination of temperature code signals in response to a mode signal. ... Sk Hynix Inc

05/11/17 / #20170133071

Semiconductor device and semiconductor system

A semiconductor system includes a first semiconductor device configured to output command addresses; and a second semiconductor device configured to generate a first control signal including a pulse controlled in its pulse width in synchronization with a toggling time of a bank active signal for selecting a bank to be activated in an active operation in response to the command addresses, a second control signal enabled in response to the bank active signal, and an internal voltage in response to the first and second control signals.. . ... Sk Hynix Inc

05/11/17 / #20170133069

Semiconductor memory apparatus having open bit line structure

A semiconductor memory apparatus may include a memory bank having a plurality of memory cell arrays. The memory bank may have an open bit line structure. ... Sk Hynix Inc

05/11/17 / #20170133068

Memory system and operation method thereof

An address generation device of a memory system includes an address generator and a synchronizer. The address generator may receive a clock and sequentially generate a first address and a second address after the first address. ... Sk Hynix Inc

05/11/17 / #20170133067

Input circuit of three-dimensional semiconductor apparatus capable of enabling testing and direct access

An input circuit of a semiconductor apparatus may include a first input buffer configured to receive a signal through a test input terminal and to output a first input signal, a second input buffer configured to receive a signal through a normal input terminal and to output a second input signal. The input circuit of the semiconductor apparatus may include a switching unit configured to transfer the signal inputted through the test input terminal to the second input buffer according to a test mode signal. ... Sk Hynix Inc

05/11/17 / #20170133065

Latch circuit and double data rate decoding device based on the same

Disclosed are a latch circuit receiving a negative output of a next latch stage circuit as a feedback input, a double data rate (ddr) ring counter based on the latch circuit to perform ddr counting of pulse periods and reduce the number of toggles, a hybrid counting device counting lower-bit portion by using the latch-based ddr ring counter and upper-bit portion by using a binary counter, and an analog-to-digital converting device and a cmos image sensor employing the hybrid counting device. A double data rate ring counter may include a plurality of latches coupled in a form of a ring. ... Sk Hynix Inc

05/11/17 / #20170132125

Selective data recycling in non-volatile memory

Embodiments are directed to methods of classifying a flash memory block of n-level cells into sub-blocks. The n-level cells can store n bits of data. ... Sk Hynix Inc

05/11/17 / #20170132074

Systems and methods for copying data in non-volatile memory

Techniques and systems are provided for copying, with or without error-fixing or corrections, data associated with a first set of locations to a second set of locations in a flash memory. Example methods disclosed, when performed by a flash memory controller, can significantly improve latency of operations. ... Sk Hynix Inc

05/11/17 / #20170132072

Semiconductor device

Provided is a semiconductor device including an error correction code circuit. The semiconductor device includes a bank including a memory area for storing data and an error correction for storing parity data, an error correction code calculation circuit that corrects an error of a failed cell in correspondence to the data and the parity data and outputs a flag signal activated at a time of a generation of failed data and an address activated in the bank, an address latch circuit that stores the address applied from the error correction code to calculation circuit and outputs a failed address according to the flag signal, and a fail prevention circuit that performs an operation for repairing the failed data in correspondence to the flag signal and the failed address.. ... Sk Hynix Inc

05/11/17 / #20170131925

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device, and a controller configured to construct logical address sets each including a start logical address and valid address flags corresponding to the start logical address, from logical addresses provided from a host device, generate an address mapping table by mapping each of the logical address sets to a physical address of the nonvolatile memory device, and perform a request from the host device, by referring to the address mapping table.. . ... Sk Hynix Inc

05/11/17 / #20170131916

Memory device and method of operating the same

Disclosed herein are a memory device and a method of operating the memory device. The memory device may include a memory cell array, a peripheral circuit, and a control logic. ... Sk Hynix Inc

05/11/17 / #20170131628

Photomask blank and method of fabricating a photomask using the same

A photomask blank includes a substrate, a phase shifting layer disposed on the substrate, a first light blocking layer disposed on the phase shifting layer, a first resist layer disposed on the first light blocking layer, a second light blocking layer disposed on the first resist layer, and a second resist layer disposed on the second light blocking layer.. . ... Sk Hynix Inc

05/11/17 / #20170131330

Semiconductor device

A semiconductor device includes a period defining block suitable for generating a period defining signal corresponding to a predetermined test time period based on a test mode signal and one or more command signals; and a monitoring block suitable for generating a monitoring signal corresponding to an oscillation signal during the test time period based on the period defining signal.. . ... Sk Hynix Inc

05/04/17 / #20170127001

Ramp voltage generator, image sensing device including the same and method for driving the image sensing device

A ramp voltage generator may include: a correction block suitable for generating a slope correction signal for first and second periods based on a period signal for distinguishing the periods; a common bias voltage generation block suitable for generating a common bias voltage based on the slope correction signal and a source bias voltage; and a first ramp voltage generation block suitable for generating a first ramp voltage having a predetermined slope during the first period based on the common bias voltage and a first ramp group control signal; and a second ramp voltage generation block suitable for generating ramp voltages having the predetermined slope during the second period based on the common bias voltage and a second ramp group control signal.. . ... Sk Hynix Inc

05/04/17 / #20170125532

Semiconductor structure having buried gate structure, method for manufacturing the same, and memory cell having the same

A method for forming a semiconductor structure includes forming a trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the trench; forming a work function layer over the gate dielectric layer; recessing the work function layer, and forming a gate electrode which is positioned in the trench; and exposing the gate electrode to a thermal process, and forming a dipole induction layer between the gate electrode and the gate dielectric layer.. . ... Sk Hynix Inc

05/04/17 / #20170125422

Semiconductor device having buried gate structure, method for manufacturing the same, memory cell having the same, and electronic device having the same

A semiconductor device includes a substrate including a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned in the trench at a level lower than a top surface of the substrate, and including a first buried portion and a second buried portion over the first buried portion; and a first doping region and a second doping region formed in the substrate on both sides of the gate electrode, and overlapping with the second buried portion, wherein the first buried portion includes a first barrier which has a first work function, and the second buried portion includes a second barrier which has a second work function lower than the first work function.. . ... Sk Hynix Inc

05/04/17 / #20170125285

Semiconductor device

A semiconductor device including a first stacked structure including first conductive layers and first insulating layers stacked alternately with each other, first semiconductor patterns arranged in a first direction, wherein each of the first semiconductor patterns passes through the first stacked structure in a stacking direction, a second stacked structure including second conductive layers and second insulating layers stacked alternately with each other, second semiconductor patterns arranged in the first direction and adjacent to the first semiconductor patterns in a second direction crossing the first direction, wherein each of the second semiconductor patterns passes through the second stacked structure in the stacking direction, a third stacked structure including air gaps and third insulating layers stacked alternately with each other and located between the first and second structures, and at least one blocking pattern passing through the third stacked structure in the stacking direction and contacting the first and second structures.. . ... Sk Hynix Inc

05/04/17 / #20170125127

Memory system and operating method thereof

A memory system may include a semiconductor memory device including a plurality of memory blocks, and a controller for controlling the semiconductor memory device to perform a general operation on a selected memory block among the plurality of memory blocks. When the selected memory block is determined as fail based on a result of a status check operation performed during the general operation, the controller performs a verify operation of determining whether the selected memory block is a fake bad block or a real bad block.. ... Sk Hynix Inc

05/04/17 / #20170125118

Adaptive scheme for incremental step pulse programming of flash memory

According to an adaptive programming method for flash memories, the cell programming speed is detected by programming a number of cells using a fixed trial program voltage. A starting program voltage vstart is then adjusted based on the detected cell programming speed. ... Sk Hynix Inc

05/04/17 / #20170125107

Storage device, memory system having the same, and operating method thereof

There are provided a storage device, a memory system having the same, and an operating method thereof. A storage device includes a plurality of memory blocks for storing data, a peripheral circuit for selecting multiple memory blocks from among the plurality of memory blocks and simultaneously performing an erase operation on the multiple memory blocks, and a control circuit for controlling the peripheral circuit so that the multiple memory blocks are simultaneously erased, and an erase operation and an erase verification operation of a selected memory block from among the multiple memory blocks are performed.. ... Sk Hynix Inc

05/04/17 / #20170125102

Semiconductor memory device and operating method thereof

A memory device includes a plurality of memory cells each programmed to have any one program state among a plurality of program states divided based on a threshold voltage thereof, and a peripheral circuit for performing a main program operation on the plurality of memory cells, and performing an additional program operation on at least one memory cell of which a threshold voltage regarding the main program operation is changed while the main program operation is being performed.. . ... Sk Hynix Inc

05/04/17 / #20170125100

Peripheral circuit, semiconductor memory device and operating method of the semiconductor device and/or peripheral circuit

The present disclosure relates to an electronic device, and more particularly, to a peripheral circuit, semiconductor memory device, and an operating method of the semiconductor memory device and/or peripheral circuit. The method of operating the semiconductor memory device may include turning on pass transistors.. ... Sk Hynix Inc

05/04/17 / #20170125094

Nonvolatile memory apparatus

A nonvolatile memory apparatus includes a sensing voltage generation unit, a memory cell, a current copy unit and a data sensing unit. The sensing voltage generation unit provides a sensing voltage with a constant level, to a sensing node. ... Sk Hynix Inc

05/04/17 / #20170125093

Nonvolatile memory apparatus

A nonvolatile memory apparatus includes a sensing voltage generation unit, a memory cell, a current copy unit and a data sensing unit. The sensing voltage generation unit provides a sensing voltage with a constant level, to a sensing node. ... Sk Hynix Inc

05/04/17 / #20170125072

Semiconductor apparatus

A semiconductor apparatus may be provided. The semiconductor apparatus may include a plurality of memory blocks. ... Sk Hynix Inc

05/04/17 / #20170125069

Semiconductor device including multiple planes

Provided herein is a semiconductor device including first and second regulators suitable for respectively generating first and second regulating voltages; first and second planes; a first peripheral circuit suitable for operating the first plane using the first regulating voltage; and a second peripheral circuit suitable for operating the second plane using the second regulating voltage, wherein the first regulator further provides a first reference voltage to the second regulator, and wherein the second regulator generates the second regulating voltage based on the first reference voltage.. . ... Sk Hynix Inc

05/04/17 / #20170124005

Electronic system and electronic device capable of capturing high speed signal

An electronic system may include a host, a memory, a data recording system, and a driving circuit. The driving circuit may drive a signal transferred between the host and the memory. ... Sk Hynix Inc

05/04/17 / #20170123990

Data storage device and operating method thereof

A method for operating a data storage device includes: dividing a cache into a plurality of cache areas; grouping a plurality of logical addresses into a plurality of logical address groups; allocating indexes to the respective logical address groups; and matching a read-requested first logical address set, a first cache area where data corresponding to the first logical address set are cached and an empty size of the first cache area, to an index corresponding to a logical address group to which the first logical address set belongs.. . ... Sk Hynix Inc

05/04/17 / #20170123974

Memory system and operation method thereof

A memory system may include a plurality of memory devices each including a plurality of memory blocks, suitable for copying data of valid pages included in a victim block selected from the plurality of memory blocks into a target block by sharing a buffer memory, during a garbage collection operation, and a buffer manager suitable for sequentially copying the data to an available area of the buffer memory.. . ... Sk Hynix Inc

05/04/17 / #20170123973

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device including a plurality of memory units; and a controller suitable for acquiring a temperature information for a current temperature, and for selectively adding a position information of a memory unit to a management list according to the temperature information.. . ... Sk Hynix Inc

05/04/17 / #20170123904

Semiconductor device and driving method thereof

Provided are a semiconductor device including an error correction code circuit and a driving method thereof. The semiconductor device includes a plurality of normal mats including a plurality of memory cells and connected to data lines, a plurality of dummy mats arranged in specific areas of the plurality of normal mats and inputting/outputting parity bits through parity lines of a specific circuit, a plurality of free ecc (error correction code) calculation circuits that perform ecc calculation corresponding to data applied through the data lines and the parity lines, and a main ecc calculation circuit that combines data applied from the plurality of free ecc calculation circuits with one another and performs ecc calculation.. ... Sk Hynix Inc

05/04/17 / #20170123896

Memory device and system including on chip ecc circuit

An on-chip logic block may include a host ecc circuit configured to correct an error based on host parity. The on-chip logic block may include a memory ecc circuit configured to correct an error based on memory parity.. ... Sk Hynix Inc

05/04/17 / #20170123892

Parity check circuit and memory device including the same

A parity check circuit may include a first signal combination unit for generating first to nthcombination signals by combining first to nth signals, wherein a kth (k is a natural number of 2≦k≦n) combination signal of the first to nthcombination signals is obtained by combining the first to kth signals of the first to nthsignals, a parity check unit for detecting whether an error is present in the first to nthsignals in response to the nth combination signal, a second signal combination io unit for generating first to nth reconstruction signals by combining the first to nth combination signals, wherein a kthreconstruction signal of the first to nthreconstruction signals is obtained by combining a (k−1)th combination signal and the kth combination signal of the first to nthcombination signals, and a signal storage unit for storing the first to nthreconstruction signals.. . ... Sk Hynix Inc

05/04/17 / #20170123695

Semiconductor device and method for driving the same

A semiconductor device includes: a first memory chip including a plurality of first memory regions; a temporary memory chip including a plurality of temporary memory regions; and a control chip suitable for accessing a first access target memory region among the plurality of first memory regions or a first temporary memory region among the plurality of temporary memory regions based on first access information and first temperature readout information corresponding to the plurality of first memory regions.. . ... Sk Hynix Inc

05/04/17 / #20170123304

Method of fabricating reflective photomask

A method of fabricating a reflective photomask is provided. The method includes sequentially forming a multi-layered reflective layer, an absorption layer and an anti-reflective coating (arc) layer on a substrate. ... Sk Hynix Inc

04/27/17 / #20170117897

Internal voltage generation circuit

An internal voltage generation circuit may be provided. The internal voltage generation circuit may include a pulse generation circuit configured to generate a first pulse and a second pulse in response to an external voltage. ... Sk Hynix Inc

04/27/17 / #20170117457

Electronic device and method for fabricating the same

An electronic device and a method for fabricating the same are provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes a magnetic tunnel junction (mtj) structure including: a free layer having a changeable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer sandwiched between the free layer and the pinned layer, wherein the free layer includes a cofealb alloy.. ... Sk Hynix Inc

04/27/17 / #20170117325

Electronic device and method for fabricating the same

An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: interlayer insulating layers and conductive first base layer patterns that are alternatively stacked over a substrate; a dielectric second base layer pattern that is in contact with sidewalls of the interlayer insulating layers; first electrodes that are in contact with sidewalls of the first base layer patterns; a second electrode disposed over outer sidewalls of the first electrodes; and a variable resistance layer pattern interposed between the first electrodes and the second electrode. Each of the first electrodes comprises an alloy that includes first and second elements. ... Sk Hynix Inc

04/27/17 / #20170117294

Electronic device and method for manufacturing the same

A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.. . ... Sk Hynix Inc

04/27/17 / #20170117287

Nonvolatile memory devices having single-layered gates and methods of fabricating the same

A nonvolatile memory device includes an active region extending in a first direction and including a source region and a drain region that are respectively disposed at both ends of the active region, a gate electrode pattern extending in a second direction and disposed between the source region and the drain region, wherein the second direction extends across the first direction, a gate insulation pattern disposed between the gate electrode pattern and the active region, a source contact plug and a drain contact plug respectively coupled to the source region and the drain region, and a coupling contact plug disposed over the gate electrode pattern and insulated from the gate electrode pattern.. . ... Sk Hynix Inc

04/27/17 / #20170117182

Semiconductor device and method of manufacturing the same

A semiconductor device may comprise a plurality of conductive lines and a plurality of contact plugs. The plurality of conductive lines may include a first conductive line a second conductive line. ... Sk Hynix Inc

04/27/17 / #20170117057

Semiconductor memory device

A semiconductor memory device includes a memory array region including normal cells and redundancy cells; a repair fuse block including a plurality of fuse sets suitable for programming repair addresses of the repair target cells as repair information, the repair fuse block being suitable for outputting the programmed repair information, in response to a boot-up signal; a fuse information storage block including a plurality of memory cells for storing the repair information outputted from the repair fuse block, the plurality of memory cells being refreshed simultaneously with the normal cells and the redundancy cells of the memory array region; and a repair control block suitable for comparing the repair information stored in the fuse information storage block and an address to generate a repair control signal to selectively activate redundant paths between the repair target cells and the redundancy cells.. . ... Sk Hynix Inc

04/27/17 / #20170117045

Electronic device

Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory unit comprising one or more columns and a date line and a data line bar connected with a column selected among the one or more columns. Each of the one or more columns includes a plurality of storage cells each configured to store 1-bit data, each storage cell including a first and second variable resistance elements; a bit line and a source line connected to the first variable resistance element; connected to the other end of the first variable resistance element; a bit line bar and a source line bar connected to the second variable resistance element; and a driving block configured to latch data of the data line and the data line bar.. ... Sk Hynix Inc

04/27/17 / #20170117031

Internal strobe signal generating circuit capable of selecting data rate and semiconductor apparatus including the same

An internal strobe signal generating circuit may include a data rate selection circuit, a division circuit and a strobe output circuit. The data rate selection circuit may enable a data rate selection signal according to operational information. ... Sk Hynix Inc

04/27/17 / #20170117025

Page buffer and semiconductor memory device including the same

A semiconductor memory device may include a memory cell array including a plurality of memory cells, and a plurality of page buffers respectively coupled to a plurality of bit lines of the memory cell array, the page buffers being supplied with internal voltages to precharge the plurality of bit lines or to sense an amount of current flowing through the plurality of bit lines, during a sensing operation, wherein each of the page buffers converts the internal voltages into supply voltages having constant potential levels.. . ... Sk Hynix Inc

04/27/17 / #20170117023

Semiconductor device and semiconductor system

A semiconductor system may include a first semiconductor device configured to output commands, addresses and data. The semiconductor system may include a second semiconductor device configured to convert a logic level combination of the data when only any one of bits of the data is a different logic level, and store the data in response to the commands and the addresses, in a write operation.. ... Sk Hynix Inc

04/27/17 / #20170116083

Memory system and method of operating the same

In one aspect of the present disclosure, there is provided a memory system comprising a memory device configured to temporarily store data therein, the data being loaded thereon for programming a selected page among multiple pages, the memory device further configured to program the selected page using the data; and a controller configured to send the data to the memory device, wherein the controller is further configured to control the memory device such that, in a failure event of the program for the selected page the memory device re-programs another page using the data temporarily stored therein without receipt of further data from the controllers. . ... Sk Hynix Inc

04/27/17 / #20170115914

Memory system and operating method thereof

A memory system may include: a memory device comprises a plurality of memory blocks, and a controller including a controller buffer. The controller may be suitable for storing command data corresponding to a command received from a host in a memory buffer included in the plurality of memory blocks or in the controller buffer based on context information included in the command data.. ... Sk Hynix Inc

04/27/17 / #20170115647

Reference voltage generation circuit, receiver, semiconductor apparatus and system using the same

A reference voltage generation circuit may be provided. The reference voltage generation circuit may be configured to generate a reference voltage according to a voltage set code. ... Sk Hynix Inc

04/20/17 / #20170111036

Duty cycle detector circuit

A duty cycle detector (dcd) circuit may include: a duty cycle detector including one or more capacitor sets which are charged, discharged, or charged and discharged a clock, and suitable for detecting a duty cycle of the clock; and a frequency detector suitable for detecting a frequency of the clock. Each of the one or more capacitor sets has an adjustable capacity according to the frequency detection result of the frequency detector.. ... Sk Hynix Inc

04/20/17 / #20170111034

Buffer circuit, semiconductor integrated circuit, and system including the buffer circuit

According to an embodiment, a buffer circuit may be provided. The buffer circuit may include a first buffer configured to receive first and second external clock signals and generate a first pre-clock signal based on falling timings of the first and second external clock signals. ... Sk Hynix Inc

04/20/17 / #20170110964

Voltage regulator and operating method thereof

A voltage regulator includes a voltage regulation unit that regulates an external power supply voltage and outputs an internal voltage, and an optimization control unit that adjusts a bias current, drivability, and output capacitance of the voltage regulation unit in response to a training enable signal and optimizes the internal voltage to a predetermined value.. . ... Sk Hynix Inc

04/20/17 / #20170110513

Electronic device and method for fabricating the same

An electronic device and a method for fabricating the same are provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a plurality of first lines extending in a first direction; a plurality of second lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements disposed between the first lines and the second lines and located at intersections of the first lines and the second lines; and a plug connected to a first portion of each of the first lines, wherein the plug comprises a conductive layer and a material layer having a resistance value higher than that of the conductive layer.. ... Sk Hynix Inc

04/20/17 / #20170110511

Semiconductor integrated circuit device capable of reducing a leakage current

A semiconductor integrated circuit device may include a semiconductor substrate, a source pattern, a drain pattern, a nano wire pattern and a gate. The source pattern may be formed on an upper surface of the semiconductor substrate. ... Sk Hynix Inc

04/20/17 / #20170110473

Semiconductor device and method for manufacturing the same

A semiconductor device includes a first stack including a plurality of alternating layers of first interlayer insulating layers and first conductive patterns; a second stack including a plurality of alternating layers of second conductive patterns and second interlayer insulating layers, the second stack being positioned above the first stack; a plurality of pillar-structures each pillar structure passing through the first and second stacks; and a ring pattern layer disposed between the first and second stacks, the ring pattern layer comprising a plurality of ring patterns, each ring pattern surrounding each pillar-structure.. . ... Sk Hynix Inc

04/20/17 / #20170110468

Semiconductor device and method for manufacturing the same

The semiconductor device may include a first sub-pipe gate having a pipe hole formed therein; a second sub-pipe gate disposed on the first sub-pipe gate and passed-through by vertical holes being coupled to the pipe hole, wherein a material of the second sub-pipe gate has a lower oxidation rate than that of a material of the first sub-pipe gate; a first oxidized layer formed within a portion of the first sub-pipe gate to conform to a contour of the pipe hole; and a second oxidized layer formed within a portion of the second sub-pipe gate to conform to a contour of the vertical holes and the contour of the pipe hole.. . ... Sk Hynix Inc

04/20/17 / #20170110457

Transistor, method for fabricating the same, and electronic device including the same

A semiconductor device includes a stressed substrate stressed by a first stress, a first stressed channel formed in the substrate and having the first stress, and a first strained gate electrode strained by a first strain generating element. A first strained gate electrode is formed over the first stressed channel, the first strained gate electrode including a first lattice-mismatched layer to induce a second stress to the first stressed channel.. ... Sk Hynix Inc

04/20/17 / #20170110365

Nonvolatile memory device and method for fabricating the same

A nonvolatile memory device may include a stair-shaped structure including a first interlayer dielectric layer and a memory cell repeatedly stacked. The nonvolatile memory device may include an etch stop layer and a second interlayer dielectric layer formed over the stair-shaped structure. ... Sk Hynix Inc

04/20/17 / #20170110207

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application, and accessing data storage memory through the first and second memory devices.. . ... Sk Hynix Inc

04/20/17 / #20170110200

Memory device and operating method thereof

A memory device includes a plurality of memory cells for storing data; a plurality of memory cells for storing data; a non-volatile memory unit; a test control unit suitable for detecting weak memory cells among the plurality of memory cells; a program control unit suitable for controlling addresses of the detected weak memory cells to be programmed in the non-volatile memory unit; and a refresh control unit suitable for refreshing the addresses stored in the non-volatile memory unit more frequently than other memory cells.. . ... Sk Hynix Inc

04/20/17 / #20170110176

Memory device and system including the same

A memory device may include: an active controller configured to output a row active signal in response to a refresh control signal and a row enable signal when an active signal is activated; a refresh controller configured to generate and store a flag bit for controlling a refresh operation in response to a refresh signal, a precharge signal, and a precharge stop signal, and output the row enable signal corresponding to the stored flag bit to the active controller; and a cell array circuit configured to perform a refresh operation in memory cell array areas in response to the row active signal.. . ... Sk Hynix Inc

04/20/17 / #20170110168

Clock control device

A clock control device is disclosed, which relates to a technology for changing a rising or falling edge trigger. The clock control device includes: a flip-flop configured to latch data in response to a delay clock signal; and a clock controller configured to output the delay clock signal by delaying a clock signal, and control the data to be triggered at a falling edge of the clock signal when the clock signal is input at a time earlier than the data.. ... Sk Hynix Inc

04/20/17 / #20170110166

Data sensing circuit and semiconductor apparatus using the same

A data sensing circuit may include a pair of first signal lines, and a pair of second signal lines precharged with a first power supply voltage. The data sensing circuit may also include a line level control block configured for applying a second power supply voltage to any one signal line of the pair of second signal lines in response to a read command.. ... Sk Hynix Inc

04/20/17 / #20170110162

Reception circuit and electronic apparatus including the same

Provided is a reception circuit provided in a chip, the reception circuit including a controller that generates a reception control signal which is activated for a preset time on a basis of a first control signal individually provided to a plurality of chips, a buffer that receives a second control signal commonly provided to the plurality of chips, and a delay circuit that receives the second control signal from the buffer in response to the reception control signal and provides the second control signal to other elements in the chip.. . ... Sk Hynix Inc

04/20/17 / #20170110161

Semiconductor device having redistribution lines

A semiconductor device includes, a semiconductor chip having a first surface over which bonding pads are positioned, a second surface which faces away from the first surface, and a plurality of signal lines formed over the first surface, extending in a first direction; a plurality of redistribution lines formed over the first surface, having one set of ends electrically coupled to the bonding pads of the semiconductor chip, and extending in a direction oblique to the first direction; and a plurality of redistribution pads disposed over the first surface, and electrically coupled with an other set of ends of the redistribution lines which face away from the one set of ends.. . ... Sk Hynix Inc

04/20/17 / #20170110160

Semiconductor chip module and semiconductor package including the same

A semiconductor chip module includes a chip unit including first and second semiconductor chips formed over a single body to be adjacent in a first direction with a scribe line region interposed therebetween, and having a first surface over which bonding pads of the first and second semiconductor chips are positioned; redistribution lines formed over the first surface, having one set of ends which are respectively electrically coupled to the bonding pads, and extending in a direction oblique to the first direction toward the scribe line region; and redistribution pads disposed over the first surface, and electrically coupled with another set of ends of the redistribution lines. The redistribution pads includes shared redistribution pads electrically coupled in common to the redistribution lines electrically coupled to the bonding pads of the first semiconductor chip and the redistribution lines electrically coupled to the bonding pads of the second semiconductor chip; and individual redistribution pads individually electrically coupled to the redistribution lines which are not electrically coupled with the shared redistribution pads.. ... Sk Hynix Inc

04/20/17 / #20170109624

Synapse and neuromorphic device including the same

A synapse and a neuromorphic device including the same are provided. The synapse includes: a first electrode; a second electrode spaced apart from the first electrode; an oxygen-containing layer disposed between the first electrode and the second electrode; a reactive metal layer disposed between the oxygen-containing layer and the second electrode and capable of reacting with oxygen ions from the oxygen-containing layer; and an oxygen diffusion-retarding layer provided between the oxygen-containing layer and the reactive metal layer, the oxygen diffusion-retarding layer hindering movement of oxygen ions from the oxygen-containing layer to the reactive metal layer.. ... Sk Hynix Inc

04/20/17 / #20170109308

Memory device

A memory device includes: a plurality of bank groups each comprising one or more banks; a first bus coupled to the plurality of bank groups; a second bus coupled to the plurality of bank groups; a toggle signal generation unit suitable for generating a first signal which toggles in response to a column command signal and a second signal having the opposite logic value of the first signal; a column command transmission unit suitable for transmitting a read command signal or write command signal to the first bus when the first signal is activated, and transmitting the read command signal or write command signal to the second bus when the second signal is activated; and a column address transmission unit suitable for transmitting one or more column address signals corresponding to the read command signal or write command signal to a bus to which the read command signal or write command signal is transmitted, between the first and second buses.. . ... Sk Hynix Inc

04/20/17 / #20170109292

Memory system and operating method of the memory system

In a memory system including a memory device including a plurality of storage regions, and a controller suitable for selecting storage regions indicated by logical addresses from among the plurality of storage regions using a mapping table storing a plurality of pieces of mapping information for mapping a plurality of logical addresses to a plurality of physical addresses corresponding to the plurality of storage regions. The controller may narrow a search range in which a second requested logical address of n logical addresses (n is an integer greater than 2) is to be searched for in the mapping table based on a position in which the mapping information corresponding to a first requested logical address of the n logical addresses has been stored in the mapping table when the n logical addresses are sequentially searched for in the mapping table.. ... Sk Hynix Inc

04/20/17 / #20170109277

Memory system

A memory system includes: a memory unit including first and second memories of different types; a processor separated from the memory unit, and suitable for executing an operating system (os) and an application to access the data storage memory through the memory unit; and a combined memory controller suitable for transferring data between the memory unit and the processor.. . ... Sk Hynix Inc

04/20/17 / #20170109276

Memory system and operation method thereof

A memory system includes a memory device comprising a plurality of blocks, and a controller suitable for erasing at least one victim block selected from among the plurality of blocks in a first garbage collection operation, and preparing a second garbage collection operation for one or more other blocks, except for the victim block among the plurality of blocks during a period in which the victim block is erased.. . ... Sk Hynix Inc

04/20/17 / #20170109274

Memory system

A memory system includes: a first memory device including a plurality of first memories and a first memory controller suitable for controlling the plurality of first memories to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. . ... Sk Hynix Inc

04/20/17 / #20170109273

Memory system and operation method thereof

A memory system may include a nonvolatile memory device including a plurality of blocks each including a plurality of pages, and a controller that selects a mapping block from the plurality of blocks, stores address information corresponding to each of other blocks, except for the mapping block and a free block among the plurality of blocks, in each of the plurality of pages, searches for a block including no valid page among the other blocks, and invalidates a page of the mapping block storing the address information corresponding to the searched block.. . ... Sk Hynix Inc

04/20/17 / #20170109086

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. . ... Sk Hynix Inc

04/20/17 / #20170109077

Memory system

A memory system includes: a memory module including: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data and a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. . ... Sk Hynix Inc

04/20/17 / #20170109076

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access data storage memory through the first and second memory devices.. . ... Sk Hynix Inc

04/20/17 / #20170109075

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. . ... Sk Hynix Inc

04/20/17 / #20170109074

Memory system

A memory system includes: a system main memory including a first memory device and a second memory device, wherein each of the first and second memory devices maintains latency information thereof; a processor suitable for executing an operating system (os) and an application to access a data storage memory through the system main memory, wherein the system main memory is separated from the processor and the processor and the first and second memory devices are electrically coupled to one another through a common bus; and a memory controller suitable for transferring data between the system main memory and the processor.. . ... Sk Hynix Inc

04/20/17 / #20170109073

Memory system

A memory system includes: a plurality of first memory devices directly or indirectly coupled to one another, each first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a multi-processor including a plurality of processors, each processor executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. . ... Sk Hynix Inc

04/20/17 / #20170109072

Memory system

A memory system includes a system main memory including first and second memories, wherein the first memory includes a cached subset of the second memory and the second memory includes a cached subset of a data storage memory; a processor suitable for executing an operating system (os) and an application to access the data storage memory through the system main memory, wherein the system main memory is separated from the processor; a memory controller suitable for transferring data between the system main memory and the processor; and a write buffer suitable for buffering write data, based on which the second memory is updated.. . ... Sk Hynix Inc

04/20/17 / #20170109071

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. . ... Sk Hynix Inc

04/20/17 / #20170109070

Memory system

A memory system includes: a plurality of first memory devices directly or indirectly coupled to one another, each first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device commonly coupled to the plurality of the plurality of first memory devices, and including a second memory and a second memory controller suitable for controlling the second memory to store data; and a multi-processor including a plurality of processors, each processor executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. . ... Sk Hynix Inc

04/20/17 / #20170109069

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. . ... Sk Hynix Inc

04/20/17 / #20170109068

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. . ... Sk Hynix Inc

04/20/17 / #20170109067

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. . ... Sk Hynix Inc

04/20/17 / #20170109066

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. . ... Sk Hynix Inc

04/20/17 / #20170109065

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. . ... Sk Hynix Inc

04/20/17 / #20170109064

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. . ... Sk Hynix Inc

04/20/17 / #20170109063

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application, and accessing data storage memory through the first and second memory devices.. . ... Sk Hynix Inc

04/20/17 / #20170109062

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application, and accessing data storage memory through the first and second memory devices.. . ... Sk Hynix Inc

04/20/17 / #20170109061

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. . ... Sk Hynix Inc

04/20/17 / #20170109060

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. . ... Sk Hynix Inc

04/20/17 / #20170109047

Data storage device and operating method thereof

A data storage device includes a controller; and a nonvolatile memory device including a plurality of memory blocks, and suitable for erasing a memory block selected from among the plurality of memory blocks, wherein the controller is suitable for managing the memory block through an erase prohibition list so that at least one predetermined erase cycle is ensured for the memory block.. . ... Sk Hynix Inc

04/20/17 / #20170109043

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access data from a data storage memory through the first and second memory devices.. . ... Sk Hynix Inc

04/13/17 / #20170104499

Efficient ldpc encoder for irregular code

A first memory location stores circulant contents of portions a, c, e, and b of a parity check matrix h. A second memory location stores circulant column counts of the portions a, c, e, and b. ... Sk Hynix Inc

04/13/17 / #20170104476

Semiconductor device

A semiconductor device includes a skew sensing block configured to generate a first output signal according to a driving force for driving a first internal node and generate a second output signal according to a driving force for driving a second internal node, in response to an input signal; and a skew control signal generation block configured to generate skew control signals for controlling a skew of an internal circuit, by the first and second output signals.. . ... Sk Hynix Inc

04/13/17 / #20170104154

Variable resistive memory device having a phase change structure and method of manufacturing the same

A variable resistive memory device may include a phase change region, a phase change layer, a gap-filling layer and an upper electrode. The phase change region may have a sidewall and a bottom surface. ... Sk Hynix Inc

04/13/17 / #20170104097

Lateral high voltage integrated devices having trencn insulation field plates and metal field plates

A high voltage integrated device includes a source region and a drain region disposed in a semiconductor layer and spaced apart from each other, a drift region disposed in the semiconductor layer and surrounding the drain region, a channel region defined in the semiconductor layer and between the source region and the drift region, a trench insulation field plate disposed in the drift region, a recessed region provided in the trench isolation field plate, a metal field plate disposed over the trench insulation field plate, and filling the recessed region, a gate insulation layer provided over the channel region and extending over the drift region and over the trench insulation field plate, and a gate electrode disposed over the gate insulation layer.. . ... Sk Hynix Inc

04/13/17 / #20170103990

Method of manufacturing semiconductor device

In an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include forming a pattern group on a substrate, the substrate being divided into first and second regions, each pattern including a silicon layer, forming an insulating pattern on the substrate, the insulating pattern partially exposing the silicon layer on the first region and blocking the silicon layer on the second region, converting the exposed silicon layer on the first region to a silicide layer while the blocked silicon layer on the second region is protected from the conversion, and performing a subsequent process using, as an overlay vernier, at least a portion of the pattern group formed on the second region.. . ... Sk Hynix Inc

04/13/17 / #20170103930

Stacked semiconductor apparatus being electrically connected through through-via and monitoring method

A semiconductor apparatus includes a plurality of stacked chips. Each of the plurality of stacked chips includes a delay chain. ... Sk Hynix Inc

04/13/17 / #20170103819

Semiconductor devices

A semiconductor device may be provided. The semiconductor device may include a test data interface, a first data interface, and a second data interface. ... Sk Hynix Inc

04/13/17 / #20170103814

Semiconductor memory device

Provided herein is a semiconductor memory device including a memory cell array including a drain select transistor and a plurality of memory cells, a voltage generator configured to apply a program voltage, first and second pass voltages, and a drain control voltage to the memory cell array, a control logic configured to control the voltage generator so that during a program operation, after the program voltage is applied to a selected one of the plurality of memory cells, the program voltage applied to the selected memory cell is discharged while the first pass voltage or the second pass voltage is applied to memory cells adjacent to the selected memory cell.. . ... Sk Hynix Inc

04/13/17 / #20170103812

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a plurality of memory blocks. The semiconductor memory device also includes a block decoder configured to output a block select signal for selecting at least one memory block of the plurality of memory blocks to at least one block word line of a plurality of word lines, and a connecting circuit including a plurality of pass transistors configured to electrically connect global lines to local lines of a plurality of memory cells included in the plurality of memory blocks in response to the block select signal. ... Sk Hynix Inc

04/13/17 / #20170103811

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a memory cell array including a plurality of memory cells, connecting circuits including pass transistors coupled between global word lines and the plurality of memory cells, an address decoder coupled to block word lines coupled to gates of the pass transistors and the global word lines, and a control logic controlling the address decoder and applying a voltage pulse to the global word lines and the block word lines according to an operation state of the semiconductor memory device.. . ... Sk Hynix Inc

04/13/17 / #20170103787

Semiconductor devices and semiconductor systems including the same

A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a power supply voltage and first data. ... Sk Hynix Inc

04/13/17 / #20170103786

Multi-chip package

A multi-chip package (mcp) includes semiconductor chips integrated therein. Each semiconductor chip includes: pad groups which extend in a first: direction and are arranged in a second direction, and each of which includes a first metal line and a second metal line that are stacked in a third direction with an interlayer dielectric layer interposed therebetween; receivers which one-to-one correspond to the respective pad groups, and each of which includes a first input terminal coupled with the first metal line of a corresponding pad group, and an output terminal coupled with the second metal line of the corresponding pad group; and selectors, each of which selects one of a feedback signal transferred from the output terminal of a corresponding receiver and a reference voltage, and provides the selected one to a second input terminal of the corresponding receiver, in response to a chip select signal.. ... Sk Hynix Inc

04/13/17 / #20170102619

Composition for coating photoresist pattern and method for forming fine pattern using the same

Disclosed are a composition for coating a photoresist pattern and a method for forming a fine pattern using the same. The composition for coating a photoresist pattern includes a polymer compound containing a hydroxyl group and an ammonium base, and a solvent the method for forming a fine pattern includes coating the composition on a previously formed photoresist pattern to thereby effectively reduce the size of a photoresist contact hole or space, and can be used in all semiconductor processes in which a fine pattern is required to be formed.. ... Sk Hynix Inc

04/06/17 / #20170099054

Electronic device and electronic system including the same

An electronic device includes a control logic portion suitable for generating a hold control signal based on a count enable signal, and a counting portion suitable for performing a counting operation while a latch operation stops during a counting section and performing the latch operation while the counting operation stops during a holding section based on the hold control signal and a counting clock signal.. . ... Sk Hynix Inc

04/06/17 / #20170099051

Data transmission circuit

A data transmission circuit may include a first driving block configured to drive an output terminal for a first time in response to a data driving signal and a level of the output terminal, and a second driving block configured to drive the output terminal for a second time after the first time, in response to the data driving signal.. . ... Sk Hynix Inc

04/06/17 / #20170099045

Semiconductor device and method for driving the same

A semiconductor device includes: an initialization block suitable for initializing an internal voltage terminal based on a first voltage of a first voltage terminal; a feedback block suitable for generating a feedback voltage based on an internal voltage of the internal voltage terminal; a comparison block suitable for comparing the feedback voltage with a reference voltage to generate a comparison signal; a driving block suitable for driving the internal voltage terminal with a second voltage of a second voltage terminal in response to the comparison signal; and a leakage current prevention block suitable for selectively blocking a current path passing through the internal voltage terminal, the driving block and the second voltage terminal in response to a power-up signal corresponding to the first voltage.. . ... Sk Hynix Inc

04/06/17 / #20170098681

Image sensor and method for fabricating the same

Provided is an image sensor having improved characteristics. An image sensor in accordance with an embodiment of the present invention may include first and second photoelectric conversion elements formed in a substrate, wherein the first photoelectric conversion element has a first impurity region; a device isolation trench formed in the substrate and between the first and the second photoelectric conversion elements, wherein a sidewall of the device isolation trench is in contact with the first impurity region; and an epitaxial layer filling the device isolation trench, and having different conductivity from the first impurity region.. ... Sk Hynix Inc

04/06/17 / #20170098657

Method of manufacturing semiconductor device

The present disclosure provides a method of manufacturing a three dimensional memory device to suppress warpage of conductive patterns. The method may include providing a multilayered structure in which different material layers are alternately stacked over a substrate, etching partially the material layers to form a multi-step structure, each step being formed of at least one pair of the material layers, forming vertical support layers, each support layer being disposed on a top face of each step, removing partially the material layers to form recesses, filling the recesses with a conductive material to form gate lines, the gate line defining an upper portion of the step, and forming vertical contact plugs respectively on the upper portion of the step.. ... Sk Hynix Inc

04/06/17 / #20170098477

Semiconductor devices

A first data input circuit receives test data from a first pad to generate first input control data for generating cell input data stored in a memory cell array during a first operation period. A first data output circuit receives first output control data generated from cell output data outputted from the memory cell array to output the first output control data to an internal node coupled to a second pad during a second operation period.. ... Sk Hynix Inc

04/06/17 / #20170098476

Compression circuit, test apparatus, and semiconductor memory apparatus and semiconductor apparatus having the same

A semiconductor memory apparatus includes a first data compressor configured to generate at least one compression signal based on test data provided in a memory circuit, and a second data compressor configured to generate grouping data by grouping the at least one compression signal in preset bit units and generate an output signal having a voltage level corresponding to a logic level of the grouping data.. . ... Sk Hynix Inc

04/06/17 / #20170097868

Data storage device and operating method thereof

A data storage device includes a controller; and a nonvolatile memory device comprising a memory region including a plurality of memory cells, the nonvolatile memory device being suitable for acquiring first data by applying a first read voltage to the plurality of memory cells and acquiring second data by applying a plurality of second read voltages to the plurality of memory cells, according to control of the controller, wherein the controller is suitable for performing an error correction operation for the first data, based on the second data, and wherein the plurality of second read voltages have nonlinear variation rates with respect to the first read voltage.. . ... Sk Hynix Inc

04/06/17 / #20170097794

Data processing system

A data processing system may include at least two memory systems including first and second memory systems to which a logical address and a command are applied in parallel from a host. The first memory system may store a plurality of first physical addresses for physically indicating a plurality of first pages included in a first non-volatile memory device as a first table, and determines whether to perform a preset operation corresponding to the applied command according to whether a physical address generated by performing a preset operation on the applied logical address exists in the first table, and the second memory system may store a plurality of second physical addresses for physically indicating a plurality of second pages included in a second non-volatile memory device as a second table, and determines whether to perform the preset operation corresponding to the applied command according to whether a physical address generated by performing the preset operation on the applied logical address exists in the second table.. ... Sk Hynix Inc

04/06/17 / #20170097563

Methods of cleaning surfaces of photomasks

A surface cleaning method includes forming a mask layer on a substrate, performing a first surface treatment process for scanning a surface of the mask layer with a first laser beam to stabilize the mask layer, patterning the mask layer to form a mask pattern, and performing a second surface treatment process for scanning surfaces of the mask pattern and the substrate with a second laser beam to remove contaminants on the mask pattern or the substrate.. . ... Sk Hynix Inc

03/30/17 / #20170094208

Image sensing device

An image sensing device includes a pixel suitable for generating a pixel signal and an amplification block suitable for amplifying the pixel signal based on a predetermined amplification gain to adjust a conversion gain of the pixel.. . ... Sk Hynix Inc

03/30/17 / #20170093602

Transmitting device for high speed communication, interface circuit and system including the same

A transmission device may include a main driver configured to drive an output node based on an input signal, and may generate an output signal with multiple levels. The transmission device may include a variable emphasis driver configured to drive the output node with various driving forces based on transition information of the input signal.. ... Sk Hynix Inc

03/30/17 / #20170093428

Techniques for adaptive ldpc decoding

Techniques are described for an adaptive low density parity check (ldpc) decoder. The techniques include receiving a first set of values corresponding to a first low density parity check codeword and noise, performing a first plurality of iterations of an iterative decoding algorithm using a first set of decoding parameters to decode the received first set of values, comparing a metric with a first threshold, and upon determining that the metric is larger than the threshold: selecting a second set of decoding parameters for the iterative ldpc decoder and performing a second plurality of iterations of the iterative ldpc decoding algorithm using the second set of decoding parameters to decode the received first set of values and generate a first set of decoded bits.. ... Sk Hynix Inc

03/30/17 / #20170092671

Image sensor

Provided is an image sensor having improved performance. An image sensor in accordance with an embodiment of the present invention including a pixel array in which a plurality of pixels are two-dimensionally arranged, wherein each of the plurality of pixels may include: a photoelectric conversion element formed in a substrate; a transfer gate overlapping with a portion of the photoelectric conversion element and formed on the substrate; and a color filter over the photoelectric conversion element, wherein the plurality of pixels include two adjacent pixels which have the same color filter, and wherein one of the two adjacent pixels comprises an incident light control pattern.. ... Sk Hynix Inc

03/30/17 / #20170092655

Semiconductor device

A semiconductor device may include first conductive patterns and first interlayer insulating layers. Each of the first conductive patterns may include a first pad pattern extending in a first direction and first line patterns extending from the first pad pattern in a second direction crossing the first direction, widths of the first line patterns increasing as a distance from the first pad pattern decreases. ... Sk Hynix Inc

03/30/17 / #20170092641

Semiconductor device and system including the same

A semiconductor device may be provided. The semiconductor device may include a first guard ring disposed in a first region, and a second guard ring disposed in a second region. ... Sk Hynix Inc

03/30/17 / #20170092372

Semiconductor device, operating method thereof, and data storage device including the same

A semiconductor device includes a memory block including a plurality of memory cells coupled with a plurality of corresponding word lines, and a peripheral circuit suitable for performing a first erase verify operation for the plurality of word lines, and a second erase verify operation for one or more weak word lines among the plurality of word lines based on a result of the first erase verify operation.. . ... Sk Hynix Inc

03/30/17 / #20170092365

Semiconductor memory device and operating method thereof

A semiconductor memory device may include a memory cell array, a peripheral circuit, a control logic, and a source line precharge path. The memory cell array may have a plurality of memory strings. ... Sk Hynix Inc

03/30/17 / #20170092364

Memory device and method of operating the same

A memory device with a plurality of memory block may include a plurality of memory cells constituting a memory blocks, and two or more select transistors coupled to the plurality of memory cells constituting the memory block and configured to select the memory block, the two or more select transistors having different threshold voltages from one another.. . ... Sk Hynix Inc

03/30/17 / #20170092363

Semiconductor memory device including three-dimensional array structure and memory system including the same

A semiconductor memory device may include first and second sub-cell strings. The first sub-cell string may be coupled to a common source line at an end of the first sub-cell string. ... Sk Hynix Inc

03/30/17 / #20170092339

Memory system and operating method thereof

There are provided a memory system and an operating method thereof. A memory system includes a memory device for storing data, and a controller for controlling the memory device by outputting control signals to the memory device. ... Sk Hynix Inc

03/30/17 / #20170092338

Semiconductor memory apparatus, and method for training reference voltage

A semiconductor memory apparatus may be configured to, in a data reference voltage training mode, set a reference pad reference voltage by training a first initial data reference voltage for a reference pad being any one of a plurality of input/output pads, and set a data reference voltage for each of remaining input/output pads by training a second initial data reference voltage being the reference pad reference voltage for each of the remaining input/output pads.. . ... Sk Hynix Inc

03/30/17 / #20170091039

Data storage device and operating method thereof

A method for operating a data storage device including a plurality of pages includes performing a read operation to a first page of the nonvolatile memory device according to a read voltage; adjusting the read voltage based on a number of error bits in the read-out data according to the read voltage; performing the read operation to the first page according to the adjusted read voltage; and performing a re-program operation to the first page based on a number of on cells as a result of the read operation according to the adjusted read voltage.. . ... Sk Hynix Inc

03/30/17 / #20170091029

Data processing device and operating method thereof

A data processing device includes a first decoder suitable for performing normal or fast decoding for a plurality of data chunks, wherein the first decoder performs the normal decoding for a first data chunk among the plurality of data chunks, and performs the normal decoding or the fast decoding for a second data chunk among the plurality of data chunks, based on a result of the normal decoding for the first data chunk.. . ... Sk Hynix Inc

03/23/17 / #20170085276

Vss ldpc decoder with improved throughput for hard decoding

Memory systems may include a memory storage, a pre-processing checksum unit suitable for, during a first decoding iteration, receiving hard read data including channel input (lch) sign values, and computing a checksum of the lch sign values as a checksum_pre value, and a low-density parity-check (ldpc) decoder including an lch memory and a checksum update unit, the ldpc decoder suitable for, during the first decoding iteration, storing the lch sign values in the lch memory of the ldpc decoder, receiving, with the checksum update unit, the checksum_pre value, and decoding a codeword in at least a second decoding iteration based at least in part on the checksum_pre value computed and received being a parity check on the hard read performed in the first decoding iteration.. . ... Sk Hynix Inc

03/23/17 / #20170085261

Initialization signal generation device and nonvolatile memory apparatus using the same

An initialization signal generation device may be provided. The initialization signal generation device may include a power supply circuit configured to provide one of an external voltage and an internal voltage in response to an initialization signal. ... Sk Hynix Inc

03/23/17 / #20170085260

Semiconductor device

A semiconductor device includes a boot-up start signal generation unit configured to generate a boot-up start signal which is enabled in synchronization with a time at which a preset delay period has passed from a time point at which an initialization signal is enabled after a power-up period is ended, and a boot-up period signal generation unit configured to generate a boot-up period signal which is enabled according to a set pulse generated in synchronization with a time point at which the boot-up start signal is enabled.. . ... Sk Hynix Inc

03/23/17 / #20170085171

Voltage regulator, memory system having the same and operating method thereof

Provided herein are a voltage regulator, a memory system having the same and an operation method thereof. The memory system includes a memory device configured to store data, a controller configured to control the memory device, and a voltage regulator configured to supply a pump-out voltage to the memory device or the controller so that the memory device or the controller is operated in the following manner: until a level of the pump-out voltage is increased to a second reference voltage lower than a first reference voltage, the pump-out voltage is output using a clock having a first frequency; when the pump-out voltage exceeds the second reference voltage and does not exceed the first reference voltage, the pump-out voltage is output using a clock having a second frequency lower than the first frequency; and when the pump-out voltage exceeds the first reference voltage, the pump-out voltage is output using the clock having the first frequency.. ... Sk Hynix Inc

03/23/17 / #20170084836

Method for fabricating electronic device with variable resistance material layer

A method for fabricating an electronic device including a semiconductor memory may include: forming a first interlayer dielectric layer over a substrate to have an opening exposing the substrate; forming a bottom electrode in a portion of the opening to have an exposed top surface; forming a variable resistance material layer along sidewalls of the remaining portion of the opening and the exposed top surface of the bottom electrode; forming a top electrode over the variable resistance material layer so as to fill the opening; etching the first interlayer dielectric layer to a predetermined depth to expose a part of the variable resistance material layer surrounding sidewalls of the top electrode; and removing the part of the variable resistance material layer to form a unit cell.. . ... Sk Hynix Inc

03/23/17 / #20170084748

Semiconductor device

A semiconductor device and a method for forming the same. The semiconductor device includes a tunnel insulating layer, a charge storage layer including a dopant, and a diffusion barrier layer including at least one of carbon, nitrogen, or oxygen interposed between the tunnel insulating layer and the charge storage layer.. ... Sk Hynix Inc

03/23/17 / #20170084740

3d semiconductor integrated circuit device and method of manufacturing the same

A 3d semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and an interlayer insulating layer is formed so that the active pillar is buried in the interlayer insulating layer. ... Sk Hynix Inc

03/23/17 / #20170084667

Electronic device and method for fabricating the same

Implementations of the disclosed technology provide an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a magnetic tunnel junction (mtj) structure including a free layer having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer sandwiched between the free layer and the pinned layer; and an under layer located under the mtj structure, wherein the under layer includes a first under layer including a silicon-based alloy, and a second under layer located on the first under layer and including a metal.. . ... Sk Hynix Inc

03/23/17 / #20170084580

Multi-chip package, system and test method thereof

A multi-chip package may include a plurality of semiconductor chips integrated in a single package and sharing one or more command pins. Each of the semiconductor chips may include: a command decoder suitable for decoding a command to generate a buffer enable signal, a mode enable signal, and a mode signal; a data input buffer suitable for buffering data to output internal data, in response to the buffer enable signal and a common test mode signal; a command controller suitable for receiving the mode enable signal to output a test mode enable signal by selectively blocking the mode enable signal based on the internal data and the common test mode signal; and a test controller suitable for generating the common test mode signal and a test mode signal, based on the test mode enable signal and the mode signal.. ... Sk Hynix Inc

03/23/17 / #20170084579

Semiconductor packages including flexible wing interconnection substrate

A semiconductor package includes a first semiconductor package, a second semiconductor package disposed on the first semiconductor package, and a flexible wing interconnection substrate disposed between the first and second semiconductor packages.. . ... Sk Hynix Inc

03/23/17 / #20170084575

Semiconductor package embedded with a plurality of chips

A semiconductor package may be provided. The semiconductor package may include a substrate. ... Sk Hynix Inc

03/23/17 / #20170084574

Semiconductor package device

A semiconductor package may include a first chip located over a substrate. The semiconductor package may include a second chip located over the substrate and adjacent to the first chip. ... Sk Hynix Inc

03/23/17 / #20170084353

Semiconductor device for performing repair operations

A semiconductor device includes a fuse block configured to store repair information corresponding to a fail address, and output fuse data in a boot-up operation; a dummy mat formed in a predetermined region of a cell array, and configured to store the fuse data in the boot-up operation; and a repair latch block configured to store the fuse data in the boot-up operation, wherein the fuse data stored in the dummy mat are updated to and stored in the repair latch block in a refresh operation.. . ... Sk Hynix Inc

03/23/17 / #20170084352

Repair device

A repair device may be provided. The repair device may include a selection controller configured to control an upper select signal and a lower select signal in correspondence to a fail address and an upper signal and a lower signal which represent a failed region of each mat. ... Sk Hynix Inc

03/23/17 / #20170084341

Storage device and operating method thereof

There are provided a storage device and an operating method thereof. A storage device includes a string including a plurality of memory cells, peripheral circuits for, in a read operation of a selected memory cell, applying a read voltage to a selected word line electrically coupled to the selected memory cell, and selectively applying a first pass voltage and a second pass voltage higher than the first pass voltage to unselected word lines electrically coupled to the other unselected memory cells according to a position of the selected word line, and a controller for controlling the peripheral circuits.. ... Sk Hynix Inc

03/23/17 / #20170084340

Storage device and operating method thereof

There are provided a storage device and an operating method thereof. A storage device includes a main block including a plurality of sub-blocks, a peripheral circuit for generating operation voltages used in a read operation of a selected sub-block among the sub-blocks and performing the read operation of the selected sub-block by using the operation voltages, and a control logic for, when an erased sub-block among the sub-blocks is included in the read operation, controlling the peripheral circuit to perform the read operation by lowering levels of some of the operation voltages.. ... Sk Hynix Inc

03/23/17 / #20170084339

High voltage switch circuit and semiconductor memory device including the same

There are provided a high voltage switch circuit and a semiconductor memory device including the same. A high voltage switch circuit may include a switching circuit including a first depletion transistor and a first high voltage transistor, which are coupled in series between an input terminal and an output terminal, and a control signal generator for applying, to the first depletion transistor, a control signal having the same potential level as an input voltage applied to the input terminal, in response to a first enable signal and a second enable signal.. ... Sk Hynix Inc

03/23/17 / #20170084325

Semiconductor memory device

A method of controlling a magnetoresistive random access memory includes receiving first signals associated with an active state through command/address pins; then receiving second signals associated with column and row addresses for a read operation, through the command/address pins, and in response reading data from a memory cell according to the row address; receiving third signals associated with column and row addresses for a write operation through the command/address pins, while reading the data; outputting the read data to data input/output pins, according to the column address for the read operation, after a lapse of a read latency; inputting data through the data input/output pins, in response to the third signals, according to the column address for the write operation, after a lapse of a write latency; and writing the data inputted from the data input/output pins to a memory cell according to the row address for the write operation.. . ... Sk Hynix Inc

03/23/17 / #20170084321

Semiconductor device and semiconductor system

A semiconductor system may include a command processor configured to decode a command to generate an active pulse and a delayed active pulse, and a bank active signal generation circuit configured to generate a bank active signal for performing an active operation for a bank accessed by an address. The bank active signal may be disabled in synchronization with the active pulse and is enabled in synchronization with the delayed active pulse.. ... Sk Hynix Inc

03/23/17 / #20170084320

Semiconductor devices and semiconductor systems including the same

A semiconductor device may include a buffer control signal generation circuit, an input control signal generation circuit and an internal data generation circuit. The buffer control signal generation circuit may be configured to generate a buffer control signal. ... Sk Hynix Inc

03/23/17 / #20170084319

Bit line equalizer

A bit line equalizer includes a first line-shaped gate extended in a first direction, a second line-shaped gate spaced apart from the first line-shaped gate by a predetermined distance and extending parallel to the first gate, a third gate configured to interconnect the first gate and the second gate, a first contact node located at one side of the first gate, a second contact node located at one side of the second gate, a third contact node located between the first gate and the second gate and located at one side of the third gate, and a fourth contact node located between the first gate and the second gate and located at the other side of the third gate.. . ... Sk Hynix Inc

03/23/17 / #20170084318

Semiconductor devices and semiconductor systems including the same

A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs command/address signals and a plurality of data. ... Sk Hynix Inc

03/23/17 / #20170084315

Memory device with shortened pre-charging time for bit-line

The present disclosure may provide a memory device including a page buffer and bit-lines coupled thereto with a less load of the bit-lines. In one aspect of the present disclosure, there is provided a memory device comprising: bit-lines, each bit-line having opposite first and second ends; plugs coupled respectively to the bit-lines, each plug disposed between and excluding the first and second ends; and a page buffer coupled to the plugs.. ... Sk Hynix Inc

03/23/17 / #20170084311

Semiconductor memory and semiconductor system using the same

A semiconductor memory includes a plurality of path circuits for transmitting data inputted from an exterior source or device to a chip. The semiconductor memory is configured to generate a plurality of pre-error detection signals by detecting whether data transmitted between the plurality of path circuits have errors, and selectively output the plurality of pre-error detection signals.. ... Sk Hynix Inc

03/23/17 / #20170083398

Repair circuit, semiconductor apparatus and semiconductor system using the same

A repair circuit may be provided. The repair circuit may include a latch array including a plurality of latch sets. ... Sk Hynix Inc

03/23/17 / #20170083264

Semiconductor system and operating method thereof

A semiconductor system may include: a command queue suitable for storing a plurality of requests provided from a host according to rank and bank information of the requests; one or more determination units suitable for determining requests having a same row address in response to row address information of the requests stored in the command queue; an arbitration unit suitable for scheduling the plurality of requests according to internal priorities of the requests; a monitoring unit suitable for providing the rank information and row hit information of the plurality of requests outputted according to the scheduling result of the arbitration unit, to the arbitration unit; a command generation unit suitable for generating a plurality of commands corresponding to and in response to the plurality of requests outputted according to the scheduling result of the arbitration unit; and a semiconductor memory device suitable for performing an internal operation in response to the command, wherein the arbitration unit reschedules the plurality of requests in response to a monitoring result of the monitoring unit and output results of the plurality of determination units, such that all requests inputted during a preset period are processed.. . ... Sk Hynix Inc

03/16/17 / #20170077957

Error correction device and error correction method

An error correction circuit may include a single error correction circuit configured to read unit write data indicated by a unit designation signal from a memory cell array as read data, correct a single bit error, and provide corrected data. The error correction circuit may include a comparison unit configured to compare the corrected data with the unit write data and provide a comparison result. ... Sk Hynix Inc

03/16/17 / #20170077181

Electronic device

An electronic device includes a transistor. The transistor includes a body including a metal oxide; a gate electrode; and a gate insulating layer interposed between the body and the gate electrode, wherein the transistor is turned on or turned off by movement of oxygen vacancies in the body according to voltages applied to the gate electrode and the body.. ... Sk Hynix Inc

03/16/17 / #20170076803

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation or erase operation of the memory cell array; and a control logic controlling the peripheral circuit. The control logic controls the peripheral circuit such that a first program allowable voltage applied to bit lines of the memory cell array during a first program operation of the program operation and a second program allowable voltage applied during a second program operation of the program operation are different from each other.. ... Sk Hynix Inc

03/16/17 / #20170076776

Semiconductor devices and semiconductor systems

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output command/address signals and receives temperature codes. ... Sk Hynix Inc

03/16/17 / #20170076767

Semiconductor devices having initialization circuits and semiconductor systems including the same

A semiconductor device may include a boot-up operation circuit configured for executing a boot-up operation during a boot-up operation period after a power supply voltage signal reaches a predetermined level. The boot-up operation circuit may be configured for generating a boot-up period signal. ... Sk Hynix Inc

03/16/17 / #20170076762

Memory device and electronic apparatus including the same

A memory device includes a plurality of channels that respectively include memory cell arrays and local input/output lines electrically coupled to the memory cell arrays and are independently operable, shared global input/output lines electrically coupled to the local input/output lines included in the plurality of channels and having a connection relation controlled through one or more path switch circuits arranged among the plurality of channels, and the path switch circuits that control the connection relation of the shared global input/output lines according to a path control signal.. . ... Sk Hynix Inc

03/16/17 / #20170075367

Circuits for setting reference voltages and semiconductor devices including the same

A circuit for setting a reference voltage is provided. The circuit includes a reference voltage information storage unit and a reference voltage input/output (i/o) control unit. ... Sk Hynix Inc

03/09/17 / #20170070663

Image sensor including phase difference detecting pixel

Provided is an image sensor including a pixel array including a plurality of unit pixel arrays. Each of the plurality of unit pixel arrays may include a plurality of unit pixel blocks arranged in a 4×4 matrix, each of the plurality of unit pixel blocks may include a phase difference detecting unit so that each of the plurality of unit pixel arrays may include phase difference detecting units, the phase difference detecting unit may include a first phase difference detecting pixel and a second phase difference detecting pixel, the first and the second phase difference detecting pixels may have first and second openings, respectively, the first and the second openings may be arranged in an eccentrically manner with respect to each other, and the phase difference detecting units arranged at each of the plurality of unit pixel blocks may be asymmetrical to each other on the basis of a boundary line between adjacent unit pixel blocks.. ... Sk Hynix Inc

03/09/17 / #20170070240

Memory system including error corrector and operating method thereof

A memory system includes a controller and a semiconductor memory device. The semiconductor memory device stores a data set having main data bits and parity bits and provide soft decision bit streams corresponding to the data set in response to control signals of the controller. ... Sk Hynix Inc

03/09/17 / #20170069837

Electronic device and method for fabricating the same

Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.. ... Sk Hynix Inc

03/09/17 / #20170069835

Method of manufacturing magnetoresistive memory device

According to one embodiment, a method of manufacturing a magnetoresistive memory device includes forming a base substrate including a conductive electrode exposed at a part of a surface, forming a stacked layer structure for a magnetoresistive element on the base substrate, processing the stacked layer structure by etching and thereby forming the magnetoresistive element on the electrode, and exposing the magnetoresistive element to an atmosphere of oxygen radicals.. . ... Sk Hynix Inc

03/09/17 / #20170069766

Mos varactors and semiconductor integrated devices including the same

A mos varactor includes a first n-type junction region and a second n-type junction region spaced apart from each other by a channel region, a gate insulation layer disposed on the channel region, a gate electrode disposed on the gate insulation layer, and an n-type well region including the channel region and surrounding the first and second n-type junction regions. The n-type well region exhibits a maximum impurity concentration in the channel region.. ... Sk Hynix Inc

03/09/17 / #20170069735

Transistor having dual work function buried gate electrode and method for fabricating the same

A transistor having a source region and a drain region which are separately formed in a substrate, a trench which is defined in the substrate between the source region and the drain region, and a gate electrode which is formed in the trench. The gate electrode includes a first electrode buried over a bottom of the trench; a second electrode formed over the first electrode; and a liner electrode having an interface part which is positioned between the first electrode and the second electrode and a side part, which is positioned on sidewalls of the second electrode and overlaps with the source region and the drain region.. ... Sk Hynix Inc

03/09/17 / #20170069731

Nonvolatile memory device and method for manufacturing the same

A nonvolatile memory device includes a pipe gate electrode layer formed over a substrate; a plurality of conductive layers stacked over the pipe gate electrode layer; source lines formed over an uppermost one of the conductive layers; first slits passing through the pipe gate electrode layer at positions overlapping with the source lines, and dividing the pipe gate electrode layer into a plurality of pipe gate electrodes, and second slits passing through the conductive layers at positions different from the first slits, and dividing the conductive layers into a plurality of memory blocks.. . ... Sk Hynix Inc

03/09/17 / #20170069726

Semiconductor structure and method for manufacturing the same

A method for manufacturing a semiconductor structure includes preparing a semiconductor substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the semiconductor substrate in the memory cell region; forming a bit line structure over the semiconductor substrate in the memory cell region; forming a dielectric layer in the peripheral circuit region and the memory cell region; forming a first opening in the dielectric layer in the memory cell region; filling a silicon filler in the first opening; forming a second opening in the dielectric layer in the peripheral circuit region; forming a sidewall spacer over a sidewall of the second opening; recessing the silicon filler to form a silicon plug, wherein the silicon plug fills a lower portion of the first opening; and forming a first metal silicide over a top surface of the silicon plug, and concurrently forming a second metal silicide in a lower portion of the second opening.. . ... Sk Hynix Inc

03/09/17 / #20170069642

Nonvolatile memory devices having single-layered gates

A nonvolatile memory device includes an active region extending in a first direction, a first single-layered gate intersecting the active region and extending in a second direction, a second single-layered gate intersecting the, active region and extending in the second direction, and a selection gate intersecting, the active region. The selection gate includes a first selection gate main line and a second selection gate main line that intersect the active region to be parallel with the first and second single-layered gates, a selection gate interconnection line that connects a first end of the first selection gate main line to a first end of the second selection gate main line and a selection gate extension that extends from a portion of the selection gate interconnection line to be disposed between first ends of the first and second single-layered gates,. ... Sk Hynix Inc

03/09/17 / #20170069398

Memory device

A memory device may include a plurality of memory cells; and an error detection unit suitable for latching first read data of one or more memory cells selected from the plurality of memory cells after refreshing the selected memory cells, in a first phase, and suitable for detecting errors of the selected memory cells before refreshing the selected memory cells, in a second phase.. . ... Sk Hynix Inc

03/09/17 / #20170069396

Semiconductor devices and semiconductor systems

A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a test mode enable signal and a switch control signal and receives test data. ... Sk Hynix Inc

03/09/17 / #20170069391

Storage device and operating method thereof

A storage device includes a main block including a plurality of sub-blocks, a peripheral circuit configured to perform a program operation, a read operation or an erase operation on the sub-blocks, and a control logic configured to control the peripheral circuit so that the erase operation of the sub-blocks is performed in a reverse order to an order of the program operation.. . ... Sk Hynix Inc

03/09/17 / #20170069386

Nonvolatile memory device and method of programming the same

A nonvolatile memory device includes a memory cell, and a switching unit. The memory cell includes a cell transistor having a floating gate and a coupling capacitor connected to the floating gate. ... Sk Hynix Inc

03/09/17 / #20170069384

Memory system and operating method thereof

There are provided a memory system having improved reliability and an operating method thereof. A memory system includes a semiconductor memory device including a memory cell array having a plurality of pages, and a controller for sequentially transmitting, to the semiconductor memory device, physical block addresses of pages to be programmed among the plurality of pages. ... Sk Hynix Inc

03/09/17 / #20170069374

Electronic devices having semiconductor magnetic memory units

An electronic device comprising a semiconductor memory unit that includes a resistance variable element configured to be changed in a resistance value according to a value of data stored therein; a first reference resistance element having a first resistance value; a second reference resistance element having a second resistance value larger than the first resistance value; and a comparison unit configured to receive a voltage corresponding to the resistance value of the resistance variable element through a first input terminal and a second input terminal thereof, a voltage corresponding to the first resistance value of the first reference resistance element through a third input terminal, and a voltage corresponding to the second resistance value of the second reference resistance element through a fourth input terminal, the comparison unit configured to output a result of comparing inputs to the first input terminal and the second input terminal and inputs to the third input terminal and fourth input terminal.. . ... Sk Hynix Inc

03/09/17 / #20170069370

Voltage generation circuit

A voltage generation circuit may include: a main code table suitable for outputting a main code based on an operation signal; a main voltage generator suitable for generating a main voltage corresponding to the main code; a trimming module suitable for comparing the main voltage with a target voltage to output a trimming signal; a trimming code table suitable for outputting a trimming code corresponding to the trimming signal; a code determination module suitable for outputting the main code and the trimming code when the trimming code is determined to be valid, and outputting the main code and a output code when the trimming code is determined to be invalid; and an operation voltage generator suitable for outputting an operation voltage based on the main code and a code selected from the trimming code and the substitute code.. . ... Sk Hynix Inc

03/09/17 / #20170069358

Memory device and method of operation thereof

An operation method of a memory device may include writing first data to a plurality of memory cells corresponding to a plurality of word lines, enabling a sense amplifier corresponding to the memory cells and setting second data in the sense amplifier, the second data having the opposite phase of the first data, and sequentially enabling the plurality of word lines for a predetermined time while enabling the sense amplifier.. . ... Sk Hynix Inc

03/09/17 / #20170069355

Semiconductor device

A semiconductor device may include an input/output block suitable for operating by using a first voltage in an input mode and a second voltage in an output mode, a common input/output line coupled to the input/output block, and a voltage level maintaining block suitable for driving the common input/output line to maintain a voltage level of a transmission signal by using the first voltage in the input mode and the second voltage in the output mode.. . ... Sk Hynix Inc

03/09/17 / #20170068604

Memory system having idle-memory devices and method of operating thereof

The memory system may include a memory device including a plurality of sub-memory devices coupled to a channel; and a controller suitable for controlling the memory device to store a first data into a selected sub-memory device and at least one idle sub-memory device among the sub-memory devices during a first program operation to a selected sub-memory device among the sub-memory devices with the first data with a first data; and to perform a second program operation to the selected sub-memory device with the first data stored in the idle sub-memory device when the first program operation to the selected sub-memory device fails.. . ... Sk Hynix Inc

03/09/17 / #20170068584

Memory device

A memory device may include a plurality of memory cells; a refresh counter suitable for generating a refresh address; an address storage circuit suitable for storing an additional refresh address; an error detection unit suitable for detecting an error of selected memory cells of the plurality of memory cells in response to a refresh command in a detection period; and a refresh control unit suitable for refreshing memory cells corresponding to the refresh address or the additional refresh address among the memory cells in response to the refresh command, and controlling the refreshing of the memory cells to be delayed in the detection period.. . ... Sk Hynix Inc

03/09/17 / #20170068583

Memory device

A memory device may include a plurality of memory cells; an error detection unit suitable for: latching data read a first time from at least one selected memory cell of the plurality of memory cells in a detection period, comparing data read a second time from the at least one selected memory cell with the latched data, and detecting an error of the at least one selected memory cell in the detection when the date read a second time from the at least one substantially the same with the latched data.. . ... Sk Hynix Inc

03/09/17 / #20170067954

Semiconductor device and semiconductor system

A semiconductor system includes a first semiconductor device suitable for outputting an external command and a termination control signal and being inputted with a data signal; and a second semiconductor device suitable for generating a termination enable signal in response to the external command and the termination control signal, generating a pull-up signal in response to the termination enable signal, and generating a pull-down signal in response to the termination enable signal and a test mode signal.. . ... Sk Hynix Inc

03/09/17 / #20170067942

Power-supply voltage sensing device

A power-supply voltage sensing device is disclosed, which relates to a technology for detecting a level of an external power-supply voltage during a test mode. The power-supply voltage sensing device includes a reference voltage trimming unit configured to trim a reference voltage in response to a code signal, a power-supply voltage detection unit configured to select one of a power-supply voltage and an external power-supply voltage in response to a test signal, compare the external power-supply voltage with the reference voltage, and output a detection signal according to the result of comparison, and a reference voltage control unit configured to output the code signal in response to the detection signal.. ... Sk Hynix Inc

03/02/17 / #20170064832

Flexible device including sliding interconnection structure

A flexible device includes a first conductive pattern, a second conductive pattern, and a dielectric layer. The first conductive pattern includes a first sliding contact portion and a first extension portion. ... Sk Hynix Inc

03/02/17 / #20170064815

3d emi suppression structure and electronic device having the same

A 3d electromagnetic interference (emi) suppression structure and an electronic device having the same, wherein a coplanar waveguide structure, an isolation layer, and a resonance layer may be installed. Furthermore, under the coplanar waveguide structure, the 3d emi structure may be installed to connect to a conductor part of the resonance layer through a conductive connection part of the isolation layer, thereby further improving the emi suppression effect and producing an excellent emi suppression effect.. ... Sk Hynix Inc

03/02/17 / #20170063582

Transmitting device for high speed communication, and interface circuit and system including the same

A transmitting device may include an encoder, a timing transmission controller, and a transmission driver. The encoder may generate transmission control signals according to control symbols. ... Sk Hynix Inc

03/02/17 / #20170063577

Equalization circuit, semiconductor apparatus and semiconductor system using the same

An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. ... Sk Hynix Inc

03/02/17 / #20170063384

Integrated circuit

An integrated circuit may include: a phase detector suitable for generating a delay control signal by comparing the phases of first and second clock signals to first and second target positions, a variable delay unit suitable for shifting the first and second clock signals to the first and second target positions, respectively, in response to the delay control signal, and a position controller suitable for varying the first and second target positions according to an operation mode.. . ... Sk Hynix Inc

03/02/17 / #20170063366

Semiconductor apparatus

A semiconductor apparatus suitable for operating by being applied with a plurality of external voltages from an exterior includes an initialization block configured to enable an initialization signal until all of the plurality of external voltages are higher than preset voltage levels after the plurality of external voltages are initially applied to the semiconductor apparatus; and an internal circuit configured to perform an initialization operation in response to the initialization signal.s. . ... Sk Hynix Inc

03/02/17 / #20170063311

Semiconductor apparatus and receiver thereof

A semiconductor apparatus includes a receiver configured to generate an output signal by amplifying an input signal received through a channel, and compensate distortion of the input signal based on a control signal preset according to a voltage level of the input signal, and an internal circuit configured to operate in response to the output signal.. . ... Sk Hynix Inc

03/02/17 / #20170062712

Electronic device and method for fabricating the same

Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.. ... Sk Hynix Inc

03/02/17 / #20170062463

Semiconductor device

A semiconductor device includes a semiconductor substrate divided into a first area and a second area, the semiconductor substrate including a first dopant of a first type, a first well formed to a first depth in the first area of the semiconductor substrate, the first well including a second dopant of a second type, wherein the second type is different from the first type, a second well including a third dopant of the first type, the second well being surrounded by the first well, and a pipe gate formed on the first area of the semiconductor substrate, the pipe gate being electrically connected to the second well.. . ... Sk Hynix Inc

03/02/17 / #20170062462

Semiconductor device and manufacturing method of the same

The present disclosure provides a semiconductor device comprising a block separator including a semiconductor film and a multi-layered insulating film, wherein the multi-layered insulating film surrounds the semiconductor film; memory block stacks divided from each other by the block separator, each memory block stack including interlayer insulating films and conductive patterns alternately stacked, wherein the conductive patterns are coupled to memory cells; and channel structures passing through the memory block stacks and electrically coupled to the memory cells.. . ... Sk Hynix Inc

03/02/17 / #20170062457

Semiconductor device and manufacturing method of the same

The present disclosure may provide a semiconductor device having a three-dimensional memory device with improved performance and reliability. The device may include a pipe gate having a pipe channel film embedded in the pipe gate. ... Sk Hynix Inc

03/02/17 / #20170062417

Semiconductor device

Disclosed is a semiconductor device including a plurality of conductive patterns formed on a semiconductor substrate while being spaced apart from one another at a preset interval and extending in a first direction, and a plurality of junction areas formed by doping impurities in the semiconductor substrate and provided between the conductive patterns. The plurality of junction areas includes transistor junction areas and dummy junction areas. ... Sk Hynix Inc

03/02/17 / #20170062402

Semiconductor device including drivers

A semiconductor device including drivers is disclosed, which can maximize driving ability of a plurality of drivers installed in a given region when the plurality of drivers is arranged in an array shape. The semiconductor device includes: a first active region; a second active region spaced apart from the first active region a predetermined distance in a first direction; a first gate finger group located in the first active region, and configured to include an odd number of gate fingers; and a second gate finger group located in the second active region, and configured to include an even number of gate fingers electrically coupled to the gate fingers of the first gate finger group.. ... Sk Hynix Inc

03/02/17 / #20170062384

Semiconductor package embedded with plurality of chips and method of manufacturing the same

A semiconductor package may include first semiconductor chips disposed in a rotationally symmetrical structure. First bonding pads are arranged over the bottom surfaces of the first semiconductor chips. ... Sk Hynix Inc

03/02/17 / #20170062326

Line structure for matching signal lines of semiconductor device

A line structure for matching of signal lines of a semiconductor device is disclosed. The line structure for matching of signal lines of a semiconductor device includes: a first signal line extended in a first direction; a second signal line extended in a second direction, and coupled to the first signal line; and a load-adjusting line spaced apart from the second signal line by a predetermined distance, and coupled to the first signal line.. ... Sk Hynix Inc

03/02/17 / #20170062057

Nonvolatile memory device, data storage device including the same, and operating method thereof

A data storage device includes a nonvolatile memory device including: memory cells of a first area grouped by page, and memory cells of a second area respectively corresponding to pages, and suitable for storing information representing whether each page of the first area is in an erased state; and a controller suitable for providing the nonvolatile memory device with a search command for searching an erased page and a search address of a page, wherein the nonvolatile memory device provides the controller with a state of at least one memory cell of the second area corresponding to the search address in response to the search command.. . ... Sk Hynix Inc

03/02/17 / #20170062050

Semiconductor device and semiconductor system

A semiconductor device may include a zq calibration circuit, a reference code setting circuit, a variable information generating circuit, and an internal circuit. The zq calibration circuit may perform a zq calibration operation in response to a zq calibration enable signal to generate a zq calibration code. ... Sk Hynix Inc

03/02/17 / #20170062029

Semiconductor apparatus, semiconductor system, and system relating to dual clock transmission

A semiconductor system may include a first semiconductor apparatus, and a second semiconductor apparatus. The first semiconductor apparatus may be configured to transmit a first system clock signal and a second system clock signal having a first frequency, and transmit a data strobe signal having a second frequency. ... Sk Hynix Inc

03/02/17 / #20170062022

Semiconductor device with hierarchical word line scheme

A semiconductor device includes: first and second memory cell regions disposed adjacent to each other in a first direction, and suitable for sharing a sub-word line driving signal, and a first sub-word line driving unit disposed in a crossing area that is disposed between the first and second memory cell regions in a diagonal direction. The first sub-word line driving unit includes a first sub-word line driver for driving the first memory cell regions, a second sub-word line driver for driving the second memory cell regions, and an interconnection for transmitting the sub-word line driving signal, which extends in the first direction.. ... Sk Hynix Inc

03/02/17 / #20170061278

Synapse and neuromorphic device including the same

A neuromorphic device may include: first to n-th row lines; first to m-th column lines; first to n-th first neuron circuits coupled to the first to n-th row lines, respectively; first to m-th second neuron circuits coupled to the first to m-th column lines, respectively; a plurality of synapses positioned at intersections of the first to n-th row lines and the first to m-th column lines, respectively, each of the plurality of synapses comprising a variable resistance element and a first transistor which are coupled in series, wherein n and m are natural numbers equal to or larger than two; and a t-th gate line to which gates of first transistors coupled to a t-th column line among the first to m-th column lines are coupled, wherein t is a natural number ranging from 1 to m.. . ... Sk Hynix Inc

03/02/17 / #20170060923

Data processing system

A data processing system may include: a memory system suitable for sorting a plurality of index data having a tree structure wherein each index data comprises information indicating a tree level thereof into a plurality of groups through a first and second sorting operations, the first sorting operation comprising sorting the index data based on their respective tree level information, the second sorting operation comprising sorting the index data based on the numbers of accesses to their respective index data, saving the groups into different storage regions; and a host suitable for managing a plurality of index data into said tree structure.. . ... Sk Hynix Inc

03/02/17 / #20170060803

Transmitting device for high speed communication, and interface circuit and system including the same

A transmitting device may include a logic circuit, a transmission controller, and a transmission driver. The encoder may generate transmission control signals based on control symbols. ... Sk Hynix Inc

03/02/17 / #20170060801

Semiconductor system and controlling method thereof

A semiconductor system may include a controller, a buffer chip electrically coupled to the controller, and a plurality of memory chips electrically coupled to the buffer chip, each memory chip including at least one chip data terminal. The buffer chip may be configured to perform logic operations on data output from at least one pair of chip data terminals among the plurality of memory chips, and to output the logic operation results to the controller or provide the logic operation results to other chip data terminals among the plurality of memory chips other than the at least one pair of chip data terminals which output the data.. ... Sk Hynix Inc

03/02/17 / #20170060768

Supporting invalidation commands for non-volatile memory

Techniques and systems are provided for tracking commands. Such methods and systems can include maintaining a meta page in a volatile memory to track commands. ... Sk Hynix Inc

03/02/17 / #20170060475

Semiconductor system and operating method thereof

A semiconductor system may include a plurality of memory devices corresponding to a plurality of channels, an address mapping unit suitable for converting addresses corresponding to provided external requests according to a selected address map among a plurality of address maps; a monitoring unit suitable for monitoring the external requests provided to each of the plurality of channels, and a control unit suitable for providing a control signal for controlling the address mapping unit to select an address map according to a result of the monitoring.. . ... Sk Hynix Inc

03/02/17 / #20170060470

Memory system and operating method thereof

A memory system may include: a memory device including: a plurality of pages each including a plurality of memory cells coupled to a plurality of word lines and suitable for storing read data and write data requested from a host; a plurality of memory blocks each including the pages; a plurality of planes each including the memory blocks; and a plurality of memory chips each including the planes; and a controller suitable for checking the write data corresponding to a command received from the host, programming the write data to pages of memory blocks included in planes of a first memory chip, and programming first data for the write data to pages of memory blocks included in planes of a second memory chip.. . ... Sk Hynix Inc

03/02/17 / #20170060452

Memory controller and memory system having the same

A memory controller includes a current information storage unit storing information about various current amounts of a memory system, a current management unit controlling an output time of an operation execution signal by calculating the information about the various current amounts, and a command controller outputting a command to operate a memory device in response to the operation execution signal.. . ... Sk Hynix Inc

03/02/17 / #20170060428

Delaying hot block garbage collection with adaptation

Memory systems may include a memory storage, and a controller suitable for measuring a write amplification (wa) value of a first, current window, comparing the wa value for the first window with a previous wa value for a previous window, and calculating and setting a value of a ratio threshold based on the comparison of the wa value for the current window threshold to the wa value of the previous window threshold.. . ... Sk Hynix Inc

03/02/17 / #20170060424

Memory system and operation method for the same

A memory system includes: a non-volatile memory device; and a controller for checking operation information of a requested isp operation, performing a first isp operation when the requested isp operation is not requested in the past, and performing a second isp operation when the requested isp operation is also requested in the past. During the first isp operation, the controller may read out two or more requested data from the non-volatile memory device in response to the operation information of the requested isp operation, generate resultant data by performing a predetermined operation to the read-out requested data, output the resultant data to a host, and store the resultant data in the non-volatile memory device. ... Sk Hynix Inc

03/02/17 / #20170060168

Semiconductor apparatus and semiconductor system

A semiconductor apparatus includes a controller configured to generate a plurality of control signals for selecting an operation mode of the semiconductor apparatus in response to a number of input chip enable pulses, and an output driving unit configured to be operated according to the operation mode of the semiconductor apparatus based on the plurality of control signals.. . ... Sk Hynix Inc

02/23/17 / #20170054442

Semiconductor device and semiconductor system

A semiconductor system may include a first semiconductor device configured to output a test stop signal and a calibration control signal. The semiconductor system may include a second semiconductor device configured to generate a first state code from an external resistor, a second state code from an internal resistor, and a third state code from a fuse array in response to the calibration control signal, and to select one of the first to third state codes as a selection code in response to the test stop signal and the calibration control signal.. ... Sk Hynix Inc

02/23/17 / #20170054436

Period signal generation circuit and semiconductor system including the same

A semiconductor system may include a first semiconductor device configured to output a command and receive data. The semiconductor system may include a second semiconductor device configured to generate a period signal, the period signals periodically toggled in response to the command, output the data in response to the period signal, and discharge the charges of an internal node if the period signal is not toggled during a predetermined section.. ... Sk Hynix Inc

02/23/17 / #20170053978

Semiconductor integrated circuit device with a capacitor having high capacitance

A semiconductor integrated circuit device may include a cell capacitor connected with any one of a first electrode and a second electrode of an access device. The cell capacitor may include a first cell cap array and a second cell cap array separated from the first cell cap array. ... Sk Hynix Inc

02/23/17 / #20170053932

Semiconductor memory device

Provided herein is a semiconductor memory device including: a memory cell array having a multilayer stacked structure; and a peripheral circuit configured to drive the memory cell array. The peripheral circuit includes a power decoupling capacitor circuit configured to provide decoupling capacitors to the memory cell array and the peripheral circuit. ... Sk Hynix Inc

02/23/17 / #20170053813

Methods of fabricating package substrates having embedded circuit patterns

There is provided a method of fabricating a package substrate. The method may include forming an isolation trench in a conductive layer, and forming a first dielectric layer on the conductive layer to provide an isolation wall portion filling the isolation trench. ... Sk Hynix Inc

02/23/17 / #20170053715

Semiconductor device and device for a semiconductor device

Various embodiments generally relate to a semiconductor device and a device for a semiconductor device, and more particularly, to a technology relating to a margin of a data retention time. The semiconductor device may include a repair detection unit configured to determine whether an inputted address is a repair address and output a repair detection signal. ... Sk Hynix Inc

02/23/17 / #20170053702

High voltage regulator

Disclosed herein is a regulator for a non-volatile memory is provided. The regulator comprises an operational amplifier for receiving a reference voltage and a feedback voltage to output a voltage amplifying the difference of the reference voltage and the feedback voltage, the feedback voltage being obtained by dividing an output voltage of the regulator; a first switching unit turning on in response to the amplified voltage; a second switching unit electrically connected between a first node and the first switching unit for protecting the first switching unit from the voltage of the first node; and a third switching unit providing the output voltage of the regulator to a second node in response to a voltage of the first node.. ... Sk Hynix Inc

02/23/17 / #20170053692

Semiconductor device with improved sense margin of sense amplifier

Semiconductor devices capable of a sensing margin of a semiconductor device are described. A semiconductor device may include a plurality of mats, a plurality of sensing circuits, a plurality of connecting circuits, and a plurality of mat dividing circuits. ... Sk Hynix Inc

02/23/17 / #20170053690

Semiconductor apparatus including multichip package

A semiconductor apparatus including a multichip package is disclosed. The semiconductor apparatus includes a slave chip having a slave region and a master region. ... Sk Hynix Inc

02/23/17 / #20170053684

Nonvolatile memory device for performing duty correction operation, memory system, and operating method thereof

A nonvolatile memory device suitable for sequentially performing a zq calibration operation and a read operation in response to a zq calibration enable signal and a read enable signal. The nonvolatile memory device includes a duty ratio control block suitable for receiving the read enable signal, performing a duty correction operation and setting a duty ratio, in a zq calibration operation period, and receiving the read enable signal and outputting a duty-corrected clock based on the set duty ratio, in a read operation period; a clock generation block suitable for generating an internal clock signal in response to the duty-corrected clock; and a data output block suitable for outputting data outputted from an internal memory cell region, in synchronization with the internal clock signal.. ... Sk Hynix Inc

02/23/17 / #20170053681

Semiconductor memory device with input/output line

Various embodiments relate to a semiconductor device. The semiconductor device may include a plurality of mats configured to input and output the data of memory cells through a plurality of mat input/output lines. ... Sk Hynix Inc

02/23/17 / #20170052840

Memory device and operating method thereof

A memory device may include: a plurality of memory cells; at least one address storage unit; a fail detection unit suitable for comparing first and second read data that are read from at least one memory cell selected among the plurality of memory cells to detect a fail, and storing an address of the selected memory cell in the address storage unit when the fail is detected; and a refresh control unit suitable for refreshing the memory cell corresponding to the address stored in the address storage unit at a higher frequency than the other memory cells.. . ... Sk Hynix Inc

02/23/17 / #20170052839

Memory system

A memory system may include a memory module including a plurality of memory devices suitable for storing a data word containing multi-bit data, and a memory controller suitable for controlling a write operation and a read operation of the memory module and distributing and mapping the data word to the plurality of memory devices, wherein as a memory device has a higher error occurrence count among the memory devices, the controller maps higher-significant bits of the multi-bit data to the memory device.. . ... Sk Hynix Inc

02/23/17 / #20170052577

Memory system and operation method thereof

A memory system may include: a memory device that operates using a first voltage received from a host and suitable for storing a value of operation information, and waking up from a sleep state in response to a request of the host; and a controller that operates using a second voltage received from the host, and suitable for selectively resetting the memory device according to a result obtained by checking a value of operation information of the memory device, when waking up the memory device in a sleep state according to a request of the host.. . ... Sk Hynix Inc

02/16/17 / #20170047421

Semiconductor device having dual work function gate structure, method for fabricating the same, transistor circuit having the same, memory cell having the same, and electronic device having the same

A semiconductor device including a substrate in which a trench is formed, a first impurity region and a second impurity region formed in the substrate separated from each other by the trench, a gate electrode formed to fill a lower part of the trench, and a capping layer formed over the gate electrode to fill an upper part of the trench. The gate electrode includes a first work function liner formed over a bottom surface and sidewalls of the lower part of the trench without overlapping with the first impurity region and the second impurity region, and including an aluminum-containing metal nitride; and a second work function liner formed over the sidewalls of the lower part of the trench over the first work function liner, overlapping with the first impurity region and the second impurity region, and including a silicon-containing non-metal material.. ... Sk Hynix Inc

02/16/17 / #20170047293

Semiconductor packages having emi shielding parts and methods of fabricating the same

A semiconductor package may include a semiconductor device mounted on a package substrate, a conductive roof located over the semiconductor device, a plurality of conductive walls disposed on the package substrate and arrayed in a closed loop line surrounding the semiconductor device. Conductive pillars may be disposed in regions between the conductive walls on the package substrate and bonded to the conductive roof. ... Sk Hynix Inc

02/16/17 / #20170047109

Semiconductor memory device and semiconductor memory system including the same

A semiconductor memory device includes: a memory cell array including a plurality of word lines; a word line driving unit suitable for activating a first word line among the plurality of word lines corresponding to an input address signal; an activation time detection unit suitable for enabling a detection signal by detecting an activation time of the first word line; an address latch unit suitable for latching an address information for a second word line corresponding to the first word line in response to the detection signal; and an address output unit suitable for providing the word line driving unit with the latched address information for the second word line during a refresh operation.. . ... Sk Hynix Inc

02/16/17 / #20170045900

Internal voltage generator of semiconductor device and method for driving the same

An internal voltage generator includes: a comparison block suitable for comparing an internal voltage with a reference voltage and generating a first comparison signal having an analog level corresponding to a comparison result a first driving block suitable for driving an output terminal of the internal voltage with a source voltage in response to the first comparison signal; a logic block suitable for generating a second comparison signal having a logic level based on the first comparison signal; and a second driving block suitable for driving the output terminal of the internal voltage with the source voltage based on the second comparison signal.. . ... Sk Hynix Inc

02/09/17 / #20170041003

Level shifter and parallel-to-serial converter including the same

A level shifter circuit includes a level shifting unit configured to receive signals that may vary in a first range via a positive input terminal and a negative input terminal, respectively and to output signals that may vary in a second range to a positive output terminal and a negative output terminal, respectively, where the second range is larger than the first range, a first pre-charging unit configured to pre-charge the positive output terminal to a predetermined level when a clock is in a first level, and a second pre-charging unit configured to pre-charge the negative output terminal to the predetermined level when the clock is in the first level.. . ... Sk Hynix Inc

02/09/17 / #20170040984

Mos pass transistors and level shifters including the same

A mos pass transistor includes a semiconductor layer having first conductivity, a trench isolation layer disposed in the semiconductor layer to define a first active region and a second active region, a first junction region having second conductivity, disposed in the first active region, and being in contact with a first sidewall of the trench isolation layer, a second junction region having the second conductivity, disposed in the second active region, being in contact with a second sidewall of the trench isolation layer, and being spaced apart from the first junction region, and a gate electrode disposed over the trench isolation layer. A lower portion of the gate electrode extends from a top surface of the trench isolation layer into the trench isolation layer to a predetermined depth.. ... Sk Hynix Inc

02/09/17 / #20170040791

Integrated circuit

An integrated circuit includes a signal transmission block suitable for transmitting signals between a pad and an internal circuit, an electrostatic discharge block suitable for protecting the internal circuit from an electrical shock transmitted through the signal transmission block, and a control block suitable for controlling decoupling/coupling operations of the signal transmission block and the electrostatic discharge block.. . ... Sk Hynix Inc

02/09/17 / #20170040382

Semiconductor apparatus with variable resistor having tapered double-layered sidewall spacers

A method for fabricating a semiconductor apparatus includes forming a variable resistor region, and forming a spacer having a top linewidth and a bottom linewidth substantially equal to each other in the variable resistor region. The forming of the spacer includes forming a first insulating layer in the variable resistor region through a first method, forming a second insulating layer along a surface of the first insulating layer in the variable resistor region through a second method for providing step coverage superior to the first method, and etching the first and second insulating layers.. ... Sk Hynix Inc

02/09/17 / #20170040291

Semiconductor package including planar stacked semiconductor chips

A semiconductor package may be provided. A semiconductor package may include a substrate. ... Sk Hynix Inc

02/09/17 / #20170040066

Semiconductor apparatus and repair method thereof

A semiconductor apparatus includes a fuse array configured to store word line failure information, a redundancy latch section, and a redundancy control block configured to store, in the redundancy latch section, word line order information generated according to the word line failure information.. . ... Sk Hynix Inc

02/09/17 / #20170040041

Memory apparatus using plurality of power sources and system including the same

A memory apparatus may include first to third pads to provide first to third voltages, respectively, to internal circuits. The first pad may receive a first external voltage, and provide the first voltage. ... Sk Hynix Inc

02/09/17 / #20170039693

Methods of detecting defects in registration controlled photomasks

A method of detecting defects of a photomask includes measuring registration errors of the photomask, correcting the measured registration errors using a registration control process with a laser beam, extracting deformation data of the photomask deformed by the registration control process, reflecting the extracted deformation data in defect detection parameters to obtain compensated defect detection parameters, and detecting defects of the photomask using the compensated defect detection parameters.. . ... Sk Hynix Inc

02/09/17 / #20170038969

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device including a buffer region and a main region; and a controller suitable for controlling a buffer write operation of the nonvolatile memory device such that write-requested first data is stored in the buffer region, and controlling a main write operation of the nonvolatile memory device such that the first data stored in the buffer region is stored in the main region according to a write mode, wherein the nonvolatile memory device performs the buffer write operation regardless of the write mode.. . ... Sk Hynix Inc

02/09/17 / #20170038428

Semiconductor devices and semiconductor systems including the same

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output a clock signal, a test mode signal and command address signals. ... Sk Hynix Inc

02/09/17 / #20170038194

Metrology apparatus for a semiconductor pattern, metrology system including the same and metrology method using the same

A metrology method includes obtaining a pattern reflection light reflected from an object by irradiating a first divided light, which is generated by reflecting a polarized light, to the object; obtaining a phase-controlled mirror reflection light reflected from a reflector by irradiating a second divided light, which is generated by transmitting the polarized light, to the reflector; and obtaining a pattern of the object based on an interference signal between the pattern reflection light and the mirror reflection light.. . ... Sk Hynix Inc

02/02/17 / #20170033791

Semiconductor devices and semiconductor systems including the same

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output set signals. ... Sk Hynix Inc

02/02/17 / #20170033780

Semiconductor device and semiconductor package using the same

A semiconductor device may include a comparator and a pad. The comparator may compare a voltage level of a reference node with a voltage level of a reference voltage to generate a code. ... Sk Hynix Inc

02/02/17 / #20170033778

Semiconductor device

A semiconductor device includes a first pre-stress block suitable for generating a first load signal, which corresponds to an active signal during an active mode and/or to a high voltage level during a precharge mode, in response to a stress section signal; a first delay amount reflection block suitable for reflecting a first delay amount in the first load signal in response to one or more first delay amount control signals; and a first main stress block suitable for generating a word line driving control signal, which corresponds to the active signal during the active mode and the high voltage level during the precharge mode, in response to the stress section signal and the first load signal.. . ... Sk Hynix Inc

02/02/17 / #20170033691

Voltage generation circuit

A voltage generation circuit may include: a current providing block configured to provide, to an output node, a current corresponding to a voltage level of a set voltage, and a voltage level control block configured to adjust the resistance value thereof in response to a voltage control signal, wherein the voltage level control block is coupled between the output node and a ground terminal, and wherein the voltage level control block comprises a first current path unit and a second current path unit having different temperature characteristics.. . ... Sk Hynix Inc

02/02/17 / #20170033690

Voltage generation circuit

A voltage generation circuit includes a voltage detection unit configured to detect a voltage level of an internal voltage and generate a detection signal, a first voltage control unit configured to be applied with a driving voltage and generate a voltage control signal in response to the detection signal, a voltage generation unit configured to generate the internal voltage in response to the voltage control signal, and a second voltage control unit configured to change a voltage level of the driving voltage in response to a voltage generation enable signal and the detection signal.. . ... Sk Hynix Inc

02/02/17 / #20170033279

Electronic device and method for fabricating the same

An electronic device may include a semiconductor memory. The semiconductor memory may include a substrate including a first region and a second region; buried gates formed in the first region and the second region, the buried gates in the second region having a different density distribution from the buried gates in the first region; first and second junction regions formed in the first and second regions, respectively, and having a same depth as each other; and a variable resistance element formed over the substrate and electrically connected to the buried gates in the first region. ... Sk Hynix Inc

02/02/17 / #20170033117

Semiconductor device and method of manufacturing the same

Provided herein is a semiconductor device including n stacked groups (where n is a natural number greater than or equal to two) sequentially stacked over a substrate, each stacked group including interlayer insulating films and conductive patterns alternately stacked, and n concave portions each having stepped sidewalls formed in the interlayer insulating films and the conductive patterns of the stacked groups, the n concave portions each having stepped sidewalls being aligned in a first direction.. . ... Sk Hynix Inc

02/02/17 / #20170033081

Stack package and method for manufacturing the stack package

A stack package may include a substrate, and a first semiconductor chip mounted over the substrate. The stack package may include a support member disposed over the substrate and the first semiconductor chip, and spaced apart from the substrate and the first semiconductor chip. ... Sk Hynix Inc

02/02/17 / #20170032960

Composition for coating photoresist pattern and method for forming fine pattern using the same

Disclosed are a composition for coating a photoresist pattern and a method for forming a fine pattern using the same. The composition for coating a photoresist pattern includes an ammonium base-containing polymer compound and a solvent. ... Sk Hynix Inc

02/02/17 / #20170032850

Semiconductor memory apparatus and test method thereof

A semiconductor memory apparatus includes a normal write pulse generator configured to generate a normal write pulse in a normal operation, a test write pulse generator configured to repeatedly generate a test write pulse a preset number of times in a test operation, and a selector configured to provide the normal write pulse to a memory cell in the normal operation and provide the test write pulse to the memory cell in the test operation.. . ... Sk Hynix Inc

02/02/17 / #20170032833

Semiconductor device having input/output line drive circuit and semiconductor system including the same

A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a command/address signal. ... Sk Hynix Inc

02/02/17 / #20170032830

Semiconductor device and semiconductor system including the same

A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs an external command. ... Sk Hynix Inc

02/02/17 / #20170032829

Semiconductor memory device, memory system including the same and operating method thereof

A semiconductor memory device includes a program and read unit suitable for programming program data in a memory cell array and for reading read data stored in the memory cell array, and a control unit suitable for generating a control signal for controlling the program and read unit in response to a command input from the outside of the semiconductor memory device, in which the control unit controls the program and read unit to read the read data in a state of storing a first bit data of the program data when a read command is input while programming the program data.. . ... Sk Hynix Inc

02/02/17 / #20170032828

Semiconductor systems and semiconductor devices

A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs data, a data strobe signal, an external command, and a clock signal. ... Sk Hynix Inc

02/02/17 / #20170032824

Nonvolatile memory device, nonvolatile memory system, and operating method of nonvolatile memory

A nonvolatile memory device may include a nonvolatile memory device may include a nonvolatile memory cell array; a peripheral circuit suitable for: activating an operation voltage in response to an operation voltage activation command, performing an operation to the nonvolatile memory cell array using the activated operation voltage in response to an operation command, and deactivating the activated operation voltage in response to an operation voltage deactivation command after the performing of the operation; and a control circuit suitable for controlling the peripheral circuit to execute an intervening operation during the activating of the operation voltage, the performing of the operation, and the deactivating of the activated operation voltage.. . ... Sk Hynix Inc

02/02/17 / #20170031848

Semiconductor device

A semiconductor device includes a memory device, a host, and an interface. The memory device includes various types of memory units configured to be mounted to one slot. ... Sk Hynix Inc

02/02/17 / #20170031836

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of pages each having a plurality of memory cells coupled to a plurality of word lines and suitable for storing read data and write data requested from a host, and a plurality of memory blocks each having the pages; and a controller suitable for grouping the pages included in the memory blocks so as to divide each of the memory blocks into a plurality of page zones, and storing data corresponding to a write command into pages of a second memory block of the memory blocks and storing program update information on a first page zone of a first memory block of the memory blocks into a list, when receiving the write command for data stored in a first page of the first page zone in the first memory block.. . ... Sk Hynix Inc

02/02/17 / #20170031824

Memory system and operating method thereof

A memory system includes a memory device of lower read operation speed; a memory cache of higher read operation speed; and a controller suitable for: setting one of access patterns to the memory device defined by pairs of former and latter addresses provided to the memory system within a set input time interval as a prefetch pattern; performing a prefetch operation of caching data corresponding to the latter address from the memory device to the memory cache according to the prefetch pattern; and reading the cached data from the memory cache in response to a read command provided with the latter address of the prefetch pattern.. . ... Sk Hynix Inc

02/02/17 / #20170031751

Data storage device and operating method thereof

A data storage device may include a plurality of nonvolatile memory devices including a plurality of blocks and a controller suitable for generating super block parity data for a super block, which is formed of one or more of the plurality of blocks.. . ... Sk Hynix Inc

02/02/17 / #20170031747

Data i/o circuits and semiconductor systems including the same

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output an external strobe signal and external data. ... Sk Hynix Inc

02/02/17 / #20170031653

Buffer, semiconductor apparatus and semiconductor system using the same

A buffer may include a first sensing unit configured to sense data, and a second sensing unit configured to generate equalization control signals according to outputs of the first sensing unit. The buffer may include an equalization delay compensation unit configured to compensate the equalization control signals for signal processing delay times of the equalization control signals, and generate delay-compensated equalization control signals. ... Sk Hynix Inc

01/26/17 / #20170025946

Voltage generators and systems

In one example, a voltage generator includes a plurality of voltage pumps, a voltage detection circuit, an oscillator, and a control circuit. The plurality of voltage pumps are configured to perform voltage pumping operations in a sequence and output a pumping voltage. ... Sk Hynix Inc

01/26/17 / #20170025599

Electronic device and method for fabricating the same

An electronic device may include a semiconductor memory. The semiconductor memory may include a variable resistance element including a ferromagnetic layer including a hydrogen group; an oxide spacer formed on sidewalls of the variable resistance element; and a nitride spacer formed on the oxide spacer.. ... Sk Hynix Inc

01/26/17 / #20170025598

Electronic device

This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes a semiconductor memory, and the semiconductor memory may include a substrate; a plurality of structures formed over the substrate to be spaced apart from each other, each structure comprising a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer; and a magnetic correction layer formed adjacent to the plurality of structures and structured to reduce an influence to the free layer by a stray magnetic field generated by the pinned layer.. ... Sk Hynix Inc

01/26/17 / #20170025459

Image sensor and method for fabricating the same

An image sensor includes a substrate including a pixel array region and a logic region where a surface of the pixel array region is higher than a surface of the logic region, and a light shielding pattern formed over the substrate of the logic region and having a surface on substantially the same plane as a surface of the substrate.. . ... Sk Hynix Inc

01/26/17 / #20170025438

Semiconductor device

Provided herein a semiconductor device including a stack including conductive layers and insulating layers that are alternately stacked, and a slit insulating layer passing through the stack in a stacking direction, the slit insulating layer including a first main pattern extending in a first direction, and a first protruding pattern protruding in a second direction crossing the first direction at an end of the first main pattern.. . ... Sk Hynix Inc

01/26/17 / #20170025433

Semiconductor device with high integration

The present disclosure may provide a semiconductor device having a stable structure and a low manufacturing degree of the difficulty. The device may include conductive layers and insulating layers which are alternately stacked; a plurality of pillars passing through the conductive layers and the insulating layers; and a plurality of deposit inhibiting patterns, each deposit inhibiting pattern being formed along a portion of an interface between a side-wall of each of the pillars and each of the conductive layers and along a portion of an interface between each of the insulating layers and each of the conductive layers.. ... Sk Hynix Inc

01/26/17 / #20170025432

Semiconductor device and method of manufacturing the same

The present disclosure may provide a semiconductor device with an enhanced integration. The device may include a lower pipe gate; an upper pipe gate including a first horizontal portion and first and second protrusions, the first horizontal portion being parallel to the lower pipe gate, the first and second protrusions extending from the first horizontal portion to the lower pipe gate and crossing each other so as to define a pipe channel region; a partition pipe gate disposed between the lower and upper pipe gates, the partition pipe gate dividing the pipe channel region into first and second pipe channel regions; and first and second pipe channel films disposed respectively in the first and second pipe channel regions.. ... Sk Hynix Inc

01/26/17 / #20170025409

Electronic circuits including diode-connected bipolar junction transistors

A diode-connected bipolar junction transistor includes a common collector region of a first conductivity, a common base region of a second conductivity disposed over the common collector region, and a plurality of emitter regions of the first conductivity disposed over the common base region, arranged to be spaced apart from each other, and arranged to have island shapes. The common base region and the common collector region are electrically coupled to each other.. ... Sk Hynix Inc

01/26/17 / #20170025284

Method for forming patterns of semiconductor device

A method for forming patterns of a semiconductor device includes preparing an etch target layer defined with a first region and a second region; forming a regular first feature which is positioned over the etch target layer in the first region and a random feature which is positioned over the etch target layer in the second region; forming a regular second feature over the regular first feature; forming first and second cutting barriers which expose a portion of the random feature, over the random feature; cutting the regular first feature using the regular second feature, to form a regular array feature; cutting the random feature using the first cutting barrier and the second cutting barrier, to form a random array feature; and etching the etch target layer by using the regular array feature and the random array feature, to form a regular array pattern and a random array pattern.. . ... Sk Hynix Inc

01/26/17 / #20170025184

Semiconductor memory device with improved program verification reliability

A semiconductor memory device includes a memory cell array including first and second groups of memory strings respectively coupled to first and second groups of bit-lines, wherein the first and second groups of memory strings respectively include first and second groups of selection transistor cells; a peripheral circuit suitable for applying a program voltage, and performing program verification operation for the memory cell array; and a control logic suitable for controlling the peripheral circuit to perform a first program verification operation for the first group of selection transistor cells and a second program verification operation for the second group of selection transistor cells.. . ... Sk Hynix Inc

01/26/17 / #20170025183

Semiconductor memory device and operating method thereof

A semiconductor memory device may include a memory cell array including a plurality of memory cells; a peripheral circuit unit suitable for performing a program operation and a verification operation to the memory cell array; and a control logic suitable for controlling the peripheral circuit unit to apply a program voltage to a selected memory cell from the plurality of memory cells during the program operation, wherein the program voltage increases by a step voltage as the program operation is repeated, and wherein the step voltage gradually increases as the program operation is repeated.. . ... Sk Hynix Inc

01/26/17 / #20170025180

Controller for biasing switching element of a page buffer of a non volatile memory

Disclosed herein is a controlling block for a non-volatile memory device including a switching element coupling a bit-line with the corresponding page buffer, comprising: a look-up table configured to store a plurality of address zones: and a matching logic configured to match one address zone among the plurality of address zones based on all inputted row address and generate a bias voltage, based on the address zone, to the switching element for reading operation of the non-volatile memory, wherein the plurality of address zones are defined by grouping word-lines having a i-v characteristic which differs for a current value different from a prefixed value.. . ... Sk Hynix Inc

01/26/17 / #20170025178

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a plurality of memory cells connected to a plurality of word lines; a peripheral circuit suitable for applying a program pulse to at least one of the word lines, performing a program verification operation to the plurality of memory cells by using a first program verification voltage; and a control logic suitable for controlling the peripheral circuit to repeat the applying of the program pulse and the performing the program verification operation until program verification passes by increasing a level of the program pulse by an amount of a step voltage at each repetition, wherein a size of the step voltage decreases at each repetition.. . ... Sk Hynix Inc

01/26/17 / #20170025177

Memory system including semiconductor memory device and operating method thereof

An operating method of a memory system including first and second one half pages includes acquiring first and second partial data from main data; performing a first program operation to the first one half page of a selected page with the first partial data; and performing a second program operation to the second one half page of the selected page with the second partial data. The first and second partial data may be programmed in the same first column region in the first and second one half pages, respectively.. ... Sk Hynix Inc

01/26/17 / #20170025176

Semiconductor memory device and operating method thereof

A semiconductor memory device may include a plurality of memory cells programmed to have one of first to nth program states differentiated according to threshold voltages of the memory cells, the method including determining whether there exists over program cells from among memory cells programmed to a n−1th program state, by using a first verify voltage of a nth program state from among the first to nth program states; when there exists over program cells, determining whether the number of the over program cells exceeds a reference value; and when the number of over program cells exceeds the reference value, outputting a program fall signal to a controller.. . ... Sk Hynix Inc

01/26/17 / #20170025162

Semiconductor memory device and method for operating the same

A semiconductor memory device includes a plurality of memory cells coupled to multiple word lines a word line deactivation voltage generation block suitable for generating word line deactivation voltages having different voltage levels corresponding to temperature ranges, and a word line driving block suitable for driving a word line to be deactivated with the word line deactivation voltages selected from the word line deactivation voltages.. . ... Sk Hynix Inc

01/26/17 / #20170024336

Electronic device and method for fabricating the same

This technology provides a method for fabricating an electronic device. A method for fabricating an electronic device including a variable resistance element, which includes a free layer having a variable magnetization direction; a pinned layer having a first non-variable magnetization direction, and including first ferromagnetic materials and a first spacer layer interposed between adjacent two first ferromagnetic materials among the first ferromagnetic materials; a tunnel barrier layer interposed between the free layer and the pinned layer; a magnetic correction layer having a second magnetization direction which is anti-parallel to the first magnetization direction; and a third spacer layer interposed between the magnetic correction layer and the pinned layer, and providing an anti-ferromagnetic exchange coupling between the magnetic correction layer and the pinned layer.. ... Sk Hynix Inc

01/26/17 / #20170024333

High performance host queue monitor for pcie ssd controller

Memory systems may include a plurality of queues, a queue ready indicator suitable for grouping the plurality of queues into a predefined number of queue ranges, each queue range having associated with it a queue range ready signal, and setting a queue range ready signal to ready when each queue in the queue range associated with the queue range ready signal is ready for processing, and a queue process sequencer suitable for determining a queue range ready for processing based on the queue range ready signals, and processing a queue within the queue range determined to be ready for processing.. . ... Sk Hynix Inc

01/26/17 / #20170024332

Programmable protocol independent bar memory for ssd controller

Memory systems may include a programmable bit control unit suitable for defining read-write properties to locations in a base address register (bar) memory, a read-write switch suitable for receiving a memory access request, and identifying whether the memory access request is a read access or a write access, and an access control unit suitable for receiving the memory access request from the read-write switch when the memory access request is identified as a write access, determining a read-write property associated with the write access, and processing the write access to a location in the bar memory with a defined read-write property that is the same as the determined read-write property associated with the write request.. . ... Sk Hynix Inc

01/26/17 / #20170024163

Data temperature profiling by smart counter

Memory systems may include a logical block address (lba) space divided into a number of zones, a counter associated with each zone, each counter suitable for incrementing a count value when a read is performed on an lba in the zone with which the counter is associated, and a controller suitable for calculating a temperature of each zone based on the count values of the counters, sorting the zones according to the calculated temperature, combining the zones into a number of superzones based on the sorting, and splitting the number of superzones into the number of zones into which the lba space was divided.. . ... Sk Hynix Inc

01/26/17 / #20170024157

Memory system and operating method of memory system

A memory system may include: a memory device including a plurality of pages having a plurality of memory cells coupled to a plurality of word lines and suitable for storing read data and write data requested from a host, a plurality of memory blocks each including the pages, a plurality of planes each including the memory blocks, and a plurality of memory chips each including the planes; and a controller suitable for searching map data of the read data corresponding to a read command received from the host on a basis of a plurality of segments, triggering memory chips corresponding to the map data searched through the searches of the respective segments, reading data stored in the triggered memory chips, and transferring the read data to the host.. . ... Sk Hynix Inc

01/19/17 / #20170019277

Interface circuit for high speed communication and system including the same

A system may include an interface circuit coupled to a wire bus. The interface circuit may receive a multi-level symbol according to a status of the wire bus. ... Sk Hynix Inc

01/19/17 / #20170019202

Interface circuit for communication, and system including the same

A system may include a processor and a memory. The processor and the memory may communicate through a wire bus. ... Sk Hynix Inc

01/19/17 / #20170019107

Semiconductor apparatus

A semiconductor apparatus may include a transmission circuit, a reception circuit, and a pad commonly coupled to the transmission circuit and the reception circuit. When either the transmission circuit or the reception circuit is activated, parasitic capacitance of a line coupled to the transmission circuit, the reception circuit, and the pad is varied.. ... Sk Hynix Inc

01/19/17 / #20170019101

Input/output circuit, input/output network, and input/output system including the same

An input/output circuit may include a driving unit including a first transistor coupled between a power supply voltage and a first node, and a second transistor coupled in series with the first transistor through the first node at an end of the second transistor. The input/output circuit may include switch elements coupled in parallel to a second node at another end of the second transistor, and the switch elements configured to be selectively turned on in an input operation and an output operation.. ... Sk Hynix Inc

01/19/17 / #20170019100

Driving signal control circuit and driving apparatus

A driving signal control circuit includes a discharge circuit, a counter circuit, and a control circuit. The discharge circuit is configured to compare a monitored voltage and a reference voltage, and generate a discharge signal. ... Sk Hynix Inc

01/19/17 / #20170019091

Signal generator adjusting a duty cycle and semiconductor apparatus using the same

A semiconductor apparatus may include a signal generator, and may operate by receiving two or more external power voltages. The signal generator may include a duty cycle circuit. ... Sk Hynix Inc

01/19/17 / #20170019089

Voltage level shifter, and embedded nonvolatile memory and system using the same

A voltage level shifter may include a first input unit, a second input unit, a first mirror unit, a second mirror unit, and a clamping block. The first and second input units may receive a first input signal and a second input signal, respectively, and form current paths of a negative output node and a positive output node. ... Sk Hynix Inc

01/19/17 / #20170019024

Switched-capacitor dc-to-dc converters and methods of fabricating the same

A switched-capacitor dc-to-dc converter includes a logic cell and a capacitor cell vertically overlapping with the logic cell. The logic cell has a plurality of active elements disposed over a first substrate. ... Sk Hynix Inc

01/19/17 / #20170019018

Power control device and method thereof

An embodiment relates to a power control device and a technology capable of stably supplying power when an electrical fuse boots up. The power control device includes a power supply unit, a power driving unit, and an electrical fuse unit. ... Sk Hynix Inc

01/19/17 / #20170018559

Method for manufacturing a nonvolatile memory device

A method for manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention may include providing a substrate comprising a cell region and a peripheral region, wherein the peripheral region comprises an nmos region and a pmos region; performing a well forming ion implantation over the substrate in the cell region and the nmos region; performing a threshold voltage adjusting ion implantation over a surface of the substrate in the cell region and the nmos region; forming a gate pattern comprising a floating gate electrode in the cell region and the peripheral region; and performing a junction ion implantation over a surface of the cell region, wherein the floating gate electrode may have p-type conductivity.. . ... Sk Hynix Inc

01/19/17 / #20170018527

Semiconductor package having a plurality of semiconductor chips stacked therein

A semiconductor package may include a first semiconductor chip having a plurality of first bonding pads arranged at a first pitch on a first active surface. The semiconductor package may include one or more reconfigurable package units each including a second semiconductor chip having a plurality of second bonding pads arranged at a second pitch on a second active surface; a semiconductor chip connector arranged spaced apart from the second semiconductor chip and having a plurality of through vias arranged at the first pitch; a molding layer surrounding side surfaces of the second semiconductor chip and the semiconductor chip connector; and redistribution lines formed over the second semiconductor chip, the semiconductor chip connector, and the molding layer. ... Sk Hynix Inc

01/19/17 / #20170018317

Random number generation circuit and semiconductor system including the same

A random number generation circuit may include a memory block. The random number generation circuit may include a fuse block configured to store an address of a failed memory cell from a memory cell array of the memory block, as a repair address, and generate a match signal by comparing the repair address with a normal address inputted from an exterior. ... Sk Hynix Inc

01/19/17 / #20170018316

Semiconductor apparatus and repair method thereof

A semiconductor apparatus includes a memory region; a fuse array including a plurality of fuse groups, each fuse group being configured to store a failed address of the memory region; a remaining-fuse information storage unit configured to store remaining-fuse information on a fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups; and a control unit configured to perform a control operation for updating the remaining-fuse information for the fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups and for storing the failed address when the failed address is detected.. . ... Sk Hynix Inc

01/19/17 / #20170018315

Test system and test method

A test system may include a memory device suitable for reading a stored data chunk; and a test device suitable for calculating a cumulative failure probability that the data chunk will contain a s predetermined number of error bits or less and decoding for the data chunk will fail.. . ... Sk Hynix Inc

01/19/17 / #20170018314

Semiconductor devices and semiconductor systems including the same

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output command signals and setting signals. ... Sk Hynix Inc

01/19/17 / #20170018300

Refresh verification circuit, semiconductor apparatus and semiconductor system

A refresh verification circuit may include a filtering circuit configured to receive a refresh pulse and to generate a filtering pulse in response to a duration of the enable period of the refresh pulse.. . ... Sk Hynix Inc

01/19/17 / #20170018296

Semiconductor memory device outputting read-busy signal and memory system including the same

A semiconductor memory device includes a plurality of memory cells; a peripheral circuit suitable for controlling the memory cells, and operating in first and second modes respectively corresponding to enablement and disablement of a chip selection signal; and a ready-busy signal generator suitable for biasing a ready-busy line according to whether the peripheral circuit is in a ready or busy state during the enablement of the chip selection signal. Communication between the semiconductor memory device and an external device is allowed in the first mode. ... Sk Hynix Inc

01/19/17 / #20170018295

Bitline senseamplifier and semiconductor memory apparatus using the same

A memory apparatus may include a bit line sense-amplifier coupled to first and second bit lines; a first precharge unit suitable for coupling the first and second bit lines in response to a bit line equalization signal; a sense-amplifier power control unit suitable for providing a plurality of powers to the bit line sense-amplifier in response to a power control signal; and a second precharge unit suitable for individually changing each voltage level of the first and second bit lines based on a precharge control signal.. . ... Sk Hynix Inc

01/19/17 / #20170018294

Semiconductor memory device and i/o control circuit therefor

An i/o control circuit, includes a mode setting unit configured to generate a first mode signal, a second mode signal, a third mode signal, and a fourth mode signal in accordance with one of a plurality of i/o option modes, a first control signal generation unit configured to generate a first mode determination signal and a first control signal enable signal in response to the first i/o option signal and the first mode signal, and a second control signal generation unit configured to generate a second control signal enable signal, a third control signal enable signal, and a fourth control signal enable signal in response to a second i/o option signal, the first mode determination signal, the second mode signal, the third mode signal, and the fourth mode signal.. . ... Sk Hynix Inc

01/19/17 / #20170017605

Interface circuit for high speed communication, and system including the same

A system may include an interface circuit and a plurality of wire buses electrically coupled with one another. The interface circuit may include transmitters which change states of the plurality of wire buses to transmit a plurality of multilevel symbols. ... Sk Hynix Inc

01/19/17 / #20170017432

Interface circuit for communication, and system including the same

A system may include a processor and a memory. The processor and the memory may communicate with each other in a balanced code multiphase signal transmission scheme. ... Sk Hynix Inc

01/19/17 / #20170017418

Memory system and operating method of memory system

A memory system includes: a memory device including a plurality of memory blocks, and suitable for storing data; and a controller suitable for performing a wear-leveling operation between source and target memory blocks selected from the memory blocks, the controller may select the source and target memory blocks based on an erase count list storing current erase count (ec) information of the memory blocks.. . ... Sk Hynix Inc

01/19/17 / #20170017417

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory apparatus including a page including a plurality of chunk areas respectively corresponding to a plurality of data chunks; and a controller including a memory, and suitable for generating parity data by independently encoding one of the plural data chunk, storing the data chunk in one of the plural chunk areas of the page and storing the parity data in the memory as intermediate parity data.. . ... Sk Hynix Inc

01/19/17 / #20170017410

Memory controller

A memory controller includes: a write performance storage circuit suitable for storing write performance indexes of physical memory areas of a memory device, a write counting circuit suitable for counting a number of requests of a write operation on logical memory areas of the memory device, and a mapping circuit suitable for mapping a logical memory area, for which the number of requests of the write operation r may be relatively large, to a physical memory area with a better write performance index.. . ... Sk Hynix Inc

01/19/17 / #20170017409

Memory system

A memory system includes a memory device including a first block group and a second block group; and a controller suitable for storing first data in the first block group, and storing second data in the second block group. The first data may be provided within a preset period of time measured from occurrence of a preset event, and the second data may be provided after the preset period of time is expired.. ... Sk Hynix Inc

01/19/17 / #20170017408

Memory system and operating method of memory system

A memory system includes: a memory device including a plurality of page buffers corresponding to a plurality of memory regions suitable for storing command data; and a controller including a memory buffer, the controller being suitable for temporarily storing first and second command data in first and second sub-buffers, respectively, and for allocating the memory buffer and first page buffers as the first sub-buffer and second page buffers as the second sub-buffer.. . ... Sk Hynix Inc

01/19/17 / #20170017400

Memory device, memory system including the same and operation method of memory device

An operation method of a memory device includes: receiving a computation command; receiving a first address corresponding to the computation command; reading first data from a first memory location designated by the first address; receiving a second address corresponding to the computation command; reading second data from a second memory location designated by the second address; and performing a computation operation corresponding to the computation command on the first and second data.. . ... Sk Hynix Inc

01/19/17 / #20170017258

Clock generation device and semiconductor device including the same

A clock generation device and a semiconductor device including the same are disclosed, which may tune an internal clock to a desired frequency. The clock generation device may include an oscillator configured to tune an oscillation signal in response to a tuning signal, and adjust a period of an internal clock. ... Sk Hynix Inc

01/12/17 / #20170012625

Voltage level shifter

A voltage level shifter includes: in stages a pull-down driving unit suitable for receiving an input signal swinging between a ground voltage and a first supply voltage, and pull-down driving an output node to the ground voltage according to a voltage level of the input signal, wherein an output signal outputted through the output node swings between the ground voltage level and a second supply voltage level higher than the first supply voltage; a pull-up driving unit suitable for pull-up driving the output node, to the second supply voltage according to the voltage level of the input signal; a bias generation unit suitable for generating a bias voltage fixed to a preset voltage level; and a bias operation unit coupled between the output node and the pull-down driving unit, and suitable for lowering a voltage level of the output node in stages based on the bias voltage to supply the lowered voltage to the pull-down driving unit when a pull-down operation is performed by the pull-down driving unit.. . ... Sk Hynix Inc

01/12/17 / #20170012613

Input circuit and semiconductor apparatus including the input circuit

An input circuit and a semiconductor apparatus having the input circuit are provided. The input circuit may include a bias generation unit configured to generate a bias voltage. ... Sk Hynix Inc

01/12/17 / #20170012609

Start-up circuit for bandgap reference

A start-up circuit for a bandgap reference circuit include an operational amplifier and a diode coupled to a second input terminal of the operational amplifier. The circuit includes a first current branch including a first transistor and a second transistor in series, for generating a first current in response to an output voltage at an output terminal of the operational amplifier and a second current branch including a third transistor and a fourth transistor in series, for generating a second current in response to the output voltage. ... Sk Hynix Inc

01/12/17 / #20170012051

Method of manufacturing semiconductor device

The present disclosure provides a method of manufacturing a semiconductor device with a controlled doped concentration of a channel film that is run-through a plurality of memory stacks. In one aspect of the present disclosure, the method may include forming a hole, forming a channel film on an inner surface of the hole, forming a buffer film on an inner surface of the channel film, forming a dopant supply film to fill the hole, and doping the channel film via a dopant diffusion from the dopant supply film into the channel film.. ... Sk Hynix Inc

01/12/17 / #20170011805

Data storage device and operating method thereof

A data storage device may include: a nonvolatile memory device including a memory block; and a controller suitable for controlling the nonvolatile memory device to perform a string read operation on the memory block, and estimating a data storage rate of the memory block based on string read data acquired through the string read operation. When performing the string read operation, the nonvolatile memory device may apply the same read voltage to a plurality of word lines included in the memory block at the same time, acquire the string read data from the memory block according to the read voltage, and transmit the string read data to the controller.. ... Sk Hynix Inc

01/12/17 / #20170011801

Semiconductor memory device and operating method thereof

A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.. . ... Sk Hynix Inc

01/12/17 / #20170011787

Data input circuit and semiconductor memory device including the same

A data input circuit may include a data latch unit suitable for latching input data as latch data in response to first and second latch signals; a data signal generation unit suitable for outputting first and second data signals corresponding to the latch data; a first drive unit suitable for pulling up or down a first input/output data line of an input/output data line pair in response to the first and second data signals; and a second drive unit suitable for pulling up or down a second input/output data line of the input/output data line pair in response to the first and second data signals, wherein the first and second drive units adjust pull-up levels of the first and second input/output data lines in response to a data input control signal.. . ... Sk Hynix Inc

01/12/17 / #20170011780

Power on reset circuit and semiconductor memory device including the same

Provided herein is a power on reset circuit including a voltage dividing unit suitable for dividing an external power supply voltage according to a resistance ratio to output a divided voltage, a signal generating unit suitable for outputting a power on reset signal when the divided voltage has a set level or higher, and a resistance adjusting unit suitable for adjusting the resistance ratio of the voltage dividing unit in response to the power on reset signal.. . ... Sk Hynix Inc

01/12/17 / #20170011002

Peripheral component interconnect express card

A peripheral component interconnect express (pcie) card may include a base card, a mezzanine card and mezz connectors. The base card may be coupled to a host device, and host a first group of solid state drives (ssds). ... Sk Hynix Inc

01/12/17 / #20170010990

Embedded storage device

An embedded storage device for use with a computer device is provided. The embedded storage device includes a microprocessor, a master storage unit, a slave storage unit, and a relay bus. ... Sk Hynix Inc

01/12/17 / #20170010960

Memory control unit and data storage apparatus including the same

The memory control unit includes a descriptor fetch block suitable for fetching a descriptor from a volatile memory; an instruction fetch block suitable for fetching an instruction set from an instruction memory through an address information, wherein the instruction fetch block obtains the address information from the instruction memory through an index information included in the fetched descriptor; and a memory instruction generation block suitable for generating a memory instruction by combining a descriptor parameter value included in the fetched descriptor to the fetched instruction set.. . ... Sk Hynix Inc

01/05/17 / #20170006206

Image sensing device

An image sensing device includes a readout circuit suitable for sequentially generating a plurality of image signals corresponding to each pixel signal, based on a ramp clock and a count clock; and a clock generation circuit suitable for generating the ramp clock and the count clock having different frequency relationships depending upon generation periods of the image signals, based on a gain code signal corresponding to an analog gain.. . ... Sk Hynix Inc

01/05/17 / #20170005782

Clock generation circuit and method and semiconductor apparatus and electronic system using the same

A clock generation circuit may include a reference clock generator configured to generate a pair of first reference clocks in an offset code generation mode, a triggering unit configured to generate a pair of second reference clocks from the pair of first reference clocks, a pulse detector configured to generate a duty detection signal based on a phase difference between the pair of second reference clocks, a correction code generator configured to generate a reference correction code based on the duty detection signal, and an offset code generator configured to generate an offset code based on the reference correction code and a preset reference code.. . ... Sk Hynix Inc

01/05/17 / #20170005657

On-die termination enable signal generator, semiconductor apparatus, and semiconductor system

A semiconductor apparatus may include an on-die termination (odt) enable signal generator configured to enable an odt enable signal in response to a data strobe signal, or enable the odt enable signal in response to a command latch enable signal and an address latch enable signal. The semiconductor apparatus may include an odt circuit configured to perform an odt operation in response to the odt enable signal.. ... Sk Hynix Inc

01/05/17 / #20170005166

Semiconductor device with air gap and method for fabricating the same

A semiconductor device may include: a substrate having first and second surfaces; an interlayer dielectric layer having a first opening to expose the first surface; a first plug positioned in the first opening and isolated from a sidewall of the first opening by a pair of gaps; a bit line extended in any one direction while covering the first plug; a second plug including a lower part adjacent to the first plug and an upper part adjacent to the bit line, and connected to the second surface; a first air gap positioned between the first plug and the lower part of the second plug; and a second air gap positioned between the bit line and the upper part of the second plug, and having a larger width than the first air gap.. . ... Sk Hynix Inc

01/05/17 / #20170005139

Electronic device

This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes a semiconductor memory, and the semiconductor memory includes a variable resistance structure including a material having a resistance that is changed by formation or dissipation of conductive filaments; and a magnetic tunnel junction (mtj) structure inserted in the variable resistance structure and comprising a first magnetic layer having a pinned magnetization direction, a second magnetic layer having a variable magnetization direction, and a tunnel dielectric layer interposed between the first magnetic layer and the second magnetic layer.. ... Sk Hynix Inc

01/05/17 / #20170005138

Electronic device

An electronic device includes a semiconductor memory. The semiconductor memory includes a line-type first electrode layer having at least one protrusion and extending in a first direction, and a plurality of memory elements, each memory element including a variable resistance layer and a second electrode, the variable resistance layers of the memory elements being disposed over a top surface and two parallel side surfaces of the protrusion, respectively, the two parallel side surfaces of the protrusion being arranged in the first direction, the second electrodes of the memory elements being disposed over the variable resistance layers of the memory elements, respectively.. ... Sk Hynix Inc

01/05/17 / #20170005137

Electronic device

An electronic device may include a semiconductor memory. The semiconductor memory may include a stack in which a plurality of dielectric layers and a plurality of first electrodes are alternately stacked over a substrate in a vertical direction relative to the substrate; a hole pattern passing through the stack in the vertical direction and having a polygonal shape when viewed in a plan view; a plurality of second electrodes disposed on respective sidewalls of the hole pattern; and a plurality of variable resistance layers interposed between the plurality of second electrodes and the plurality of horizontal electrodes.. ... Sk Hynix Inc

01/05/17 / #20170005109

Semiconductor device having three-dimensional structure and method of manufacturing the same

A semiconductor device includes a semiconductor pattern; conductive layers each including a first portion through which the semiconductor pattern passes and a second portion having a thickness greater than the first portion, wherein the first portion of each conductive layer includes a first barrier pattern surrounding the semiconductor pattern and a material pattern, which is formed. In the first barrier pattern and has an etch selectivity with respect to the first barrier pattern, and the second portion of each conductive layer includes a conductive pattern; and contact plugs connected to the second portion of each of the conductive layers.. ... Sk Hynix Inc

01/05/17 / #20170005096

Sub word line driver of a semiconductor memory device

A sub word line driver of a semiconductor memory device including a sub word line driver is disclosed. The sub word line driver of a semiconductor memory device comprising: a semiconductor substrate including an active region extended in a first direction; a plurality of gate electrodes extended in a second direction perpendicular to the active region; first and second metal contacts formed over the active region between the gate electrodes; a plurality of metal pads coupled to the first metal contacts; and a plurality of metal signal lines coupled to the second metal contacts, extended in the second direction, and bent at specific parts adjacent to the metal pads.. ... Sk Hynix Inc

01/05/17 / #20170004967

Method of fabricating hafnium oxide layer and semiconductor device having the same

Provided are a method of fabricating a hafnium oxide layer and a method of fabricating a semiconductor device using the same. The method of fabricating a tetragonal hafnium oxide layer includes providing a substrate and then forming an initial hafnium oxide layer on the substrate. ... Sk Hynix Inc

01/05/17 / #20170004891

Nonvolatile memory and semiconductor device including the same

A nonvolatile memory includes a plurality of memory sets, wherein each of the memory sets includes a fir memory cell suitable for storing validity signal indicating data validity of the corresponding memory set, and second memory cells suitable for storing multi-bit data or one or more-bit defect information.. . ... Sk Hynix Inc

01/05/17 / #20170004890

Semiconductor device and operating method thereof

A semiconductor device may include: a first latch configured to store data outputted from a memory cell during a first operation; and a fail detection circuit configured to detect a fail by comparing the data outputted from the memory cell to the data stored in the first latch through a second operation performed at a predetermined time after the first operation.. . ... Sk Hynix Inc

01/05/17 / #20170004887

Anti-fuse type one-time programmable memory cell array and method of operating the same

An anti-fuse type one-time programmable (otp) memory cell array includes a plurality of unit cells which are respectively located at cross points of a plurality of rows and a plurality of columns, a well region shared by the plurality of unit cells, a plurality of anti-fuse gates respectively disposed in the plurality of columns to intersect the well region, a plurality of source/drain regions respectively disposed in portions of the well region between the plurality of anti-fuse gates, and a plurality of drain regions respectively disposed in portions of the well region located at one sides of the anti-fuse gates arrayed in a last column, which are opposite to the anti-fuse gates arrayed in a first column. Each of the unit cells includes one anti-fuse transistor having a mos transistor structure without a selection transistor.. ... Sk Hynix Inc

01/05/17 / #20170004885

Semiconductor device and operating method thereof

The semiconductor device includes a memory block including programmed pages and non-programmed pages, a peripheral circuit configured to perform a read operation of the memory block, and a control circuit configured to control the peripheral circuit so that a read voltage is applied to a word line coupled to a selected page among the pages for the read operation, a first pass voltage is applied to word lines coupled to the programmed pages among pages that are not selected for the read operation, and a second pass voltage lower than the first pass voltage is applied to word lines coupled to non-programmed pages among the pages that are not selected for the read operation.. . ... Sk Hynix Inc

01/05/17 / #20170004037

Memory device with different parity regions

The present disclosure memory includes a controller for a semiconductor memory device, the device including a memory cell array including a plurality of pages. The controller includes a memory control module suitable for translating a logical address for data provided from a host to a physical address representing one of the plurality of pages, and determining one of a plurality of operation modes based on the physical address and pre-stored parity-related information. ... Sk Hynix Inc

01/05/17 / #20170003909

Memory system for controlling semiconductor memory devices through plurality of channels

A memory system includes a plurality of channels; a plurality of semiconductor memory devices connected to the channels; and a controller that controls the semiconductor memory devices through the channels, wherein the controller writes program data in a first semiconductor memory device of the plurality of semiconductor memory devices, and wherein, when the writing of the program data fails, the program data is temporarily stored in a page buffer unit of a second semiconductor memory device of the plurality of semiconductor memory devices connected to a channel other than the channel corresponding to the first semiconductor memory device.. . ... Sk Hynix Inc

01/05/17 / #20170003703

Internal voltage generation circuit

An internal voltage generation circuit includes a comparison block suitable for generating a comparison signal by comparing an internal voltage with a reference voltage; and an internal voltage generation circuit suitable for controlling an amount of an internal current in response to a bias voltage corresponding to an operation current of the comparison block, and generating the internal voltage corresponding to the internal current in response to the comparison signal.. . ... Sk Hynix Inc








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