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Sk Hynix Inc patents (2018 archive)


Recent patent applications related to Sk Hynix Inc. Sk Hynix Inc is listed as an Agent/Assignee. Note: Sk Hynix Inc may have other listings under different names/spellings. We're not affiliated with Sk Hynix Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Sk Hynix Inc-related inventors


Magnetic memory device

According to one embodiment, a magnetic memory device includes a magnetoresistive element, the magnetoresistive element including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. The first magnetic layer includes first and second sub-magnetic layers each containing at least iron (fe) and boron (b), and a concentration of boron (b) contained in the first sub-magnetic layer is different from a concentration of boron (b) contained in the second sub-magnetic layer.. ... Sk Hynix Inc

Mos capacitor and image sensor having the same

A mos capacitor may include: an isolation layer formed in a substrate and defining an active region; a first electrode formed in the active region, and including an impurity region spaced from the isolation layer; and a second electrode formed over the substrate overlapping the impurity region, and including a gate having a plurality of gate patterns adjacent to each other with a gap therebetween.. . ... Sk Hynix Inc

Nonvolatile memory device

A nonvolatile memory device includes a semiconductor substrate, a tunnel insulation layer disposed on the semiconductor substrate, a charge trap layer disposed on the tunnel insulation layer, and a control gate electrode disposed on the charge trap layer. The tunnel insulation layer includes an antiferroelectric material.. ... Sk Hynix Inc

Image sensor

An image sensor includes: a pixel array where a plurality of pixel groups are arrayed in two dimensions, wherein each of the plurality of the pixel groups includes: a first pixel suitable for sensing a first color signal that is color-separated through a first color filter; and a second pixel suitable for sensing a second color signal that is color-separated through a second color filter and has a longer wavelength than the first color signal, and a volume of a first color filter or a second color filter that is positioned in a peripheral area of the pixel array is different from a volume of a first color filter or a second color filter that is positioned in a central area of the pixel array.. . ... Sk Hynix Inc

Semiconductor device and method of manufacturing the same

Provided herein is a semiconductor device. The semiconductor device may include conductive layers each including a line, and a pad which is coupled with the line and has a thickness greater than that of the line, the conductive layers being stacked such that the pads are exposed; insulating layers interposed between the conductive layers; first spacers each of which is interposed between the pad of the corresponding upper conductive layer and the pad of the corresponding low conductive layer; and second spacers covering the respective first spacers.. ... Sk Hynix Inc

Semiconductor device and method of manufacturing the same

Provided herein may be a semiconductor device. The semiconductor device may include a stack, channel holes passing through the stack, dummy channel holes passing through the stack and disposed between the channel holes, a slit passing through the stack and the dummy channel holes.. ... Sk Hynix Inc

Ferroelectric memory device

A ferroelectric memory device includes a substrate, a ferroelectric structure having a first ferroelectric material layer, an electrical floating layer, and a second ferroelectric material layer sequentially stacked on the substrate, and a gate electrode layer disposed on the ferroelectric structure. A hysteresis loop of the second ferroelectric material layer differs from a hysteresis loop of the first ferroelectric material layer.. ... Sk Hynix Inc

Memory system with diagnose command and operating method thereof

A memory system and an operating method thereof include: at least a cpu configured to generate a special command; at least a pcie link coupled with the cpu, wherein the pcie link includes at least a pcie switch; and a plurality of memory devices connected with the pcie switch, wherein each of the plurality of memory devices includes a memory controller, an operational mode switch, and a plurality of memory components, and the operational mode switch is configured to perform a loopback from the memory controller corresponding to the special command at loopback operational mode.. . ... Sk Hynix Inc

Ferroelectric memory device and method of manufacturing the same

The ferroelectric memory device includes a substrate having a base doped region doped with a dopant of a first conductivity type and a trench disposed in the base doped region having an inner wall with a bottom and sidewalls. Also, the ferroelectric memory device includes a ferroelectric gate insulation layer, disposed along the inner wall of the trench, a gate electrode layer disposed on the ferroelectric gate insulation layer inside the trench, and a source region and a drain region, disposed in the substrate at respective ends of the trench and doped with a dopant of a second conductivity type. ... Sk Hynix Inc

Ferroelectric memory device and method of manufacturing the same

A ferroelectric memory device according to an embodiment includes a substrate, a ferroelectric gate insulation layer disposed along an inner wall of a trench formed in the substrate, and a gate electrode layer disposed on the ferroelectric gate insulation layer. The ferroelectric gate insulation layer has a variable thickness on the inner wall of the trench.. ... Sk Hynix Inc

Semiconductor device

A semiconductor device includes a buffer control circuit suitable for generating a buffer control signal in response to a power-down mode signal and a detection pulse, a first buffer circuit suitable for generating a first internal chip select signal by buffering a chip select signal depending on a select signal which is generated in response to the buffer control signal in a power-down mode, and a detection pulse generation circuit suitable for generating the detection pulse in response to the first internal chip select signal.. . ... Sk Hynix Inc

Memory system and operating method thereof

A memory system includes: a memory device; and a controller suitable for controlling the memory device to perform a serial read operation by providing a serial read command and a start physical address for the serial read command when an external read command includes a request for the serial read operation, the serial read command includes consecutive physical address numbers information, in response to the serial read command, the memory device sets a read bias, reads data stored therein with the set read bias according to the start physical address and the consecutive physical address numbers information, and then discharges the read bias.. . ... Sk Hynix Inc

Memory module including battery

A memory module may include a module substrate having first and second surfaces facing away from each other, a plurality of first memories mounted over one or more of the first and second surfaces, one or more second memories and a controller each mounted over one of the first and second surfaces of the module substrate, and a plurality of batteries mounted over one or more of the first and second surfaces of the module substrate.. . ... Sk Hynix Inc

Pcie virtual switches and an operating method thereof

A memory system and an operating method thereof include: at least a host; and at least pcie coupled with the host, wherein the at least pcie link includes at least a pcie switch and a plurality of pcie endpoints, wherein the plurality of pcie endpoints includes used pcie endpoints and unused pcie endpoints, the used pcie endpoints are mapped into a pcie enumeration tree, and the unused pcie endpoints are removed from the pcie enumeration tree, at virtual switch mode.. . ... Sk Hynix Inc

09/27/18 / #20180276158

System including interface circuit for high speed communication

A system includes a data transmission unit, a termination resistor and a data reception unit. The data transmission unit may drive a data transmission line based on data, and drive the data transmission line to a voltage level corresponding to a termination voltage during a specified operation period. ... Sk Hynix Inc

09/27/18 / #20180276136

Data storage device and operating method thereof

An operating method for a data storage device may include: reading data from a first memory region of a storage medium; storing the read data in a data buffer; and writing the data stored in the data buffer to a second memory region of the storage medium, based on a read count for the first memory region.. . ... Sk Hynix Inc

09/27/18 / #20180275920

Memory system and operating method thereof

A memory system may include: a memory device; and a controller suitable for: receiving a plurality of commands from a host; performing command operations corresponding to the commands to the memory device; providing operation results of the command operations to the host; and performing processing results including processing receptions of the commands, requests for performing the command operations and operation results for the command operations at a regular time duration interval.. . ... Sk Hynix Inc

09/27/18 / #20180275891

Memory system with latency distribution optimization and an operating method thereof

A memory system and an operating method thereof include: at least a cpu including multiple cpu cores, wherein the multiple cpu cores include reserved cpu cores and host cpu cores; at least a pcie link coupled with the cpu, wherein the pcie link includes at least a pcie switch and a plurality of memory devices; and the plurality of memory devices coupled with the host cpu cores through respective workload threads and interrupt handlers, wherein the workload threads and interrupt handlers of each of the host cpu cores are configured to be optimized, the host cpu cores are isolated for the optimized workloads threads and interrupt handlers, and the workload threads and interrupt handlers are executed at the host cpu cores coupled thereto.. . ... Sk Hynix Inc

09/27/18 / #20180275890

Memory system and method for operating the same

A memory system includes: two or more memory devices; and a controller suitable for: distributively storing input data in a primary memory device and in a secondary memory device when the input data requested to be stored in the primary device has a greater size than a transfer size for a single interleaving operation of the primary device; and collecting the input data stored in the secondary device into the primary device when the primary and secondary memory devices are in an idle state.. . ... Sk Hynix Inc

09/20/18 / #20180269905

State-based decoding of product codes

Techniques for reducing the latency for decoding product codewords with minimal hardware architecture changes are described. In an example, multiple decoding procedures are available a system. ... Sk Hynix Inc

09/20/18 / #20180269901

Semiconductor device

A semiconductor device may be provided. The semiconductor device may include an input and output (i/o) circuit configured to output transfer data generated from input data as internal data based on a write enablement signal and configured to output error information on the input data based on the write enablement signal. ... Sk Hynix Inc

09/20/18 / #20180269893

Successive approximation register analog-digital converter having a split-capacitor based digital-analog converter

A successive approximation register analog-digital converter including a split-capacitor based digital-analog converter includes a comparator, a split-capacitor based digital-analog converter including a positive capacitor array and a negative capacitor array, and a successive approximation register logic. The positive capacitor array and the negative capacitor array each includes a positive capacitor array of a first stage and a negative capacitor array of a first stage that generate input signals of the comparator corresponding to upper bits including an msb, respectively, a positive capacitor array of a second stage and a negative capacitor array of a second stage that generate input signals corresponding to intermediate bits, and a positive capacitor array of a third stage and a negative capacitor array of a third stage that generate input signals corresponding to lower bits of an lsb and a next to bit of the lsb.. ... Sk Hynix Inc

09/20/18 / #20180269858

Semiconductor device

A semiconductor device includes a first mode signal generation circuit suitable for generating a first mode signal in response to a command, the first mode signal being enabled in the case where a first period determined depending on a current characteristic of a first mos transistor is longer than a second period determined by a first passive element; and a second mode signal generation circuit suitable for generating a second mode signal in response to the command, the second mode signal being enabled in the case where a third period determined by a second passive element is longer than a fourth period determined depending on a current characteristic of a second mos transistor.. . ... Sk Hynix Inc

09/20/18 / #20180269238

Image sensor

An image sensor may include: a pixel array having a plurality of pixels arranged in a matrix structure; and an image array including a plurality of image dots which are arranged in a matrix structure, and implemented by output signals of the respective pixels. The position of a first pixel in the pixel array may not correspond to the position of an image dot corresponding to the first pixel in the image array, and the position of a second pixel adjacent to the first pixel in the pixel array may correspond to the position of an image dot corresponding to the second pixel in the image array.. ... Sk Hynix Inc

09/20/18 / #20180269216

Ferroelectric memory device and cross-point array apparatus including the same

A ferroelectric memory device includes a first electrode layer disposed on a substrate, a first tunnel barrier layer disposed on the first electrode layer, a second electrode layer disposed on the first tunnel barrier layer, a second tunnel barrier layer disposed on the second electrode layer, and a third electrode layer disposed on the second tunnel barrier layer. Any one of the first and second tunnel barrier layers includes a ferroelectric material.. ... Sk Hynix Inc

09/20/18 / #20180269211

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes: forming a bottom electrode of a high aspect ratio; forming an interface layer by sequentially performing a first plasma process and a second plasma process onto a surface of the bottom electrode; forming a dielectric layer over the interface layer; and forming a top electrode over the dielectric layer.. . ... Sk Hynix Inc

09/20/18 / #20180268919

Data storage device and operating method thereof

An operating method for a data storage device may include: determining a displacement value based on section memory cell numbers regarding a plurality of threshold voltage sections divided by a first read voltage and second read voltages; determining an adjustment direction based on the displacement value; adjusting at least one reliability value corresponding to at least one threshold voltage section among the threshold voltage sections, positioned in the adjustment direction from the first read voltage; and performing an error correction operation on data read from memory cells based on the first read voltage, using reliability values corresponding to the threshold voltage sections.. . ... Sk Hynix Inc

09/20/18 / #20180268917

Memory device and test method thereof

A test method for a memory device may include: performing a first write operation of writing test data to first regions of a normal cell region and a parity cell region, and storing a parity bit generated based on the test data in a temporary storage circuit; performing a second write operation of writing the parity bit stored in the temporary storage circuit to a second region of the parity cell region; performing a first read operation of reading the parity bit from the second region of the parity cell region, and storing the parity bit into the temporary storage circuit; and performing a second read operation of reading the test data from the first regions of the normal cell region and the parity cell region, correcting an error of the test data using the parity bit stored in the temporary storage circuit, and outputting error-corrected test data.. . ... Sk Hynix Inc

09/20/18 / #20180268892

Semiconductor memory device

A semiconductor memory device includes a memory cell array and a row decoder disposed in a first direction over a substrate and a plurality of coupling lines for electrically coupling the memory cell array and the row decoder. Each of the coupling lines includes a first conductive line disposed in the first direction; a second conductive line disposed parallel to the first conductive line; and a pad coupling the first conductive line and the second conductive line, and coupled to the memory cell array or the row decoder through a contact plug. ... Sk Hynix Inc

09/20/18 / #20180268884

Semiconductor devices

A semiconductor device may be provided. The semiconductor device may include a period code generation circuit configured to generate a period code having a logic level combination corresponding to a first command or a second command. ... Sk Hynix Inc

09/20/18 / #20180268880

Semiconductor memory device, flag generating circuit, and method of outputting data in a semiconductor device

A semiconductor memory device may include a memory circuit including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines, and configured to output data from the memory cell coupled to each of the bit lines through a global input/output line; a flag-generating circuit configured to generate a flag signal received with respect to the bit lines. The flag signal may include at least one of a duplicate data flag signal and a data bus inversion flag signal based on number of data having a specific logic level among the data in the memory cell for each of the bit lines that may be provided through the global input/output line in a read operation; and an output circuit configured to output the data based on at least one of the duplicate data flag signal and the data bus is inversion flag signal.. ... Sk Hynix Inc

09/20/18 / #20180268879

Semiconductor data multiplexer circuit

A semiconductor device includes a data output selection circuit suitable for outputting first pattern data as selection data in the case where a training operation is performed, outputting information data as the selection data in the case where a mode register read operation is performed, and outputting second pattern data in the case where the training operation is performed; and a data pad circuit including a first data pad and a second data pad, wherein the first data pad outputs the selection data and the second data pad outputs the second pattern data.. . ... Sk Hynix Inc

09/20/18 / #20180267903

Memory system and operating method thereof

A memory system includes: a controller suitable for generating a control signal for changing a data output status of a memory device to an abnormal status; and the memory device suitable for, when the data output status is the abnormal status, changing second data, which correspond to a read command from the controller among first data stored therein, into encrypted data, and outputting the encrypted data.. . ... Sk Hynix Inc

09/20/18 / #20180267897

Memory system and operating method thereof

A memory system includes: a memory device; and a controller including a cache which is coupled between a host and the memory device and includes a plurality of storing regions, for determining whether or not a storing region corresponding to address information which is requested by the host exists in the cache among the plurality of the storing regions based on bitmap information which hierarchically represents the plurality of the storing regions.. . ... Sk Hynix Inc

09/20/18 / #20180267895

Memory system

A memory system include: a plurality of first memory devices each coupled to a first channel and including a plurality of first memory blocks; a plurality of second memory devices each coupled to a second channel and including a plurality of second memory blocks; a first access controller suitable for controlling an access to the first memory blocks; a second access controller suitable for controlling an access to the second memory blocks; and a bad block controller suitable for: selecting one between the first and second access controllers by comparing bad physical addresses corresponding to bad blocks included in each of the first and second memory devices with first and second physical addresses respectively corresponding to the first and second memory blocks, and transferring one of the first and second physical addresses and substitute physical address that replace the bad physical addresses.. . ... Sk Hynix Inc

09/20/18 / #20180267877

Circuits relating to the calculation of power consumption of phase change memory devices, phase change memory systems including the same, and methods relating to the calculation of power consumption of phase change memory devices

A circuit for calculating power consumption of a phase change memory (pcm) device may be provided. The circuit may include a plurality of pipelines and an arithmetic logic circuit. ... Sk Hynix Inc

09/20/18 / #20180267852

Semiconductor devices

A semiconductor device includes an error count signal generation circuit and a row error control circuit. The error count signal generation circuit generates an error count signal which is enabled if the number of erroneous data of cells selected to perform an error scrub operation is equal to a predetermined number. ... Sk Hynix Inc

09/20/18 / #20180267743

Electronic device including semiconductor memory

An electronic device includes a semiconductor memory. The semiconductor memory includes a first variable resistance element, a first switching element coupled to the first variable resistance element via a first line, a second variable resistance element, and a second switching element coupled to the second variable resistance element via a second line, wherein a distance between the first switching element and the first variable resistance element is larger than a distance between the second switching element and the second variable resistance element, and wherein a second path from a first terminal of the second switching element to the second variable resistance element includes a resistance component, a resistance of the second path being greater than a resistance of a first path, the first path being from a first terminal of the first switching element to the first variable resistance element.. ... Sk Hynix Inc

09/20/18 / #20180267724

Data transfer training method and data storage device performing the same

A data transfer training method includes determining whether a program data transfer training command or a read data transfer training command is received from a host device; transferring normal program signals to non-training memory devices among a plurality of memory devices and performing a program data transfer training to a training memory device among a plurality of memory devices while performing normal program operations to the non-training memory devices in response to a received program data transfer training command; and transferring normal read signals to the non-training memory devices, and performing a read data transfer training to the training memory device while performing normal read operations to the non-training memory devices in response to a received read data transfer training command.. . ... Sk Hynix Inc

09/20/18 / #20180267708

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of pages in which data are stored, a plurality of memory blocks in which the pages are included, and a plurality of memory dies in which the memory blocks are included; and a controller suitable for performing command operations corresponding to a plurality of commands received from the host, predicting peak operation durations when performing the command operations, and scheduling the commands by minimizing overlaps between the peak operation durations.. . ... Sk Hynix Inc

09/06/18 / #20180255215

Image sensor

Disclosed is an image sensor device including a pixel array in which a plurality of pixel blocks are arranged. Each of the pixel blocks may include: a light receiver comprising a floating diffusion and a plurality of unit pixels and configured to receive incident light and generate photo charges in response to the received incident light, the plurality of unit pixels sharing the floating diffusion; a first driver located at a first side of the light receiver and comprising a driver transistor; a second driver located at a second side of the light receiver and comprising a reset transistor; and a conductive line having a first region coupling the driver transistor to the floating diffusion and a second region coupling the floating diffusion to the reset transistor, wherein the driver transistor and the reset transistor are respectively located the first side and the second side of the light receiver in a diagonal direction.. ... Sk Hynix Inc

09/06/18 / #20180254297

Image sensor with phase difference detection pixel

An image sensor includes a pixel array having a plurality of pixels arranged therein. At least any one of the plurality of pixels include: a photoelectric conversion unit including first and second photoelectric conversion elements; a first sub-lens formed over the first photoelectric conversion element, and having a vertex out of a central axis of the first photoelectric conversion element; a second sub-lens formed over the second photoelectric conversion element, and having a vertex out of a central axis of the second photoelectric conversion element; and a microlens formed over the photoelectric conversion element so as to overlap the first and second sub-lenses. ... Sk Hynix Inc

09/06/18 / #20180254285

Electronic device and method for manufacturing the same

A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.. . ... Sk Hynix Inc

09/06/18 / #20180254261

Semiconductor packages having asymmetric chip stack structure

A semiconductor package may include first chip stack including first chips which are stacked on a package substrate and offset to form a first reverse stepwise sidewall. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate and offset to form a second reverse stepwise sidewall. ... Sk Hynix Inc

09/06/18 / #20180254248

Electronic device and method for fabricating the same

An electronic device includes a semiconductor memory, wherein the semiconductor memory may include: a cell mat disposed over a substrate, the cell mat including a plurality of memory cells; an insulating layer disposed over the cell mat; a conductive pattern disposed over the insulating layer, the conductive pattern overlapping a first portion of the cell mat without overlapping a second portion of the cell mat; and a shielding layer disposed in the insulating layer, the shielding layer overlapping at least the second portion of the cell mat, the shielding layer being capable of blocking plasma. . ... Sk Hynix Inc

09/06/18 / #20180254080

Semiconductor devices

A semiconductor device may be provided. The semiconductor device may include an address input circuit and a target address generation circuit. ... Sk Hynix Inc

09/06/18 / #20180254078

Semiconductor device and method of driving the same

A semiconductor device according to an embodiment includes a plurality of memory regions suitable for performing a refresh operation based on a row address signal; an initialization circuit suitable for generating an initialization pulse signal for each refresh period during which a refresh pulse signal toggles as many times as the number of the memory regions; a control circuit suitable for activating a control pulse signal based on the refresh pulse signal and a plurality of memory address signals corresponding to the memory regions, and deactivating the control pulse signal based on the initialization pulse signal; and a row address generation circuit suitable for sequentially generating the row address signal based on the control pulse signal.. . ... Sk Hynix Inc

09/06/18 / #20180254072

Semiconductor apparatus including a sense amplifier control circuit

A semiconductor apparatus includes a sense amplifier configured to sense data transmitted through a data line and a sense amplifier control circuit configured to detect whether a level of an external voltage is equal to or larger than an reference voltage level and control a power voltage of the sense amplifier according to a detection result.. . ... Sk Hynix Inc

09/06/18 / #20180253394

Storage device, data processing system, and method for operating the storage device

A storage device may include: a protocol processing unit suitable for communicating with a host based on a predetermined protocol, and transferring a response signal to at least one status request signal that is received from the host; a power management unit suitable for supplying a power source voltage, and outputting a detection signal which represents a low voltage detection status where the power source voltage has a voltage level lower than a predetermined voltage level; and a core unit suitable for blocking a transfer of the response signal by the protocol processing unit in response to the detection signal, and processing at least one task request which is received from the host through the protocol processing unit after the blocking.. . ... Sk Hynix Inc

09/06/18 / #20180253345

Memory system and operating method thereof

A memory system comprising: a memory device including a plurality of memory dies each having a plurality of the memory blocks; and a controller suitable for performing a command operation to the memory dies, wherein the memory device comprises means for performing an error check operation to a first data provided from the controller to store the first data the memory device.. . ... Sk Hynix Inc

08/23/18 / #20180241542

Serializer, and semiconductor apparatus and system including the same

A serializer may be provided. The serializer may include a first data output circuit and a second data output circuit. ... Sk Hynix Inc

08/23/18 / #20180240973

Method for fabricating electronic device

A method for fabricating an electronic device including a semiconductor memory may include forming a buffer layer over a substrate, the buffer layer operable to aide in crystal growth of an under layer; forming the under layer over the buffer layer, the under layer operable to aide in crystal growth of a free layer; and forming a magnetic tunnel junction (mtj) structure including the free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer over the under layer.. . ... Sk Hynix Inc

08/23/18 / #20180240888

Method for manufacturing a transistor and method for manufacturing a ring oscillator using the same

In a method for manufacturing a transistor, a gate structure may be formed on a semiconductor substrate. A first material layer may be formed on the gate structure to expose an upper sidewall of the gate structure. ... Sk Hynix Inc

08/23/18 / #20180240846

Neuromorphic device including a synapse having carbon nano-tubes

A neuromorphic device is provided. The neuromorphic device may include a pre-synaptic neuron; a row line extending in a row direction from the pre-synaptic neuron; a post-synaptic neuron; a column line extending in a column direction from the post-synaptic neuron; and a synapse disposed at an intersection between the row line and the column line. ... Sk Hynix Inc

08/23/18 / #20180240826

Image sensor

An image sensor device includes a photoelectric conversion element configured to receive incident light and generate photocharges in response to the received incident light; a floating diffusion coupled to the photoelectric conversion element to store the photocharges generated by the photoelectric conversion element, the floating diffusion having a first capacitance value; a conductive pattern electrically coupled to the floating diffusion; and a variable electrode located apart from the conductive pattern by a gap, wherein the conductive pattern and the variable electrode form a variable capacitor coupled to the floating diffusion and having a second capacitance value and operable to change an effective capacitance of the floating diffusion in response to a control signal applied to the variable electrode.. . ... Sk Hynix Inc

08/23/18 / #20180240813

Semiconductor device

A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source layer; a plurality of conductive layers stacked substantially over the first source layer; channel layers that pass through the plurality of conductive layers and couple to the second source layer; and at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer.. . ... Sk Hynix Inc

08/23/18 / #20180240804

Ferroelectric memory device and method of manufacturing the same

In an embodiment, a ferroelectric memory device includes a substrate having a source region and a drain region. The ferroelectric memory device includes a ferroelectric superlattice structure disposed on the substrate and having at least two kinds of different dielectric layers alternately stacked. ... Sk Hynix Inc

08/23/18 / #20180240803

Ferroelectric memory device and method of manufacturing the same

In an embodiment, a ferroelectric memory device includes a substrate having a source region and a drain region, a ferroelectric structure disposed on the substrate, and a gate electrode layer disposed on the ferroelectric structure. The ferroelectric structure includes a ferroelectric material layer having a concentration gradient of a dopant.. ... Sk Hynix Inc

08/23/18 / #20180240528

Nonvolatile memory device, memory system including thereof and operating method thereof

A method for operating a memory system includes determining at least one erased memory cell among a plurality of erased memory cells as an unstable memory cell based on read data read from the at least one erased memory cell; determining the unstable memory cell as an unwritable memory cell based on write data to be written in the unstable memory cell; and prohibiting the plurality of erased memory cells from being used, depending on the number of erased memory cells as the unwritable memory cell among the plurality of erased memory cells.. . ... Sk Hynix Inc

08/23/18 / #20180240516

Memory system and operation method of the same

A memory system includes: a memory device; a cache memory suitable for caching a portion of a data stored in the memory device; and a read voltage controller suitable for controlling a level of a read voltage of the memory device by comparing a cache data in the cache memory with a data from the memory device corresponding to the cache data.. . ... Sk Hynix Inc

08/23/18 / #20180240506

Semiconductor memory device

A semiconductor memory device may include a memory cell array area, a peripheral area, and an interface area. The memory cell array area may include at least one memory plane. ... Sk Hynix Inc

08/23/18 / #20180240504

Semiconductor memory device having power mesh structure

A semiconductor memory device includes a peripheral circuit including a first unit circuit block and a second unit circuit block that are respectively disposed in a second region and a third region adjacent to each other in a first direction with a first region interposed therebetween, a first metal layer disposed over the peripheral circuit, a second metal layer disposed over the first metal layer, first power lines disposed in the first metal layer and suitable for transferring operating voltages to the first unit circuit block, second power lines disposed in the first metal layer and suitable for transferring the operating voltages to the second unit circuit block, and bridge power lines disposed in the second metal layer in the first region, and extending in a second direction intersecting with the first direction. The first power lines have lengths that extend from the second region to the first region, and the second power lines have lengths that extend from the third region to the first region. ... Sk Hynix Inc

08/23/18 / #20180240009

Neuromorphic device including a synapse having a variable resistor and a transistor connected in parallel with each other

A neuromorphic device may include a pre-synaptic neuron, a row line extending in a row direction from the pre-synaptic neuron, a post-synaptic neuron, a column line extending in a column direction from the post-synaptic neuron, and a synapse disposed at an intersection region between the row line and the column line. The synapse may include a first node electrically connected with the row line, a second node electrically connected with the column line, and a variable resistor and a first transistor electrically coupled between the first node and the second node. ... Sk Hynix Inc

08/23/18 / #20180239557

Nonvolatile memory device, data storage device including the same, and operating method of data storage device

A nonvolatile memory device includes a memory cell region including an external data area and an internal data area; and a control logic suitable for storing history data collected based on control signals received from an external device, in the internal data area, and controlling an operation for the external data area according to the control signals.. . ... Sk Hynix Inc

08/23/18 / #20180239548

Operating method of memory system

A method for operating a memory system includes updating, after accessing ail of one or more first memory regions included in a first list for a purpose of data storage, map data for the first memory regions; determining a list size based on a workload of the memory system, and generating a second list including one or more second memory regions depending on the list size; and accessing, after the updating of the map data, the second memory regions for a purpose of data storage.. . ... Sk Hynix Inc

08/16/18 / #20180233215

Semiconductor test device and semiconductor test method

A semiconductor test device and a semiconductor test method are disclosed. A semiconductor test device may include a dq signal receiver, a test mode register set signal processor, and a test mode command generator. ... Sk Hynix Inc

08/16/18 / #20180233214

Test apparatus and semiconductor chip

A test apparatus may be provided. The test apparatus may include a delay compensator configured to generate delayed read data by delaying read data according to a difference between an external turnaround delay value provided externally from the test apparatus and a turnaround delay detection value detected within the test apparatus. ... Sk Hynix Inc

08/16/18 / #20180233212

Semiconductor device

A semiconductor device may include a first pad configured to provide a first voltage. The semiconductor device may include a second pad. ... Sk Hynix Inc

08/16/18 / #20180233207

Memory device and method of operating the same

Provided herein are a memory device and a method of operating the memory device. The memory device comprises a plurality of memory cells stacked along a pillar vertical to a substrate, a peripheral circuit configured to program and verifying memory cells coupled to a selected word line, among the memory cells, and a control logic configured to control the peripheral circuit so that a pass voltage applied to unselected word lines is adjusted depending on a location of the selected word line when the memory cells are verified.. ... Sk Hynix Inc

08/16/18 / #20180233204

Semiconductor memory device and operating method thereof

The present disclosure relate a method of operating a semiconductor memory device including at least two memory blocks sharing one block word line. The method including applying an erase voltage to a source line commonly coupled to the memory blocks, one of which is a selected memory block and applying a first voltage to the block word line and a third voltage to a global word line of an unselected memory block of the memory blocks when the erase voltage is applied to the source line, wherein the first voltage is higher than a turn-on voltage to turn on a pass transistor coupled to the block word line, and wherein the third voltage floats a local word line included in the unselected memory block according to a level of the first voltage.. ... Sk Hynix Inc

08/16/18 / #20180233201

Memory device and method of operating the same

A memory device with a plurality of memory block may include a plurality of memory cells constituting a memory blocks, and two or more select transistors coupled to the plurality of memory cells constituting the memory block and configured to select the memory block, the two or more select transistors having different threshold voltages from one another.. . ... Sk Hynix Inc

08/16/18 / #20180233192

Semiconductor device

A semiconductor device is disclosed, which relates to a technology for a sense-amplifier (sense-amp) configured to compensate for mismatch of a sensing bit-line. The semiconductor device includes a sense-amplifier configured to selectively control connection between a pair of bit lines and a pair of sensing bit lines in response to a connection control signal in an offset compensation period, and precharge a pull-down power-supply line with a bit line precharge voltage level in the offset compensation period. ... Sk Hynix Inc

08/16/18 / #20180233187

Electronic devices and method for fabricating the same

An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer including a cofebal alloy and having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the cofebal alloy may have an al content less than 10 at %.. . ... Sk Hynix Inc

08/16/18 / #20180233184

Electronic device and method of operating the same

Provided herein may be a semiconductor memory device. The semiconductor memory device may include a memory unit configured to store the write data. ... Sk Hynix Inc

08/16/18 / #20180233179

Data output buffer

A data output buffer may be provided. The data output buffer may include a pull-up circuit configured to output a pull-up feedback signal by pull-up driving an output node. ... Sk Hynix Inc

08/16/18 / #20180233178

Sense amplifier for high speed sensing, memory apparatus and system including the same

A sense amplifier includes a current supply unit, an amplification unit, a pass transistor and a latch unit. The current supply unit may be configured to provide a sensing current to a sensing node. ... Sk Hynix Inc

08/16/18 / #20180232325

Memory system and method for operating the same

A memory system includes: a memory device for including a plurality of memory blocks each of which includes a plurality of pages, a plurality of planes each of which includes the memory blocks, and a plurality of memory dies each of which includes the planes; and a controller for grouping a plurality of read commands that are transferred from a host into one or more read command groups based on a policy that is designed in such a manner that a read operation is performed in an order from a relatively big physical area unit to a relatively small physical area unit based on a physical address value of each of the read commands, when the read commands are transferred from the host, and applying each of the read command groups to a read operation of the memory device.. . ... Sk Hynix Inc

08/16/18 / #20180232267

Memory device, memory controller and operation method thereof

An operation method of a memory controller may include: performing a preset number of write operations on a redundancy region of a memory device, reading data of the redundancy region of the memory device, and detecting error bits which occur in the data, and generating an identifier corresponding to the memory device based on the detected error bits.. . ... Sk Hynix Inc

08/16/18 / #20180232177

Memory system and operating method thereof

A memory system may include: a memory device having a plurality of blocks; and a controller suitable for performing a count operation on each of the blocks in response to a preset number of write requests, and performing a wear leveling operation based on the result of the count operation on each of the blocks.. . ... Sk Hynix Inc

08/09/18 / #20180227520

Image sensing device

An image sensing device includes pixel groups, each pixel group including two or more neighboring pixels and grouped into a same pattern; and a timing generator controlling the pixel groups based on one or more row units, wherein readout orders of first and second pixel groups arranged in different rows among the pixel groups are controlled differently, wherein the first pixel group reads out two or more pixel signals based on two or more first transmission control signals, wherein the second pixel group reads out two or more pixel signals based on two or more second transmission control signals, wherein the timing generator generates the first transmission control signals in a first order during one or more first row readout times, wherein the timing generator generates the second transmission control signals in a second order, which is different from the first order, during one or more second row readout times.. . ... Sk Hynix Inc

08/09/18 / #20180226965

Semiconductor device and system including the same

A semiconductor apparatus may be provided. The semiconductor apparatus may include a first buffer configured to generate a first preliminary clock and a first preliminary clock bar based on an external clock, an external clock bar, and a node voltage code. ... Sk Hynix Inc

08/09/18 / #20180226956

Internal clock generation circuits

An internal clock generation circuit includes an interpolation clock generation circuit and a locked clock generation circuit. The interpolation clock generation circuit generates an interpolation clock signal from a division clock signal in response to a switching control signal and a current control signal. ... Sk Hynix Inc

08/09/18 / #20180226568

Electronic devices having semiconductor magnetic memory units

A semiconductor device includes a resistance variable element including a free magnetic layer, a tunnel barrier layer and a pinned magnetic layer; and a magnetic correction layer disposed over the resistance variable element to be separated from the resistance variable element, and having a magnetization direction which is opposite to a magnetization direction of the pinned magnetic layer.. . ... Sk Hynix Inc

08/09/18 / #20180226567

Electronic device and method for fabricating the same

An electronic device may include a semiconductor memory, and the semiconductor memory may include a substrate; an interlayer dielectric layer formed over the substrate and patterned to include a contact hole; a lower contact structure formed over the substrate in the contact hole; and a variable resistance element formed over and electrically coupled to the lower contact structure, wherein the lower contact structure comprises: a spacer formed on sidewalls of the contact hole in the interlayer dielectric layer and including a material having a lower etch rate than that of silicon nitride (sin); a contact plug filling a portion of the contact hole; and a contact pad formed over the contact plug and filling a remaining portion of the contact hole.. . ... Sk Hynix Inc

08/09/18 / #20180226452

Electronic device and method for fabricating the same

An electronic device may include a semiconductor memory, and the semiconductor memory may include a variable resistance element. The variable resistance element may include a lower electrode; a spacer formed on a side surface of the lower electrode; and a variable resistance pattern disposed over the lower electrode, wherein a portion of the lower electrode covers a top surface of the spacer.. ... Sk Hynix Inc

08/09/18 / #20180226345

Fuse structure and method of manufacturing the same

A fuse structure may include an anode pattern, a cathode pattern and a connection member. The anode pattern may be formed on a semiconductor substrate. ... Sk Hynix Inc

08/09/18 / #20180226344

Fuse structure and method of manufacturing the same

A fuse structure may include an anode pattern, a cathode pattern and a connection member. The anode pattern may be formed on a semiconductor substrate. ... Sk Hynix Inc

08/09/18 / #20180226131

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device; a voltage detector suitable for detecting an operating voltage of the nonvolatile memory device; and a control unit suitable for making a first determination whether the operating voltage is dropped intentionally or unintentionally based on a first reference time and an elapsed time for which the operating voltage decreases from a first reference voltage to a second reference voltage.. . ... Sk Hynix Inc

08/09/18 / #20180226129

Method of programming semiconductor memory device

In a method of programming a semiconductor memory device, during a standby period, a standby voltage is applied to word lines coupled to a plurality of memory cells included in a selected memory cell string, and, during a first program period, a first pre-bias voltage is applied to a word line coupled to at least one of programmed memory cells of the selected memory cell string. The first pre-bias voltage is greater than the standby voltage.. ... Sk Hynix Inc

08/09/18 / #20180226119

Semiconductor device

A semiconductor device includes a period signal generation circuit and an interruption signal generation circuit. The period signal generation circuit generates a period signal in response to a refresh pulse and an end pulse. ... Sk Hynix Inc

08/09/18 / #20180226108

Electronic device and operating method thereof

According to an embodiment, a storage device may be provided. The storage device may include a semiconductor memory device, and a memory controller configured for controlling the semiconductor memory device. ... Sk Hynix Inc

08/09/18 / #20180225566

Neuromorphic device including a synapse having a plurality of synapse cells

A neuromorphic device is provided. The neuromorphic device may include a plurality of pre-synaptic neuron circuits, a plurality of post-synaptic neuron circuits, and a plurality of synapses. ... Sk Hynix Inc

08/09/18 / #20180225234

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device; a power management unit suitable for outputting first and second low voltage detection signals, each low voltage detection signal representing a voltage level of a source voltage equal to or lower than a predetermined reference voltage level; and a processor suitable for computing a detection interval between the first low voltage detection signal and the second low voltage detection signal before the first low voltage detection signal, comparing the computed detection interval and a predetermined threshold detection interval, and determining a subject to manage performing of a recovery operation according to low voltage generation based on a comparison result.. . ... Sk Hynix Inc

08/09/18 / #20180225220

Memory device and method of operating the same

A memory device and a method of operating the same. The memory device may include a memory block including a plurality of pages, and a control logic configured to include at least one register in which a plurality of program algorithms and a plurality of pieces of operation information are stored, select any one of the program algorithms in response to an address of a program target page, among the pages, and perform a program operation on the program target page based on the selected program algorithm and operation information corresponding to the selected program algorithm.. ... Sk Hynix Inc

08/09/18 / #20180225200

Operating method of data storage device

A method for operating a data storage device includes storing an erase count corresponding to a physical address, as a reference value, in response to a first event; comparing a current value of the erase count with the reference value in response to a second event; and selectively performing a purge operation for the physical address, depending on a result of the comparing.. . ... Sk Hynix Inc

08/09/18 / #20180225199

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device; and a controller suitable for setting a termination condition of a garbage collection operation based on an over-provisioning ratio of the nonvolatile memory device, performing the garbage collection operation, and terminating the garbage collection operation according to the termination condition.. . ... Sk Hynix Inc

08/09/18 / #20180225185

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device including a memory block having a plurality of memory regions; and a controller suitable for searching a first memory region for which error correction is passed, by scanning the plurality of memory regions in a reverse order of a write sequence for the memory block, determining a target memory region in the memory block based on data stored in the first memory region, and performing a recovery operation for the target memory region.. . ... Sk Hynix Inc

08/09/18 / #20180225173

Memory systems having extended product lifetime and methods of operating the same

A memory system includes a first memory device, a second memory device, and a controller. The second memory device has a write endurance which is higher than a write endurance of the first memory device. ... Sk Hynix Inc

08/09/18 / #20180225151

Data storage device and operating method thereof

A method for operating a data storage device includes determining a first weight based on the sum of data sizes for commands queued in a command queue; determining a second weight by summing weights by types of the commands; and controlling an urgent command selection threshold value for selecting an urgent command existing in the command queue, based on at least one of the first weight and the second weight.. . ... Sk Hynix Inc

08/09/18 / #20180225060

Memory system

A memory system includes a memory controller, a first memory module including first and second groups of first memory chips, a second memory module including first and second groups of second memory chips, and a channel including a first group of signal lines suitable for coupling the memory controller with the first memory module, and a second group of signal lines suitable for coupling the memory controller with the second memory module.. . ... Sk Hynix Inc

08/02/18 / #20180219572

Semiconductor device

A semiconductor device includes a plurality of chips, at least one line, and a controller. Each of the chips includes a chip input/output (i/o) pad, a transceiver configured to perform a transmission operation in response to a transmission enable signal or perform a reception operation in response to a reception enable signal, and a switch configured to couple the chip input/output (i/o) pad to the transceiver in response to a switch enable signal. ... Sk Hynix Inc

08/02/18 / #20180219537

Electronic device

An electronic device may include a ramp signal generator suitable for generating a ramp signal having a slope corresponding to an analog gain, and a slope correction circuit suitable for correcting the slope based on a correction code signal.. . ... Sk Hynix Inc

08/02/18 / #20180219023

Semiconductor memory device including a slit

A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block.. . ... Sk Hynix Inc

08/02/18 / #20180218945

Electronic device and method for fabricating the same

A semiconductor device may include: a plurality of first contacts arranged at a predetermined distance in a first direction and a second direction crossing the first direction; a plurality of second contacts alternately arranged between the first contacts and arranged at a predetermined distance in the first direction and the second direction; a plurality of dog bone-type conductive lines connected to the second contacts arranged in the second direction, respectively, among the plurality of second contacts, and having concave parts and convex parts; and a plurality of etching prevention patterns formed over the plurality of conductive lines so as to overlap the conductive lines, respectively.. . ... Sk Hynix Inc

08/02/18 / #20180218777

Memory apparatus relating to determination of a failed region and test method thereof, memory module and system using the same

A memory device may be provided. The memory device may include a test data output circuit configured to compare lower data output from a lower data storage region with upper data output from an upper data storage region and make a decision. ... Sk Hynix Inc

08/02/18 / #20180218776

Integrated circuits

An integrated circuit including semiconductor devices may be provided. The semiconductor device may be configured to compare phases of strobe signals which are generated according to internal delay times of the semiconductor devices and configured to control points of time that an internal command is inputted to the internal circuits of the semiconductor devices according to a comparison result of the phases of the strobe signals.. ... Sk Hynix Inc

08/02/18 / #20180217928

Data storage device and operating method thereof

A method for operating a data storage device includes determining an nth garbage collection throughput by multiplying a rate of a number of used pages of an open memory block to an amount of write data to be processed to a sum of the number of used empty memory blocks and an immediately previous garbage collection throughput average value; and performing a garbage collection operation based on the nth garbage collection throughput.. . ... Sk Hynix Inc

08/02/18 / #20180217895

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of memory blocks each having a plurality of sub memory blocks; and a controller suitable for performing an error correction operation to the memory blocks during a read operation to the memory blocks, updating a characteristic list for the memory blocks at each error correction operation to the memory blocks, classifying the memory blocks and the sub memory blocks according to the updated values in the characteristic list, and performing a program operation to the memory blocks according to the classification.. . ... Sk Hynix Inc

08/02/18 / #20180217894

Memory module, memory system including the same, and error correcting method thereof

An error correcting method of a memory system may include: reading read data and an error correction code from a plurality of memory chips; correcting an error of the read data using the error correction code; temporarily storing the read data and the error correction code in a buffer when the correcting of the error fails; writing a certain input test pattern in the plurality of memory chips, reading an output test pattern written in the plurality of memory chips, and detecting a fail chip in which a chipkill occurs; recorrecting, based on a location of the detected fall chip, the error of the read data stored in the buffer using the error correction code stored in the buffer; and rewriting error-corrected read data and the error correction code in the plurality of memory chips.. . ... Sk Hynix Inc

08/02/18 / #20180217785

Data storage device

A data storage device includes a nonvolatile memory device; and a controller suitable for controlling the nonvolatile memory device through a command, the controller comprising a memory controller including a queue which includes multiple slots, each of the multiple slots being mapped to one type among a plurality of types of the command, and suitable for processing a descriptor for the command enqueued to the queue to generate the command; and a processor suitable for requesting one slot of the multiple slots mapped to one type among the plurality of types of the command, to the memory controller, and enqueuing, when allocated with the one slot, the descriptor for the command, to the one slot.. . ... Sk Hynix Inc

08/02/18 / #20180217761

Data storage device and operating method thereof

A data storage device includes a storage medium including a plurality of logical units; and a controller suitable for accessing the storage medium by logical unit, the controller comprising: a first processor suitable for aligning tasks corresponding to at least one logical unit among the plurality of logical units, depending on a priority; and a second processor suitable for accessing other logical units among the plurality of logical units, wherein the first processor entrusts a task alignment operation for the other logical units, to the second processor, based on workloads of the first and second processors.. . ... Sk Hynix Inc

08/02/18 / #20180217754

Memory system and operating method thereof

A memory system may include: a plurality of memory dies; and a controller suitable for identifying a dependency between first and second commands and a priority order of the first and the second commands through a check engine, and control the memory dies to sequentially perform first and second command operations in response to the first and second commands according to the dependency and the priority order.. . ... Sk Hynix Inc

07/26/18 / #20180213168

Unit pixel apparatus with noise reduction function, operation method thereof, and cmos image sensor using the same

A unit pixel apparatus includes a unit pixel suitable for supporting initialization an output node and outputting a pixel signal corresponding to incident light through the output node; and a switching block suitable for initializing the output node and deciding an initial voltage of the output node.. . ... Sk Hynix Inc

07/26/18 / #20180212623

Controller and operating method thereof

A controller includes a processor suitable for determining whether to store further data corresponding to a command from a host into a first region in a main memory of the host when receiving the command from the host, requesting the host to store the further data corresponding to the command into the first region of the main memory when the first region is determined to store the further data corresponding to the command; and an error correction code unit suitable for encoding the further data stored in the first region in response to the storage request. The processor may control a memory device to store the encoded data.. ... Sk Hynix Inc

07/26/18 / #20180212621

Semiconductor device

Disclosed may be a repair information storage circuit. The repair information storage circuit may include a fuse set. ... Sk Hynix Inc

07/26/18 / #20180212597

Input buffer circuit

An input buffer circuit is disclosed, which relates to a technology for a receiver circuit including a plurality of input buffers having different characteristics. The input buffer circuit includes a first buffer configured to output a first input signal by buffering a command address received based on a flag signal, a second buffer configured to output a second input signal by buffering the command address based on the flag signal, a first delay matching circuit configured to output a first matching signal by delaying the first input signal by a first delay time, a second delay matching circuit configured to output a second matching signal by delaying the second input signal by a second delay time, and a selection circuit configured to select any one of the first matching signal and the second matching signal based on a selection signal.. ... Sk Hynix Inc

07/26/18 / #20180211994

Electronic device and method for fabricating the same

An electronic device including a semiconductor memory is provided. The semiconductor memory may include an mtj (magnetic tunnel junction) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer formed under the mtj structure, wherein the under layer may include metals and oxides of the metals.. ... Sk Hynix Inc

07/26/18 / #20180211913

Cross-point array device including conductive fuse material layer

A cross-point array device includes a pillar-shaped structure disposed in an intersection region where a first conductive line overlaps a second conductive line. The pillar-shaped structure includes a resistance change material layer disposed between the first conductive line and the second conductive line. ... Sk Hynix Inc

07/26/18 / #20180211696

Semiconductor systems performing double-write operations and methods of operating the same

A semiconductor system includes a controller. The controller is configured to have a write buffer that stores first write data outputted from a host before the first write data is written into a memory circuit. ... Sk Hynix Inc

07/26/18 / #20180211694

Memory module

A memory module includes a front side interface configured to serial-to-parallel convert a command, an address, and data, based on a host clock, and transfer the converted command, address, and data; a processing block configured to operate in synchronization with a division clock, process the command, address, and data transferred from the front side interface, and transfer the processed command, address, and data; a back side interface configured to include a pll for generating a media clock having a frequency different from the host clock, to parallel-to-serial convert the command, address, and data transferred from the processing block, based on the media clock, and to transfer the converted command, address, and data; and memory devices configured to operate in synchronization with the media clock, and to write the data transferred from the back side interface therein in response to the command and address transferred from the back side interface.. . ... Sk Hynix Inc

07/26/18 / #20180210826

Memory device, memory system, and operation method thereof

A memory device is provided. The memory device includes a plurality of normal memory blocks; and at least two or more bad memory blocks, wherein data having the same number of bits as data to be stored in a normal memory block and a parity code having the number of bits at least twice greater than that of a parity code to be stored in the normal memory block are stored in a first bad memory block and a second bad memory block among the bad memory blocks.. ... Sk Hynix Inc

07/26/18 / #20180210789

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of pages for storing data and a plurality of memory blocks including the pages; and a controller configured to read data, which corresponds to a read command received from a host, from the pages, perform bit flipping with respect to a plurality of constituent codes for the read data, and perform an error correction operation, the bit flipping is updated corresponding to a number of error correction bits in the constituent codes.. . ... Sk Hynix Inc

07/26/18 / #20180210786

Memory systems and electronic systems performing an adaptive error correction operation with pre-checked error rate, and methods of operating the memory systems

A memory system may include a test vector generator configured for generating a test vector to be written into a memory device, a data discrepancy checker configured for comparing read data outputted from the memory device with the test vector to generate an information signal corresponding to a comparison between the read data and the test vector, an error correction code (ecc) controller configured for performing an ecc encoding operation and an ecc decoding operation according to any one among a plurality of ecc levels based on a control signal, and a memory controller controlling the test vector generator, the data discrepancy checker and the ecc controller. The memory controller configured to transmit the control signal corresponding to an error rate of the memory device to the ecc controller, based on the information signal generated by the data discrepancy checker.. ... Sk Hynix Inc

07/26/18 / #20180210669

Memory system

A memory system includes: a non-volatile memory device for including a first storage region and a second storage region; and a controller for including first and second interfaces for inputting/outputting a data to/from a host, inputting/outputting a first data of the first storage region through the first interface, and inputting/outputting a second data of the second storage region through the second interface, wherein when the first data is programmed in the first storage region, the controller detects a value of the first data, selectively inverts the value of the first data based on the detection result, and program a resultant value, and when the second data is programmed in the second storage region, the controller detects a state of the second storage region where the second data is programmed, selectively inverts a value of the second data based on the state detection result, and program a resultant value.. . ... Sk Hynix Inc

07/26/18 / #20180210352

Methods of forming imprint patterns

A method of forming patterns is provided. The method may include forming a resist layer on a substrate and curing an extrusion confining pattern to define anchoring regions in the resist layer. ... Sk Hynix Inc

07/19/18 / #20180205377

Impedance calibration circuit and semiconductor apparatus including the same

An impedance calibration circuit includes a first detection unit configured to generate a first pull-up impedance detection signal according to a resistance value of an internal reference resistor, a second detection unit configured to generate a second pull-up impedance detection signal according to a resistance value of an external reference resistor coupled to an external reference resistor pad, a switching unit configured to select the first pull-up impedance detection signal or the second pull-up impedance detection signal according to the internal impedance calibration enable signal and output the selected pull-up impedance detection signal, and an impedance calibration signal generation unit configured to generate a plurality of impedance calibration signals according to an output of the switching unit.. . ... Sk Hynix Inc

07/19/18 / #20180204961

Image sensor having light refractive patterns

An image sensor is provided. The image sensor may include a photodiode formed in a substrate; a light refraction pattern formed on the photodiode; a color filter covering the light refraction pattern; and a micro-lens formed on the color filter.. ... Sk Hynix Inc

07/19/18 / #20180204850

Semiconductor device and manufacturing method of the same

A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.. . ... Sk Hynix Inc

07/19/18 / #20180204629

Input/output terminal characteristic calibration circuit and semiconductor apparatus including the same

An input/output terminal characteristic calibration circuit may include a plurality of input/output terminals a subset of which is configured to partially and selectively receive a characteristic calibration signal according to an external input, such that characteristics of the input/output terminals corresponding to the characteristic calibration signal are calibrated. The input/output terminal characteristic calibration circuit may also include a characteristic calibration signal generation circuit coupled to the plurality of input/output terminals in common through a test signal line, and configured to provide the characteristic calibration signal to the plurality of input/output terminals in common through the test signal line.. ... Sk Hynix Inc

07/19/18 / #20180204605

Semiconductor devices

A semiconductor device includes a latch signal generation circuit latching an external signal in synchronization with an internal clock signal to generate a latch signal, a test pulse generation circuit buffering the internal clock signal according to the latch signal to generate a test pulse signal, and a test period signal generation circuit generating a test period signal which is enabled, in response to a pulse of the test pulse signal, to execute a predetermined function.. . ... Sk Hynix Inc

07/19/18 / #20180203816

System including hot plug module and memory module

A system may include a host and a hot plug module. The hot plug module may include a training memory for performing a training operation with the host. ... Sk Hynix Inc

07/19/18 / #20180203775

Memory module, memory system including the same and operation method thereof

A memory module may include a first memory module comprising a plurality of first memory devices each having an extra memory region, a second memory module comprising a plurality of second memory devices each having an extra memory region, and a control logic suitable for writing/reading data to/from the first memory devices, wherein the control logic writes/reads target data to be transferred to/from a third memory device having an error among the first memory devices, to/from the extra memory regions of the second memory devices.. . ... Sk Hynix Inc

07/19/18 / #20180203760

Memory system and operation method thereof

A memory system may include: a nonvolatile memory device comprising a plurality of memory blocks; and a controller suitable for checking a read operation time, a read level class, an error occurrence, and an error occurrence class when performing the read operation on each of the memory blocks, classifying the memory blocks into various classes based on a result of the checking, and differently setting a durability parameter for each of the memory blocks based on a result of the classifying of the memory blocks.. . ... Sk Hynix Inc

07/19/18 / #20180203621

Semiconductor apparatus, memory module and operation method thereof

A memory module may be provided. The memory module may include a normal memory device, a spare memory device, and a row hammering determination circuit. ... Sk Hynix Inc

07/19/18 / #20180203616

Nonvolatile memory device and operating method thereof

A memory device may include a memory cell array having a plurality of memory cells, and a controller suitable for reading data of a memory cell corresponding to an address of write data, among the memory cells, and comparing the write data and the read data to check specific bits different from corresponding bits of the read data, among a plurality of bits of the write data, according to a write operation request. The controller may output a check result to outside after a preset time from the write operation request.. ... Sk Hynix Inc

07/12/18 / #20180198470

Operating method of memory system

An operating method of a memory system includes: reading a first data from a particular data group among a plurality of data groups included in a memory device; performing a first error correction code (ecc) decoding for the first data; when the first ecc decoding fails, reading a plurality of the remaining data other than the first data from the particular data group; performing a second ecc decoding for the plurality of the remaining data; when the second ecc decoding fails, identifying data, to which the second ecc decoding fails, among the plurality of the remaining data; obtaining first and second soft read values respectively corresponding to the first data, to which the first ecc decoding fails, and the second data, to which the second ecc decoding fails; determining reliability of the first and second data based on the first and second soft read values; and correcting the first data based on the reliability of the first and second data.. . ... Sk Hynix Inc

07/12/18 / #20180198468

Error correction code (ecc) decoders sharing logic operations, memory controllers including the error correction code decoders, and methods of decoding error correction codes

An error correction code (ecc) decoder includes a finite state machine (fsm) controller and a shared logic circuit. The fsm controller generates a first control signal and a second control signal each corresponding to a certain state. ... Sk Hynix Inc

07/12/18 / #20180197968

Nonvolatile storage circuit and semiconductor memory device including the same

A nonvolatile storage circuit may include a nonvolatile storage unit configured to include fuse set groups respectively including a plurality of fuse sets and a flag fuse; a rupture control unit configured to program an input address to the fuse sets in a first program mode, and to program a same input address to a specific fuse set among the plurality of fuse sets in a specific fuse set group among the fuse set groups and to program the flag fuse of the specific fuse set group in a second program mode; and a boot-up control unit configured to control the address programmed in the fuse sets to be outputted as fuse data, and to control the address programmed in the specific fuse set to be outputted as fuse data of remaining fuse sets among the plurality of fuse sets in the specific fuse set group.. . ... Sk Hynix Inc

07/12/18 / #20180197967

Nonvolatile memory device including multiple planes

A nonvolatile memory device includes bit lines arranged in a first direction over a substrate; a memory cell array disposed between the substrate and the bit lines, and including a plurality of planes which are arranged in a second direction perpendicular to the first direction; page buffer circuits disposed between the substrate and the memory cell array; contact pads disposed between the substrate and the memory cell array, the contact pads being suitable for electrically coupling the bit lines and the page buffer circuits; and routing lines disposed at the same layer as the contact pads, and extending in the second direction, wherein the contact pads are disposed to overlap with at least two lines which are arranged in the second direction, and the routing lines are formed in a bent pattern to pass between the contact pads which are disposed to overlap with different lines.. . ... Sk Hynix Inc

07/12/18 / #20180197880

Multi-level ferroelectric memory device and method of manufacturing the same

A ferroelectric memory device may include a semiconductor substrate, a plurality of ferroelectric layers, a source, a drain and a gate. The semiconductor substrate may have a recess. ... Sk Hynix Inc

07/12/18 / #20180197879

Multi-level ferroelectric memory device and method of manufacturing the same

A ferroelectric memory device may include a semiconductor substrate, a plurality of ferroelectric layers, a source, a drain and a gate. The semiconductor substrate may have a recess. ... Sk Hynix Inc

07/12/18 / #20180197866

Semiconductor device having buried gate structure and method for manufacturing the same, memory cell having the same and electronic device having the same

A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer.. . ... Sk Hynix Inc

07/12/18 / #20180197621

E-fuse circuit

An electrical fuse (e-fuse) circuit is disclosed, which relates to a technology for processing a failed part of the e-fuse circuit. The e-fuse circuit may be configured to detect failed data and or store a failed address.. ... Sk Hynix Inc

07/12/18 / #20180197597

Semiconductor devices

A semiconductor device may be provided. The semiconductor device may include an error scrub control circuit and or an active period signal generation circuit. ... Sk Hynix Inc

07/12/18 / #20180197590

Semiconductor device

Disclosed is a semiconductor device, including a memory cell array including a plurality of memory cells, a read circuit suitable for generating read data corresponding to a read current flowing in a first direction through a selected memory cell of the plurality of memory cells, a reverse read control circuit suitable for generating a reverse read control signal corresponding to the read data, and a reverse current generation circuit suitable for generating a reverse current flowing in a second direction through the selected memory cell in response to the reverse read control signal.. . ... Sk Hynix Inc

07/12/18 / #20180197587

Semiconductor device and operating method thereof

A semiconductor memory device may include a memory cell array. The semiconductor memory device may include a peripheral circuit coupled to the memory cell array through word lines. ... Sk Hynix Inc

07/12/18 / #20180196756

Address mapping method of memory system

Disclosed is an address mapping method of a memory system. The address mapping method may include grouping adjacent memory cells into multiple cubes, from a plurality of memory cells respectively located at intersections of a plurality of row lines and a plurality of column lines; allocating most significant bit (msb) n bits of a physical address for identifying the cubes; allocating least significant bit (lsb) m bits of the physical address for designating locations of memory cells included in each of the cubes, m and n being positive integers; storing information about a mapping between a logical address and the (m+n)-bit physical address in a mapping table; and when the logical address in response to an external request is received, translating the logical address to the physical address based on the mapping table.. ... Sk Hynix Inc

07/12/18 / #20180196749

Memory system and operating method of the same

An memory system includes a memory device that includes a first memory block and a super memory block including simultaneously controllable second memory blocks and a controller including a memory, and suitable for storing a data corresponding to a command in the memory, deciding a type of the command and a type of the data, and controlling the memory device to write the data in the first memory block or the super memory block based on the type of the command and the type of the data.. . ... Sk Hynix Inc

07/12/18 / #20180196713

Semiconductor device

A semiconductor device includes a write read control circuit for outputting a write enable signal which is enabled in response to a write command, and a test mode signal; and an error correction circuit suitable for performing a calculation operation of determining an error information of input data in response to the write enable signal and then outputting an internal parity signal including the error information, and outputting internal data by delaying the input data in response to the write enable signal.. . ... Sk Hynix Inc

07/12/18 / #20180196712

Apparatuses and methods for correcting errors and memory controllers including the apparatuses for correcting errors

An error correction apparatus may be provided. The error correction apparatus may be configured to perform a scrambling operation before an error correction code (ecc) operation is performed.. ... Sk Hynix Inc

07/12/18 / #20180196621

Memory module, memory system and operating method of memory system

An operating method of memory system may include: transmitting a write command from a memory controller to a memory module; transmitting write data corresponding to the write command from the memory controller to the memory module; generating compressed data by compressing the write data in the memory module; writing the compressed data to one or more memory devices in the memory module; and transmitting unused r memory capacity information on the memory module to the memory controller from the memory module.. . ... Sk Hynix Inc

07/12/18 / #20180196620

Data storage device and operating method thereof

A data storage device includes a plurality of nonvolatile memory devices; and a controller suitable for determining a write sequence for the nonvolatile memory devices, based on respective write times of the nonvolatile memory devices, and transmitting write commands sequentially in an interleaving manner to the nonvolatile memory devices according to the write sequence.. . ... Sk Hynix Inc

07/12/18 / #20180196616

Memory device and memory module

A memory device may be provided. The memory device may include a plurality of memory banks, an at least one spare bank. ... Sk Hynix Inc

07/12/18 / #20180196602

Data storage device and data processing system including the same

A data storage device includes a controller suitable for updating a first pointer based on a command inputted to a first queue included in a host device, and updating a second pointer based on a command execution completion report inputted to a second queue included in the host device, wherein the controller determines whether it is in an idle state based on the first pointer and the second pointer.. . ... Sk Hynix Inc

07/12/18 / #20180196464

Semiconductor device

A semiconductor device includes a detection signal generation circuit generating a detection signal by detecting a phase difference of an input signal and an internal clock, and generating delayed input signals by delaying the input signal. The semiconductor device further includes an output enable signal generation circuit outputting an output enable signal by selecting one of the delayed input signals in response to the detection signal and latching the selected one of the delayed input signals in synchronization with the internal clock. ... Sk Hynix Inc

07/05/18 / #20180191971

Analog-to-digital converter and analog-to-digital conversion method

An analog-to-digital conversion method may include: generating an initial comparison signal by storing adjacent pixel signals and comparing the adjacent pixel signals, and generating a first control signal based on the generated initial comparison signal; generating a reference comparison signal by comparing the adjacent pixel signals based on the reference signal and a ramp-up signal switched according to the generated first control signal, and determining a ramping direction according to the generated reference comparison signal and generating a second control signal; and performing data conversion by selecting any one of the ramp-up signal and a ramp-down signal according to the generated second control signal, and by comparing the selected ramp signal with a ‘difference value between the adjacent pixel signals’.. . ... Sk Hynix Inc

07/05/18 / #20180191373

Error correction method of data storage device

An error correction code processing method includes performing a first encoding operation for a data group of a first direction; performing a second encoding operation for a data group of a second direction, wherein the data group of the first direction shares one or more data with the data group of the second direction; performing a first decoding operation of correcting an error included in the data group of the first direction; and performing a second decoding operation of correcting an error included in the data group of the second direction when the first decoding operation fails.. . ... Sk Hynix Inc

07/05/18 / #20180190498

Memory device and method of operating the same

Provided herein may be a memory device and a method of operating the same. The memory device may include a memory block including a plurality of pages, and peripheral circuits configured to sequentially program the pages. ... Sk Hynix Inc

07/05/18 / #20180190366

Semiconductor memory device and operating method thereof

A semiconductor memory device may include a memory core unit including a plurality of memory cells suitable for storing data, an error correction code (ecc) control unit suitable for detecting an error of the data to output a flag signal corresponding to a result of detection of the error, and an address control unit suitable for adjusting a refresh interval of at least one memory cell that stores data in which the error is detected, or repairing the memory cell among the memory cells, in response to the flag signal.. . ... Sk Hynix Inc

07/05/18 / #20180190358

Semiconductor memory device and method of operating the same

There may be provided a semiconductor memory device including a memory cell array, an erase count storage unit, and a control logic. The memory cell array may include a plurality of memory blocks. ... Sk Hynix Inc

07/05/18 / #20180190356

Semiconductor memory device and method of operating the same

Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a plurality of pages each including a plurality of memory cells, peripheral circuits configured to perform a program operation of a selected page among the plurality of pages and a control logic configured to control the peripheral circuits such that a main program operation is performed on the selected page and, when the main program operation is completed, a compensation program operation is performed on memory cells having lower threshold voltage retention characteristics compared to remaining memory cells, among the memory cells included in the selected page.. ... Sk Hynix Inc

07/05/18 / #20180190355

Semiconductor memory device and operating method thereof

A semiconductor memory device including a memory cell array including a plurality of memory blocks, a voltage generator applying operation voltages to a selected memory block, among the plurality of memory blocks, a control logic generating converted data by converting data bit sets respectively corresponding to at least one set of program states among a plurality of program states, during a program operation, and a read and write circuit temporarily storing the converted data and performing a program operation by controlling potential levels of bit lines of the memory cell array in accordance with stored converted data.. . ... Sk Hynix Inc

07/05/18 / #20180190354

Semiconductor device, operating method thereof and memory system

A method for operating a semiconductor device includes activating a first selection line coupled to a selected first memory string and deactivating a second selection line coupled to an unselected second memory string, applying a read voltage to a selected word line and a pass voltage to an unselected word line, and equalizing the selected word line and the unselected word line, wherein the second selection line is turned on during the equalizing of the selected and unselected word lines.. . ... Sk Hynix Inc

07/05/18 / #20180190330

Memory module capable of measuring temperature and system using the same

A memory module may be provided. The memory module may include a thermocouple and a temperature sensor. ... Sk Hynix Inc

07/05/18 / #20180189200

Memory system and operation method of the same

A memory system includes memory devices sharing a data bus and a control bus and controlling the memory devices through the control bus, wherein the memory devices have different latencies each other, and a controller transceiving a data with the memory devices through the data bus, wherein the controller may transceive a data with the memory devices during a time corresponding to a data burst length for a moment being the each latencies of the memory devices after transmitting same control signals to the memory devices.. . ... Sk Hynix Inc

07/05/18 / #20180189172

Data storage apparatus and operating method thereof

A data storage apparatus includes a nonvolatile memory device, a random-access memory including an address mapping table configured to store mapping information between a logical address received from a host apparatus and a physical address for the nonvolatile memory device, and a processor configured to generate a modified write logical address by changing a value of a specific bit among bits of a write logical address when a write request is received from the host apparatus, and store the modified write logical address in the address mapping table.. . ... Sk Hynix Inc

07/05/18 / #20180189153

Memory apparatus, memory module and semiconductor system capable of dynamic mirroring

A semiconductor system may include a host, a memory controller and a memory apparatus. The host may generate a mirror request when a program requiring a mirroring operation is executed. ... Sk Hynix Inc

07/05/18 / #20180189134

Semiconductor device

A semiconductor device includes a delay selection signal generation circuit, an internal read signal generation circuit, and an internal write signal generation circuit. The delay selection signal generation circuit generates a delay selection signal in response to an information code signal. ... Sk Hynix Inc

07/05/18 / #20180188962

Controller and operation method thereof

A controller includes a memory suitable for storing first data read from first memory blocks of a first super memory block included in a memory device; a rearranging unit suitable for rearranging the first data stored in the memory based on sequence-information of the first data stored in the memory; and a processor suitable for controlling the memory device to write the rearranged first data in a second super memory block of the memory device.. . ... Sk Hynix Inc

07/05/18 / #20180188958

Control logic, semiconductor memory device, and operating method

Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.. . ... Sk Hynix Inc

07/05/18 / #20180188957

Operating methods of nonvolatile memory device and data storage device including the same

A method for operating a data storage device including a nonvolatile memory device and a controller which controls the nonvolatile memory device includes the controller transmitting to the nonvolatile memory device one of a command, an address, seed data and data via a input/output line and first, second and third control signals via corresponding signal lines; and the nonvolatile memory device receiving any one of the transmitted command, the address, the seed data and the data depending on at least two of the first, second and third control signals.. . ... Sk Hynix Inc

06/28/18 / #20180183630

Receiving circuit, and semiconductor device and system configured to use the receiving circuit

A receiving circuit may include a decision feedback equalizer circuit and buffer. The buffer may be configured to receive an external signal and to generate an input signal. ... Sk Hynix Inc

06/28/18 / #20180183474

Symbol interference cancellation circuit and system including the same

A symbol interference cancellation circuit may include a ctle (continuous time linear equalizer) configured for cancelling a first post cursor component of an input signal according to a first weight application signal, and generating a pre-interference-cancelled signal; an interference cancellation circuit configured for cancelling second to fourth post cursor components of the pre-interference-cancelled signal according to second to fourth weight application signals, a sampling signal and output signals of shift registers, and generating an interference-cancelled signal; a sampling circuit configured for sampling the interference-cancelled signal based on a clock signal, and outputting the sampled interference-cancelled signal as the sampling signal; and the shift registers configured for shifting the sampling signal by a predetermined cycle of a clock bar signal which has a phase opposite to the clock signal, shifting the sampling signal by a predetermined cycle of the clock signal, and thereby providing shifted signals to the interference cancellation circuit.. . ... Sk Hynix Inc

06/28/18 / #20180183408

Common signal attenuation circuit and ramp signal generator using the same

A common signal attenuation circuit may include a sensing block suitable for sensing differential signals to generate sensed differential signals; a common signal generation block suitable for generating an common signal having a common voltage noise by combining the sensed differential signals; and an attenuation block suitable for adjusting the common voltage noise in the original common signal by combining the common signal having the adjusted common voltage noise to the differential signals.. . ... Sk Hynix Inc

06/28/18 / #20180183328

Charge pump circuit and voltage generating device including the same

A charge pump circuit may include: input units suitable for receiving a first input pulse signals and outputting second input pulse signals that are out of phase; an internal voltage generation unit suitable for generating an internal voltage by performing a voltage pumping operation in response to an external voltage and the second input pulse signals, and adjusting a well bias voltage at a power-up period and a normal operation period after the power-up period, in response to a switching control signal; and a switching control signal generation unit suitable for generating the switching control signal which is activated differently on the power-up period and the normal operation period.. . ... Sk Hynix Inc

06/28/18 / #20180182956

Electronic device and method for fabricating the same

An electronic device including a semiconductor memory. The semiconductor memory may include a variable resistance element. ... Sk Hynix Inc

06/28/18 / #20180182861

Semiconductor device and method for fabricating the same

A method for fabricating a semiconductor device includes: forming a semiconductor structure including a pattern; forming an epitaxial layer having a first dopant concentration in the pattern; forming in-situ an interface layer having a second dopant concentration higher than the first dopant concentration, over the epitaxial layer; forming a metal silicide layer over the interface layer; and forming a metal plug over the metal silicide layer.. . ... Sk Hynix Inc

06/28/18 / #20180182722

Semiconductor memory device including a dummy word line

A semiconductor memory device having dummy word lines is disclosed. In the semiconductor memory device, a number of dummy word lines are arranged at both ends of a cell mat.. ... Sk Hynix Inc

06/28/18 / #20180182468

Electronic device

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a plurality of first lines; a plurality of second lines; a plurality of memory cells disposed in respective intersection regions between the plurality of first lines and the plurality of second lines; a first test circuit configured to apply a stress pulse to a first selection line coupled to a defective memory cell among the plurality of memory cells during a first test period, in response to a first test control signal, the first selection line including any one of the plurality of first lines; and a control unit configured to generate the first test control signal based on a first test mode signal.. ... Sk Hynix Inc

06/28/18 / #20180182461

Semiconductor device and operating method thereof

A semiconductor device and or method of operating the same may be provided. The semiconductor device may include a pass circuit unit configured to connect global signal lines to signal lines to set voltage levels of the signal lines.. ... Sk Hynix Inc

06/28/18 / #20180182452

Memory system and operating method of memory system

A memory system may include: a memory device including a plurality of memory dies and suitable for performing, in the plurality of memory dies, command operations; and a controller suitable for: dividing sub-jobs of a command job corresponding to the command operations on a logical unit size basis; queuing the divided sub-jobs; and performing the queued sub-jobs to the memory dies with variable operating energy levels and operating clocks. The controller may monitor a status and a job load for at least one queued sub-job while performing the at least one queued sub-job to the memory dies, and interactively and dynamically adjusts an energy level and an operating clock for the at least one queued sub-job according to a result of the monitoring.. ... Sk Hynix Inc

06/28/18 / #20180182448

Sub word line driver of semiconductor memory device

A layout structure of a sub word line of a semiconductor memory device is disclosed. A sub word line driver of a semiconductor memory device includes: a plurality of first active regions arranged in a line shape in a first direction; a plurality of second active regions spaced apart from the plurality of first active regions a predetermined distance in a second direction, and arranged in a line shape in the first direction; a first main word line disposed over the first active regions, and formed in a diagonal direction in the first active regions; a second main word line disposed over the second active regions, and formed in a diagonal direction in the second active regions; and a pickup active region disposed between the first main word line and the second main word line.. ... Sk Hynix Inc

06/28/18 / #20180182447

Semiconductor memory apparatus

A semiconductor memory apparatus includes a driving voltage providing circuit suitable for selectively providing a first driving voltage, a second driving voltage, a third driving voltage, a ground voltage, and a precharge voltage to a first driving line and a second driving line in response to an active signal, a cell characteristic information signal, and a precharge signal. The semiconductor memory apparatus also includes a sense amplifier suitable for operating by being applied with voltages provided from the first and second driving lines.. ... Sk Hynix Inc

06/28/18 / #20180182445

Memory device, memory system including the same, and operation method thereof

A memory device may include first and second latch sections configured to respectively store a target address and a recent input address, a comparison unit configured to compare an input address with the target address and the recent input address respectively stored in the first and second latch sections, and output a resultant signal, a counting section configured to increase a count corresponding to the recent address stored in the second latch section in response to the resultant signal, and a control unit configured to check the count of the counting section and update the input address to the second latch section in response to the resultant signal.. . ... Sk Hynix Inc

06/28/18 / #20180182442

Semiconductor memory device

According to one embodiment, a semiconductor memory device comprises a first bank and a second bank. Each of the first bank and the second bank comprises a memory cell having a variable resistor element, a reference cell, a sense amplifier having a first input terminal electrically coupled to the memory cell and a second input terminal electrically coupled to the reference cell, and a first transistor electrically coupling the memory cell and the first input terminal of the sense amplifier. ... Sk Hynix Inc

06/28/18 / #20180182441

Semiconductor device and semiconductor system

Disclosed are a semiconductor device and a semiconductor system. The semiconductor device includes a command processing circuit for generating a write enable signal and a read enable signal in response to a command, a data strobe signal processing circuit for generating a data strobe signal in response to a clock and the read enable signal or for receiving the data strobe signal in response to the write enable signal and outputting a write data strobe signal, and a data processing circuit for converting analog data into digital data in response to the write data strobe signal and the write enable signal and converting the digital data into the analog data in response to the read enable signal.. ... Sk Hynix Inc

06/28/18 / #20180181856

Neuromorphic device including a synapse array with inverting circuits

A neuromorphic device may include: a pre-synaptic neuron; a synapse electrically connected with the pre-synaptic neuron through a row line; and a post-synaptic neuron electrically connected with the synapse through a column line. The post-synaptic neuron may include a first inverter, the first inverter comprising a first pull-up transistor and a first pull-down transistor, a body of the first pull-up transistor and a body of the first pull-down transistor being electrically connected with a first output node of the first inverter.. ... Sk Hynix Inc

06/28/18 / #20180181695

Electronic device and method for fabricating the same

An electronic device includes a semiconductor memory. The semiconductor memory includes first and second lower plugs, a first pad, a second pad, a first lower line, a second lower line, a first insulation pattern, a second insulation pattern, an upper plug, an upper line, and a plurality of variable resistance elements disposed at regions where the first and second lower lines overlap the upper line.. ... Sk Hynix Inc

06/28/18 / #20180181511

Dynamic termination circuit, semiconductor apparatus and system including the same

A semiconductor apparatus may include a receiver circuit and a termination circuit. The receiver circuit may be coupled to a receiving node, and configured to receive a signal transmitted through a signal transmission line. ... Sk Hynix Inc

06/28/18 / #20180181463

Semiconductor memory device including an error correction code circuit

A semiconductor memory device may be disclosed. The semiconductor memory device may include a first memory cell array region and a second memory cell array region, each of which includes memory cells. ... Sk Hynix Inc

06/28/18 / #20180181460

Data storage device and operatig method thereof

A data storage device includes a nonvolatile memory device including a first page group coupled to a first word line and a second page group coupled to a second word line, which is subsequent to the first word line in order of a write operation; and a controller suitable for, after an abnormal power-off during a write operation to the first page group, copying a first data stored in a weak page of the first page group to a stable page of the second page group when a first error correction operation to data stored in the first page group is a success.. . ... Sk Hynix Inc

06/28/18 / #20180181346

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of memory blocks which include pages; and a controller suitable for: performing command operations in response to commands, recording a count information of the respective memory blocks in a count information table according to the command operations, listing memory blocks satisfying a predetermined first condition in a source memory block candidate list by referring to the count information corresponding to a offset, and selecting as a source memory block a memory block satisfying a predetermined second condition among the memory blocks listed in the source memory block candidate list. The offset may indicate a difference between the count information of the respective memory blocks and an average of the count information.. ... Sk Hynix Inc

06/28/18 / #20180181326

Memory system and method for operating the same

A memory system includes: a memory device including a plurality of memory blocks; and a controller suitable for selecting one or more first memory blocks based on a predetermined condition among the plurality of the memory blocks in a booting section, and increasing a read reclaim count value of one or more second memory blocks among the one or more first memory blocks for which a number of failed bits of read data exceeds a predetermined threshold.. . ... Sk Hynix Inc

06/28/18 / #20180181325

Memory system and operating method thereof

A memory system includes a memory controller; a first memory module, the first memory module including first volatile memory devices; a second memory module, the second memory module including nonvolatile memory devices; a data bus for transmitting data between the memory controller and the first memory module and between the memory controller and the second memory module; a first control bus for transmitting first control signals between the memory controller and the first memory module and between the memory controller and the second memory module; a second control bus for transmitting second control signals between the memory controller and the first memory module; and a third control bus for transmitting third control signals between the memory controller and the second memory module, wherein, in a backup operation, the second control bus and the third control bus are electrically coupled.. . ... Sk Hynix Inc

06/28/18 / #20180181320

Controller and operation method thereof

A controller includes a calculation unit suitable for calculating a first criteria value, a second criteria value, and a valid page ratio of each of a plurality of first memory blocks included in a first memory block group a memory device of the memory system, a decision unit suitable for deciding as a copy candidate a first memory block having a valid page ratio equal to or smaller than the first criteria value; and a processor suitable for controlling the memory device to copy data of the copy candidate to a second memory block in the memory device when the valid page ratio of the copy candidate is equal to or smaller than the second criteria value.. . ... Sk Hynix Inc

06/28/18 / #20180181230

Sensing devices for sensing electrical characteristics

A sensing device may include an integrator configured to sense electrical characteristics of first and second nodes to generate an output voltage. A sensing device may include a switching portion configured to include a plurality of switches, wherein the plurality of switches operate to connect at least one of the plurality of switches to the first node and to connect the remaining switches of the plurality of switches to the second node during each of a plurality of successive switching cycles.. ... Sk Hynix Inc

06/21/18 / #20180175876

Analog-to-digital converters

An analog-to-digital converter adc may be provided. The adc may include a current driving circuit. ... Sk Hynix Inc

06/21/18 / #20180175844

Duty-cycle correction circuit and method

A duty-cycle correction circuit may include a delayed clock generation unit suitable for generating a plurality of delayed clocks by delaying a target clock by different delay values, an up/down signal generation unit suitable for selecting a delayed clock having a delay value corresponding to a first section of the target clock, and generating an up/down signal according to the lengths of a second section of the target clock and the first section of the selected delayed clock, a duty-cycle control code generation unit suitable for generating a duty-cycle control code in response to the up/down signal, a duty-cycle adjusting unit suitable for generating a duty-cycle correction clock by adjusting the duty-cycle of a source clock, and a control unit suitable for enabling the delayed clock generation unit during a duty-cycle correction period, and disabling the delayed clock generation unit during periods except for the duty-cycle correction period.. . ... Sk Hynix Inc

06/21/18 / #20180175053

Semiconductor device and method of manufacturing the same

Provided herein may be a semiconductor device and a method of manufacturing the same. The method of manufacturing the semiconductor device may include forming a tunnel insulating layer in a channel hole passing through a preliminary stack structure in which interlayer insulating layers and material layers are alternately stacked. ... Sk Hynix Inc

06/21/18 / #20180175042

Semiconductor device and method for fabricating the same

A method for fabricating a semiconductor device includes: forming a transistor in a semiconductor substrate; forming a capacitor including a hydrogen-containing top electrode over the transistor; and performing an annealing process for hydrogen passivation after the capacitor is formed.. . ... Sk Hynix Inc

06/21/18 / #20180175011

Semiconductor packages including heat transferring blocks and methods of manufacturing the same

A semiconductor package may be provided. The semiconductor package may include a first semiconductor chip and a second semiconductor chip disposed on an interconnection layer. ... Sk Hynix Inc

06/21/18 / #20180174905

Semiconductor device and method of manufacturing the semiconductor device

An interconnection structure of the semiconductor integrated circuit device may be provided. The interconnection structure may include a first conductive pattern, a second conductive pattern, a dielectric layer and a contact part. ... Sk Hynix Inc

06/21/18 / #20180174845

Semiconductor device having buried gate structure and method for fabricating the same

A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.. . ... Sk Hynix Inc

06/21/18 / #20180174664

Memory device

A memory device includes: a normal cell array; a parity cell array; a plurality of normal write drivers suitable for writing normal write data in the normal cell array; a plurality of parity write drivers suitable for writing parity write data corresponding to the normal write data, in the panty cell array; and an error injection circuit suitable for injecting error write data to at least one among the plurality of the normal write drivers and the plurality of the parity write drivers.. . ... Sk Hynix Inc

06/21/18 / #20180174662

Memory controller, memory system including the same and operating method thereof

A memory controller may include a detector configured for checking whether the number of bits having a first state among a plurality of bits constituting write data is less than a reference value. The memory controller may include an inverter configured for inverting/non-inverting the write data according to the check result of the detector. ... Sk Hynix Inc

06/21/18 / #20180174651

Electronic device

An electronic device including a semiconductor memory. The semiconductor memory may include a cell array including a plurality of resistive storage cells; a current code generation block suitable for generating a current code which has a value corresponding to an average value of current amounts of test currents respectively flowing through at least two first resistive storage cells among the plurality of resistive storage cells, in a test operation; and a sensing block suitable for comparing a read current flowing through a second resistive storage cell selected among the plurality of resistive storage cells with a reference current, and thereby sensing data of the second resistive storage cell, wherein the semiconductor memory is operable to adjust a current amount of at least one current flowing through the sensing block based on the value of the current code.. ... Sk Hynix Inc

06/21/18 / #20180174638

Semiconductor devices

A semiconductor device includes a counter control signal generation circuit and an access information generation circuit. The counter control signal generation circuit generates a count enablement signal, a reset signal and a count increment signal in response to a first row address selected as a target address and a second row address selected as a neighboring address. ... Sk Hynix Inc

06/21/18 / #20180174633

Semiconductor apparatus, semiconductor system, and training method

A semiconductor apparatus may be provided. The semiconductor apparatus may include a fine training circuit configured to generate a fine result signal based on a clock signal, a data strobe signal, and a command. ... Sk Hynix Inc

06/21/18 / #20180174632

Semiconductor device and semiconductor system

A semiconductor system includes a first semiconductor device and a first semiconductor device. The first semiconductor device outputs a clock, a chip selection signal and addresses. ... Sk Hynix Inc

06/21/18 / #20180174629

Memory system and method for operating the same

Provided herein may be a memory system and a method of operating the same. A semiconductor memory device may include a write protect pin mode setting unit configured to set, depending on a parameter value stored therein, a write protect pin of the semiconductor memory device as any one of an input pin and an output pin and a control logic configured to output, when the write protect pin serves as the output pin, internal state information of the semiconductor memory device to an external device.. ... Sk Hynix Inc

06/21/18 / #20180174628

Data storage device and operating method thereof

A data storage device includes a memory device suitable for storing and outputting data in synchronization with a strobe signal; and a controller suitable for delaying the strobe signal based on each of different test delay values, testing capture of the data by using a delayed strobe signal, and determining a delay value of the strobe signal based on a test result.. . ... Sk Hynix Inc

06/21/18 / #20180174045

Apparatus and method for recognizing information of neuromorphic device

A neuromorphic device according to various embodiments of the present disclosure includes a recognizing unit suitable for recognizing information based on a plurality of learned results to generate a plurality of recognition signals, a maximum value extracting unit suitable for respectively extracting values of the plurality of recognition signals and extracting a recognition signal having a maximum value among the plurality of recognition signals, and a control unit suitable for processing the information based on the to recognition signal having the maximum value.. . ... Sk Hynix Inc

06/21/18 / #20180174025

Apparatus and method for normalizing neural network device

A neural network device may include an input unit suitable for applying input signals to corresponding first lines, a calculating unit including memory elements cross-connected between the first lines and second lines, wherein the memory elements have respective weight values and generate product signals of input signals of corresponding first lines from among the plurality of first lines and weights to output the product signals to corresponding second lines from among the second lines, a drop-connect control unit including switches connected between the plurality of first lines and the plurality of memory elements, and suitable for randomly dropping a connection of an input signal applied to a corresponding memory element from among the plurality of memory elements, and an output unit connected to the plurality of second lines, and suitable for selectively activating signals of the plurality of second lines to apply the activated signals to the input unit and performing an output for the activated signals when the calculating unit performs generating of the product signals a set number of times.. . ... Sk Hynix Inc

06/21/18 / #20180173653

Electronic device

This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the pinned layer and the free layer, wherein the free layer may include a first magnetic layer; a second magnetic layer formed over the first magnetic layer; and a zirconium (zr)-containing material layer interposed between the first magnetic layer and the second magnetic layer.. ... Sk Hynix Inc

06/21/18 / #20180173650

Memory system and operating method thereof

A method for operating a memory system including a memory controller and a memory mudule, the method includes: by the memory controller, applying a read command to the memory module; by the memory module, determining whether the memory module is able to transfer the read data to the memory controller during a regulated section; by the memory module, notifying the memory controller by using a data strobe signal that the memory module is not able to transfer the read data to the memory controller during the regulated section; by the memory controller, applying a status check-out command to the memory module in response to the notification for checking out a status of the memory module; and by the memory module, transferring status information of the memory module to the memory controller in response to the status check-out command.. . ... Sk Hynix Inc

06/21/18 / #20180173462

Memory system and operation method thereof

Provided are a memory control device and a method. The memory control device may include a memory device, and a controller operatively coupled to the memory device. ... Sk Hynix Inc

06/21/18 / #20180173270

Semiconductor devices

A semiconductor device includes a phase comparison circuit, an output enablement signal generation circuit, and a data input/output (i/o) circuit. The phase comparison circuit compares a phase of a clock signal with a phase of a delay locked loop (dll) clock signal to generate a phase information signal. ... Sk Hynix Inc

06/21/18 / #20180172744

Capacitance sensing circuits

A capacitance sensing circuit includes a buffer circuit, a modulation circuit, and an integral circuit. The buffer circuit is coupled to an external capacitor through a touch-sensing pad, and includes a pull-up device and a pull-down device. ... Sk Hynix Inc

06/14/18 / #20180167574

Counting apparatus, analog-to-digital converter and image sensor including the same

A counting apparatus may include: a count control unit suitable for controlling a counting operation of a common value and a differential value of two pixel signals according to two neighboring output signals of a comparator unit; a counting unit suitable for counting a clock during a period corresponding to the common value and the differential value, according to control of the count control unit; and a memory unit suitable for storing count information from the counting unit and operation information from the count control unit.. . ... Sk Hynix Inc

06/14/18 / #20180166384

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate including a cell area, a first contact area, and a second contact area; a lower stacked structure extending over the second contact area from the cell area; an upper stacked structure extending over the first contact area from the cell area, the upper stacked structure leaving the second contact area open; n (n is a natural number of 2 or more) first group of stepped grooves penetrating at least one portion of the upper stacked structure in the first contact area; and m (m is a natural number equal to or smaller than n) second group of stepped grooves penetrating at least one portion of the lower stacked structure in the second contact area.. . ... Sk Hynix Inc

06/14/18 / #20180166152

Semiconductor device and semiconductor system including the same

A semiconductor device may include a repair address storage circuit, an address comparison circuit, and a word line selection circuit. The repair address storage circuit may store a first repair address and a second repair address. ... Sk Hynix Inc

06/14/18 / #20180166149

Semiconductor device and operating method thereof

A semiconductor device includes: a fuse set unit including a plurality of fuse sets, each fuse set including one or more address fuses and an enable fuse; a rupture control unit suitable for controlling the enable fuse of a selected fuse set to be programmed after the address fuses of the selected fuse set is programmed, during a program operation; a cell data verify unit suitable for repeatedly performing a verify and rupture operation on the selected fuse set during the program operation, determining whether read data from the selected fuse set is identical to target data corresponding to a rupture address through a final verify operation, and outputting fail information; and a fuse set control unit suitable for controlling the program operation to be performed on a different fuse set after the program operation on the selected fuse set is terminated, in response to the fail information.. . ... Sk Hynix Inc

06/14/18 / #20180166146

Semiconductor device and semiconductor system including the same

A semiconductor device may be provided. The semiconductor device may include a first oscillation signal generation circuit for generating a first oscillation signal. ... Sk Hynix Inc

06/14/18 / #20180166144

Semiconductor device, semiconductor system and operating method thereof

A semiconductor device includes an internal command generation circuit suitable for generating a first internal command, a second internal command, and a third internal command based on a command/address signal. The semiconductor device also includes a driving signal generation circuit suitable for enabling a fuse driving signal for reading fuse data from a nonvolatile memory circuit, where the fuse signal is enabled while the second internal command is inputted a predetermined number of times. ... Sk Hynix Inc

06/14/18 / #20180166119

Sub word line driver of semiconductor memory device

A layout structure of a sub word line driver for use in a semiconductor memory device may be disclosed. The sub word line driver may include a first active region through which first and second main word lines pass. ... Sk Hynix Inc

06/14/18 / #20180166117

Memroy device and operating method thereof

An operating method of a memory device including a plurality of memory cells may include: measuring data retention times of at least a portion of the plurality of memory cells; and optimizing a refresh operation on the plurality of memory cells using the measurement result.. . ... Sk Hynix Inc

06/14/18 / #20180166114

Electronic device

An electronic device including a semiconductor memory. The semiconductor memory includes a bit line; a source line; a plurality of resistive memory cells among which a selected memory cell forms a current path between the bit line and the source line; a read current supply unit configured to supply read current to the bit line in a read operation; a sense amplifier configured to generate read data in response to a voltage level of the bit line in the read operation; and a variable switch element configured to flow current from the source line to a ground terminal in the read operation, and be decreased in its resistance value as a voltage level of the source line is high.. ... Sk Hynix Inc

06/14/18 / #20180166112

Semiconductor device

A semiconductor device may be provided. The semiconductor device may operate in a 2n mode as well as a normal mode.. ... Sk Hynix Inc

06/14/18 / #20180166110

Semiconductor devices

A semiconductor device includes a flag signal generation circuit and a power-down signal generation circuit. The flag signal generation circuit generates a flag signal which is enabled in response to an operational frequency information signal. ... Sk Hynix Inc

06/14/18 / #20180166108

Semiconductor memory device, and signal line layout structure thereof

A memory device includes first and second memory blocks each including a memory cell array, a sub-word line drive region and a bit line sense amplifier region corresponding to the memory cell array, first and second data transmission lines disposed in the bit line sense amplifier region of each memory block, wherein the first and second data transmission lines extend on an identical row and transmit data of the memory cell array of the memory block, a row decoder configured to select one of the first and second memory blocks in response to a row address and enable a word line of the memory cell array included in the selected memory block, and a column decoder configured to generate, in response to a column address, first and second column select signals corresponding to the first and second data transmission lines of the bit line sense amplifier region.. . ... Sk Hynix Inc

06/14/18 / #20180166107

Semiconductor devices and semiconductor systems including the same

A semiconductor system includes a semiconductor device. The semiconductor device outputs a first group of data and a second group of data to a first group of input/output (i/o) lines and a second group of i/o lines in response to a command and an address. ... Sk Hynix Inc

06/14/18 / #20180166106

Nonvolatile memory device, nonvolatile memory system, and operating method of nonvolatile memory

A nonvolatile memory device may include a nonvolatile memory device may include a nonvolatile memory cell array; a peripheral circuit suitable for: activating an operation voltage in response to an operation voltage activation command, performing an operation to the nonvolatile memory cell array using the activated operation voltage in response to an operation command, and deactivating the activated operation voltage in response to an operation voltage deactivation command after the performing of the operation; and a control circuit suitable for controlling the peripheral circuit to execute an intervening operation during the activating of the operation voltage, the performing of the operation, and the deactivating of the activated operation voltage.. . ... Sk Hynix Inc

06/14/18 / #20180165187

Semiconductor system and method for operating the semiconductor system

A semiconductor system may include: a volatile memory device that stores an address mapping table including mapping information for a non-volatile memory device; and a control device suitable for reading one or more seed values from the volatile memory device before the address mapping table is stored, generating a plurality of random values based on the seed values, and initializing mapping information to the plurality of random values.. . ... Sk Hynix Inc

06/14/18 / #20180165151

Memory system and error correcting method of the same

An error correcting method of a memory system includes: reading data and an error correction code from a plurality of memory chips; correcting an error of the data based on the error correction code; determining whether or not a miscorrection occurs in the correcting of the error of the data; designating one memory chip among the plurality of the memory chips as a chip-killed memory chip when a miscorrection occurs; re-correcting the error of the data based on the error correction code in consideration of the designated chip-killed memory chip; and re-determining whether a miscorrection occurs in the re-correcting of the error of the data.. . ... Sk Hynix Inc

06/14/18 / #20180165149

Semiconductor device and operating method thereof

A semiconductor device includes: a control signal generation unit configured to generate a second control signal having a cycle shorter than a first control signal in response to a clock signal and the first control signal; a cyclic redundancy check (crc) control unit configured to perform a control to receive first and second data groups in response to the second control signal, and to output the first and second data groups with a time lag; and a crc operation unit configured to perform a cyclic redundancy check on each of the first and second data groups sequentially output through the crc control unit.. . ... Sk Hynix Inc

06/14/18 / #20180165098

Pipe latch circuit and data output circuit including the same

A pipe latch circuit includes: a pipe pipe latch control block suitable for controlling a plurality of pipe input signals and a plurality of pipe output signals to be activated sequentially or be divided into at least two groups and be activated sequentially by group, depending on a latency setting value, and outputting at least one pipe input signal and at least one pipe output signal; and a pipe latch block coupled between an input node and an output node, and suitable for storing data of the input node in response to the pipe input signal and outputting stored data to the output node in response to the pipe output signal.. . ... Sk Hynix Inc

06/14/18 / #20180165024

Semiconductor devices

A semiconductor device includes a group control circuit configured to generate a specified address and a control code in response to a row address and an active command, a comparison control signal generation circuit configured to generate a comparison control signal in response to the active command and a set code, and a target address generation circuit configured to output the specified address as a target address in response to the control code and the comparison control signal.. . ... Sk Hynix Inc

06/07/18 / #20180159543

Semiconductor device including dll and semiconductor system

A semiconductor system includes: a controller suitable for outputting an external clock signal and a command/address signal; and a semiconductor device suitable for selecting one of pre-stored code values of a delay control signal to output an initial value control signal according to the command/address signal, and outputting an internal clock signal by delaying the external clock signal by a predetermined time based on the delay control signal having an initial value that is set in response to the initial value control signal.. . ... Sk Hynix Inc

06/07/18 / #20180158868

Electronic device

An electronic device may be provided to include: first and second active regions arranged adjacent to each other in a second direction; a gate structure extended in the second direction; a first source region and a first drain region formed in the first active region; a second source region and a second drain region formed in the second active region; a source line contact formed over the first and second source regions and connected to the first and second source regions; a source line connected to the source line contact over the source line contact and extended in a first direction; first and second stacked structures formed over the first and second drain regions; and first and second bit lines formed over the first and second stacked structures, wherein the first and second bit lines are extended in the first direction.. . ... Sk Hynix Inc

06/07/18 / #20180158864

Image sensor including photodiodes having different sizes

Disclosed is an image sensor may include a pixel array having a central region and peripheral regions around the central region, one or more first unit pixels arranged in the peripheral regions. Each of the first unit pixels comprising a pair of left and right photodiodes. ... Sk Hynix Inc

06/07/18 / #20180158528

Control logic, semiconductor memory device, and method of operating the same

Provided herein may be a control logic, semiconductor memory device, method of operating the control logic, and or method of operating the semiconductor memory device. The semiconductor memory device may include a control logic. ... Sk Hynix Inc

06/07/18 / #20180158524

Non-volatile memory apparatus including voltage clamping circuit

A memory apparatus may be provided. The memory apparatus may include a global bit line configured to receive a drift current. ... Sk Hynix Inc

06/07/18 / #20180158523

Electronic device

An electronic device includes a semiconductor memory that includes: resistive storage cells; a reference resistance cell; a comparison block electrically coupled to the resistive storage cells and the reference resistance cell through first and second input terminals, to compare a cell current flowing through the first input terminal and a reference current flowing through the second input terminal; a first clamp part to control a maximum current amount of the cell current depending on a voltage level of a first node; a second clamp part to control a maximum current amount of the reference current depending on the voltage level of the first node; a voltage stabilization block to stabilize a voltage of the first node during a charging or a discharging period; and a switching part electrically coupled with the first node and the voltage stabilization block in the charging period or the discharging period.. . ... Sk Hynix Inc

06/07/18 / #20180158509

Semiconductor device

A semiconductor device includes an input clock generation circuit able to shift a write command in synchronization with a clock, and generating first and second input clocks. The semiconductor device also includes a write leveling control circuit able to divide a frequency of the clock in response to a write leveling control signal, and generating first to fourth write clocks. ... Sk Hynix Inc

06/07/18 / #20180158505

Semiconductor memory device and method for operating the same

Provided herein is a semiconductor memory device and a method for operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory blocks, each including dummy cells coupled to dummy word lines and normal memory cells coupled to normal word lines, a peripheral circuit configured to perform an erase operation on a memory block selected from among the plurality of memory blocks and control logic configured to control the peripheral circuit, during the erase operation, to apply a pre-program voltage pulse to the dummy word lines and the normal word lines, and to control application of dummy word line voltages to the dummy word lines based on erase-write (ew) cycling information while applying an erase voltage to a common source line of the selected memory block, wherein the ew cycling information indicates a number of erase-write cycles of the selected memory block.. ... Sk Hynix Inc

06/07/18 / #20180158493

Apparatus and method for controlling memory device

An apparatus for controlling a memory device may include: a table storing information of a plurality of read voltages; an error correction unit suitable for correcting an error of read data; and a processor functionally coupled to the rr table and the error correction unit. The processor selects a default read voltage among the plurality of read voltages from the table when a read fail for the memory device is recognized, sets a shift direction of the default read voltage based on the number of read cells of the memory device read by the default read voltage, and controls a read retry operation of the memory device based on at least one read voltage in the set shift direction in the table.. ... Sk Hynix Inc

06/07/18 / #20180157586

Data storage device and operating method thereof

A data storage device includes a memory device including a plurality of memory regions; and a controller suitable for selecting one or more candidate memory regions among the plurality of memory regions based on erase counts of the plurality of memory regions, determining an adjustment value based on the number of the candidate memory regions, selecting victim memory regions by the number that is equal to or less than the adjustment value among the candidate memory regions, and performing a garbage collection operation to the selected victim memory regions.. . ... Sk Hynix Inc

06/07/18 / #20180157546

Semiconductor memory device and method for operating the same

Provided herein may be a semiconductor memory device and a method for operating the same. The semiconductor memory device may include a memory cell array, a peripheral circuit, control logic, a status storage unit, and an operating characteristic checking unit. ... Sk Hynix Inc

06/07/18 / #20180157427

Memory system and operating method thereof

A memory system includes a wear-leveling module detecting a hot memory block among a plurality of memory blocks based on the number of times write operations are performed on each of the memory blocks, and moving data from the hot memory block to a spare memory block, a counting unit counting the number of data movement from the hot memory block to the spare memory block, on each of memory regions formed by grouping the plurality of memory blocks, and output data movement counts, a first detection unit selecting one from the plurality of memory regions based on the data movement count, and detecting a cold memory block among memory blocks included in the selected memory region, and a management unit moving data from the cold memory block to the hot memory block, and managing the cold memory block as the spare memory block.. . ... Sk Hynix Inc

06/07/18 / #20180157415

Apparatus and method for controlling memory device

A memory control apparatus may include a memory device including at least two memories respectively coupled to at least two channels, and a controller functionally coupled with the memory device. The controller may receive at least one command for performing a host task from a host, control the memory device to perform the host task with the memories based on the received command, and control the r memory device such that, when a trigger point of a device task for a memory of the memory device is recognized, a first memory of the memory device coupled with a corresponding channel performs the device task and a second memory of the memory device coupled with the other channel process the host task.. ... Sk Hynix Inc

05/31/18 / #20180152203

Error correction circuits and memory controllers including the same

An error correction circuit includes a syndrome calculator suitable for generating syndromes from an “n”-bit codeword for a single unit of time, an error location polynomial calculator suitable for generating error location polynomial coefficients based on the syndromes provided for the single unit of time, an error location calculator suitable for calculating error locations based on the error location polynomial coefficients for the single unit of time, and an error corrector suitable for correcting errors of the codeword based on the error locations for the single unit of time. The error correction circuit operates in a pipelining manner.. ... Sk Hynix Inc

05/31/18 / #20180152186

Internal voltage generation circuit

An internal voltage generation circuit includes a comparison circuit, a driving signal generation circuit and a driving circuit. The comparison circuit generates a comparison signal from an internal voltage in response to a reference voltage. ... Sk Hynix Inc

05/31/18 / #20180151509

Semiconductor apparatus and memory system

A semiconductor apparatus includes a chip id generation unit, a chip id transmission unit and a chip stack information generation unit. The chip id generation unit is configured to generate a chip id signal. ... Sk Hynix Inc

05/31/18 / #20180151251

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of memory blocks configured in a plurality of super memory blocks; and a controller suitable for detecting two or more bad super memory blocks each including at least one bad block among the super memory blocks, selecting at least one victim super memory block among the bad super memory blocks, and replacing the at least one bad block in each remaining bad super memory block with at least one normal block of the victim super memory block.. . ... Sk Hynix Inc

05/31/18 / #20180151250

Memory device

A memory device may include: a plurality of memory cells; a weak cell information storage unit suitable for storing a weak address and parity information corresponding to one or more weak cells having a shorter data retention time than a reference time, among the plurality of memory cells; an ecc (error correction code) circuit suitable for detecting and correcting an error bit of the one or more weak cells using the parity information; and a refresh control unit suitable for controlling the plurality of memory cells to be refreshed at a cycle equal to or more than the reference time.. . ... Sk Hynix Inc

05/31/18 / #20180151249

Data storage apparatus and operating method thereof

A data storage apparatus includes a nonvolatile memory device and a controller configured to determine whether or not one or more addresses of defective bit lines are included in an address of a write data to be written into the nonvolatile memory device or an address of a read data read from the nonvolatile memory device, and write the write data or read the read data by skipping the defective bit lines based on a determination result.. . ... Sk Hynix Inc

05/31/18 / #20180151230

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a voltage generator suitable for applying an erase voltage to a source line of at least one memory block selected from among the plurality of memory blocks during an erase operation, a read and write circuit suitable for applying an initial setting voltage, to bit lines of at least one memory block during the erase operation, and a control logic suitable for controlling the voltage generator and the read and write circuit to apply the initial setting voltage to the bit lines before applying the erase voltage to the source line.. . ... Sk Hynix Inc

05/31/18 / #20180151217

Semiconductor device

A semiconductor device may be provided. The semiconductor device may include a data input and output circuit (i/o) configured to selectively or simultaneously drive input and output lines according to a burst length and a location of a memory area selected by an address to allow the semiconductor device to receive or output data regardless of the burst length being changed.. ... Sk Hynix Inc

05/31/18 / #20180151216

Circuit for generating periodic signal and memory device including same

Provided is a periodic signal generation circuit including a clock generation unit suitable for generating first to nth clocks which have a basic period and have a phase increasing sequentially by a time interval obtained by dividing the basic period by “n”; a pulse generation unit suitable for generating first to nth periodic pulses having an equal pulse width and having a phase increasing sequentially by a time interval obtained by dividing the basic period by “n” by combining two or more clocks among the first to nth clocks; and a periodic signal generation unit suitable for generating a periodic signal by combining one or more periodic pulses among the first to nth periodic pulses depending on combination information.. . ... Sk Hynix Inc

05/31/18 / #20180151208

Semiconductor system

A semiconductor system may include a controller and a semiconductor memory device. The controller may provide an external command, an external address and a first external clock. ... Sk Hynix Inc

05/31/18 / #20180151205

Memory device, operating method thereof, and operating method of memory system including the same

A method for operating a memory device includes: receiving a write command; checking out whether a data strobe signal toggles or not after a given time passes from a moment when the write command is received; when the data strobe signal is checked out to be maintained at a uniform level, detecting voltage levels of a plurality of data pads; and performing an operation that is selected based on the voltage levels of the plurality of the data pads among a plurality of predetermined operations.. . ... Sk Hynix Inc

05/31/18 / #20180151204

Electronic device and method for driving the same

An electronic device includes a semiconductor memory. The semiconductor memory may include: a memory circuit comprising a plurality of memory cells; a read circuit configured to generate a first read data signal by reading data from a read target memory cell according to a first read control signal, the read target memory cell being among the plurality of memory cells; and a control circuit configured to control the read circuit to reread the data from the read target memory cell by generating a second read control signal, the second read control signal being based on a data value of the first read data signal.. ... Sk Hynix Inc

05/31/18 / #20180151197

Error correction code encoder, encoding method, and memory controller including the encoder

An error correction code (ecc) encoder includes a plurality of exclusive or (xor) gates configured to receive a “k”-bit original data in parallel and configured to perform a plurality of xor operations to the “k”-bit original data to output a “(n−k)”-bit parity data. The “k”-bit original data and the “(n−k)”-bit parity data form an “n”-bit codeword, “k” denotes a natural number and “n” denotes a natural number which is greater than “k”.. ... Sk Hynix Inc

05/31/18 / #20180150248

Memory device, semiconductor system including the same, and method for driving the semiconductor system

A semiconductor device includes at least one normal block suitable for storing normal data; at least one sample block suitable for storing sample data; a phenomenon analysis block suitable for generating at least one phenomenon analysis signal based on the sample data; and a control block suitable for controlling a level of reference data required when the normal data are read based on the at least one phenomenon analysis signal.. . ... Sk Hynix Inc

05/31/18 / #20180150247

Memory system and method for operating the same

Provided herein may be a memory system and a method of operating the memory system. The memory system may include a semiconductor device in which data are stored, and a memory controller for communicating with the semiconductor device, sequentially processing tasks included in a descriptor, detecting an error section by checking the tasks in reverse order when an error occurred in the tasks, and reprocessing the tasks included in the detected error section.. ... Sk Hynix Inc

05/31/18 / #20180150245

Data storage device and data processing system

A data processing system includes a host device; and a data storage device suitable for detecting a voltage drop state in the voltage received from the host device, changing a first key received from the host device to a second key when detecting the voltage drop state, generating a cyclical redundancy check (crc) data based on the second key, and transmitting the generated crc data to the host device.. . ... Sk Hynix Inc

05/31/18 / #20180150225

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of memory dies each having a plurality of memory blocks; and a controller suitable for performing one or more of data defragmentation and data remapping operations for a target transaction group in the memory device in response to a request message provided from a host, transmitting a completion message to the host as a response to the request message, and receiving an access to the transaction group, from the host.. . ... Sk Hynix Inc

05/31/18 / #20180150224

Memory system and operation method for the same

A memory system, may include: a memory device including a plurality of memory blocks each including a plurality of stacked word lines; and a controller suitable for dividing the plurality of word lines into two or more word line groups according to heights thereof, programming data of a relatively high access frequency into a word line group having word lines of relatively low physical heights and data of a relatively low access frequency into a word line group having word lines of relatively high physical heights among the word line groups included in each of the memory blocks.. . ... Sk Hynix Inc

05/31/18 / #20180150100

Training device and semiconductor system including the same

A training device may include a pattern generation circuit configured to generate a pattern signal in response to a read command, a delay calculation circuit configured to calculate a delay amount based on comparison results between a generation timing of the pattern signal and generation timings of pattern signals which are generated from one or more other training devices and transmitted to a corresponding training device, and a delay adjusting circuit configured to adjust a delay of a dq signal in a chip including the corresponding training device, based on the delay amount.. . ... Sk Hynix Inc

05/24/18 / #20180145705

Data mapping scheme for generalized product codes

Memory systems and operating methods thereof comprise a memory storage and an error control coding (ecc) unit. The memory storage stores data which is split into a plurality of data chunks. ... Sk Hynix Inc

05/24/18 / #20180145698

Analog-to-digital converter (adc) with improved power disturbance reduction

Disclosed herein is an analog-to-digital converter (adc) for converting an input analog voltage to an output digital code, the adc comprising a first node of the input analog voltage: nodes of a plurality of reference voltages; a plurality of comparators, inputs of each comparator being coupled to the first node and a node of a corresponding reference voltage of the plurality of reference voltages; a logic circuit block for receiving outputs of the plurality of comparators and generating the output digital code; and a voltage stabilizer, terminals of the voltage stabilizer being coupled with the first node and a node of a first reference voltage among the plurality of reference voltages.. . ... Sk Hynix Inc

05/24/18 / #20180145639

Amplifier for contorlling output range and multi-stage amplification device using the same

An amplifier includes a differential amplification block suitable for receiving and amplifying a first differential input signal and a second differential input signal; an output block suitable for determining an output signal according to a state of amplified signals outputted from the differential amplification block; and an output range restriction block suitable for controlling an output range of the output signal outputted from the output block based on a maximum clamping signal and a minimum clamping signal.. . ... Sk Hynix Inc

05/24/18 / #20180145087

Manufacturing method for semiconductor device

A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure, forming a reflective metal pattern in the first hole, filling an etch stop layer in the first hole and over the reflective metal pattern, forming a second stacked structure over the first stacked structure, and forming a second hole penetrating the second stacked structure to expose the etch stop layer.. . ... Sk Hynix Inc

05/24/18 / #20180144944

Methods of forming patterns using imprint process

A method for forming patterns is provided. The method includes forming a resist layer on a substrate, imprinting a convex pattern and a concave pattern on the resist layer using a template, forming a silicon diffusion layer containing silicon containing diffusion species in an upper portion of the convex pattern, and selectively removing a recessed portion of the resist layer under the concave pattern using the silicon diffusion layer as an etch mask.. ... Sk Hynix Inc

05/24/18 / #20180144813

Fail bit counter and semiconductor memory device having the same

Provided herein is a fail bit counter. The fail bit counter includes a pass/fail data receiver receiving pass/fail data indicating whether memory cells coupled to a bit line sequentially pass or fail, and a fail bit accumulator receiving a fail bit generation signal from the pass/fail data receiver, and accumulating and counting fail bits which are generated.. ... Sk Hynix Inc

05/24/18 / #20180144806

Memory system and operating method thereof

A memory system'may include: a nonvolatile memory device suitable for storing write-requested data; and a controller including a first volatile memory region suitable for storing meta-data for the write-requested data and a second volatile memory region suitable for storing a meta-log for the meta-data the controller may store the meta-data or the meta-log according to a logical address range of the meta-data.. . ... Sk Hynix Inc

05/24/18 / #20180144799

Phase change memory device capable of decreasing a disturbance

A phase change memory device may include a plurality of word lines, a plurality of bit lines, a phase change memory cell, and a discharging circuit. The word lines and the bit lines may intersect each other. ... Sk Hynix Inc

05/24/18 / #20180144798

Phase change memory device

A phase change memory device may be provided. The phase change memory device may include a plurality of mats, a row control block and a column control block. ... Sk Hynix Inc

05/24/18 / #20180144794

Cross point array type phase change memory device and method of driving the same

A phase change memory device may include a cross point array and a sensing circuit block. The cross point array may include a plurality of word lines, a plurality of bit lines and phase change memory cells. ... Sk Hynix Inc

05/24/18 / #20180144789

Semiconductor device, semiconductor system including the same and read and write operation method thereof

A semiconductor device may be provided. The semiconductor device may include a word line selector configured to generate an active signal for selecting a word line, based on a row address. ... Sk Hynix Inc

05/24/18 / #20180144785

Buffer circuit, semiconductor apparatus and system using the same

A buffer circuit may include first amplifier coupled to a first common node. The buffer circuit may include a second amplifier coupled to the first common node. ... Sk Hynix Inc

05/24/18 / #20180144781

Semiconductor memory device and method for operating the same

Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a delay code determining unit configured to output a final delay trim code reflecting process, voltage and temperature (pvt) conditions of the semiconductor memory device, using an internal clock generated for a reference time and a delay circuit configured to reflect a delay of a data line on a clock signal in response to the final delay trim code.. ... Sk Hynix Inc

05/24/18 / #20180143922

Data inversion circuit

A data inversion circuit in accordance with an embodiment may include a data input circuit and an inversion latch circuit. The data input circuit may output latch data by latching input data, perform a data inversion by performing a logical operation on the latch data and flag data, generate selective inversion data, and output data composed of multiple bits by aligning the selective inversion data. ... Sk Hynix Inc

05/24/18 / #20180143902

Data storage device and operating method thereof

A data storage device includes a storage medium including a plurality of memory units; and a controller suitable for performing a state determination operation to first memory units in order of a write sequence until a memory unit stored with an error-correction-failed data when a power supply is restored after an abnormal power-off, skipping the state determination operation to second memory units between the memory unit storing the error-correction-failed data and a pointed memory unit, performing the state determination operation to third memory units after the pointed memory unit in order of the write sequence, and performing a garbage collection operation to the first to third memory units based on a result of the state determination operation.. . ... Sk Hynix Inc

05/24/18 / #20180143899

Controller, memory system and operating method thereof

A controller includes a memory suitable for storing valid data of first data in a first data region and storing second data in a second data region, wherein the first data includes the valid data and dummy data; a translation unit suitable for performing a first translation operation of changing the first data to the valid data by eliminating the dummy data from the first data, performing a second translation operation of changing the valid data to the first data by adding the dummy data to the valid data, and exchanging the valid data with the memory; and a processor suitable for exchanging the first data with the translation unit, and exchanging the second data with the memory.. . ... Sk Hynix Inc

05/17/18 / #20180138229

Image sensor

An image sensor may include a pixel array that includes a plurality of pixel blocks arranged in an m×n (where m and n are natural numbers) matrix structure, wherein, among the plurality of pixel blocks, when compared to any one pixel block as a first pixel block, any one pixel block as a second pixel block adjacent to the first pixel block in an m direction or an n direction has a planar shape that is obtained by inverting a planar shape of the first pixel block in the m direction. Each of the plurality of pixel blocks may include a light reception unit including a plurality of unit pixels which generate photocharges in response to incident light and are arranged in an m×n matrix structure to have a shared pixel structure; and a driving circuit suitable for outputting an image signal corresponding to the photocharges.. ... Sk Hynix Inc

05/17/18 / #20180138195

Semiconductor device and method of manufacturing the same

Provided here may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a first source seed layer, a second source seed layer disposed over the first source seed layer at a position spaced apart from the first source seed layer with a source area interposed between the first source seed layer and the second source seed layer, cell plugs configured to penetrate through the second source seed layer and extend into the source area, the cell plugs being disposed at positions spaced apart from the first source seed layer. ... Sk Hynix Inc

05/17/18 / #20180138191

Semiconductor integrated circuit device relating to resistance characteristics

A semiconductor integrated circuit device may include a structure, a first capping layer, a channel layer and a second capping layer. The structure may have an opening formed in the structure. ... Sk Hynix Inc

05/17/18 / #20180138150

Semiconductor package having a redistribution line structure

A semiconductor package may include a first semiconductor chip having first bonding pads on a first active surface. The semiconductor package may include a second semiconductor chip having second bonding pads which are arranged on a second active surface. ... Sk Hynix Inc

05/17/18 / #20180138041

Methods for forming fine patterns using spacers

There is provided a method for forming fine patterns. The method includes forming a pattern divider on an underlying layer, forming a mask layer on the underlying layer to cover the pattern divider, forming an opening pattern that vertically penetrates the mask layer to expose a portion of the pattern divider and intersects the exposed portion of the pattern divider, and selectively removing portions of the underlying layer exposed by the opening pattern of the mask layer to form a couple of opening sub-patterns.. ... Sk Hynix Inc

05/17/18 / #20180137924

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a reference voltage generation block suitable for selecting and outputting one of a plurality of reference voltages in response to a voltage division enable signal, as an input reference voltage, in response to a selection enable signal; and a control signal generation block suitable for generating the voltage division enable signal and the selection enable signal in response to a reference voltage information.. . ... Sk Hynix Inc

05/17/18 / #20180137919

Semiconductor memory device and method of operating the same

Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory blocks, each including dummy cells coupled to dummy word lines and normal memory cells coupled to normal word lines, and a peripheral circuit configured to perform an erase operation on a memory block selected from among the plurality of memory blocks. ... Sk Hynix Inc

05/17/18 / #20180137901

Receiver circuit, and semiconductor device and system including the same

A receiver circuit may be provided. The receiver circuit may include a delay circuit and a synchronization circuit. ... Sk Hynix Inc

05/17/18 / #20180137003

Media quality aware ecc decoding method selection to reduce data access latency

A memory system and operating method thereof includes a semiconductor memory device, and a memory controller controlling actions of the memory device. The memory controller contains a processor executing instruction and programs stored in the memory controller, a memory characterizer characterizing the memory system, and generating an index decision table, an in-flight assessor assessing read command, and predicting a proposed error recovery action in accordance with the index decision table, and a selective decoder executing the proposed error recovery action.. ... Sk Hynix Inc

05/17/18 / #20180136996

Semiconductor devices and semiconductor systems including the same

A semiconductor device and or system may be provided. The semiconductor system may include a first semiconductor device and a second semiconductor device. ... Sk Hynix Inc

05/17/18 / #20180136860

Semiconductor memory device

Provided herein may be a semiconductor memory device. The semiconductor memory device may include a memory cell array including a plurality of memory cells, and a peripheral circuit disposed under the memory cell array. ... Sk Hynix Inc

05/17/18 / #20180136844

Arithmetic circuit and a semiconductor device

A semiconductor device may include an input control circuit, a first operation control circuit, an arithmetic circuit and a second operation control circuit. The input control circuit may generate a read signal, write signal, a read address, and write address based on an external control signal. ... Sk Hynix Inc

05/10/18 / #20180131390

Semiconductor memory device performing randomization operation

Provided herein is a semiconductor memory device. The semiconductor memory device may include a plurality of planes including a plurality of memory cells, read/write circuits coupled to the plurality of planes, respectively, and temporarily storing normal data inputted from an external device, random data, and parity data, and an error correction circuit generating the random data by randomizing the normal data, generating parity data for the random data during a program operation, correcting an error of the random data by using the parity data and de-randomizing the random data during a read operation.. ... Sk Hynix Inc

05/10/18 / #20180131389

Bit-flipping ldpc decoding algorithm with hard channel information

Memory systems may include a memory storage, and an error correcting code (ecc) unit suitable for determining a number of unsatisfied check nodes of a channel output in a decoding iteration of a decoding process, updating a flipping indicator of a variable node, comparing the flipping indicator of the variable node with a flipping threshold associated with the decoding process, flipping a bit of the variable node when the flipping indicator is greater than the flipping threshold, and ending the decoding process when decoding is determined to be successful or a maximal iteration number is reached.. . ... Sk Hynix Inc

05/10/18 / #20180131355

Input buffer circuit

An input buffer circuit is disclosed, which relates to a technology for a receiver circuit including a plurality of input buffers having different characteristics. The input buffer circuit includes a first buffer configured to output a first input signal by buffering a command address received based on a flag signal, a second buffer configured to output a second input signal by buffering the command address based on the flag signal, a first delay matching circuit configured to output a first matching signal by delaying the first input signal by a first delay time, a second delay matching circuit configured to output a second matching signal by delaying the second input signal by a second delay time, and a selection circuit configured to select any one of the first matching signal and the second matching signal based on a selection signal.. ... Sk Hynix Inc

05/10/18 / #20180130945

Electronic device and method for fabricating the same

Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.. ... Sk Hynix Inc

05/10/18 / #20180130837

Image sensor

An image sensor may include a pixel array. The pixel array may include a plurality of sub pixel arrays arranged two-dimensionally, wherein each of the plurality of sub pixel arrays including a plurality of pixel blocks arranged in an m×n (where m and n are natural numbers) matrix structure, and an (m,n+1) pixel block has a planar configuration obtained by inverting a planar configuration of the (m,n) pixel block in an n direction. ... Sk Hynix Inc

05/10/18 / #20180130834

Image sensor and methods for fabricating the same

Disclosed is an image sensor, which includes a first pd isolation region for determining first to fourth pd regions, an fd isolation region formed between the first to fourth pd regions, and a floating diffusion formed in the fd isolation region. Horizontal distances from a perimeter of the floating diffusion to interfaces between the fd isolation region and the first to fourth pd regions are equal to each other.. ... Sk Hynix Inc

05/10/18 / #20180130823

Nonvolatile memory device and method of manufacturing the same

Disclosed is a method of manufacturing a nonvolatile memory device. In the method, a stacked structure is formed on a conductive substrate structure. ... Sk Hynix Inc

05/10/18 / #20180130818

Semiconductor memory device

A semiconductor memory device includes a cell array region formed on a substrate, a word line contact region, and a page buffer region coupled to the cell array region through bit lines, wherein at least one of the bit lines has a curved structure toward the word line contact region. According to an embodiment, a misalignment between a cell plug and a contact plug caused by a natural cell plug bending phenomenon may be reduced to improve operational reliability of a semiconductor memory device.. ... Sk Hynix Inc

05/10/18 / #20180130817

Method for manufacturing semiconductor device

Provided herein is a method of manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes: alternately stacked first material layers and second material layers on a lower structure; forming first holes passing through the first material layers and the second material layers, each of the first holes defining a channel region; removing the second material layers through the first holes such that interlayer spaces between the first material layers are formed; and forming, through the first holes, conductive patterns which fill respective interlayer spaces.. ... Sk Hynix Inc

05/10/18 / #20180130814

Semiconductor device and manufacturing method thereof

A semiconductor device includes gate stacked structures surrounding channel layers, a common source line filling a separation area between the gate stacked structures adjacent to each other and having an upper surface including first concave portions, and a support insulating layer filling the first concave portions and having sidewalls facing portions of the channel layers.. . ... Sk Hynix Inc

05/10/18 / #20180130813

Semiconductor device and method of manufacturing the same

A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first channel layers arranged in a first direction. ... Sk Hynix Inc

05/10/18 / #20180130737

Semiconductor memory device

Provided herein is a semiconductor memory device. The semiconductor memory device may include channel layers protruding away from a substrate. ... Sk Hynix Inc

05/10/18 / #20180130547

Repair control device and semiconductor device including the same

A repair control device for memory cells divided into a plurality of banks may include a failed address storage circuit configured to sort and store a plurality of failed addresses each containing a failed bank address and a failed row address, according to the failed row address, and store the failed row address by matching the failed row address with total failed bank information representing one or more failed banks indicated by the failed row address. The repair control device also includes an address comparison circuit configured to compare an input address to a pair comprised of the failed row address and the total failed bank information, stored in the failed address storage circuit, and generate a hit signal based on the comparison result. ... Sk Hynix Inc

05/10/18 / #20180130544

Semiconductor device and operating method thereof

A method of operating a semiconductor memory device includes applying a program pulse at least once to each of a plurality of pages; performing a pre-read operation on a reference page among the plurality of pages through an initial test voltage; repeating the pre-read operation by controlling the initial test voltage until a result of the pre-read operation is a pass; setting the initial test voltage of when the result of the pre-read operation is the pass as a reference test voltage; and detecting a defective page among the plurality of pages by performing read operations on the plurality of pages through the reference test voltage.. . ... Sk Hynix Inc

05/10/18 / #20180130540

Semiconductor memory device with improved program verification reliability

A semiconductor memory device includes a memory cell array including first and second groups of memory strings respectively coupled to first and second groups of bit-lines, wherein the first and second groups of memory strings respectively include first and second groups of selection transistor cells; a peripheral circuit suitable for applying a program voltage, and performing program verification operation for the memory cell array; and a control logic suitable for controlling the peripheral circuit to perform a first program verification operation for the first group of selection transistor cells and a second program verification operation for the second group of selection transistor cells.. . ... Sk Hynix Inc

05/10/18 / #20180130537

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device; and a controller suitable for controlling the nonvolatile memory device, wherein the controller performs a first read retry voltage setting operation, performs a first read retry control operation, performs a second read retry voltage setting operation after an internal operation time of the nonvolatile memory device according to the first read retry control operation passes, and performs a second read retry control operation.. . ... Sk Hynix Inc

05/10/18 / #20180130535

Semiconductor memory device and method of operating the same

Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device in accordance with an embodiment may include a memory cell array, a peripheral circuit, and a control circuit. ... Sk Hynix Inc

05/10/18 / #20180130527

Phase changeable memory device having a cross point array structure

A phase changeable memory device may include a plurality of word lines, a plurality of bit lines, a memory cell, at least one source line, and a discharge unit. The bit lines may cross the word lines. ... Sk Hynix Inc

05/10/18 / #20180130526

Method for refreshing memory cells and memory system

A method for refreshing memory cells includes: reading data from a plurality of memory cells; and performing a write operation with a first data onto memory cells from which the first data is read among the plurality of memory cells.. . ... Sk Hynix Inc

05/10/18 / #20180130523

Data output circuit and semiconductor memory device including the same

A data output circuit includes: a first data latch unit enabled in response to a first bank selection signal including clock information, for storing first lower bank data and first upper bank data in response to a first input control signal, and outputting lower preliminary output data and upper preliminary output data in response to an output control signal; a second data latch unit enabled in response to a second bank selection signal including clock information, for storing second lower bank data and second upper bank data in response to a second input control signal, and outputting the lower preliminary output data and the upper preliminary output data in response to the output control signal; and a data output unit for driving the lower preliminary output data to send rising output data, and synchronizing the upper preliminary output data with the clock to send falling output data.. . ... Sk Hynix Inc

05/10/18 / #20180130518

Dual interlocked storage cell (dice) latch sharing active region with neighbor dice latch and semiconductor device including the same

A dual interlocked storage cell (dice) latch may be provided. A semiconductor device may be provided. ... Sk Hynix Inc

05/10/18 / #20180130517

Semiconductor memory device and operating method thereof

Various embodiments of the invention relate generally to an electronic device, and more particularly, to a semiconductor memory device and an operating method thereof. A semiconductor memory device including a plurality of memory cells using an optimal input buffer reference voltage may include at least one input buffer receiving data to be stored in the plurality of memory cells and an input buffer reference voltage control unit setting one of a plurality of internal voltages having different voltage levels as a reference voltage of the at least one input buffer in response to a control signal.. ... Sk Hynix Inc

05/10/18 / #20180130516

Training controller, and semiconductor device and system including the same

A training controller, semiconductor device and a system including the same are disclosed, which relates to technology for training a phase of data. The training controller may include a read training circuit configured to control a read training operation based on a read signal and a control signal. ... Sk Hynix Inc

05/10/18 / #20180130512

Electronic device and method for fabricating the same

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an under layer including first and second metal layers and a barrier layer having a dual phase structure of different crystal structures and interposed between the first and second metal layers; a first magnetic layer positioned over the under layer and having a variable magnetization direction; a tunnel barrier layer positioned over the first magnetic layer; and a second magnetic layer positioned over the tunnel barrier layer and having a pinned magnetization direction, and the under layer may further include a barrier layer having a dual phase structure between the first and second metal layers.. ... Sk Hynix Inc

05/10/18 / #20180130507

Memory device

A memory device includes: a plurality of bank groups each comprising one or more banks; a first bus coupled to the plurality of bank groups; a second bus coupled to the plurality of bank groups; a toggle signal generation unit suitable for generating a first signal which toggles in response to a column command signal and a second signal having the opposite logic value of the first signal; a column command transmission unit suitable for transmitting a read command signal or write command signal to the first bus when the first signal is activated, and transmitting the read command signal or write command signal to the second bus when the second signal is activated; and a column address transmission unit suitable for transmitting one or more column address signals corresponding to the read command signal or write command signal to a bus to which the read command signal or write command signal is transmitted, between the first and second buses.. . ... Sk Hynix Inc

05/10/18 / #20180129932

Neuromorphic device having an error corrector

A neuromorphic device includes a pre-synaptic neuron, a synapse electrically coupled to the pre-synaptic neuron through a row line, and a post-synaptic neuron electrically coupled to the synapse through a column line. The post-synaptic neuron includes an integrator, a comparator, and an error corrector including an error detector and a correction signal generator. ... Sk Hynix Inc

05/10/18 / #20180129809

Semiconductor memory system and operating method thereof

A semiconductor memory system and an operating method thereof includes: a one-time-programmable memory device storing at least a customer identification (id) identifying a customer; a memory device; and a memory controller including a processor, and coupled to the memory device, containing instructions executed by the processor, and suitable for authenticating whether a program is authorized by a controller provider for the customer in a first-level signature authentication, in accordance with a customer image format, authenticating whether the program is authorized by the customer in a second-level signature authentication, in accordance with a program image format, after the first-level signature authentication is passed, when the customer image indicates the second-level signature authentication, wherein the program image format is different than the customer image format, storing the program into the memory device after the first-level signature authentication and second-level signature authentication are passed, and executing the program after the program is authenticated.. . ... Sk Hynix Inc

05/10/18 / #20180129621

Apparatus and method for accessing data in memory

Disclosed are a direct memory access (dma) apparatus and method. The dma apparatus may include memory, a buffer, a dma controller suitable for setting group regions from which data of the memory is to be read, reading data of each odd-numbered group region in a first direction and writing the read data of each odd-numbered group region in the buffer in the first direction, and reading data of each even-numbered group region in the first direction and writing the read data of each even-numbered group region in the buffer in a second direction, and a read module suitable for reading the data of each odd-numbered group region written in the buffer in the second direction and reading the data of each even-numbered group region in the first direction.. ... Sk Hynix Inc

05/10/18 / #20180129565

Memory system and operation method thereof

The memory system includes a bch error correction circuit suitable for generating a bch error correction code using a first write data which is a portion of a write data from a host, a hamming error correction circuit suitable for generating a hamming error correction code using a second write data which is a remaining portion of the write data, a plurality of first memory devices suitable for storing first write data and the bch error correction code, and one or more second memory devices suitable for storing the second write data and the hamming error correction code.. . ... Sk Hynix Inc

05/10/18 / #20180129560

Memory device and semiconductor package including the same

A semiconductor package includes: memory devices that are stacked one on another; and an inter-layer channel for communication between the memory devices, wherein each memory device includes: a data pad; a memory core; a data input/output circuit that inputs/outputs data through the data pad; an inter-layer channel transfer circuit that transfers a read data transferred from the memory core to the inter-layer channel or transfers a data inputted through the data input/output circuit to the inter-layer channel; an inter-layer channel reception circuit receiving the data of the inter-layer channel; a read error correction circuit correcting an error of the data transferred from the inter-layer channel reception circuit to produce an error-corrected data and transfers the error-corrected data to the data input/output circuit; and a write error correction circuit generating a parity data to be stored in the memory core based on the data transferred from the inter-layer channel reception circuit.. . ... Sk Hynix Inc

05/10/18 / #20180129559

Semiconductor memory device, controller, and operating methods thereof

A semiconductor memory device includes a memory cell array, a read/write circuit, a control logic, and a block defect information storage unit. The control logic controls the read/write circuit to perform a read/write operation on the memory cell array. ... Sk Hynix Inc

05/10/18 / #20180129445

Memory system and operating method thereof

A memory system may include: a memory device; and a controller configured to: perform a read operation and an erase operation to the memory device; predict a first required time when a read command is received during the performing of the erase operation, the first required time being based on a sum including a first time required for the read operation in response to the read command and a second time required for the on-going erase operation; and determine whether to halt or continue the erase operation according to the first required time.. . ... Sk Hynix Inc

05/10/18 / #20180129430

Cyclically interleaved xor array for error recovery

Memory systems may include a memory storage including at least a first stripe and a second stripe, the first stripe including data pages corresponding to the first stripe and a first parity page suitable for storing a first xor parity, and the second stripe including data pages corresponding to the second stripe and a second parity page suitable for storing a second xor parity, the data pages and parity pages being stored over a plurality of memory dies, wherein each memory die includes a number of planes; and a controller suitable for cyclically interleaving the data pages corresponding to the first stripe and the data pages corresponding to the second stripe.. . ... Sk Hynix Inc

05/10/18 / #20180129425

Data management system and method for processing distributed data

A data management system and method for processing distributed data, which adaptively adjusts the amounts of data to be read from a plurality of storages, depending on i/o performances of the respective storages, thereby improving the performance.. . ... Sk Hynix Inc

05/10/18 / #20180129418

Memory controller, memory module, and memory system and operation methods thereof

A memory controller may be provided. A memory module may be provided. ... Sk Hynix Inc

05/03/18 / #20180124337

Pixel biasing apparatus with noise cancellation function, and cmos image sensor including the same

An image sensor device is provided to include: a pixel bias voltage sampling unit suitable for sampling a pixel bias voltage; a pixel power noise addition control unit suitable for controlling the magnitude of added pixel power noise; a pixel power noise addition unit suitable for adding pixel power noise to a node of the pixel bias voltage sampled by the pixel bias voltage sampling unit according to control of the pixel power noise addition control unit; and a biasing unit suitable for offsetting pixel power noise transmitted from the pixel by inverting the pixel power noise added by the pixel power noise addition unit.. . ... Sk Hynix Inc

05/03/18 / #20180123600

Clock generation circuit, and semiconductor device and system using the same

A clock generation circuit may include a first clock generator and a second clock generator. The first clock generator may generate a first output clock toggling in synchronization with a rising edge of a first input clock. ... Sk Hynix Inc

05/03/18 / #20180123572

Electronic device

Provided is an electronic device including a ramp signal generation circuit configured to generate a ramp signal having a second slope that is greater by a first level than a first slope which corresponds to an analog gain, and a slope correction circuit configured to correct the second slope of the ramp signal by the first level to obtain the first slope.. . ... Sk Hynix Inc

05/03/18 / #20180123030

Electronic device and method for fabricating the same

A method for fabricating an electronic device including a semiconductor memory includes: forming an etching target layer over a substrate; forming an initial hard mask pattern including a carbon-containing material over the etching target layer; forming a hard mask pattern by doping an impurity which increases a hardness of the carbon-containing material into a surface portion of the initial hard mask pattern; and etching the etching target layer by using the hard mask pattern as an etching barrier.. . ... Sk Hynix Inc

05/03/18 / #20180122898

Semiconductor device with air gap and method for fabricating the same

A semiconductor device may include: a substrate having first and second surfaces; an interlayer dielectric layer having a first opening to expose the first surface; a first plug positioned in the first opening and isolated from a sidewall of the first opening by a pair of gaps; a bit line extended in any one direction while covering the first plug; a second plug including a lower part adjacent to the first plug and an upper part adjacent to the bit line, and connected to the second surface; a first air gap positioned between the first plug and the lower part of the second plug; and a second air gap positioned between the bit line and the upper part of the second plug, and having a larger width than the first air gap.. . ... Sk Hynix Inc

05/03/18 / #20180122854

Electronic device and method for fabricating the same

This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a substrate; an interlayer dielectric layer over the substrate and patterned to include a contact hole; a lower contact structure formed over the substrate in the contact hole; and a variable resistance element formed over and electrically coupled to the lower contact structure, wherein the lower contact structure may include: a spacer formed on sidewalls of the contact hole in the interlayer dielectric layer and having a substantially uniform thickness along a direction perpendicular to a surface of the substrate; a contact plug filling a portion of the contact hole; and a contact pad formed over the contact plug and filling a remaining portion of the contact hole.. ... Sk Hynix Inc

05/03/18 / #20180122771

Semiconductor packages having asymmetric chip stack structure

A semiconductor package may include first chip stack including first chips which are stacked on a package substrate and offset to form a first reverse stepwise sidewall. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate and offset to form a second reverse stepwise sidewall. ... Sk Hynix Inc

05/03/18 / #20180122490

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device including word lines each including one or more pages; and a controller suitable for, in the case where recovery is made to a normal state from a power-off state, searching a word line including an erased page among the word lines, and selecting, when all pages of the word line including the erased page are erased pages, the corresponding word line as a reliability verification word line.. . ... Sk Hynix Inc

05/03/18 / #20180122469

Resistive memory apparatus

A resistive memory apparatus of the technology includes a memory circuit divided into a plurality of partitions and an input/output (i/o) circuit including a plurality of power supply circuits and an output circuit. The plurality of power supply circuits are configured in one-to-one correspondence with the plurality of partitions.. ... Sk Hynix Inc

05/03/18 / #20180122462

Electronic device

An electronic device including a semiconductor memory the semiconductor memory includes one or more resistive storage cells; at least one reference resistance block including at least two reference resistance transistors which are coupled in series; a data sensing block suitable for comparing resistance values of a resistive storage cell selected among the one or more resistive storage cells and the reference resistance block, and sensing data of the selected resistive storage cell; and a reference resistance adjustment block suitable for adjusting the resistance value of the reference resistance block by adjusting gate voltages of the reference resistance transistors.. . ... Sk Hynix Inc

05/03/18 / #20180122461

Resistive memory apparatus

A resistive memory apparatus in accordance with an embodiment may include a memory circuit and a plurality of unit input/output (i/o) circuits. The memory circuit may be divided into a plurality of partitions. ... Sk Hynix Inc

05/03/18 / #20180122454

Address counting circuit, memory device and operating method thereof

An address counting circuit includes an address counter suitable for counting an address in response to a counting signal; and a counting control block suitable for controlling the address counter to skip the address of at least one predetermined value.. . ... Sk Hynix Inc

05/03/18 / #20180122441

Semiconductor device

A semiconductor device includes an input/output control circuit configured to generate a first driving signal and a second driving signal by shifting a latency signal in synchronization with a clock, and generating a strobe signal which toggles according to logic levels of the first driving signal and the second driving signal; and a data input/output circuit configured to latch input data in synchronization with the strobe signal, and outputting the latched input data as output data.. . ... Sk Hynix Inc

05/03/18 / #20180122436

Power control device and semiconductor memory device including the same

A power control device and a semiconductor memory device including the same may be provided. The power control device, may include an amplifier configured to amplify an input signal having a second power-supply voltage level to a first power-supply voltage level having a voltage level different from the second power-supply voltage level. ... Sk Hynix Inc

05/03/18 / #20180122435

Reference selection circuit

A reference selection circuit may be provided. The reference selection circuit may include a plurality of reference drivers configured to respectively output a plurality of reference voltages having different voltage levels, and a plurality of selectors configured to select any one of the plurality of reference voltages based on a selection signal, and output the selected reference voltage to a monitoring pad.. ... Sk Hynix Inc

05/03/18 / #20180121343

Apparatus and method for controlling memory device

An apparatus may include: a memory device suitable for writing data while erasing at least one monitor cell among a plurality of memory cells in a write mode, and reading the at least one monitor cell by supplying a monitor voltage in a monitor mode; and a controller suitable for transmitting a monitor command and address information for reading the at least one monitor cell to the memory device in the monitor mode, and determining whether to perform a reclaim operation based on the values of the at least one monitor cell read by the memory device.. . ... Sk Hynix Inc

05/03/18 / #20180121135

Data processing system and data processing method

A data processing system includes: a memory device suitable for performing an operation corresponding to a command and outputting a memory data; a data collecting device suitable for collecting big data by integrating the command and the memory data at a predetermined cycle or at every predetermined time, splitting the collected big data based on a predetermined unit, and transferring the split big data; and a data processing device suitable for storing the split big data received from the data collecting device in block-based files in a high-availability distributed object-oriented platform (hadoop) distributed file system (hdfs), classifying the block-based files based on a particular memory command, and processing the block-based files.. . ... Sk Hynix Inc

05/03/18 / #20180121097

Memory system and operation method thereof

A memory system may include: a memory device comprising a plurality of memory blocks each having n word line groups; and a controller suitable for: selecting bad memory blocks among the plurality of memory blocks, arranging normal word line groups of the selected bad memory blocks into one or more memory-block-word-line groups each including non-conflicting n normal word line groups, and managing each of the memory-block-word-line groups as a reused memory block.. . ... Sk Hynix Inc

05/03/18 / #20180121096

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of memory dies; and a controller suitable for generating instruction information instructing sequential completion of program operations for the plurality of memory dies in response to a write command and transmitting the write command and the instruction information to the memory device.. . ... Sk Hynix Inc

05/03/18 / #20180120707

Composition for coating photoresist pattern and method for forming fine pattern using the same

Disclosed are a composition for coating a photoresist pattern and a method for forming a fine pattern using the same. The composition for coating a photoresist pattern includes a polymer compound containing a hydroxyl group and an ammonium base, and a solvent. ... Sk Hynix Inc

05/03/18 / #20180120374

Wafer burn-in test circuit and semiconductor memory including the same

A wafer burn-in test circuit may be provided. The wafer burn-in test circuit may include a timing correction unit configured to generate a plurality of timing-compensated input signals by synchronizing a plurality of pulse signals generated according to a plurality of input signals with an input signal among the plurality of input signals. ... Sk Hynix Inc

04/19/18 / #20180109264

Low power crystal oscillation circuits

A crystal oscillation circuit includes a crystal oscillator coupled between an input pad node and an output pad node, a current mirror inverting amplifier configured to have a first input terminal coupled to the input pad node and an output terminal coupled to the output pad node, a detection logic circuit configured to detect a signal of the output pad node to generate an output pad node detection signal, and an automatic control logic circuit configured to apply a pull-up driver control signal to a second input terminal of the current mirror inverting amplifier in response to the output pad node detection signal. The current mirror inverting amplifier operates with a first gain or a second gain lower than the first gain according to the pull-up driver control signal.. ... Sk Hynix Inc

04/19/18 / #20180109255

High voltage output driver with low voltage devices

A high voltage output driver may be provided. The high voltage output driver may include a pull-up driver and a pull-down driver. ... Sk Hynix Inc

04/19/18 / #20180108707

Threshold switching device, method for fabricating the same and electronic device including the same

A threshold switching device may include: a first electrode layer; a second electrode layer; a first insulating layer interposed between the first and second electrode layers, and provided adjacent to the first electrode layer; and a second insulating layer interposed between the first and second electrode layers, and provided adjacent to the second electrode layer, wherein the first and second insulating layers contain a plurality of neutral defects, a concentration of the plurality of neutral defects being at a maximum along a first interface between the first insulating layer and the second insulating layer, and wherein the threshold switching device has an on or off state according to whether electrons are ejected from the plurality of neutral defects.. . ... Sk Hynix Inc

04/19/18 / #20180108674

Semiconductor device and manufacturing method thereof

A semiconductor device includes bit lines extending along a first direction, the bit lines being arranged along a second direction intersecting the first direction, a plurality of channel layers disposed under the bit lines, the plurality of channel layers extending in a third direction perpendicular to a plane extending along the first and second directions and spaced apart along the second direction, so that each channel layer is at least partially overlapped with at least two of the bit lines, and a contact plug extending, from the channel layer, toward one of the bit lines overlapped with the channel layer.. . ... Sk Hynix Inc

04/19/18 / #20180108673

Semiconductor device and manufacturing method thereof

A semiconductor device includes bit lines extending along a first direction, the bit lines being arranged along a second direction intersecting the first direction, a plurality of channel layers disposed under the bit lines, the plurality of channel layers extending in a third direction perpendicular to a plane extending along the first and second directions and spaced apart along the second direction, so that each channel layer is at least partially overlapped with at least two of the bit lines, and a contact plug extending, from the channel layer, toward one of the bit lines overlapped with the channel layer.. . ... Sk Hynix Inc

04/19/18 / #20180108428

Input/output terminal characteristic calibration circuit and semiconductor apparatus including the same

An input/output terminal characteristic calibration circuit may include a plurality of input/output terminals a subset of which is configured to partially and selectively receive a characteristic calibration signal according to an external input, such that characteristics of the input/output terminals corresponding to the characteristic calibration signal are calibrated. The input/output terminal characteristic calibration circuit may also include a characteristic calibration signal generation circuit coupled to the plurality of input/output terminals in common through a test signal line, and configured to provide the characteristic calibration signal to the plurality of input/output terminals in common through the test signal line.. ... Sk Hynix Inc

04/19/18 / #20180108427

Semiconductor memory apparatus

A semiconductor memory apparatus may include a control circuit, a decoding circuit, and a memory circuit. The control circuit may output one of bank group signals as either a first bank group distribution signal or a second bank group distribution signal and output one of data designation addresses as either a first data designation distribution address or a second data designation distribution address, in response to a first test signal and a second test signal. ... Sk Hynix Inc

04/19/18 / #20180108424

Semiconductor device and method for operating the same

A semiconductor device includes a fuse array section suitable for performing program and read operations; a control signal generation section suitable for generating a precharge control signal and a word line control signal; a bit line control section suitable for controlling a precharge operation of a bit line in response to the precharge control signal and a source signal; and a word line control section suitable for controlling activation of a program word line and a read word line for performing the program and read operations in response to the word line control signal, wherein the control signal generation section controls the word line control signal to be activated after a predetermined time from the activation of the precharge control signal.. . ... Sk Hynix Inc

04/19/18 / #20180108419

Memory system with file level secure erase and operating method thereof

An apparatus of a memory system and an operating method thereof include: a plurality of memory devices, wherein each of the plurality of memory devices includes a plurality of blocks, each of the plurality of blocks has multiple pages corresponding to multiple wordlines, respectively; and a memory controller coupled with the plurality of memory devices, wherein the memory controller is configured to determine an overhead of an erase block where a deleted file resides therein, perform file level secure erase operation on the erase block in accordance with at least the overhead, and mark target pages corresponding to the deleted file as “trimmed” in a logic block address (lba) table.. . ... Sk Hynix Inc

04/19/18 / #20180108417

Memory system of 3d nand flash and operating method thereof

An apparatus of a memory system and an operating method thereof include: memory blocks, each of the memory blocks includes strings, each of the stings has flash cells and select gates thereon, wherein the select gates of each of the strings with a same index number in each of the memory blocks are connected with each other, in each of the memory blocks, the strings are divided into groups, each of the groups includes at least one string, and each of the groups has own read counts management thereof.. . ... Sk Hynix Inc

04/19/18 / #20180108411

Resistive memory apparatus, selective write circuit therefor, and operation method thereof

A resistive memory apparatus may include a memory cell array and a selective write circuit. The memory cell array may include a plurality of resistive memory cells coupled between a plurality of word lines and a plurality of bit lines. ... Sk Hynix Inc

04/19/18 / #20180108408

Resistive memory device and memory system including the same

A resistive memory device includes a first region including a first region including a plurality of first resistive memory cells, and a second region including a plurality of second resistive memory cells, wherein the resistive memory device is suitable for applying a first recovery pulse cyclically at a regular interval to the first resistive memory cells for recovering a drift of the first memory cells, and for applying a second recovery pulse to a read target memory cell among the second memory resistive cells.. . ... Sk Hynix Inc

04/19/18 / #20180108407

Voltage regulator and resistance variable memory apparatus having the same

A voltage compensation circuit may be provided. The voltage compensation circuit may include a replica circuit block configured to be selected and driven to generate a resistance value for compensating a voltage level.. ... Sk Hynix Inc

04/19/18 / #20180108406

Resistive memory device and method relating to a read voltage in accordance with variable situations

A resistive memory device and a method may be provided. The resistive memory device may include a reset voltage-detecting circuit, a set voltage-detecting circuit, a control circuit and a read voltage-generating circuit. ... Sk Hynix Inc

04/19/18 / #20180108401

Memory device

A memory device includes a plurality of memory cells, a weak address storage block suitable for storing a weak address of a weak cell of which data retention time is shorter than a reference time, among the plurality of memory cells, a refresh counter suitable for generating a counting address, and an address selection block suitable for outputting a refresh address by selecting one of the counting address and the weak address, wherein, in selecting the counting address, the address selection block selects the weak address for a predetermined period, when a value of at least one preset bit of the counting address is changed.. . ... Sk Hynix Inc

04/19/18 / #20180108400

Memory device and operating method thereof

A memory device includes a plurality of word lines; a plurality of bit lines; a plurality of memory cells, each memory cell coupled to a corresponding word line among the plurality of word lines and a corresponding bit line among the plurality of bit lines; and a control block suitable for controlling at least two word lines among the plurality of word lines to be activated together, and determining whether or not a weak cell exists, based on a voltage of a bit line corresponding to the activated word lines.. . ... Sk Hynix Inc

04/19/18 / #20180108399

Data sense amplification circuit and semiconductor memory device including the same

A semiconductor memory device includes: a first memory cell coupled to a first bit line; a second memory cell coupled to a second bit line; and a sense amplification circuit for sensing and amplifying a voltage difference between the first and second bit lines, wherein the sense amplification circuit includes: a first sense amplifier including a cross-coupled pair of first and second transistors coupled to the first bit line and the second bit line, respectively; a second sense amplifier including a cross-coupled pair of third and fourth transistors coupled to the first and second bit lines, respectively; and an offset supplier for controlling a timing for supplying a voltage of the first bit line to the first transistor and a timing for supplying a voltage of the second bit line to the second transistor according to a selected memory from the first and second memory cells.. . ... Sk Hynix Inc

04/19/18 / #20180108394

Semiconductor device

A semiconductor memory device may include first to fourth data storage regions. The semiconductor memory device may include a first to fourth capacitor groups and a voltage-generating circuit. ... Sk Hynix Inc

04/19/18 / #20180108389

Semiconductor memory device and method for operating the same

Provided herein are a semiconductor memory device and a method for operating the same. The semiconductor memory device includes a memory cell array, a status signal generator, an rb output control unit and a control logic. ... Sk Hynix Inc

04/19/18 / #20180107625

Data transmission systems having a plurality of transmission lanes and methods of testing transmission data in the data transmission systems

A data transmission system is provided. The data transmission system includes a plurality of data transmitters that respectively constitute a plurality of transmission lanes. ... Sk Hynix Inc

04/19/18 / #20180107597

Memory system and method for operating the same

A memory system includes: a memory device; and a memory controller suitable for controlling the memory device, and the memory device includes: a plurality of normal memory cells; a plurality of redundant memory cells; and a soft repair circuit suitable for replacing a portion of normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, and the memory controller controls the soft repair circuit to repair the portion of the normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, commands the memory device to write a secure data in the plurality of the redundant memory cells, and controls the soft repair circuit to recover the repairing of the portion of the normal memory cells with the plurality of the redundant memory cells.. . ... Sk Hynix Inc

04/19/18 / #20180107594

Memory system and operating method thereof

A memory control device may include a buffer memory in which data is accessed by a unit of a slot; and a buffer interface suitable for controlling an access to the buffer memory. The buffer interface may include a mapping table suitable for storing the mapping between multiple virtual slot identification information (vbids) and multiple physical slot identification information (pbids); a buffer allocation unit suitable for determining a start vbid of the mapping table and the number of slots (nid) based on a size of data to write in the buffer memory, and allocating pbids of a free status to a buffer slot sequence in the mapping table, the buffer slot sequence including slots determined based on the start vbid and the nid; and a buffer access unit suitable for accessing data at positions of the pbids of the buffer memory based on the mapping table.. ... Sk Hynix Inc

04/19/18 / #20180107540

Data storage apparatus and operation method thereof

An operation method of a data storage apparatus includes performing a first read operation using an optimal read voltage on read-failed memory cells, performing ecc decoding operation on read data, performing a second read operation using an oversampling read voltage on the read-failed memory cells when the ecc decoding operation fails, determining whether potential error memory cells which are turned on through the optimal read voltage and are turned off through the oversampling read voltage are present in the read data, determining whether neighboring memory cells which share a bit line with the potential error memory cells and are coupled to neighboring word lines are in erased state when the potential error memory cells are present, and inverting bit values corresponding to the potential error memory cells in the read data from the read-failed memory cells through the first read operation when neighboring memory cells are in erased state.. . ... Sk Hynix Inc

04/19/18 / #20180107539

Semiconductor memory device

A semiconductor memory device includes: a normal data storing region suitable for storing normal cell data and outputting n normal cell data to a first local data line in response to one of a plurality of column selection signals, and a parity storing region suitable for storing parity bits and outputting m parity bits to a second local data line in response to at least one of the plurality of the column selection signals, n and m being positive integers, wherein, when m is smaller than n, the parity storing region outputs the m parity bits in response to one of the plurality of the column selection signals, and when m is greater than n, the parity storing region outputs the m parity bits in response to at least two column selection signals that are enabled simultaneously among the plurality of the column selection signals.. . ... Sk Hynix Inc

04/19/18 / #20180107412

Memory system and operating method thereof

A method of rebuild operation of a memory controller, the method includes: searching a reference page information stored in a first memory block when a power is restored after occurrence of a sudden power off; identifying a reference page of a second memory block and storing the reference page information of the reference page into the first memory block when the reference page information is determined not to be stored in the first memory block; and performing a rebuild operation to data stored in the second memory block based on the reference page information stored in the first memory block.. . ... Sk Hynix Inc

04/19/18 / #20180107386

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device including a memory region, the memory region including a plurality of memory units; and a controller suitable for monitoring an elapsed time and a write count of the memory region, and performing a wear leveling operation for at least one memory unit selected among the plurality of memory units depending on a monitoring result.. . ... Sk Hynix Inc

04/12/18 / #20180102392

Image sensor

An image sensor includes: a pixel array including a plurality of unit pixels that are arrayed in two dimensions, wherein each of the plurality of the unit pixels includes: a substrate that including a photoelectric conversion element; a recess pattern formed in the substrate to overlap with the photoelectric conversion element and correspond to a center of the photoelectric conversion element; a first gate suitable for filling at least the recess pattern; a second gate formed over the substrate to overlap with the photoelectric conversion element and to be adjacent to the first gate in a first diagonal direction; and a third gate formed over the substrate to overlap with the photoelectric conversion element and to be adjacent to the first gate in a second diagonal direction which intersects with the first diagonal direction.. . ... Sk Hynix Inc

04/12/18 / #20180102378

Memory device and manufacturing method thereof

There are provided a memory device and a manufacturing method thereof. A method of manufacturing a memory device may include forming, on a substrate, a conductive layer, a sacrificial layer, and a stack structure. ... Sk Hynix Inc

04/12/18 / #20180102314

Semiconductor device

A semiconductor device may be provided. The semiconductor device may include conductive patterns surrounding a channel film. ... Sk Hynix Inc

04/12/18 / #20180102185

Fuse circuit, repair control circuit, and semiconductor apparatus including the same

A fuse circuit may include a plurality of first fuse sets and a plurality of second fuse sets. The plurality of first fuse sets may be used to store a defect address detected before packaging of a semiconductor apparatus. ... Sk Hynix Inc

04/12/18 / #20180102183

Methods of testing cell arrays and semiconductor devices executing the same

A semiconductor device includes a pattern data generation circuit generating pattern data, a data comparison circuit receiving read data which are outputted from cell arrays included in a core area by a read operation and comparing the read data with the pattern data to generate a fail code, and a fail flag generation circuit comparing the fail code with a set code to generate a fail flag.. . ... Sk Hynix Inc

04/12/18 / #20180102172

Memory device and operating method of the memory device

A memory device includes a memory cell array including a plurality of blocks, a power supply unit suitable for generating at least one erase voltage and supplying the at least one erase voltage to the memory cell array, a control logic suitable for receiving multi-block erase information for the same plane, sequentially transmitting block address information included in the multi-block erase information to the row decoder, and outputting an erase control signal to the power supply unit when a last block address information is transmitted, and a row decoder suitable for decoding the block addresses and selecting an erase block of the memory cell array.. . ... Sk Hynix Inc

04/12/18 / #20180102169

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device including a reference memory region and a normal memory region, and suitable for determining whether to perform a refresh operation, based on the reference memory region; and a controller suitable for determining a first memory region in the normal memory region based on wear leveling operation data, and controlling the nonvolatile memory device to perform the refresh operation for a second memory region excluding the first memory region in the normal memory region.. . ... Sk Hynix Inc

04/12/18 / #20180102156

Resistance change memory

According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.. ... Sk Hynix Inc

04/12/18 / #20180102154

Electronic device

In one implementation, an electronic device is provided to include a semiconductor memory, wherein the semiconductor memory may include: a variable resistance element including a magnetic tunnel junction (mtj) structure including a free layer having a changeable magnetization direction free layer, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer, and the electronic device may further include, in a first direction in which the free layer, the tunnel barrier layer and the pinned layer are arranged, a first permanent magnet having a first surface facing a first surface of the variable resistance element and spaced from the variable resistance element, wherein a magnetic field generated by the first permanent magnet may have a direction which offsets or reduces an influence of a stray field generated by the pinned layer.. . ... Sk Hynix Inc

04/12/18 / #20180102150

Semiconductor devices

A semiconductor device may include a valid command generation circuit and a training control circuit. The valid command generation circuit may be configured to latch an internal chip selection signal and an internal control signal in synchronization with a division clock signal to generate a latch chip selection signal and a latch control signal. ... Sk Hynix Inc

04/12/18 / #20180102148

Latch control signal generation circuit and semiconductor devices

A semiconductor device may be provided. The semiconductor device may include a latch control signal generation circuit configured to compare a count signal counted according to the number of times that a command is inputted to the latch control signal generation circuit with a random signal having a random combination to generate a latch control signal which is enabled, based on an update signal. ... Sk Hynix Inc

04/12/18 / #20180101454

Memory system and operation method for the same

A memory system includes: a non-volatile memory device that includes a plurality of memory blocks each of which includes a plurality of pages; and a controller suitable for programming write data together with corresponding write order information in the plurality of the pages during a write operation, wherein when two or more open blocks are detected among the plurality of the memory blocks during a recovery operation, the controller generates an order table where physical page numbers of the pages of the open blocks are arrayed based on the write order information and determines at least one recovery target page among pages of the open blocks based on the order table.. . ... Sk Hynix Inc

04/12/18 / #20180101192

Bus architecture with reduced skew and peak power consumption

Disclosed herein is a bus architecture for transferring data from a bus signal generator to a receiver comprises a plurality of bus lines comprising a plurality of odd bus lines and a plurality of even bus lines, each of the even bus lines being arranged between adjacent odd bus lines; and at least one repeater coupled with the plurality of bus lines, wherein each of the plurality of bus lines comprises a plurality of unit length paths(ulps), wherein the repeater is arranged between adjacent ulps of the bus lines, wherein one of the adjacent ulps is coupled to one among inputs of the repeater and the other of the adjacent ulps is coupled to one among outputs of the repeater for each of the bus lines, wherein either of the odd bus lines or the even bus lines are inverting bus lines.. . ... Sk Hynix Inc

04/12/18 / #20180101187

Trimming circuit and operating method thereof

Disclosed herein is a method for trimming a voltage regulator by a trimming circuit comprising a voltage divider configured to divide a divide reference voltage according to a divider code and to output a first divider output voltage, a comparator configured to receive the first divider output voltage and a compare reference voltage and to output an output voltage of the comparator by comparing the first divider output voltage and the compare reference voltage and a logic unit configured to output the divider code to the voltage divider and to determine a final divider code based on the output voltage of the comparator.. . ... Sk Hynix Inc

04/05/18 / #20180097013

Semiconductor device and manufacturing method thereof

Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer.. . ... Sk Hynix Inc

04/05/18 / #20180097012

Electronic device and method for manufacturing the same

A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.. . ... Sk Hynix Inc

04/05/18 / #20180097010

Semiconductor device and method of manufacturing the same

The semiconductor device includes a stacked structure having alternately stacked conductive patterns and interlayer insulating patterns, a through-hole passing through the stacked structure, a channel pattern formed in the through-hole and protruding from an inside of the through hole over the through-hole, and a capping conductive pattern formed to be in contact with the protruded channel pattern and have a width greater than the through-hole.. . ... Sk Hynix Inc

04/05/18 / #20180096731

Semiconductor device and operating method thereof

A semiconductor device includes: first to nth non-volatile memory areas, each including a plurality of cells positioned at cross points between row lines and column lines; a storage circuit including a plurality of unit latches suitable for storing data transferred from the first to nth non-volatile memory areas; and an operation control circuit suitable for controlling setup information of first to nth operation modes to be programmed in the first to nth non-volatile memory areas, respectively, during a rupture mode, and controlling a data transferred from the first non-volatile memory area to be written in the unit latches and controlling a data transferred from one of the second to nth non-volatile memory areas to be over-written in the unit latches in response to an operation mode change request, during a boot-up mode.. . ... Sk Hynix Inc

04/05/18 / #20180096716

Precharge control device and semiconductor device including the same

A precharge control device includes a pulse generator, a bank address controller, and a precharge signal generator. The pulse generator generates a write precharge signal in response to a write burst end signal activated after a write burst operation and a read precharge signal in response to a read burst end signal activated after a read burst operation. ... Sk Hynix Inc

03/29/18 / #20180091753

Count circuit, method for driving count circuit, and image sensor including count circuit

A count circuit includes a count block suitable for generating count code signals for a predetermined count period including a first period and a second period; and a storage block suitable for storing first bit signals among a plurality of bit signals included in the count code signals, for the first period, and storing remaining bit signals among the plurality of bit signals for the second period.. . ... Sk Hynix Inc

03/29/18 / #20180091124

Buffer circuit, reciever and system using the same

A buffer circuit may include an amplification circuit, a main load circuit, and a sub-load circuit. The amplification circuit and the main load circuit may generate first and second output signals by amplifying first and second input signals. ... Sk Hynix Inc

03/29/18 / #20180091120

Voltage generation circuits, semiconductor devices including the same, and methods of generating voltages

A voltage generation circuit includes a current source connected to a first node to generate a first internal current corresponding to a constant current, a comparison circuit generating a drive voltage whose level is controlled according to a voltage difference between the first node whose voltage level is controlled by the first internal current and a second node, and a charge supply circuit controlling an amount of charge supplied to the first and second nodes from a power supply voltage terminal according to a level of the drive voltage to generate a supply voltage.. . ... Sk Hynix Inc

03/29/18 / #20180090534

Image sensor including depletion inducing layer

An image sensor may include a pixel array where a plurality of unit pixels are arranged in a two dimensional matrix, wherein each of the unit pixels includes: a substrate including a photoelectric conversion element; one or more depletion inducing layers formed in the photoelectric conversion element; an inter-layer dielectric layer formed over the substrate; and one or more floating electrodes formed in the inter-layer dielectric layer to overlap each of the depletion inducing layers.. . ... Sk Hynix Inc

03/29/18 / #20180090383

Stack type semiconductor memory device

A stack type memory device and a method of manufacturing the same are provided. The stack type memory device includes a semiconductor substrate, a plurality of active layers stacked on the semiconductor substrate, and a gate structure overlapping the plurality of active layers. ... Sk Hynix Inc

03/29/18 / #20180090368

Isolation structure and method for manufacturing the same

A method for manufacturing a semiconductor device includes forming a first trench and a second trench in a substrate, the first and the second trenches communicate with each other, the second trench may be formed wider than the first trench; forming a liner layer over an inner surface of the first trench and over an inner surface of the second the trench; forming a capping layer over the liner layer to form a merged overhang and a non-merged overhang, the merged overhang may be fill a top portion of the first trench, the non-merged overhang may be open a top portion of the second trench; and forming a gap-fill layer over the capping layer to fill a lower portion of the first trench and the second trench.. . ... Sk Hynix Inc

03/29/18 / #20180090227

Semiconductor memory device and operating method thereof

A semiconductor memory device includes: a memory array region including normal memory cells and redundant memory cells; a fuse circuit including fuse cells for programming repair addresses, outputting fuse data including the programmed repair addresses and fuse enable signals in response to a boot-up signal; a fuse information storage including n latch circuits for storing the fuse data, wherein each of the n latch circuits drives fuse lines assigned from n fuse lines based on the fuse enable signals and a comparison result of the corresponding repair addresses and an input address; and a repair control circuit generating a repair activation signal and an m-bit repair control signal based on signals of the n fuse lines, and outputting the m-bit repair control signal to multiple address lines by selectively mapping the m-bit repair control signal to some bits of the input address, based on the repair activation signal.. . ... Sk Hynix Inc

03/29/18 / #20180090224

Semiconductor memory device and method of operating the same

Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit configured to control the memory cell array, the peripheral circuit including a first region disposed under the memory cell array and a second region; and a fall sensing unit configured to sense whether a failure has occurred in the first or the second regions.. ... Sk Hynix Inc

03/29/18 / #20180090221

Boot-up control circuit and semiconductor apparatus including the same

A boot-up control circuit may be provided. The boot-up control circuit may include a fuse array including a one or more normal fuses and one or more dummy fuses. ... Sk Hynix Inc

03/29/18 / #20180090217

Memory device and operating method thereof

There are provided a memory device and an operating method thereof. A memory device may include a memory block, peripheral circuits, and a control logic. ... Sk Hynix Inc

03/29/18 / #20180090209

Semiconductor memory device and method for operating the same

Provided herein are a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes a memory cell array including a memory cell array including a plurality of memory cells, a peripheral circuit configured to perform a program operation, which includes a plurality of program loops, on selected memory cells among the plurality of memory cells and a control circuit configured to control the peripheral circuit so that a program voltage applied to a selected word line, to which the selected memory cells are coupled, is stepwisely increased from a program start voltage to a target program voltage by a step voltage, which is a voltage increment of the program voltage, during a preset time period of a respective program loop.. ... Sk Hynix Inc

03/29/18 / #20180090199

Refresh control device

A refresh control device may include a first oscillator configured to generate a first oscillation signal, a second oscillator configured to generate a second oscillation signal having a different cycle from the first oscillation signal, a first address controller configured to latch an address in response to the first oscillation signal, and output the latched address when a refresh signal is enabled. The refresh control device may also include a second address controller configured to latch the address in response to the second oscillation signal, and output the latched address when the refresh signal is enabled. ... Sk Hynix Inc

03/29/18 / #20180090196

Semiconductor device relating to generate target address to execute a refresh operation

A semiconductor device may be provided. The semiconductor device may include a target address storage circuit and a first row address generation circuit. ... Sk Hynix Inc

03/29/18 / #20180090192

Semiconductor device and method thereof

A semiconductor device may be provided. The semiconductor device may include an address conversion circuit configured for generating a converted address. ... Sk Hynix Inc

03/29/18 / #20180090190

Semiconductor device and semiconductor system

A semiconductor device includes a comparison circuit suitable for comparing a reference voltage and a strobe signal, and generating a first comparison strobe signal. The semiconductor device also includes a reference voltage training circuit suitable for sequentially changing a voltage level of the reference voltage if a training mode is entered, and setting the voltage level of the reference voltage by sensing a duty ratio of the first comparison strobe signal.. ... Sk Hynix Inc

03/29/18 / #20180090184

Apparatus and method for controlling memory

This technology relates to a memory control apparatus for processing data into a memory device and an operating method of the memory control apparatus. A method for controlling a memory may include converting received program data with a first address into compressed data, searching a deduplication table including compressed data, a second address of a memory device in which non-compressed data corresponding to the compressed data has been written and a counter indicative of the write number of the data for the converted compressed data, and if the converted compressed data is searched for in the deduplication table, mapping a second address corresponding to the compressed data in the deduplication table to the first address, not performing a write operation of the memory device for the received program data, and updating the deduplication table.. ... Sk Hynix Inc

03/29/18 / #20180089562

Operation apparatus and method for convolutional neural network

Disclosed herein is a convolutional neural network (cnn) operation apparatus, including at least one channel hardware set suitable for performing a feature extraction layer operation and a classification layer operation based on input data and weight data, and a controller coupled to the channel hardware set. The controller may control the channel hardware set to perform the feature extraction layer operation and perform a classification layer operation when the feature extraction layer operation is completed.. ... Sk Hynix Inc

03/29/18 / #20180088848

Memory module and method system including the same

A memory module includes: a front interface suitable for performing a serial-to-parallel conversion of a command, an address, and data that are received from a host memory controller; a module controller suitable for communicating with the host memory controller through the front interface; and a memory device suitable for receiving the command and the address from the module controller and transferring and receiving data to and from the module controller. The number of lines for transferring the command, the address, and the data between the host memory controller and the front interface is greater than the number of lines for transferring the command, the address, and the data between the module controller and the memory device.. ... Sk Hynix Inc

03/29/18 / #20180088840

Memory system and operating method for the same

A memory system includes a memory device including one or more memory blocks, and configured to store data in a plurality of pages included in each memory block through a write operation, and a memory controller configured to count an operation number of write operations performed on the memory block, check whether the write operation is performed for each of the pages, select one or more victim pages among the pages, and copy data stored in the victim pages.. . ... Sk Hynix Inc

03/22/18 / #20180084213

Comparison device and image sensor including the same

A comparison device includes a comparison block suitable for comparing an upper ramp signal or a lower ramp signal with a pixel signal, and outputting a comparison signal; a cds block provided between a first input terminal into which the pixel signal is inputted and a negative input terminal of the comparison block, and configured to perform correlated double sampling; a second switch provided between a second input terminal into which the lower ramp signal is inputted and a positive input terminal of the comparison block; a third switch provided between a third input terminal into which the upper ramp signal is inputted and the positive input terminal of the comparison block; and a feedback control unit suitable for checking a magnitude of the pixel signal according the comparison signal and outputting a second control signal or a third control signal for controlling the second or third switch.. . ... Sk Hynix Inc

03/22/18 / #20180083616

Power-up signal generation circuit and semiconductor device including the same

A power-up signal generation circuit including a pre-power-up signal generation block operates by using a first power supply voltage, and generates a pre-power-up signal when the first power supply voltage becomes higher than a first level, and a second power supply voltage becomes higher than a second level; a level shifting block suitable for pull-down driving a first node when the pre-power-up signal is not in an activated state, and pull-up driving the first node with the second power supply voltage when the pre-power-up signal is in the activated state; a driving block suitable for pull-down driving the first node when the second power supply voltage is lower than the second level; and a power-up signal driving block operates by using the second power supply voltage, and generates a power-up signal through a second node by driving the second node based on a voltage level of the first node.. . ... Sk Hynix Inc

03/22/18 / #20180083035

Electronic device and method for fabricating the same

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate; and a stepped structure including first interlayer dielectric layers and conductive layers which are alternately stacked over the substrate, wherein ends of the conductive layers are exposed along the profile of the stepped structure, and the stepped structure further includes a barrier layer formed on a sidewall of the conductive layer.. ... Sk Hynix Inc

03/22/18 / #20180082949

Fuse structure and method of manufacturing the same

A fuse structure may include an anode pattern, a cathode pattern and a connection member. The anode pattern may be formed on a semiconductor substrate. ... Sk Hynix Inc

03/22/18 / #20180082892

Semiconductor device and manufacturing method thereof

Provided herein is a method of manufacturing a semiconductor device. The method may include forming an amorphous channel layer. ... Sk Hynix Inc

03/22/18 / #20180082754

Semiconductor device

A semiconductor device may be provided. The semiconductor device may be configured for detecting a defect of a fuse set. ... Sk Hynix Inc

03/22/18 / #20180082752

Semiconductor memory device and operating method thereof

Provided herein is a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell array and a control logic. ... Sk Hynix Inc

03/22/18 / #20180082749

Eprom device for storing multi-bit data and read circuit of eprom device

An eprom device may include a unit cell, a switching unit, a multiplexer, and a comparator. The unit cell may be disposed between a bit line, which is coupled to a program voltage supply line, and a ground voltage terminal. ... Sk Hynix Inc

03/22/18 / #20180082748

Control circuit, peripheral circuit, semiconductor memory device and method of operating the same

Provided herein may be a control circuit, peripheral circuit, semiconductor memory device and methods of operating the device and circuits. The method of operating a semiconductor memory device may include applying a control signal having a form, in which a step pulse is combined with a ramp signal, to a gate electrode of a transistor for setting up a voltage of a bit line of the selected memory cell. ... Sk Hynix Inc

03/22/18 / #20180082744

Semiconductor memory device

Disclosed is a semiconductor memory device. The semiconductor memory device includes: a first memory block; and a second memory block sharing a block word line with the first memory block, in which the block word line includes a first block word line disposed so as to overlap the first memory block and a second block word line disposed so as to overlap the second memory block. ... Sk Hynix Inc

03/22/18 / #20180082741

Resistive memory apparatus and line selection circuit thereof

A resistive memory apparatus includes a memory cell array, a local switch, and a global switch. The memory cell array may include a plurality of resistive memory cells coupled to a plurality of connection lines. ... Sk Hynix Inc

03/22/18 / #20180082740

Resistance variable memory apparatus

A resistance variable memory apparatus includes a memory cell array region and a peripheral region disposed along an edge of the memory cell region. The memory cell array region may have a plurality of memory banks each of which includes at least one memory block. ... Sk Hynix Inc

03/22/18 / #20180082739

Voltage controlling circuit

A voltage controlling circuit may include a first voltage terminal, a second voltage terminal and a plurality of ovonic threshold switch (ots) units. The second voltage terminal may have a voltage different from that of the first voltage terminal. ... Sk Hynix Inc

03/22/18 / #20180082737

Address decoder and active control circuit and semiconductor memory including the same

An address decoder includes decoding logic configured to generate a decoding address by decoding one of a first die id having a value according to a first operation mode, a second die id having a value according to a second operation mode, and a bank address according to a signal having different values in the first operation mode and the second operation mode.. . ... Sk Hynix Inc

03/22/18 / #20180082736

Refresh control device

A refresh control device for reducing power consumption during a target row refresh operation is disclosed. The refresh control device includes a refresh address generator configured to generate a refresh address by selecting any one of a target row refresh address and a normal refresh address according to a target row refresh flag signal, an address control signal generator configured to generate a multiple address control signal in response to the target row refresh flag signal and a multiple refresh signal, and a final refresh address generator configured to generate a plurality of final refresh addresses from the refresh address in response to the multiple address control signal.. ... Sk Hynix Inc

03/22/18 / #20180082734

Semiconductor memory device

Provided herein is a semiconductor memory device. The semiconductor memory device may include a memory cell array including a plurality of memory cells coupled to a plurality of bit lines and a page buffer circuit coupled to the plurality of bit lines and including a plurality of page buffers, wherein the plurality of page buffers sense program states of the plurality of memory cells through the plurality of bit lines during a verify operation or a read operation of a program operation, and wherein the plurality of page buffers perform in an alternate way a latch operation for latching sensing data in accordance with current amounts of the plurality of bit lines.. ... Sk Hynix Inc

03/22/18 / #20180082731

Semiconductor memory device and operating method thereof

A semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell array, a peripheral circuit and a control logic. ... Sk Hynix Inc

03/22/18 / #20180082727

Electronic device including a semiconductor memory

This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a contact plug; a first stack structure disposed over the contact plug and coupled to the contact plug, wherein the first stack structure includes a pinning layer controlling a magnetization of a pinned layer; and a second stack structure disposed over the first stack structure and coupled to the first stack structure, wherein the second stack structure includes a mtj (magnetic tunnel junction) structure which includes the pinned layer having a pinned magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer interposed between the pinned layer and the free layer, wherein a width of the first stack structure is larger than a width of the contact plug and a width of the second stack structure.. ... Sk Hynix Inc

03/22/18 / #20180082723

Semiconductor memory apparatus

A semiconductor memory apparatus includes a write control circuit suitable for generating a write cancel signal and a rewrite signal in response to a voltage level of a write voltage in a write operation, and a driving circuit suitable for transferring data to a data storage region in response to the write cancel signal and the rewrite signal in the write operation.. . ... Sk Hynix Inc

03/22/18 / #20180081582

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device; a control unit suitable for generating a descriptor in which works for controlling the nonvolatile memory device are described; a memory control unit suitable for performing a control operation for the nonvolatile memory device and a data input operation, based on the descriptor; and a calibrator suitable for performing a calibration operation for a signal to be provided to the nonvolatile memory device, in response to an enable signal provided from the memory control unit, wherein the memory control unit controls the calibrator such that the control operation for the nonvolatile memory device and the calibration operation of the calibrator are performed in parallel.. . ... Sk Hynix Inc

03/22/18 / #20180081576

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of memory blocks each memory block having a plurality of pages; and a controller suitable for checking parameters and deviations of the parameters for the respective memory blocks, which are recorded in a count information, and selecting source memory blocks among the memory blocks based on a result of the checking.. . ... Sk Hynix Inc

03/22/18 / #20180081552

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of memory blocks each memory block having a plurality of pages; and a controller suitable for performing a plurality of operations to first memory blocks among the memory blocks at a first time, recording a checkpoint information for the operations in the memory blocks, selecting second memory blocks among the first memory blocks through the checkpoint information at a second time after a power-off in the memory system while performing the operations, and performing a dummy write operation to the second memory blocks.. . ... Sk Hynix Inc

03/22/18 / #20180081551

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of memory blocks each memory block having a plurality of pages; and a controller suitable for performing a program operation of storing data segments and meta segments in the pages, and recording a checkpoint information for the program operation in the pages.. . ... Sk Hynix Inc

03/22/18 / #20180081545

Resistance variable memory apparatus, and circuit and method for operating therefor

A resistance variable memory apparatus may include a memory circuit configured to include a plurality of blocks, each including a plurality of memory cells. The resistance variable memory apparatus may include a disturbance preventing circuit configured to be driven based on a counting signal corresponding to the number of write access for each of the plurality of blocks, a write command, and an address signal and to allow scrubbing to be performed on a memory cell having a preset scrubbing condition when the counting signal satisfied with the scrubbing condition is output based on the scribing condition according to a physical position of the memory cell in the block.. ... Sk Hynix Inc

03/15/18 / #20180076709

Charge pump switching controller for reducing standby current and charge pumping apparatus using the same

A charge pumping apparatus in accordance with an embodiment may include a charge pump output voltage detector, a pump oscillator, and a charge pump switching controller. The charge pump output voltage detector may detect a charge pump output voltage, and may selectively output an enable signal according to the detected charge pump output voltage. ... Sk Hynix Inc

03/15/18 / #20180076218

Semiconductor device and method of manufacturing the same

There is provided a semiconductor device. The semiconductor device includes a source layer, a well pickup layer formed on the source layer, a body structure formed on the well pickup layer and including a well region contacting the well pickup layer and first junctions formed on side walls of the body structure, channel pillars contacting the body structure and protruding from the body structure, and contact layers formed on the side walls of the body structure and electrically connecting the body structure and the well pickup layer.. ... Sk Hynix Inc

03/15/18 / #20180076022

Method of treating semiconductor substrate

In a method of treating a semiconductor substrate, a plurality of active regions and a plurality of trench isolation regions are formed by selectively etching the semiconductor substrate. The semiconductor substrate is washed by providing deionized water to the semiconductor substrate. ... Sk Hynix Inc

03/15/18 / #20180075916

Memory device and operating method thereof

Provided herein are a memory device and an operating method thereof. The memory device may include a plurality of memory blocks and one or more peripheral circuits. ... Sk Hynix Inc

03/15/18 / #20180075915

High voltage switch circuit and semiconductor memory device including the same

Disclosed are a high voltage switch circuit and a semiconductor memory device including the same. The high voltage switching circuit includes: a control signal generating circuit configured to supply a supply voltage to an internal node and generate a control signal in response to a first enable signal; a well bias generating circuit configured to apply a well bias to a well of a transistor included in the control signal generating circuit in response to a second enable signal; and a switching circuit configured to switch an input voltage to an output voltage in response to the control signal.. ... Sk Hynix Inc

03/15/18 / #20180075910

Semiconductor memory device and method of operating the same

Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory cell array including a plurality of memory cells, a status signal generator configured to output an internal status signal indicating whether an operation of the memory cell array has been completed or is being performed and a ready/busy line input mode control unit configured to output a ready/busy signal through a ready/busy line based on the internal status signal or to receive an input signal from an external device through the ready/busy line.. ... Sk Hynix Inc

03/15/18 / #20180075909

Semiconductor memory device and method of operating the same

A semiconductor memory device in accordance with an embodiment may include a memory cell array, a peripheral circuit, and a control circuit. The memory cell array may include a plurality of memory cells programmed to any one of first to n-th program states divided based on threshold voltages. ... Sk Hynix Inc

03/15/18 / #20180075905

Electronic device

Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory unit including one or more column, a data line, and a data line bar connected with a column selected among the one or more columns. Each of the one or more columns may include a plurality of storage cells each configured to store 1-bit data, each storage cell including a first and a second variable resistance elements; a bit line connected to one end of the first variable resistance element; a bit line bar connected to one end of the second variable resistance element; a source line connected to the other ends of the first and second variable resistance elements; and a driving block configured to latch data of the data line and the data line bar.. ... Sk Hynix Inc

03/15/18 / #20180075885

Semiconductor device and system performing calibration operation

A semiconductor device may include a calibration circuit and an output circuit. The calibration circuit may perform a calibration operation for setting a resistance value of the output circuit. ... Sk Hynix Inc

03/15/18 / #20180075344

Neural network hardware accelerator architectures and operating method thereof

A memory-centric neural network system and operating method thereof includes: a processing unit; semiconductor memory devices coupled to the processing unit, the semiconductor memory devices contain instructions executed by the processing unit; a weight matrix constructed with rows and columns of memory cells, inputs of the memory cells of a same row are connected to one of axons, outputs of the memory cells of a same column are connected to one of neurons; timestamp registers registering timestamps of the axons and the neurons; and a lookup table containing adjusting values indexed in accordance with the timestamps, the processing unit updates the weight matrix in accordance with the adjusting values.. . ... Sk Hynix Inc

03/15/18 / #20180075339

Neural network hardware accelerator architectures and operating method thereof

A memory-centric neural network system and operating method thereof includes: a processing unit; semiconductor memory devices coupled to the processing unit, the semiconductor memory devices contain instructions executed by the processing unit; weight matrixes including a positive weight matrix and a negative weight matrix constructed with rows and columns of memory cells, inputs of the memory cells of a same row are connected to one of axons, outputs of the memory cells of a same column are connected to one of neurons; timestamp registers registering timestamps of the axons and the neurons; and a lookup table containing adjusting values indexed in accordance with the timestamps, the processing unit updates the weight matrixes in accordance with the adjusting values.. . ... Sk Hynix Inc

03/15/18 / #20180074989

Semiconductor device

A semiconductor device includes: various types of memories; an interface configured to transmit memory characteristic information of the memories to a host, receive information needed to control operations of the memories from the host, and perform interfacing between the host and the memories; and a controller configured to control operations of the memories in response to information received from the host, and control an operation of the interface.. . ... Sk Hynix Inc

03/15/18 / #20180074895

Semiconductor device, semiconductor system, and method thereof

A semiconductor system may be provided. The semiconductor system may include a first semiconductor device configured for outputting a command and an address, and inputting/outputting data. ... Sk Hynix Inc

03/15/18 / #20180074718

Memory system and method for operating the same

A memory system includes: a nonvolatile memory device; a volatile memory; and a controller suitable for storing a plurality of operation information and a plurality of version information, and selectively copying updated operation information from the volatile memory into the nonvolatile memory device at a predetermined moment based on the plurality of version information, the plurality of operation information may be respectively to be used during the plurality of predetermined operations to the nonvolatile memory device, and the plurality of version information respectively may represent whether the plurality of operation information are updated or not.. . ... Sk Hynix Inc

03/15/18 / #20180074711

Memory system and method for operating the same

A memory system includes: a nonvolatile memory device that includes a plurality of memory blocks; a volatile memory device; and a controller suitable for grouping the plurality of the memory blocks by a predetermined number of memory blocks into k block groups, storing in the volatile memory k operation information groups and k version information groups, and selectively copying updated operation information in the k operation information groups from the volatile memory into the nonvolatile memory device at a predetermined moment based on the k version information groups.. . ... Sk Hynix Inc

03/15/18 / #20180074710

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of pages in which data are stored and a plurality of memory blocks which include the pages; and a controller suitable for storing data segments of user data corresponding to a write command received from a host, in the pages included in the memory blocks, generating map segments of map data corresponding to storage of the data segments and lists, and searching and updating the map segments through the lists.. . ... Sk Hynix Inc

03/15/18 / #20180074419

Methods of forming patterns using nanoimprint lithography

A method of forming patterns is provided. The method includes forming a resist layer on a substrate, imprinting transfer patterns of a template on the resist layer, performing an alignment operation to correct a position of the substrate or the template, increasing a viscosity of the resist layer while the alignment operation is performed, and curing the resist layer after the alignment operation terminates.. ... Sk Hynix Inc

03/15/18 / #20180074396

Photomask including transfer patterns for reducing a thermal stress

A photomask includes a light transmission substrate, a plurality of pattern regions disposed over the light transmission substrate, a shape of the plurality of pattern regions being transferred onto a wafer during an exposure process, and a light blocking region surrounding the plurality of pattern regions. Each of the plurality of pattern regions is a light transmitting region that exposes a portion of the light transmission substrate. ... Sk Hynix Inc

03/08/18 / #20180069532

Duty correction device and semiconductor device including the same

A duty correction device may be provided. The duty correction device may include a duty controller configured to output a control signal by controlling a duty of a duty corrected signal, and detect a level of a feedback signal to convert the duty based on a code signal which is applied at a section where the level of the feedback signal corresponds to a logic level. ... Sk Hynix Inc

03/08/18 / #20180069037

Stacked image sensor having an air gap

A stacked image sensor includes: a lower device including a lower inter-layer dielectric layer over an upper surface of a lower substrate, and a lower capping layer over the lower inter-layer dielectric layer; an upper device stacked over the lower device, including photodiodes in an upper substrate, an upper inter-layer dielectric layer below a lower surface of the upper substrate, and an upper capping layer below the upper inter-layer dielectric layer; and an air gap formed between the lower inter-layer dielectric layer and the upper inter-layer dielectric layer.. . ... Sk Hynix Inc

03/08/18 / #20180069036

Image sensor having guard dams

An image sensor is described. The image sensor may include a substrate including a pixel area, a logic area, and a guard area disposed between the pixel area and the logic area. ... Sk Hynix Inc

03/08/18 / #20180069021

Semiconductor device and method of manufacturing the same

A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and one or more openings. The pad structure may be disposed between the first cell structure and the second cell structure, and may be electrically coupled to the first and second cell structures. ... Sk Hynix Inc

03/08/18 / #20180068996

Electro-static discharge protection devices having a low trigger voltage

An electro-static discharge (esd) protection device includes a first pn diode, a second pn diode and a silicon controlled rectifier (scr). The first pn diode and the second pn diode are coupled in series between a pad and a ground voltage to provide a first discharge current path. ... Sk Hynix Inc

03/08/18 / #20180068981

Semiconductor apparatus and semiconductor system including the same

A semiconductor apparatus may include a package substrate, and a plurality of semiconductor chips. Wherein the package substrate and the semiconductor chips may be configured based on a load value of the semiconductor apparatus.. ... Sk Hynix Inc

03/08/18 / #20180068743

Test methods of semiconductor devices and semiconductor systems used therein

A semiconductor system includes a medium controller and a semiconductor module. The medium controller outputs an address that is sequentially counted in a test mode, senses levels of data corresponding to the address in the test mode to determine if the data has a row error or a chip error, and changes a combination of a host address to generate and store a spare address if a combination of the address corresponds to the chip error in the test mode. ... Sk Hynix Inc

03/08/18 / #20180068740

Semiconductor memory device and method of operating the same

A semiconductor memory device includes a memory cell array, a read/write circuit and a control logic. The memory cell array includes a plurality of memory cells. ... Sk Hynix Inc

03/08/18 / #20180068736

Memory system and method for operating the memory system

A memory system includes: a memory device; and a controller that is functionally coupled to the memory device, wherein the controller sets a first read bias for distinguishing erased cells and programmed cells from each other, and detects the number of cells that are read in the memory device by controlling a read operation of the memory device based on the first read bias, analyzes the detected number of the cells with the number of reference cells, and when the number of the cells that are read goes out of an error tolerance range, generates a second read bias by offsetting the first read bias.. . ... Sk Hynix Inc

03/08/18 / #20180068733

Semiconductor memory device and programming method thereof

A semiconductor memory device includes a memory cell array, a peripheral circuit and a control logic. The memory cell array includes a plurality of memory cells each of which stores 2 or more bits of data. ... Sk Hynix Inc

03/08/18 / #20180068731

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of memory blocks; and a controller suitable for managing the memory blocks as a plurality of super memory blocks by grouping them in a type corresponding to a predetermined condition, managing a bad block pool of the form of bitmaps and indexes by setting super memory blocks among the super memory blocks, in each of which one or more bad memory blocks are included, as bad super memory blocks, and managing regenerated super memory blocks by checking, through the bad block pool, normal memory blocks included in the respective bad super memory blocks and then performing grouping in the type corresponding to the predetermined condition.. . ... Sk Hynix Inc

03/08/18 / #20180068730

Semiconductor memory device and method of operating the same

A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes a plurality of memory layers stacked on a semiconductor substrate, wherein each of the plurality of memory layers includes one or more connection control transistors, one or more drain select transistors, a plurality of memory cells, and a source select transistor electrically coupled in series between a plurality of bit lines and a common source line, and the plurality of memory layers share the plurality of bit lines, and the common source lines electrically coupled to each of the plurality of memory layers are electrically disconnected.. ... Sk Hynix Inc

03/08/18 / #20180068706

Semiconductor memory device and operating method thereof

Provided herein are a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell array to which a plurality of word lines are coupled, a voltage generation circuit configured to apply operating voltages to the plurality of word lines during a program operation, and a control logic configured to control the voltage generation circuit to perform a discharge operation for the plurality of word lines when an external power supply voltage is reduced during the program operation, wherein the control logic controls the voltage generation circuit such that, during the discharge operation, a potential level of a selected word line among the plurality of word lines is discharged, and then potential levels of the other unselected word lines are discharged.. ... Sk Hynix Inc

03/08/18 / #20180068698

Semiconductor device

A semiconductor device includes an internal operation control circuit suitable for generating a set period signal which is enabled for a set period, in response to a write command and an internal operation control signal, and generating a column select signal, an output control signal and an input control signal in response to the set period signal; and an internal operation circuit suitable for performing an internal operation of converting parity data generated from input data and storing the converted parity data in a memory cell array, in response to the column select signal, the output control signal and the input control signal.. . ... Sk Hynix Inc

03/08/18 / #20180068692

Semiconductor device and power distribution network

In a semiconductor device, some regions of a memory cell array region may be used as reservoir regions. A semiconductor device may include at least one reservoir cell disposed with the memory cells in a cell array region.. ... Sk Hynix Inc

03/08/18 / #20180067801

Integrated circuit

An integrated circuit includes a first semiconductor device suitable for outputting a first error information signal by performing a first error correction operation, and a second semiconductor device suitable for outputting a second error information signal by performing a second error correction operation. The first error correction operation and the second error correction operation are performed simultaneously, and the second error information signal is outputted from the second semiconductor device after the first error information signal is outputted from the first semiconductor device.. ... Sk Hynix Inc

03/08/18 / #20180067796

Semiconductor devices and semiconductor systems including the same

A semiconductor device may be provided. The semiconductor device may include a memory area. ... Sk Hynix Inc

03/08/18 / #20180067696

Memory system and operating method thereof

A memory system includes: a memory device comprising a plurality of memory dies in which command operations corresponding to a plurality of commands received from a host are performed; and a controller suitable for issuing rs (read status) commands to memory dies included in a first memory die group among the memory dies, issuing the rs commands to memory dies included in a second memory die group, checking whether the command operations are performed in the memory dies, through responses to the rs commands, and resetting an issue period of the rs commands in response to a change of the memory dies to which the rs commands are issued.. . ... Sk Hynix Inc

03/08/18 / #20180067693

Memory device and memory system having the same

The invention relates to a memory device and a memory system having the same. The memory device includes a memory block including a plurality of pages, a peripheral circuit including a plurality of buffers sensing data stored in a selected page of the plurality of pages, temporarily storing high usage frequency data, and outputting the data, and a control circuit controlling the peripheral circuit to output the data after performing a sensing operation on the selected page, storing the high usage frequency data to at least one of the buffers, or outputting the high usage frequency data without performing the sensing operation in response to a read command.. ... Sk Hynix Inc

03/08/18 / #20180067692

Controller, memory system and operating method thereof

A controller may include a first map buffer and a second map buffer suitable for storing map data and hit counts respectively corresponding to the map data, wherein each of the hit counts represents a number of accesses to data stored in a memory device by using a corresponding one among the map data, and wherein the controller swaps the map data and corresponding hit counts between the first and second map buffers such that the first map buffer stores relatively higher hit counts and corresponding map data than the second map buffer.. . ... Sk Hynix Inc

03/08/18 / #20180067686

Memory system

A memory system includes a memory controller, a first memory module including first and second groups of first memory chips, a second memory module including first and second groups of second memory chips, and a channel including a first group of signal lines suitable for coupling the memory controller with the first memory module, and a second group of signal lines suitable for coupling the memory controller with the second memory module.. . ... Sk Hynix Inc

03/01/18 / #20180062968

System including master device and slave device, and operation method of the system

A system includes: a master device; and a slave device including a temperature variation measuring circuit for measuring a temperature variation amount of the salve device for a predetermined time. The slave device transfers temperature information to a master device when a temperature variation amount for the predetermined time is equal to or greater than a threshold value, the temperature information representing that the temperature variation amount for the predetermined time is equal to or greater than the threshold value. ... Sk Hynix Inc

03/01/18 / #20180062651

Data transmission device, and semiconductor device and system including the same

A data transmission device may include a calibration circuit and an output driver. The calibration circuit may generate a pull-up calibration voltage and a pull-down calibration voltage. ... Sk Hynix Inc

03/01/18 / #20180062378

System level esd detection device and restart system using the same

A system level electrostatic discharge (esd) detection device includes a phase detection unit including at least one phase detector suitable for detecting a phase difference between a plurality of supply voltages or between a plurality of input signals; a storage unit suitable for shifting between a first and a second state, the second state indicating a phase difference detected by the phase detection unit; and an output unit suitable for outputting a system level electrostatic discharge (esd) detection signal according to the first or second state of the storage unit.. . ... Sk Hynix Inc

03/01/18 / #20180061996

Semiconductor integrated circuit device including nano-wire selector and method of manufacturing the same

In a method of manufacturing a semiconductor integrated circuit device, an active region including a nano-wire may be formed on a bulk insulating layer. A hard mask pattern may be formed to partially expose the nano-wire. ... Sk Hynix Inc

03/01/18 / #20180061891

Variable resistive memory device

A variable resistive memory device may include a semiconductor substrate, a device layer, an upper metal interconnect, a plurality of memory cells, and an uppermost metal interconnect. The device layer may be formed on the semiconductor substrate including memory cell array regions, and may include a plurality of lower metal interconnect layers. ... Sk Hynix Inc

03/01/18 / #20180061889

Switching device, and resistive random access memory including the same as a selection device

A switching device includes a first electrode, a switching layer having a non-memory characteristic, and a second electrode that are disposed over a substrate. The switching layer includes an oxide of a first atom or a nitride of the first atom, and a second atom is doped in the oxide or the nitride. ... Sk Hynix Inc

03/01/18 / #20180061881

Successive approximation register analog-to-digital converter, cmos image sensor including the same and operating method thereof

A complementary metal oxide semiconductor (cmos) image sensor includes a pixel array suitable for outputting a pixel signal corresponding to incident light; a row decoder suitable for selecting and controlling pixels in the pixel array by row lines; a tracking voltage generator suitable for generating a tracking voltage; a plurality of successive approximation register (sar) analog-to-digital converters suitable for analog-to-digital converting a pixel signal by repeatedly performing n times (where n is a natural number representing desired resolution) a process of comparing the pixel signal generated by the pixel array with the tracking voltage generated by the tracking voltage generator and modulating the pixel signal; and a control unit suitable for controlling operations of the row decoder, the tracking voltage generator, and the plurality of sar analog-to-digital converters.. . ... Sk Hynix Inc

03/01/18 / #20180061510

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device; and a control unit suitable for controlling a program operation for memory cells of a page of the nonvolatile memory device, and processing a program fail in the case where the program operation fails, wherein the control unit adjusts a read voltage for discriminating an erase state and a program state having a threshold voltage most adjacent to the erase state, reads out data by applying the adjusted read voltage to the memory cells of the page, and performs an error handling operation to data stored in the memory cells of the page according to a result of comparing a reference value and a number of flipped bits of the data read out by applying the varied read voltage.. . ... Sk Hynix Inc

03/01/18 / #20180061501

Memory device and method of operating the same

Provided herein are a memory device and a method of operating the same. The memory device includes a memory block including a plurality of stacked sub-memory blocks, peripheral circuits configured to perform program, read and erase operations on the memory block or on a block selected from among the sub-memory blocks, and control logic configured to control the peripheral circuits so that, during a read operation on the memory block, if a block on which a partial erase operation has been performed is not present among the sub-memory blocks, voltages to be used for the read operation are set and so that, if a block on which the partial erase operation has been performed is present among the sub-memory blocks, the voltages to be used for the read operation are varied depending on a position of a sub-memory block that is a target of the read operation.. ... Sk Hynix Inc

03/01/18 / #20180061493

Semiconductor memory apparatus for adjusting voltage level of global word line, and operating method thereof

A semiconductor memory apparatus may include a memory cell, a write driver, and a voltage adjustment circuit. The write driver may provide the memory cell with a program current based on a write data. ... Sk Hynix Inc

03/01/18 / #20180061491

Semiconductor system including a phase changeable memory device

A semiconductor system may be provided. The semiconductor system may include a phase changeable memory device. ... Sk Hynix Inc

03/01/18 / #20180061485

Refresh control circuit and memory device including same

A memory device may include: at least one memory bank; and a control circuit suitable for: refreshing the at least one memory bank through a first refresh operation in response to a refresh command; and refreshing the at least one memory bank through a second refresh operation when an active operation is performed between a current refresh command and a previous refresh command.. . ... Sk Hynix Inc

03/01/18 / #20180061479

Semiconductor memory device and operating method thereof

A semiconductor memory device may include a sense amplifier for sensing and amplifying data of a bit line pair with pull-up and pull-down driving voltages; a voltage supplier for supplying a power supply voltage or an internal voltage lower than the power supply voltage as the pull-up driving voltage through a pull-up power supply line in response to a first or second pull-up control signal, and supplying a ground voltage as the pull-down driving voltage through a pull-down power supply line in response to a pull-down control signal; a voltage detector for detecting a voltage level of the power supply voltage and outputting a detection signal; and a control signal generator for generating the first and second pull-up control signals, and the pull-down control signal and delaying an enabling timing of one of the first pull-up and pull-down control signals in response to the detection signal.. . ... Sk Hynix Inc

03/01/18 / #20180061476

Refresh control circuit for target refresh operation of semiconductor memory device, and operating method thereof

A semiconductor memory device may include: a memory cell region including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines; and a refresh control block suitable for performing a first refresh operation onto the plurality of the word lines in response to a refresh signal, counting the number of active signals that are inputted between at least two neighboring refresh signals and when the counted number of the active signals is equal to or greater than a reference number, performing a second refresh operation onto a word line corresponding to a target address.. . ... Sk Hynix Inc

03/01/18 / #20180061474

Semiconductor devices

A semiconductor device includes a bank address generation circuit, a row/column address generation circuit, and an operation control circuit. The bank address generation circuit generates a bank address signal according to a bank group selection signal which is generated in response to a first temperature code and a second temperature code. ... Sk Hynix Inc

03/01/18 / #20180061472

Semiconductor system

A semiconductor system may include: an external channel including a ca (command/address) channel, and first and second data channels; and first and second semiconductor chips, which are coupled in common to the ca channel and coupled to respective different ones of the first and second data channels, and each of which includes a coupling information pad. A first value may be inputted to the coupling information pad of one of the first and second semiconductor chips that is coupled to the first data channel, and a second value may be inputted to the coupling information pad of the other semiconductor chip that is coupled to the second data channel. ... Sk Hynix Inc

03/01/18 / #20180061466

Semiconductor memory system and operating method thereof

A semiconductor memory system comprising: a memory device including a plurality of data cells; a read/write circuit suitable for performing a write operation to a target data cell among the data cells; and a state transition recognition circuit suitable for detecting a state transition of the target data cell, and ending the write operation according to the detection result of the state transition of the target data cell.. . ... Sk Hynix Inc

03/01/18 / #20180060166

Semiconductor systems

A semiconductor system includes a host and a media controller. The host may generate first host parities from first host data based on an error check matrix. ... Sk Hynix Inc

03/01/18 / #20180060165

Semiconductor devices

A semiconductor device may include an error correction circuit and a fuse signal generation circuit. The error correction circuit may be configured to generate a syndrome signal from data using an error correction code. ... Sk Hynix Inc

03/01/18 / #20180059971

Memory system and operating method thereof

A memory device may include: a memory cell array comprising a plurality of search regions, each of the search regions comprising a plurality of group regions, each of the group regions comprising a flag cell, each flag cell comprising information indicating whether the corresponding group region is programmed; a voltage generator suitable for generating a read bias voltage for the memory cell array according to a voltage control signal; and a memory controller suitable for selecting a search region and controlling the voltage generator to adjust the read bias voltage based on information of flag cell of the selected search region when a read command is received, and controlling a read operation for the selected search region based on the adjusted read bias voltage.. . ... Sk Hynix Inc

03/01/18 / #20180059968

Memory system and method for operating the memory system

A memory system may include: a memory device including a memory cell array, the memory cell array including a plurality of scan areas, each of the plurality of the scan areas including at least two group areas, each of the group areas including a flag area storing a flag that represents whether a corresponding group area is programmed or not; and a controller suitable for requesting the memory device to read the flag of each of the group areas a flag when a sudden power-off occurs, and rebuilding at least one of the group areas when at least one of the flags is in an erase state.. . ... Sk Hynix Inc

03/01/18 / #20180059967

Memory device and system including the same

A memory device may include a command controller configured to buffer an address based on a refresh enable signal and a repair enable signal. The memory device may include a fuse circuit configured to control a rupture operation of a refresh cell array and repair cell array corresponding to the address according to the refresh enable signal and the repair enable signal, and output a refresh control signal and a repair control signal during a boot-up operation. ... Sk Hynix Inc

03/01/18 / #20180059938

Sense amplifier, memory apparatus and system including the same

A sense amplifier includes a current supply unit, an amplification unit, a pass transistor and a latch unit. The current supply unit may be configured to provide a sensing current to a sensing node. ... Sk Hynix Inc

03/01/18 / #20180059937

Memory system and operating method thereof

A memory system comprises a memory device including a normal cell region and a redundancy cell region, and a controller suitable for programming data in duplicate in both the normal and the redundancy cell regions, wherein when detecting an error in the data read from the normal cell region, the controller invalidates the data of the normal cell region and validates the data of the redundancy cell region.. . ... Sk Hynix Inc

03/01/18 / #20180059935

Data storage device

A data storage device includes nonvolatile memory devices coupled to a plurality of channels; and a controller including a processor, a buffer and memory controllers which are respectively coupled to the channels, wherein the processor transmits a first access command to a first memory controller in response to a first access request from a host device, regardless of a state of the buffer, and wherein the first memory controller controls an internal operation of a first nonvolatile memory device by determining the state of the buffer, in response to the first access command.. . ... Sk Hynix Inc

03/01/18 / #20180059537

Methods of forming patterns using nanoimprint lithography

A method of forming patterns is provided. The method includes forming a resist layer on a substrate, forming a lattice-shaped extrusion barrier region in the resist layer to define pattern transfer regions corresponding to a plurality of separate windows, and positioning a template on the resist layer so that a patterned surface of the template faces the resist layer. ... Sk Hynix Inc

03/01/18 / #20180059181

Semiconductor device method relating to latch circuit testing

A semiconductor device may be provided. The semiconductor device may include a latch comparison circuit configured for generating a latched address by latching a pattern signal inputted through an address, and generate a comparison signal by comparing a pattern signal inputted through the address and the latched address. ... Sk Hynix Inc

02/22/18 / #20180054307

Encryption device

An encryption device includes a zeroth encryption core suitable for receiving and encrypting data, and outputting an encryption result; first to (n-1)-th encryption cores, each suitable for receiving and encrypting an encryption result of a previous encryption core and transferring the encrypted encryption of the previous encryption core result to a subsequent encryption core; an n-th encryption core suitable for receiving and encrypting an encryption result of the (n-1)-th encryption core, and outputting the encrypted encryption result of the (n-1)-th encryption core as encrypted data; and a key expansion logic circuit suitable for generating first to n-th encryption keys to be used in the first to nth encryption cores, by using an initial encryption key used in the zeroth encryption core.. . ... Sk Hynix Inc

02/22/18 / #20180054206

Delay control device and method for the same

A delay control device and method are disclosed, which relate to a technology for compensating for a delay difference of a delay locked loop (dll). The delay control device may include a delay locked loop (dll) configured to adjust a delay time of a delay line, and compensate for a delay time of a replica delay circuit based on a calibration signal. ... Sk Hynix Inc

02/22/18 / #20180054193

Clock detectors and methods of detecting clocks

A clock detector a first delay circuit delaying an input clock by a first delay time and outputting the delayed input clock as a delayed clock signal, an edge detection circuit receiving the input clock and the delayed clock signal to generate an output signal including pulses which are created in synchronization with edges of the input clock, a delay/inversion circuit delaying the output signal of the edge detection circuit by a second delay time and inverting the delayed output signal to output the inverted signal as an output signal, a first flip-flop receiving the input clock to generate a first output signal, a second flip-flop receiving the first output signal to generate a second output signal, and a clock detection signal generation circuit receiving the first and second output signals to generate a clock detection signal.. . ... Sk Hynix Inc

02/22/18 / #20180053782

Semiconductor memory device including 3-dimensional structure and method for manufacturing the same

A semiconductor memory device mc des a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.. . ... Sk Hynix Inc

02/22/18 / #20180053780

Semiconductor device

The present disclosure relates to a semiconductor device including a stress control insulating layer or a stress control pattern to control a stress applied to an interlayer insulating layer or a stacked body in a desirable direction.. . ... Sk Hynix Inc

02/22/18 / #20180053779

Manufacturing method of semiconductor device

A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. ... Sk Hynix Inc

02/22/18 / #20180053770

Method for forming buried bit line, semiconductor device having the same, and fabricating method thereof

A method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies separated from one another by a plurality of trenches; forming a protective layer with open parts to expose both sidewalls of each of the bodies; forming buried bit lines in the bodies by silicidizing exposed portions of the bodies through the open parts; and forming a dielectric layer to gap-fill the trenches and define air gaps between adjacent buried bit lines.. . ... Sk Hynix Inc

02/22/18 / #20180053747

Fan-out packages including vertically stacked chips and methods of fabricating the same

A fan-out package may include a core supporter having a through hole, a first semiconductor chip disposed on a first surface of the core supporter in a way that a portion of the first semiconductor chip is exposed by the through hole, a second semiconductor chip disposed on a second surface of the core supporter, a first photosensitive dielectric layer disposed on the first surface of the core supporter to cover the first semiconductor chip, a second photosensitive dielectric layer disposed on the second surface of the core supporter to cover the second semiconductor chip and to fill the through hole, a first trace pattern disposed on the second photosensitive dielectric layer, and a first conductive via penetrating the second photosensitive dielectric layer in the through hole to be connected to both of the first trace pattern and the first semiconductor chip.. . ... Sk Hynix Inc

02/22/18 / #20180053567

Semiconductor devices, semiconductor systems, and methods thereof

A semiconductor system may be provided. The semiconductor system may include a first semiconductor device, a second semiconductor device, and a third semiconductor device. ... Sk Hynix Inc

02/22/18 / #20180053565

Memory system and operating method for the same

A memory system comprises a memory device including a plurality of memory blocks, the memory device being configured to perform a program operation and a program verify operation to program data to the memory blocks, and a controller configured to detect program error bit information as a result of the program verify operation, select a victim memory block among the memory blocks based on the detected program error bit information, and copy programmed data of the victim memory block.. . ... Sk Hynix Inc

02/22/18 / #20180053543

Semiconductor memory device and method of operating the same

Provided herein are a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device having improved reliability includes a memory cell array including memory cells coupled to a plurality of word lines, a peripheral circuit configured to perform a program operation on a word line selected from among the plurality of word lines, and control logic configured to control the peripheral circuit so that, when the selected word line is a reference word line during the program operation, a partial erase operation is performed on memory cells included in a memory cell group corresponding to the reference word line.. ... Sk Hynix Inc

02/22/18 / #20180053541

Semiconductor memory apparatus

A semiconductor memory apparatus may be provided. The semiconductor memory apparatus may include a row decoder configured to generate one or more row decoding signals based on a plurality of row addresses. ... Sk Hynix Inc

02/22/18 / #20180052732

Semiconductor device and semiconductor system

A semiconductor system may be provided. The semiconductor system may include a first semiconductor device configured for outputting a transmission command and a transmission address, being inputted with and outputting transmission data, and generating an error flag signal when an error bit is included in the transmission data inputted in a read operation. ... Sk Hynix Inc

02/22/18 / #20180052724

Memory system and operating method thereof

A memory system includes: a nonvolatile memory device; and a controller operatively coupled to the nonvolatile memory device and to a host, the controller including first and second interfaces suitable for inputting and/or outputting data from or to the host, wherein the controller is suitable for selecting any one of the first and second interfaces depending on a result of a durability check of the nonvolatile memory device.. . ... Sk Hynix Inc

02/22/18 / #20180052710

Data processing system and operating method thereof

A memory system may include: a memory device; and a controller, wherein the controller includes: a receiving unit suitable for receiving a plurality of tasks from a host; and a task processing unit suitable for re-arranging the plurality of the tasks based on the number of the plurality of the tasks and a priority order, and performing the re-arranged tasks.. . ... Sk Hynix Inc

02/22/18 / #20180052638

Memory device, memory system having the same, and operating method thereof

A memory system includes a memory controller transferring a search command, and a memory device searching a plurality of pages a memory device operatively coupled to a memory controller, the memory device being suitable for detecting a last erased page among a plurality of pages included in a memory block of the memory device, and for providing an address of the last erased page to the memory controller, and the memory controller is configured to control the memory device according to the address of the last erased page.. . ... Sk Hynix Inc

02/22/18 / #20180052601

Memory system including multi-interfaces

A memory system includes: a nonvolatile memory device including first and second storage regions; and a controller including first and second interfaces, the first interface being suitable for exchanging data between the first storage region and a host, and the second interface being suitable for exchanging data between the second storage region and the host.. . ... Sk Hynix Inc

02/22/18 / #20180052600

Data processing system and operating method thereof

A data processing system include: a host suitable for selecting and loading any one of a plurality of operating systems (oss); and a memory system comprising a memory device and a controller that includes a plurality of firmwares, wherein the controller enables any one of the firmwares based on the os loaded to the host, and controls an operation of the memory system based on the enabled firmware.. . ... Sk Hynix Inc

02/15/18 / #20180048434

Page health prediction using product codes decoder in nand flash storage

An apparatus of a memory system and an operating method thereof includes: a plurality of memory devices; and a controller including a decoder and a ber predictor, coupled with the plurality of memory devices, configured to perform a decoding iteration includes to conduct nand read and generate nand data; decode in accordance with the nand data and generate decoder information by the decoder; predict a ber in accordance with at least the decode information by the ber predictor; and evaluate the predicted ber and generate evaluation result by the ber predictor.. . ... Sk Hynix Inc

02/15/18 / #20180048332

Low latency soft decoder architecture for generalized product codes

Techniques for reducing the latency for decoding product codewords with minimal hardware architecture changes are described. In an example, a system accesses and decodes a generalized product code (gpc) codeword by using at least one of a plurality of chase decoding procedures available on the system. ... Sk Hynix Inc

02/15/18 / #20180047785

Semiconductor apparatus

A semiconductor apparatus may include a first circuit forming region formed over a substrate, a first interlayer dielectric layer formed over the first circuit forming region, a first metal layer formed over the first interlayer dielectric layer, a second interlayer dielectric layer formed over the first metal layer, and a second circuit forming region formed over the second interlayer dielectric layer. A first circuit and a second circuit that are included in the first circuit forming region and a third circuit that is included in the second circuit forming region may be electrically coupled to each other.. ... Sk Hynix Inc

02/15/18 / #20180047748

Nonvolatile memory device and method for fabricating the same

A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.. . ... Sk Hynix Inc

02/15/18 / #20180047456

Techniques for dynamically determining performance of read reclaim operations

Disclosed are techniques for determining a threshold number of read operations on memory depending on one or more conditions of the memory. If a number of read operations for the memory meets the threshold number of read operations, a read reclaim operation can be performed to preserve data stored therein.. ... Sk Hynix Inc

02/15/18 / #20180047453

Layer-based memory controller optimizations for three dimensional memory constructs

Disclosed are techniques for selecting one or more reference voltages for performing one or more operations on a memory cell based on a determined layer of a three-dimensional memory construct to which the memory cell belongs. The one or more operations can include read or write operations. ... Sk Hynix Inc

02/15/18 / #20180047450

Semiconductor memory device

Provided herein is a semiconductor memory device including a memory cell array including a drain select transistor and a plurality of memory cells, a voltage generator configured to apply a program voltage, first and second pass voltages, and a drain control voltage to the memory cell array, a control logic configured to control the voltage generator so that during a program operation, after the program voltage is applied to a selected one of the plurality of memory cells, the program voltage applied to the selected memory cell is discharged while the first pass voltage or the second pass voltage is applied to memory cells adjacent to the selected memory cell.. . ... Sk Hynix Inc

02/15/18 / #20180047447

Current driver, write driver, and semiconductor memory apparatus using the same

A current driver may include a current applying circuit and a current adjusting circuit. The current applying circuit may include a threshold switching element, and may provide unlimited amount of current while occupying small circuit area therefor. ... Sk Hynix Inc

02/15/18 / #20180047445

Semiconductor memory apparatus

A semiconductor memory apparatus may be provided. The semiconductor memory apparatus may include a memory element. ... Sk Hynix Inc

02/15/18 / #20180047444

Memory system with read threshold estimation and operating method thereof

An apparatus of a memory system and an operating method thereof includes a plurality of memory devices; and a controller coupled to the plurality of memory devices, wherein the controller is configured to perform a symmetric ovs read with at least an initial read threshold, and create a symmetric read result; perform an asymmetric ovs read with at least the initial read threshold, and create an asymmetric read result; adjust the initial read threshold according to at least the symmetric read result and asymmetric read result, and create an optimal read threshold; and execute data recovery process with the optimal read threshold.. . ... Sk Hynix Inc

02/15/18 / #20180047441

Semiconductor memory apparatus

A semiconductor memory apparatus includes a bias voltage generation circuit configured to generate a bias voltage according to a read voltage or a write voltage in response to a read signal and a write signal, a data discrimination circuit configured to generate a set enable signal and a reset enable signal in response to data and the write signal. The semiconductor memory apparatus also includes a current selection circuit configured to generate a first current in response to the read signal, the set enable signal, and the reset enable signal. ... Sk Hynix Inc

02/15/18 / #20180047435

Semiconductor device

A semiconductor device may be provided. The semiconductor device may include a signal mixing circuit suitable for generating a strobe signal which toggles in synchronization with a divided clock. ... Sk Hynix Inc

02/15/18 / #20180047433

Level shifter and operation method thereof

A level shifter includes an input control unit suitable for outputting an output control signal according to a pulse width of a data signal and a pulse width of an input control signal; and an output control unit suitable for controlling an output driving signal according to the output control signal.. . ... Sk Hynix Inc

02/15/18 / #20180046540

Redundant bytes utilization in error correction code

Techniques for codeword decoding are described. In an example, a system accesses information about a block of a storage device of the system. ... Sk Hynix Inc

02/15/18 / #20180046538

Modifiable stripe length in flash memory devices

A memory device including a memory having a plurality of memory cells for storing data. The memory device includes a controller communicatively coupled to the memory and configured to organize the data as a plurality of stripes. ... Sk Hynix Inc

02/15/18 / #20180046389

Memory controller and memory system including the same

A memory system includes: a memory device including a plurality of memory banks; and a memory controller suitable for monitoring a workload of the memory device and applying one of a first refresh command and a second refresh command to the memory device according to a result of the monitoring. In the memory device, the number of memory banks to be refreshed by the second refresh command may be greater than the number of memory banks to be refreshed by the first refresh command.. ... Sk Hynix Inc

02/15/18 / #20180046373

Memory system of optimal read reference voltage and operating method thereof

An apparatus of a memory system and an operating method thereof includes a plurality of memory devices; and a controller coupled with the plurality of memory devices, configured to determine a range of read reference voltages having a plurality of read reference voltages, the read reference voltages achieving a minimal rber; calculate an optimal read reference voltage in accordance with at least the range of read reference voltages; achieve a rber in accordance with at least the optimal read reference voltage; and execute error correction process with at least the optimal read reference voltage.. . ... Sk Hynix Inc

02/15/18 / #20180046372

Unusable column mapping in flash memory devices

A memory device for generating a mapping between one or more unusable columns and one or more backup columns within a memory. The memory includes a plurality of memory cells for storing data. ... Sk Hynix Inc

02/15/18 / #20180046370

Memory system and operating method thereof

A memory system includes: a memory device; and a controller suitable for controlling the memory device, wherein the controller performs a read operation in a first region of the memory device in response to a read command from a host, and sets a second region of the memory device, into which data stored in the first region is to be copied, based on a read number of the first region.. . ... Sk Hynix Inc

02/08/18 / #20180041197

Current break circuit, semiconductor device having the same and operating method thereof

A current break circuit includes a current break control circuit suitable for sequentially outputting a first enable signal and a second enable signal with a time difference in response to at least one control signal, and a current break switch circuit suitable for outputting or blocking a second voltage in response to a first voltage, wherein the current break switch circuit forms a first current path in response to the first enable signal and a second current path in response to the second enable signal when blocking the second voltage.. . ... Sk Hynix Inc

02/08/18 / #20180040814

Electronic device and method for fabricating the same

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a variable resistance element that exhibits different resistance states for storing data; and a lower contact plug coupled to the variable resistance element and disposed under the variable resistance element, and wherein a width of the lower contact plug increases from a top surface of the lower contact plug to a bottom surface of the lower contact plug.. ... Sk Hynix Inc

02/08/18 / #20180040809

Electronic device and method for fabricating the same

This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a semiconductor memory, wherein the semiconductor memory may include: one or more variable resistance elements each exhibiting different resistance states for storing data, wherein each variable resistance element may include: a magnetic tunnel junction (mtj) structure including a free layer having a changeable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a seed layer disposed under the mtj structure to facilitate a growth of the pinned layer or the free layer; and an amorphous metallic carbon layer disposed under the seed layer.. ... Sk Hynix Inc

02/08/18 / #20180040808

Electronic device and method for fabricating the same

This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a semiconductor memory, wherein the semiconductor memory may include: a variable resistance element disposed over a substrate and structured to exhibit different resistance states for storing data; and an upper contact plug disposed over the variable resistance element and coupled to the variable resistance element, wherein the upper contact plug includes a first portion that is disposed between an upper end of the upper contact plug and a lower end of the upper contact plug and the first portion has a width smaller than a width of each of the upper end and the lower end.. ... Sk Hynix Inc

02/08/18 / #20180040670

Electronic device and method for fabricating the same

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a first portion of a variable resistance element, the first portion having an island shape and including at least a free layer which has a variable magnetization direction; a second portion of the variable resistance element, the second portion having a line shape which extends in a direction over the first portion and including at least a pinned layer which has a pinned magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer.. ... Sk Hynix Inc

02/08/18 / #20180040629

Semiconductor device and manufacturing method thereof

A semiconductor device in accordance with an embodiment may include a cell structure, a source coupling structure, and a source discharge transistor. The cell structure may include alternately stacked first conductive patterns and first interlayer insulating layers enclosing a channel layer. ... Sk Hynix Inc

02/08/18 / #20180040553

Semiconductor memory device with 3d structure

A semiconductor memory device with a three-dimensional (3d) structure may include: a cell region arranged over a substrate, including a cell structure; a peripheral circuit region arranged between the substrate and the cell region; an upper wiring structure arranged over the cell region; main channel films and dummy channel films formed through the cell structure. The dummy channel films are suitable for electrically coupling the upper wiring structure.. ... Sk Hynix Inc

02/08/18 / #20180040383

Semiconductor device

A semiconductor device may be provided. The semiconductor device may include sense-amplifier test device. ... Sk Hynix Inc

02/08/18 / #20180040378

Semiconductor memory device and operating method thereof

The semiconductor memory device includes: a memory unit having a plurality of memory blocks; a voltage supply circuit configured to generate a plurality of operating voltages and transmit the operating voltages to global word lines; and a pass unit coupled between respective local word lines of the plurality of memory blocks and the global word lines, and configured to couple the local word lines of a selected memory block to the global word lines in response to block select signals corresponding to the respective memory blocks, wherein the pass unit couples local word lines of an unselected memory block to the global word lines for a preset time and then isolates local word lines of the unselected memory block from the global word lines in response to the block select signals while coupling local word lines of the selected memory block to the global word lines.. . ... Sk Hynix Inc

02/08/18 / #20180040372

Memory and electronic device including the same

A semiconductor memory includes a cell array including a plurality of resistive memory cells in which a plurality of columns and a plurality of rows are arranged, a read voltage application circuit configured to apply a read voltage to a selected memory cell of the plurality of resistive memory cells, a sensing circuit configured to detect an amount of a current flowing through the selected memory cell and sense data, and an overcurrent prevention circuit configured to reduce voltage levels at both ends of the selected memory cell when an overcurrent flows through the selected memory cell.. . ... Sk Hynix Inc

02/08/18 / #20180040371

Nonvolatile memory apparatus and resistance compensation circuit thereof

A nonvolatile memory apparatus may include a memory cell array including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines. The nonvolatile memory apparatus may include and a resistance compensation circuit configured to generate a compensation resistance value according to a position of a memory cell to be accessed.. ... Sk Hynix Inc

02/08/18 / #20180040364

Memory device

A memory device may include: a plurality of cell mats arranged in a plurality of rows and columns; a plurality of first drivers, each first driver being disposed on a left side of a corresponding cell mat of the plurality of cell mats and configured to drive a first sub-word line of the corresponding cell mat; and a plurality of second drivers, each second driver being disposed on a right side of the corresponding cell mat of the plurality of cell mats and configured to drive a second sub-word line of the corresponding cell mat, wherein, during an active operation, among the plurality of cell mats, sub-word lines of cell mats disposed in odd-numbered columns or sub-word lines of cell mats disposed in even-numbered columns are selectively activated.. . ... Sk Hynix Inc

02/08/18 / #20180040363

Semiconductor devices and operations thereof

A semiconductor device may be provided. The semiconductor device may include a power-down signal generation circuit and a refresh signal generation circuit. ... Sk Hynix Inc

02/08/18 / #20180040361

Semiconductor devices and integrated circuits including the same

An integrated circuit may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a chip section signal and command/address signals. ... Sk Hynix Inc

02/08/18 / #20180040355

Semiconductor devices and semiconductor systems

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output commands and addresses. ... Sk Hynix Inc

02/08/18 / #20180040354

Semiconductor devices and semiconductor systems

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a reset signal, command/address signals and data. ... Sk Hynix Inc

02/08/18 / #20180040353

Semiconductor memory device and method of operating the same

Provided herein may be a semiconductor memory device. The semiconductor memory device may include a memory cell array, a peripheral circuit, and a control logic. ... Sk Hynix Inc

02/08/18 / #20180039532

Data i/o circuits and semiconductor systems including the same

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output an external strobe signal and external data. ... Sk Hynix Inc

02/08/18 / #20180039447

Memory system and operation method for the same

A memory system includes: a non-volatile memory device; a host controller suitable for generating a cache read command for controlling a cache read operation of the non-volatile memory device and at least one other command for controlling at least one other operation of the non-volatile memory device excluding the cache read operation in response to a request received from a host; and a memory controller suitable for controlling an operation of the non-volatile memory device in response to the cache read command and the at least one other command that are inputted from the host controller. The memory controller suitable for checking out the operation of the non-volatile memory device corresponding to a command that is inputted next to the input of the cache read command, and adding a read operation command including a read preparation command or a read end command next to the cache read command.. ... Sk Hynix Inc

02/08/18 / #20180039295

Semiconductor device

A semiconductor device may be provided. The semiconductor device may include a reference voltage generation circuit suitable for controlling a level of a reference voltage depending on an internal resistance value, and controlling the level of the reference voltage depending on the internal resistance value.. ... Sk Hynix Inc

02/08/18 / #20180036859

Method of processing thin layer

In a method of processing a thin layer according to an embodiment, a substrate having a processing target layer is provided into a polishing module of a thin layer processing apparatus. A chemical mechanical polishing process using a polishing slurry is performed on the processing target layer. ... Sk Hynix Inc

02/01/18 / #20180035107

Image sensor having test pattern and offset correction method thereof

An image sensor includes a substrate including an active pixel and a test pattern, wherein the test pattern is located adjacent to the active pixel, wherein the active pixel comprises a first photodiode, a floating diffusion, a first channel provided between the first photodiode and the floating diffusion, and a first transfer gate electrode provided over the first channel, wherein the test pattern comprises a first test photodiode, a test floating diffusion, a second channel provided between the first test photodiode and the test floating diffusion, a first test transfer gate electrode provided over the second channel, and a first contact plug connected to the first test photodiode, and wherein the first test photodiode, the test floating diffusion, the second channel, and the first test transfer gate have substantially the same alignment errors as the first photodiode, the floating diffusion, the first channel, and the first transfer gate electrode, respectively.. . ... Sk Hynix Inc

02/01/18 / #20180033688

Gap-fill polymer for filling fine pattern gaps and method for fabricating semiconductor device using the same

A gap-fill polymer for filling fine pattern gaps, which has a low dielectric constant (flow-k) and excellent gap filling properties may consist of a compound formed by condensation polymerization of a first oligomer represented by the formula 1 and a second oligomer represented by the formula 2.. . ... Sk Hynix Inc

02/01/18 / #20180033494

Semiconductor memory device and method of operating the same

A semiconductor memory device includes memory cells coupled to a word line; and a peripheral circuit configured to read first to kth page data from the memory cells by sequentially applying first to kth test voltages to the word line, where k is a natural number greater than 3, wherein the peripheral circuit is configured to gradually reduce times during which the first to kth test voltages are applied to the word line.. . ... Sk Hynix Inc

02/01/18 / #20180033492

Memory device and method of operating the same

Provided herein are a memory device and a method of operating the memory device. The memory device comprises a plurality of memory cells stacked along a pillar vertical to a substrate, a peripheral circuit configured to program and verifying memory cells coupled to a selected word line, among the memory cells, and a control logic configured to control the peripheral circuit so that a pass voltage applied to unselected word lines is adjusted depending on a location of the selected word line when the memory cells are verified.. ... Sk Hynix Inc

02/01/18 / #20180033485

Volatile memory, memory module including the same, and method for operating the memory module

A memory module includes an emergency power supplier, a plurality of ranks each including one or more volatile memories a non-volatile memory, and a controller suitable for backing up data of the ranks into the non-volatile memory by using the emergency power supplier during a power failure, wherein the ranks are sequentially backed up, and while one rank is backed up among the ranks, the other ranks are controlled in a self-refresh mode.. . ... Sk Hynix Inc

02/01/18 / #20180033473

Semiconductor device

A semiconductor device may be provided. The semiconductor device may include a driving voltage supply unit configured to supply a voltage such that a main word line signal has the voltage. ... Sk Hynix Inc

02/01/18 / #20180033466

Semiconductor apparatus and method of operating the same

A semiconductor apparatus includes a decoder configured to decode an internal command, and generate a first decoding command and a second decoding command. The semiconductor apparatus may include an output timing control circuit configured to delay the second decoding command by a predetermined cycle of the internal clock, and output a delayed decoding command. ... Sk Hynix Inc

02/01/18 / #20180032445

Memory system having nonvolatile memory and volatile memory

A memory system may include a volatile memory, a nonvolatile memory, and a controller. The controller may copy data from a memory to the other memory. ... Sk Hynix Inc

02/01/18 / #20180032415

Semiconductor device and system relating to data mapping

A semiconductor system may be provided. The semiconductor system may include a fail information generator and a data mapping circuit. ... Sk Hynix Inc

02/01/18 / #20180032392

Data bus inversion controller and semiconductor device including the same

A dbi (data bus inversion) controller may be provided. The dbi controller may include an address generation circuit configured to generate a dbi address from an input address. ... Sk Hynix Inc

02/01/18 / #20180032271

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a memory cell array including a plurality of pages, peripheral circuits programming memory cells included in a selected page of the plurality of pages into a plurality of program states, and a control logic controlling the peripheral circuits to perform a program operation, wherein the control logic controls the peripheral circuits so that a first variable pass voltage applied to a page adjacent to the selected page is different from a pass voltage applied to remaining unselected pages during a program operation for a first set program state having a low threshold voltage distribution, among the plurality of program states.. . ... Sk Hynix Inc

01/25/18 / #20180027197

Unit pixel apparatus and operation method thereof

A unit pixel apparatus may include a plurality of unit pixels including a reset transistor, each unit pixel being suitable for outputting a pixel signal corresponding to incident light; a reset transistor gate voltage transmission unit suitable for transmitting a plurality of reset transistor gate voltages; and a first voltage switching unit suitable for transmitting a first supply voltage among the plurality of reset transistor gate voltages to a gate terminal of the reset transistor in each of the unit pixels during a period from an exposure start time to just before a readout time.. . ... Sk Hynix Inc

01/25/18 / #20180026026

Semiconductor integrated circuit device relating to an electrical over stress protecting circuit

A semiconductor integrated circuit device may include a first discharging unit and a second discharging unit. The first discharging unit may be coupled between a first line having a first voltage level and a second line having a second voltage level different from the first voltage level. ... Sk Hynix Inc

01/25/18 / #20180025972

Power line layout structure for semiconductor device

A power line layout structure of the semiconductor device may include first through fifth power lines. The first and second power lines may be located at a first layer, and may provide different types of power-supply voltages. ... Sk Hynix Inc

01/25/18 / #20180025934

Semiconductor integrated circuit device having electrostatic discharge protection circuit

A semiconductor integrated circuit device may include a first electrostatic discharge (esd) protecting circuit and a second esd protecting circuit. The first esd protecting circuit may include at least one resistance changeable device connected between a power voltage line and a data pad to discharge an electrostatic. ... Sk Hynix Inc

01/25/18 / #20180025784

Memory device and operating method thereof

Disclosed are a memory device, including: a memory block including a plurality of cell strings; a peripheral circuit configured to set voltages for a program operation of selected memory cells in the cell strings, and program the selected memory cells by using the set voltages; and a control circuit configured to control the peripheral circuit so that the selected memory cells are programmed in response to a program command, and increase a channel voltage of non-selected cell strings including non-selected memory cells while the selected memory cells are programmed, and an operating method thereof.. . ... Sk Hynix Inc

01/25/18 / #20180025772

Semiconductor devices having a refresh operation

A semiconductor device includes a first row address generation circuit and a second row address generation circuit. The first row address generation circuit generates a first row address for refreshing memory cells connected to word lines included in a first up block and a second up block from a refresh command and an active signal in response to a period selection signal and a first period signal. ... Sk Hynix Inc

01/25/18 / #20180025769

Refresh control circuit and memory device including the same

A refresh control circuit may be provided. The refresh control circuit may include a row address control circuit configured to reset a corresponding block control signal among a plurality of block control signals, based on a stop signal for stopping a refresh operation of a specific block being enabled. ... Sk Hynix Inc

01/25/18 / #20180025762

Semiconductor device including a column decoder

A semiconductor device may be provided. The semiconductor device may include a first power line located in a memory cell array region. ... Sk Hynix Inc

01/25/18 / #20180024897

Efficient data recovery for write path errors

Systems and methods are provided for flash memory devices to improve the write performance in case of write path errors and to hide the write path error correction latency. Some embodiments can provide instant parity correction to allow user data sharing the same strip with the data block having an error to be programmed into the flash memory before the failed data is corrected. ... Sk Hynix Inc

01/25/18 / #20180024774

Memory system and operating method thereof

A memory system includes a memory device including a plurality of command registers; and a memory controller configured to determine whether an empty command register exists among the plurality of command registers, and transmit a new command to the memory device, when an empty command register exists, wherein, when the new command is transmitted from the memory controller, the memory device stores the transmitted new command in the empty command register.. . ... Sk Hynix Inc

01/25/18 / #20180024770

Memory system and operating method thereof

A memory system may include: a memory device including memory blocks each memory block including pages, each page including memory cells which are coupled to a word line for storing data; and a controller including a memory, the controller receiving a write command and a read command from a host, storing write data corresponding to the write command in the memory, transmitting and storing the write data stored in the memory to and in at least one first memory device buffer coupled to a first memory block in a page of which the write data are to be stored, reading read data corresponding to the read command from a page of a second memory block, storing the read data in at least one second memory device buffer coupled to the second memory block, and storing the read data stored in the second memory device buffer, in the memory.. . ... Sk Hynix Inc

01/25/18 / #20180024745

Memory system and operating method thereof

A memory system includes: a memory device including a plurality of pages which include a plurality of memory cells coupled to a plurality of word lines and in which data are stored, and a plurality of memory blocks in which the pages are included; and a controller including a memory, and suitable for storing data segments of user data corresponding to a write command received from a host, in pages included in a first memory block and a second memory block among the memory blocks and generating map data corresponding to storage of the data segments by sorting map segments of the map data according to logical informations of the data segments.. . ... Sk Hynix Inc

01/18/18 / #20180020176

Pixel signal readout device, method thereof, and cmos image sensor including the same

A pixel signal readout device includes a unit pixel including a drive transistor and a reset transistor; and a column select transistor suitable for outputting a voltage applied to one terminal thereof, to a common terminal of the drive transistor and the reset transistor through the other terminal thereof, in response to a column select control signal applied to a gate terminal thereof.. . ... Sk Hynix Inc

01/18/18 / #20180019753

Frequency divider regarding variable division ratio

A frequency divider may be provided. The frequency divider may be configured to generate a division signal having a variable cycle according to transition timing information and a division ratio signal.. ... Sk Hynix Inc

01/18/18 / #20180019751

Impedance calibration circuit and semiconductor apparatus including the same

An impedance calibration circuit includes a first detection unit configured to generate a first pull-up impedance detection signal according to a resistance value of an internal reference resistor, a second detection unit configured to generate a second pull-up impedance detection signal according to a resistance value of an external reference resistor coupled to an external reference resistor pad, a switching unit configured to select the first pull-up impedance detection signal or the second pull-up impedance detection signal according to the internal impedance calibration enable signal and output the selected pull-up impedance detection signal, and an impedance calibration signal generation unit configured to generate a plurality of impedance calibration signals according to an output of the switching unit.. . ... Sk Hynix Inc

01/18/18 / #20180019336

Three-dimensional semiconductor integrated circuit device and method of manufacturing the same

A semiconductor integrated circuit device may include an isolating layer, a buried gate, source and drain regions, a dielectric layer having a high dielectric constant and an insulating interlayer. The isolating layer may be formed on a semiconductor substrate to define an active region. ... Sk Hynix Inc

01/18/18 / #20180019188

Stretchable semiconductor packages and semiconductor devices including the same

A semiconductor package includes an extendible molding member, a chip embedded in the molding member to have a warped shape, and connectors disposed in the molding member. First surfaces of the connectors are exposed at a surface of the molding member, and second surfaces of the connectors are coupled to the chip.. ... Sk Hynix Inc

01/18/18 / #20180019024

Semiconductor memory device for performing a post package repair operation and operating method thereof

A semiconductor memory device includes a fuse array circuit including a row fuse region and a column fuse region, and suitable for outputting fuse information from row fuse sets and from column fuse sets and outputting programmed row and column addresses as row and column fail data, during a boot-up operation; a fuse array control circuit suitable for storing a fail address based on a fail cell information during a repair operation, searching unused fuse sets to from the row fuse region and the column fuse region based on the fuse information during the boot-up operation, and controlling the fail address to be programmed in the unused fuse sets during a rupture operation; and a row and column redundancy circuit suitable for performing a row or column redundancy operation in correspondence to the row and column fail data.. . ... Sk Hynix Inc

01/18/18 / #20180019023

Semiconductor test device and semiconductor test method

A semiconductor test device and a semiconductor test method are disclosed. A semiconductor test device may include a dq signal receiver, a test mode register set signal processor, and a test mode command generator. ... Sk Hynix Inc

01/18/18 / #20180019015

Memory device having negative voltage generator

Provided herein is a voltage generating circuit including: a negative voltage pump configured to generate a first negative voltage; and a negative voltage regulator configured to generate a second negative voltage using the first negative voltage and output the second negative voltage through an output terminal. The negative voltage regulator includes a first amplifier circuit configured to be controlled by a voltage of the output terminal, and a voltage booster configured to increase a voltage of the output terminal depending on an output voltage of the first amplifier circuit.. ... Sk Hynix Inc

01/18/18 / #20180019010

Semiconductor device and semiconductor system

A semiconductor system includes a controller operatively coupled to a semiconductor device, the controller being suitable in a training mode for receiving an external signal and a first data signal from an external device and for transmitting the received external signal and the first data signal to the semiconductor device; and the semiconductor device being suitable in the training mode for determining a level of a reference voltage in response to the first data signal, and for transmitting a second data signal to the controller by buffering the external signal based on the reference voltage without performing a termination operation during an output period of the second data signal, wherein the controller controls an enable timing of the external signal by receiving the second data signal.. . ... Sk Hynix Inc

01/18/18 / #20180019007

Data processing systems and a plurality of memory modules

A data processing system may include a memory/storage circuit and a host. The memory/storage circuit may include a first memory module and a second memory module. ... Sk Hynix Inc

01/18/18 / #20180018263

Electronic device and method for fabricating the same

An electronic device is provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a substrate including a first region in which a plurality of memory cells are disposed and a second region adjacent to the first region; a first interlayer insulating layer disposed over the substrate; a plurality of first memory cells penetrating through the first interlayer insulating layer in the first region, an uppermost portion of each memory cell of the first memory cells having a first conductive carbon-containing pattern; and a first insulating carbon-containing pattern located over the first interlayer insulating layer in the second region.. ... Sk Hynix Inc

01/18/18 / #20180018219

Semiconductor devices and semiconductor systems

A semiconductor system including a first semiconductor device and a second semiconductor device may be provided. The first semiconductor device may be configured to outputs commands and addresses. ... Sk Hynix Inc

01/18/18 / #20180018134

Electronic device and operating method thereof

Disclosed is an operating method of an electronic device which includes a semiconductor memory having a plurality of resistive storage cells. The operating method may include: writing data to the resistive storage cells using a write current of a set condition; determining whether the writing of data to the resistive storage cells is successful, wherein the writing of data is determined to be failed when the number of resistive storage cells with failed writing of data exceeds a reference value, and successful when the number of resistive storage cells with failed writing of data is equal to or less than the reference value; strengthening the set condition when the writing of data is determined to be failed; and easing the set condition when the writing of data is determined to be successful.. ... Sk Hynix Inc

01/18/18 / #20180018128

Memory system

Provided herein is a memory device including a memory cell array, a peripheral circuit configured to perform a first operation for the memory cell array, and a control circuit configured to generate an operation status code and output the operation status code. The first operation includes a plurality of second operations that are successively performed. ... Sk Hynix Inc

01/18/18 / #20180018114

Memory controller, memory system including the same and operation method of memory controller

An operating method of a memory controller may include determining a physical page to be accessed in a plurality of memory devices by mapping a logical address to a physical address; and determining a distribution pattern in which data of the physical page are distributed to the plurality of memory devices using the logical address.. . ... Sk Hynix Inc

01/18/18 / #20180018112

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of memory blocks, each of the memory blocks including a plurality of pages; and a controller suitable for: storing user data corresponding to a write command, in the memory blocks; storing map data corresponding to the stored user data, in the memory blocks; determining entropies indicating amounts of the map data updated in the memory blocks which correspond to the stored user data; and selecting source memory blocks among the memory blocks, which correspond to the entropies.. . ... Sk Hynix Inc

01/18/18 / #20180018111

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of memory dies, each die including a plurality of memory blocks, each block including a plurality of pages; and a controller suitable for performing a command operation for the memory device and storing segments of user data and metadata for the command operation in a super memory block including memory blocks of memory dies included in a first memory die group and a second memory die group among the plurality of memory dies.. . ... Sk Hynix Inc

01/18/18 / #20180018106

Nonvolatile memory device, data storage device and operating method thereof

A nonvolatile memory device includes a target memory area; a control unit configured to apply a program pulse one or more times to the target memory area in response to a program command, until program verification passes; and a status storage unit configured to store a program status information for the target memory area, wherein the control unit is supplied with a first operation voltage, and the status storage unit is supplied with a second operation voltage.. . ... Sk Hynix Inc

01/18/18 / #20180018094

Memory device, memory system including the same and operation method of the memory system

A memory system includes: a first memory device including a first internal voltage generation circuit; and a second memory device including a second internal voltage generation circuit, wherein the first memory device and the second memory device receive an identical chip enable signal, and when the chip enable signal is disabled, the first internal voltage generation circuit a no the second internal voltage generation circuit are controlled in a standby mode, and when the chip enable signal is enabled, the first internal voltage generation circuit and the second internal voltage generation circuit are independently controlled to have one mode between a weak active mode and a strong active mode.. . ... Sk Hynix Inc

01/18/18 / #20180018091

Memory system and operation method for the same

A memory system includes a memory device including a plurality of memory arrays, each of which includes a plurality of memory blocks, and a controller suitable for setting super blocks each including respective memory blocks that belong to two or more memory arrays among the plurality of the memory arrays and performing a garbage collection operation on the super blocks based on a valid page information and a wearing level of each super block.. . ... Sk Hynix Inc

01/11/18 / #20180012936

Electronic device

An electronic device is provided to comprise a semiconductor memory unit that comprises: a substrate including active regions, which are extended in a second direction and disposed from each other in a first direction; a plurality of gates extended in the first direction and across with the active regions; a lower contact disposed in both sides of gates and coupling the active regions in the first direction; an upper contact of the lower contact overlapping with the active region out of the active regions in a side of each gate, and overlapping with the active regions in the other side of each gate; and first and second interconnection lines coupled to the upper contact, extended in the second direction, and being alternately disposed from each other in the first direction, wherein the upper contact of a side of the gates has a zigzag shape in a first oblique direction.. . ... Sk Hynix Inc

01/11/18 / #20180012905

Semiconductor device and method of manufacturing the same

Disclosed is a method of manufacturing a semiconductor device, including: forming a slacked structure including first material layers and second material layers alternately stacked on each other; forming a pillar passing through the stacked structure, the pillar including a protruding portion protruding above an uppermost surface of the stacked structure; forming a conductive layer surrounding the protruding portion of the pillar; and forming a conductive pattern in contact with the protruding portion of the pillar by oxidizing a surface of the conductive layer.. . ... Sk Hynix Inc

01/11/18 / #20180012904

Manufacturing method of semiconductor device including barrier pattern

The invention is related to a method for manufacturing a semiconductor device having a barrier pattern. The method includes alternately forming first sacrificial layers and insulating layers forming channel patterns penetrating the first sacrificial layers and the insulating layers, and forming a slit penetrating the first sacrificial layers and the insulating layers. ... Sk Hynix Inc

01/11/18 / #20180012840

Semiconductor device and method of manufacturing the same

A semiconductor device may include a first pattern. The semiconductor device may include a second pattern intersecting with the first pattern and including an intersection region with the first pattern and a non-intersection region.. ... Sk Hynix Inc

01/11/18 / #20180012835

Semiconductor device and method for manufacturing the same

A semiconductor device and a method for manufacturing the same are disclosed, which guarantee an overlay margin between a contact and a metal line. A method for manufacturing a semiconductor device includes: forming a stacked insulation film in which a first interlayer insulation film, an etch stop film, and a second interlayer insulation film are sequentially stacked, over a lower structure; forming a contact hole by etching the stacked insulation film; forming a contact by burying a conductive film in the first interlayer insulation film and the etch stop film within the contact hole; and forming a metal line coupled to a top surface of the contact.. ... Sk Hynix Inc

01/11/18 / #20180012666

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of pages, each page including a plurality of memory cells coupled with a word line, a plurality of memory blocks in which the pages are included, a plurality of planes which include the memory blocks, and a plurality of memory dies in which the planes are included; and a controller suitable for performing at least one of a foreground operation and a background operation for the memory blocks, for checking parameters of the respective memory blocks in correspondence to performing the at least one of the foreground operation and the background operation, generating normalized parameters of the respective memory blocks, and performing the foreground operation and the background operation by using the normalized parameters of the respective memory blocks.. . ... Sk Hynix Inc

01/11/18 / #20180012665

Semiconductor memory device

Provided herein is a semiconductor memory device. The semiconductor memory device includes: a memory cell array including a plurality of memory blocks; a voltage generation circuit configured to generate a plurality of operating voltages; a decoder circuit configured to transmit the plurality of operating voltages to the memory cell array in response to a serial data signal that is sequentially inputted; and a control logic configured to generate the data signal, internal address signals and an internal clock signal in response to a command.. ... Sk Hynix Inc

01/11/18 / #20180012661

Eprom device for storing multi-bit data and read circuit of eprom device

An eprom device may include a unit cell, a switching unit, a decoder, and a comparing unit. The unit cell may be disposed between a ground voltage terminal and a bit line coupled to a program voltage supply line. ... Sk Hynix Inc

01/11/18 / #20180011754

Nonvolatile memory system and error determination method thereof

A memory system may be provided. The memory system may include a memory apparatus including a plurality of memory cells. ... Sk Hynix Inc

01/11/18 / #20180011645

Semiconductor apparatus, memory system and repair method thereof

A semiconductor apparatus may include a fuse cell array, an address generation circuit, a control circuit, and a command generation circuit. The fuse cell array may store a fail address. ... Sk Hynix Inc

01/11/18 / #20180011635

Memory system and operating method thereof

A semiconductor memory device according to the present disclosure includes: a memory cell array including a plurality of planes; a command processing unit configured to generate an internal command to be executed by at feast one plane among the plurality of planes on the basis of external commands received from an external controller; a status register configured to store status information of the external commands by a tag included in the external command according to results of performing the internal command.. . ... Sk Hynix Inc

01/11/18 / #20180011527

Memory system and operating method thereof

A memory system includes: a memory device including a plurality of memory blocks configured to store data; and a controller configured to determine a power level for an operation corresponding to a command received from a host, and provide the determined power level to a memory block which is subject to the operation.. . ... Sk Hynix Inc

01/04/18 / #20180006077

Image sensor having photodiodes sharing one color filter and one micro-lens

An image sensor is provides. The image sensor may include first and second photodiodes, a first color filter shared by the first and the second photodiodes, and first and second floating diffusion regions coupled to the first and the second photodiodes, respectively.. ... Sk Hynix Inc

01/04/18 / #20180006052

Manufacturing method of semiconductor device

There are provided a manufacturing method of a semiconductor device. A manufacturing method of a semiconductor device includes forming a preliminary source stack structure including a first source layer, a first protective layer, a sacrificial layer, a second protective layer, and a second source layer, which are sequentially stacked in the recited order, forming channel layers extending through the second source layer and partially inside the first source layer, and growing a first region of an interlayer source layer from each channel layer, the first region of the interlayer source layer surrounding each channel layer in a region between the first and second protective layers.. ... Sk Hynix Inc

01/04/18 / #20180006047

Semiconductor device

A semiconductor device includes a common source region formed in a semiconductor substrate, a bit line formed over the semiconductor substrate, first and second vertical channel layers coupled between the bit line and the common source region, wherein the first and second vertical channel layers are alternately arranged on the semiconductor substrate, first conductive layers stacked over the semiconductor substrate to surround one side of the first vertical channel layer, second conductive layers stacked over the semiconductor substrate to surround one side of the second vertical channel layer, and a charge storage layer formed between the first vertical channel layer and the first conductive layers and between the second vertical channel layer and the second conductive layers.. . ... Sk Hynix Inc

01/04/18 / #20180005696

Method of programming semiconductor memory device

In a method of programming a semiconductor memory device, during a standby period, a standby voltage is applied to word lines coupled to a plurality of memory cells included in a selected memory cell string, and, during a first program period, a first pre-bias voltage is applied to a word line coupled to at least one of programmed memory cells of the selected memory cell string. The first pre-bias voltage is greater than the standby voltage.. ... Sk Hynix Inc

01/04/18 / #20180005675

Input circuit and semiconductor device including the same

An input circuit may include: an internal bias generation unit suitable for generating first and second bias voltages in response to a first enable signal; a buffer control unit suitable for comparing a reference voltage to the first and second bias voltages, and generating a plurality of buffer control signals based upon the comparison of the reference voltage with the first and second bias voltages; and a buffer unit including a plurality of buffers, wherein a buffer is driven to receive the reference voltage and an external input signal, and generates an internal signal, in response to an activated buffer control signal among the plurality of buffer control signals.. . ... Sk Hynix Inc

01/04/18 / #20180005673

Electronic device and method of driving the same

An electronic device includes a semiconductor memory that includes: a memory cell coupled between first and second lines and having a specific resistance state; a first read circuit suitable for supplying a predetermined pattern of a read voltage to the first line to generate a cell current corresponding to the specific resistance state of the memory cell during a read operation mode; and a second read circuit suitable for generating read data based on the cell current flowing through the second line during the read operation mode.. . ... Sk Hynix Inc

01/04/18 / #20180004677

Memory system and method for operating the same

A memory system includes a memory device including a memory block, the memory block including a plurality of memory cell groups, an address translator that maps a logical address of a data to a physical address of the memory block, and a controller configured to divide the plurality of memory cell groups into a plurality of first memory cell groups and at least one second memory cell group, and control the address translator so that the address translator maps a logical address of a data to a physical address of the first memory cell groups of the memory block and not in the at least one second memory cell group and switches the at least one second memory cell group with a selected first memory cell group among the plurality of the first memory cell groups when a predetermined period of time elapses.. . ... Sk Hynix Inc

01/04/18 / #20180004446

Memory controller, memory buffer chip and memory system

A memory system may be provided. The memory system may include a memory buffer chip coupled to one or more memory chips. ... Sk Hynix Inc

01/04/18 / #20180004440

Memory system and operating method thereof

A memory system may include: a memory device comprising a plurality of pages, which include a plurality of memory cells coupled to a plurality of word lines, and in which data is stored, a plurality of memory blocks in which the pages are included, a plurality of planes including the memory blocks, and a plurality of memory dies in which the planes are included; and a controller including a first memory, the controller configured to perform a command operation to store data segments of user data for the command operation in the memory blocks, and store meta segments of metadata for the command operation in the memory blocks and a second memory included in the host.. . ... Sk Hynix Inc

01/04/18 / #20180004439

Memory system and operating method thereof

A memory system may include: a memory device including a plurality of memory blocks, each memory block including a plurality of pages, each page including a plurality of memory cells operatively coupled to a word line for storing data; and a controller including a memory, the controller being suitable for performing a command operation corresponding to a command received from a host, storing data segments of user data and meta segments of metadata for the command operation in the memory, storing the data segments in first pages included in a first memory block among the memory blocks, storing the meta segments in second pages included in the first memory block, and storing segment informations for the meta segments, in spare regions of the second pages.. . ... Sk Hynix Inc

01/04/18 / #20180004429

Memory device for high speed data transfer

A memory device may include a data output controller for generating a first clock signal and a second clock signal in response to a read enable clock signal, a page buffer for storing data, and outputting the data to the data output controller in synchronization with the first clock signal, and a data output buffer for receiving the data from the page buffer and outputting the received data to the external device in synchronization with the second clock signal. The first clock signal is generated in response to a data output delay control signal, the second clock signal is generated irrespective of the data output delay control signal.. ... Sk Hynix Inc

01/04/18 / #20180004421

Semiconductor memory device and method of operating the same

Provided herein are a semiconductor memory device and a method of operating the semiconductor memory device, which have an improved processing speed for a suspend operation. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to perform a data operation corresponding to an externally provided command on the memory cell array and a control circuit configured to control the peripheral circuit to perform the data operation by sequentially executing instructions corresponding to a plurality of instruction lines of an operation algorithm for the data operation and, when a suspend command is provided during the data operation, to perform a preset suspend operation in any one of a checker mode and an instant mode.. ... Sk Hynix Inc

01/04/18 / #20180004420

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device including a plurality of memory blocks each of which includes a plurality of pages; and a controller suitable for obtain block physical to logical (p2l) data corresponding to a first memory block among the plurality of memory blocks, determine first and second target logical to physical (l2p) pages, one or more first target l2p segments stored in the first target l2p page and one or more second target l2p segments stored in the second target l2p page, based on the block p2l data and an l2p segment position table, obtain the first target l2p segments, and verify validity for one or more first p2l data included in the block p2l data, based on the first target l2p segments, wherein the controller obtains the second target l2p segments while verifying the validity for the first p2l data.. . ... Sk Hynix Inc








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