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Taiwan Semiconductor Manufacturing Company patents


Recent patent applications related to Taiwan Semiconductor Manufacturing Company. Taiwan Semiconductor Manufacturing Company is listed as an Agent/Assignee. Note: Taiwan Semiconductor Manufacturing Company may have other listings under different names/spellings. We're not affiliated with Taiwan Semiconductor Manufacturing Company, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Taiwan Semiconductor Manufacturing Company-related inventors


 new patent  Semiconductor device having a low power consumption

An amplifying unit includes a converter and a feedback mechanism. The converter has a supply input coupled to a supply node. ... Taiwan Semiconductor Manufacturing Company

 new patent  High voltage ldmos transistor and methods for manufacturing the same

A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. ... Taiwan Semiconductor Manufacturing Company

 new patent  Contact plugs and methods forming same

A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an inter-layer dielectric (ild). The dummy gate stack is in the ild, and the ild covers a source/drain region in the semiconductor region. ... Taiwan Semiconductor Manufacturing Company

 new patent  Semiconductor device structure and method for forming the same

A method for forming a semiconductor device structure is provided. The method includes forming a metal gate electrode structure and an insulating layer over the semiconductor substrate. ... Taiwan Semiconductor Manufacturing Company

 new patent  Semiconductor device with silicided source/drain region

A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.. . ... Taiwan Semiconductor Manufacturing Company

 new patent  Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same

Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. ... Taiwan Semiconductor Manufacturing Company

 new patent  Image sensor with reduced optical path

Among other things, one or more image sensors and techniques for forming image sensors are provided. An image sensor comprises a photodiode array configured to detect light. ... Taiwan Semiconductor Manufacturing Company

 new patent  Bsi image sensor and method of forming same

A backside illumination (bsi) image sensor and a method of forming the same are provided. A method includes forming a plurality of photosensitive pixels in a substrate, the substrate having a first surface and a second surface, the second surface being opposite the first surface, the substrate having one or more active devices on the first surface. ... Taiwan Semiconductor Manufacturing Company

 new patent  Semiconductor device and manufacturing method thereof

A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. ... Taiwan Semiconductor Manufacturing Company

 new patent  Finfet transistor with fin back biasing

A semiconductor device includes multiple first fins oriented lengthwise along a first direction and multiple first gate structures oriented lengthwise along a second direction generally perpendicular to the first direction. Each of the first fins includes an end that is narrower than a main body of the respective first fin. ... Taiwan Semiconductor Manufacturing Company

 new patent  Semiconductor device containing hemt and misfet and method of forming the same

A semiconductor structure with a misfet and a hemt region includes a first iii-v compound layer. A second iii-v compound layer is disposed on the first iii-v compound layer and is different from the first iii-v compound layer in composition. ... Taiwan Semiconductor Manufacturing Company

 new patent  Package-on-package structures and methods for forming the same

A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. ... Taiwan Semiconductor Manufacturing Company

 new patent  Packaging mechanisms for dies with different sizes of connectors

A semiconductor package includes a package substrate. A redistribution structure is bonded to the package substrate. ... Taiwan Semiconductor Manufacturing Company

 new patent  Packages with metal line crack prevention design

A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of metal pads electrically coupled to the plurality of redistribution lines. The plurality of metal pads includes a corner metal pad closest to the corner, wherein the corner metal pad is a center-facing pad having a bird-beak direction substantially pointing to a center of the package. ... Taiwan Semiconductor Manufacturing Company

07/12/18 / #20180197837

 new patent  Integrated fan-out package and the methods of manufacturing

A method includes forming a first through-via from a first conductive pad of a first device die, and forming a second through-via from a second conductive pad of a second device die. The first and second conductive pads are at top surfaces of the first and the second device dies, respectively. ... Taiwan Semiconductor Manufacturing Company

07/12/18 / #20180197826

 new patent  Three dimensional integrated circuit (3dic) with support structures

Some embodiments of the present disclosure relate to an integrated circuit. The integrated circuit has a first semiconductor die and a second semiconductor die. ... Taiwan Semiconductor Manufacturing Company

07/12/18 / #20180197811

 new patent  Molding compound structure

A device comprises a package component comprising a plurality of bumps formed on a first side of the package component, a semiconductor die mounted on the first side of the package component, a dielectric material formed over the first side of the package component, wherein four corners of the top surface of the package component are free from the dielectric material and a top package bonded on the first side of the package component, wherein the semiconductor die is located between the top package and the package component.. . ... Taiwan Semiconductor Manufacturing Company

07/12/18 / #20180197795

 new patent  Replacement gate process for semiconductor devices

Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (hm) layer over the electrode layer, and a second hm layer over the first hm layer. ... Taiwan Semiconductor Manufacturing Company

07/12/18 / #20180197783

 new patent  Method of forming a fin structure of semiconductor device

A method of forming a fin structure of a semiconductor device, such as a fin field effect transistor (finfet) is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin. ... Taiwan Semiconductor Manufacturing Company

07/12/18 / #20180197782

 new patent  Fin spacer protected source and drain regions in finfets

A method includes forming shallow trench isolation (sti) regions in a semiconductor substrate and a semiconductor strip between the sti regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. ... Taiwan Semiconductor Manufacturing Company

07/12/18 / #20180197775

 new patent  Semiconductor device with an interconnect structure and method for forming the same

A method for forming a semiconductor device structure includes providing a substrate and forming a gate electrode on the substrate. A first contact structure is formed in and on the gate electrode. ... Taiwan Semiconductor Manufacturing Company

07/12/18 / #20180197771

 new patent  Method for forming fin field effect transistor (finfet) device structure with interconnect structure

A semiconductor device structure includes a first metal layer formed over a substrate and an interconnect structure formed over the first metal layer. The interconnect structure includes an upper portion, a middle portion and a lower portion, the middle portion is connected between the upper portion and the lower portion. ... Taiwan Semiconductor Manufacturing Company

07/12/18 / #20180197755

 new patent  Integrated passive device package and methods of forming same

An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The package further includes redistribution layers (rdls) extending laterally past edges of the first die and the second die. ... Taiwan Semiconductor Manufacturing Company

07/12/18 / #20180197750

 new patent  Via connection to a partially filled trench

An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.. . ... Taiwan Semiconductor Manufacturing Company

07/12/18 / #20180197601

 new patent  Memory read stability enhancement with short segmented bit line architecture

In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. ... Taiwan Semiconductor Manufacturing Company

07/12/18 / #20180197582

 new patent  Memory architecture having first and second voltages

A memory macro includes: word lines; memory cells arranged in an array of columns and rows, the rows corresponding to the word lines; and switching circuits corresponding to the columns, each switching circuit being configured to selectively provide a first voltage value of a first voltage source or a different second voltage value of a second voltage source to corresponding voltage supply nodes of the columns; and wherein the word lines are configured to receive the second voltage value as a high logical value of the word lines; a selected one or more of the word lines is activated during a write operation, thereby defining an elapse of the write operation; and each switching circuit is further configured to selectively provide the corresponding first voltage value or the second voltage value substantially for an entirety of the write operation.. . ... Taiwan Semiconductor Manufacturing Company

07/12/18 / #20180196085

 new patent  Testing device

A testing device includes a circuit board, a carrier, a probe pin, a main body, a shaft, a pressing portion and a resilient spiral spring. The carrier is used to hold a device under test (dut). ... Taiwan Semiconductor Manufacturing Company

07/12/18 / #20180195999

 new patent  Method of using biochip with biosensors

A method of sensing a biological sample includes introducing a fluid containing the biological sample through a first opening in a substrate. The method further includes passing the fluid from the first opening to a first cavity through at least one microfluidic channel. ... Taiwan Semiconductor Manufacturing Company

07/12/18 / #20180195998

 new patent  Cmos compatible biofet

The present disclosure provides a bio-field effect transistor (biofet) and a method of fabricating a biofet device. The method includes forming a biofet using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (cmos) process. ... Taiwan Semiconductor Manufacturing Company

07/12/18 / #20180194618

 new patent  Mems devices and methods of forming the same

A mems device and methods of forming are provided. A dielectric layer of a first substrate is patterned to expose conductive features and a bottom layer through the dielectric layer. ... Taiwan Semiconductor Manufacturing Company

07/12/18 / #20180194613

 new patent  Mems devices including mems dies and connectors thereto

An embodiment is mems device including a first mems die having a first cavity at a first pressure, a second mems die having a second cavity at a second pressure, the second pressure being different from the first pressure, and a molding material surrounding the first mems die and the second mems die, the molding material having a first surface over the first and the second mems dies. The device further includes a first set of electrical connectors in the molding material, each of the first set of electrical connectors coupling at least one of the first and the second mems dies to the first surface of the molding material, and a second set of electrical connectors over the first surface of the molding material, each of the second set of electrical connectors being coupled to at least one of the first set of electrical connectors.. ... Taiwan Semiconductor Manufacturing Company

07/05/18 / #20180190833

Semiconductor device and manufacturing method thereof

A semiconductor device including a field effect transistor (fet) device includes a substrate and a channel structure formed of a two-dimensional (2d) material. An interfacial layer is formed on the channel structure. ... Taiwan Semiconductor Manufacturing Company

07/05/18 / #20180190810

Semiconductor device and manufacturing method thereof

A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. ... Taiwan Semiconductor Manufacturing Company

07/05/18 / #20180190809

Semiconductor device and a method for fabricating the same

A semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ild) layer formed over the electronic device, a wiring pattern formed on the ild layer and a contact formed in the ild layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. An insulating liner layer is provided on sidewalls of the contact between the contact and the ild layer. ... Taiwan Semiconductor Manufacturing Company

07/05/18 / #20180190799

Devices having a semiconductor material that is semimetal in bulk and methods of forming the same

Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. ... Taiwan Semiconductor Manufacturing Company

07/05/18 / #20180190796

Devices including gate spacer with gap or void and methods of forming the same

Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. ... Taiwan Semiconductor Manufacturing Company

07/05/18 / #20180190788

Devices with strained source/drain structures and method of forming the same

A device includes a substrate and a gate structure over the substrate. The device further includes source/drain (s/d) features in the substrate. ... Taiwan Semiconductor Manufacturing Company

07/05/18 / #20180190754

Semiconductor device and a method for fabricating the same

A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.. ... Taiwan Semiconductor Manufacturing Company

07/05/18 / #20180190654

Semiconductor device and manufacturing method thereof

In a method for manufacturing a semiconductor device, a doped layer doped with a first dopant is formed in a substrate. A semiconductor layer is formed on the doped layer. ... Taiwan Semiconductor Manufacturing Company

07/05/18 / #20180190653

Semiconductor device and manufacturing method thereof

In in a method of manufacturing a semiconductor device, an interlayer dielectric (ild) layer is formed over an underlying structure. The underlying structure includes a gate structure disposed over a channel region of a fin structure, and a first source/drain epitaxial layer disposed at a source/drain region of the fin structure. ... Taiwan Semiconductor Manufacturing Company

07/05/18 / #20180190652

Semiconductor device and manufacturing method thereof

In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. ... Taiwan Semiconductor Manufacturing Company

07/05/18 / #20180190638

Cowos structures and method of forming the same

Chip on wafer on substrate structures and methods of forming are provided. The method includes attaching a first die and a second die to an interposer. ... Taiwan Semiconductor Manufacturing Company

07/05/18 / #20180190578

Fan-out package structure and method

A device comprises a semiconductor structure in a molding compound layer, a first polymer layer on the molding compound layer, a second polymer layer on the first polymer layer, a first interconnect structure having a first via portion in the first polymer layer and a first metal line portion in the second polymer layer, a third polymer layer on the second polymer layer, a fourth polymer layer on the third polymer layer and a second interconnect structure having a second via portion in the third polymer layer and a second metal line portion in the fourth polymer layer, wherein the second via portion is vertically aligned with the first via portion.. . ... Taiwan Semiconductor Manufacturing Company

07/05/18 / #20180190559

Packaged semiconductor devices and methods of packaging semiconductor devices

Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a molding compound disposed around the integrated circuit die, and an interconnect structure disposed over the integrated circuit die and the molding compound. ... Taiwan Semiconductor Manufacturing Company

07/05/18 / #20180190555

Molding structure for wafer level package

Apparatus, and methods of manufacture thereof, in which a molding compound is formed between spaced apart microelectronic devices. The molding compound comprises micro-filler elements. ... Taiwan Semiconductor Manufacturing Company

07/05/18 / #20180190504

Semiconductor device and a method for fabricating the same

In a method of manufacturing a semiconductor device, an interlayer dielectric (ild) layer is formed over an underlying structure. The underlying structure includes gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate, source/drain epitaxial layers disposed between two adjacent gate structures, and an etching-stop layer (esl) covering the source/drain epitaxial layers. ... Taiwan Semiconductor Manufacturing Company

07/05/18 / #20180190494

Gate electrodes with notches and methods for forming the same

A device includes a semiconductor substrate, and a device isolation (di) region extending from a top surface of the semiconductor substrate into the semiconductor substrate. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the di region. ... Taiwan Semiconductor Manufacturing Company

07/05/18 / #20180190345

Three dimensional dual-port bit cell and method of using same

A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.. ... Taiwan Semiconductor Manufacturing Company

07/05/18 / #20180188756

Low-dropout regulator

A low-dropout (ldo) regulator is provided. The ldo regulator comprises a first circuit operating as a closed loop control system. ... Taiwan Semiconductor Manufacturing Company

07/05/18 / #20180188451

Method of fabrication polymer waveguide

A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (rdl) over the substrate in the electro-interconnection region. ... Taiwan Semiconductor Manufacturing Company

06/28/18 / #20180183449

Pipelined sar with tdc converter

The present disclosure, in some embodiments, relates to an analog-to-digital converter (adc). The adc has a successive approximation register (sar) configured to receive an input signal and to generate a first digital signal having a plurality of most significant bits and a residue voltage. ... Taiwan Semiconductor Manufacturing Company

06/28/18 / #20180183414

Cell of transmission gate free circuit and integrated circuit layout including the same

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.. ... Taiwan Semiconductor Manufacturing Company

06/28/18 / #20180182866

Finfet isolation structure and method for fabricating the same

A semiconductor device includes a semiconductor substrate and a semiconductor fin on the semiconductor substrate and a fin isolation structure on the semiconductor substrate. The fin isolation structure has an air gap dividing the semiconductor fin into two portions of the semiconductor fin, in which the air gap extends into the semiconductor substrate for a distance. ... Taiwan Semiconductor Manufacturing Company

06/28/18 / #20180182859

Metal gate structure and methods thereof

Provided is a metal gate structure and related methods that include forming a first fin and a second fin on a substrate. In various embodiments, the first fin has a first gate region and the second fin has a second gate region. ... Taiwan Semiconductor Manufacturing Company

06/28/18 / #20180182858

Circuits using gate-all-around technology

A semiconductor structure includes a first gaa transistor and a second gaa transistor. The first gaa transistor includes: a first diffusion region, a second diffusion region, and a first nanowire. ... Taiwan Semiconductor Manufacturing Company

06/28/18 / #20180182857

Semiconductor device and manufacturing method thereof

A fin fet semiconductor device includes a fin structure extending in a first direction and extending from an isolation insulating layer. The fin fet device also includes a gate stack including a gate electrode layer, a gate dielectric layer, side wall insulating layers disposed at both sides of the gate electrode layer, and interlayer dielectric layers disposed at both sides of the side wall insulating layers. ... Taiwan Semiconductor Manufacturing Company

06/28/18 / #20180182792

Protection ring for image sensors

Some embodiments relate to a pixel sensor array including a plurality of photosensors arranged in a semiconductor substrate. A protection ring circumscribes an outer perimeter of the pixel sensor array. ... Taiwan Semiconductor Manufacturing Company

06/28/18 / #20180182772

Semiconductor device and method of manufacturing the same

In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. ... Taiwan Semiconductor Manufacturing Company

06/28/18 / #20180182724

Packaging assembly and method of making the same

A packaging assembly includes a semiconductor device. The semiconductor device includes a conductive pad having a first width, and an under-bump metallization (ubm) layer on the conductive pad, wherein the ubm layer has a second width greater than the first width. ... Taiwan Semiconductor Manufacturing Company

06/28/18 / #20180182703

Interconnect structure and method of forming the same

An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (lk) dielectric layer over a substrate; a first conductive feature in the lk dielectric layer, wherein the first conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a first bottom surface contacting the lk dielectric layer; a first dielectric feature along an upper portion of the first sidewall, wherein a length of the first dielectric feature is at least 10 percent less than a length of the first sidewall; and a second dielectric feature along an upper portion of the second sidewall. ... Taiwan Semiconductor Manufacturing Company

06/28/18 / #20180182673

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. ... Taiwan Semiconductor Manufacturing Company

06/28/18 / #20180181738

Fingerprint sensor pixel array and methods of forming same

A device package includes a sensor die, one or more additional dies adjacent the sensor die, and a molding compound encircling the sensor die and the one or more additional dies. The device package further includes redistribution layers over the sensor die, the one or more additional dies, and the molding compound. ... Taiwan Semiconductor Manufacturing Company

06/28/18 / #20180181012

Homogeneous thermal equalization with active device

A system and method is provided for providing a thermal distribution on a workpiece during a lithographic process. The system provides a source of lithographic energy to workpiece, such as a workpiece having a lithographic film formed thereover. ... Taiwan Semiconductor Manufacturing Company

06/28/18 / #20180179047

Rough anti-stiction layer for mems device

The present disclosure relates to a mems package with a rough metal anti-stiction layer, to improve stiction characteristics, and an associated method of formation. In some embodiments, the mems package includes a mems ic bonded to a cmos ic. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180177055

Material composition and methods thereof

Provided is a material composition and method that includes forming a patterned resist layer on a substrate. The patterned resist layer has a first pattern width, and the patterned resist layer has a first pattern profile having a first proportion of active sites. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175288

Determining a characteristic of a monitored layer on an integrated chip

The present disclosure relates to a method for determining a characteristic of a monitored layer of an integrated chip structure. In some embodiments, the method may be performed by forming an integrated chip structure over a substrate. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175214

Semiconductor device and manufacturing method thereof

A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175213

2-d material transistor with vertical structure

Semiconductor structures including two-dimensional (2-d) materials and methods of manufacture thereof are described. By implementing 2-d materials in transistor gate architectures such as field-effect transistors (fets), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2-d materials such as graphene, transition metal dichalcogenides (tmds), or phosphorene.. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175203

Semiconductor device and method

A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a first lateral width, and forming a first via opening over the gate structure. The first via opening has a lowermost portion that exposes an uppermost surface of the gate structure. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175201

Finfet structures and methods of forming the same

A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175200

Pmos finfet

A system is configured to perform plasma related fabrication processes. The system includes a process chamber and a wafer stage positioned within the process chamber. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175196

Semiconductor epitaxy bordering isolation structure

A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175175

Conformal transfer doping method for fin-like field effect transistor

Doping techniques for fin-like field effect transistors (finfets) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175173

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate, a fin structure protruding from the substrate, a gate insulating layer covering a channel region formed of the fin structure, a gate electrode layer covering the gate insulating layer, and isolation layers disposed on opposite sides of the fin structure. The fin structure includes a bottom portion, a neck portion, and a top portion sequentially disposed on the substrate. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175172

Finfet structures and methods of forming the same

A method includes forming a first fin and a second fin over a substrate, depositing an isolation material surrounding the first and second fins, forming a gate structure along sidewalls and over upper surfaces of the first and second fins, recessing the first and second fins outside of the gate structure to form a first recess in the first fin and a second recess in the second fin, epitaxially growing a first source/drain material protruding from the first and second recesses, and epitaxially growing a second source/drain material on the first source/drain material, wherein the second source/drain material grows at a slower rate on outermost surfaces of opposite ends of the first source/drain material than on surfaces of the first source/drain material between the opposite ends of the first source/drain material, and wherein the second source/drain material has a higher doping concentration than the first source/drain material.. . ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175171

Method of fabricating a semiconductor device

A method for fabricating a semiconductor device includes forming a gate electrode structure over a first region of a semiconductor substrate, and selectively forming an oxide layer overlying the gate electrode structure by reacting a halide compound with oxygen to increase a height of the gate electrode structure. The halide compound may be silicon tetrachloride, and the oxide layer may be silicon dioxide. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175170

Source and drain formation technique for fin-like field effect transistor

Source and drain formation techniques for fin-like field effect transistors (finfets) are disclosed herein. An exemplary method includes forming a fin structure, wherein the fin structure include a channel region disposed between a source region and a drain region; forming a gate structure over the channel region of the fin structure; forming a solid phase diffusion (spd) layer over the source region and the drain region of the fin structure; and performing a microwave annealing (mwa) process to diffuse a dopant from the spd layer into the source region and the drain region of fin structure. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175168

Vertical power mosfet and methods for forming the same

A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175165

Etching back and selective deposition of metal gate

A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175164

3d capacitor and method of manufacturing same

A three-dimensional (3d) capacitor includes a semiconductor substrate; a fin structure including one or more fins formed on the semiconductor substrate; an insulator material formed between each of the one or more fins; a dielectric layer formed on a first portion of the fin structure; a first electrode formed on the dielectric layer; spacers formed on sidewalls of the first electrode; and a second electrode formed on a second portion of the fin structure. The first and second portions are different. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175162

Method for manufacturing semiconductor structure with multi spacers

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175159

Bi-layer metal deposition in silicide formation

A method includes performing a first sputtering to form a first metal film on a surface of a semiconductor region. The first sputtering is performed using a first ion energy. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175144

Semiconductor device and manufacturing method thereof

A method includes forming a crown structure over a substrate; forming fins in the crown structure; forming an intra-device isolation region between the fins and forming inter-device isolation regions on opposing sides of the crown structure; forming a gate structure over the fins; forming a dielectric layer that extends continuously over the inter-device isolation regions, the fins and the intra-device isolation region; performing an etching process to reduce a thickness of the dielectric layer, where after the etching process, upper surfaces of the inter-device isolation regions and upper surfaces of the fins are exposed while an upper surface of the intra-device isolation region is covered by a remaining portion of the dielectric layer; and forming an epitaxial structure over the exposed upper surfaces of the fins, where after the epitaxial structure is formed, there is a void between the epitaxial structure and the intra-device isolation region.. . ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175137

Semiconductor devices, methods of manufacture thereof, and capacitors

Semiconductor devices, methods of manufacture thereof, and capacitors are disclosed. In some embodiments, a semiconductor device includes a first capacitor and a protection device coupled in series with the first capacitor. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175046

Source and drain formation technique for fin-like field effect transistor

Source and drain formation techniques are disclosed herein for fin-like field effect transistors (finfets). An exemplary method for forming epitaxial source/drain features for a finfet includes epitaxially growing a semiconductor material on a plurality of fins using a silicon-containing precursor and a chlorine-containing precursor. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175036

Multi-gate device and method of fabrication thereof

A semiconductor includes a first transistor and a second transistor. The first transistor includes a first and a second epitaxial layer, formed of a first semiconductor material. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175032

Fin-like field effect transistor (finfet) device and method of manufacturing same

A semiconductor device includes a semiconductor substrate and two fin structures. Channels of the fin structures include a second semiconductor material portion over a first semiconductor material portion. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175031

Integrated circuit and manufacturing method thereof

An integrated circuit includes first and second semiconductor fins, first and second epitaxy structures, and first and second dielectric fin sidewall structures. The first and second epitaxy structures are respectively on the first and second semiconductor fins. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175030

Semiconductor device

A semiconductor device includes a substrate, a core device disposed above the substrate, and an input/output (i/o) device disposed above the substrate. The core device includes a first gate electrode having a bottom surface and a sidewall that define a first interior angle therebetween. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175029

Integrated circuit with a gate structure and method making the same

The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure on a substrate; a first gate stack and a second gate stack formed on the fin structure; a dielectric material layer disposed on the first and second gate stacks, wherein the dielectric layer includes a first portion disposed on a sidewall of the first gate stack with a first thickness and a second portion disposed on a sidewall of the second gate stack with a second thickness greater than the first thickness; a first gate spacer disposed on the first portion of the dielectric material layer; and a second gate spacer disposed on the second portion of the dielectric material layer.. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175026

Rom chip manufacturing structures

An integrated circuit (ic) chip embodiment includes first and second rom cells arranged in a same row of a rom array. The first and second rom cells include first portions of first and second gate structures, respectively. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175013

Wafer-level underfill and over-molding

A mold includes a top portion, and an edge ring having a ring-shape. The edge ring is underlying and connected to edges of the top portion. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180175012

Seal ring structures and methods of forming same

A three-dimensional (3d) integrated circuit (ic) includes a first ic die and a second ic die. The first ic die includes a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174984

Packaging devices and methods for semiconductor devices

Packaging devices and methods for semiconductor devices are disclosed. In some embodiments, a packaging device for a semiconductor device includes a packaging substrate including a semiconductor device mounting region. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174967

Power strap structure for high performance and low current density

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method is performed by forming gate structures and middle-end-of-the-line (meol) structures extending in a first direction over an active area of a substrate. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174963

Conductive structure and method of forming the same

Conductive structures and method of manufacture thereof are disclosed. A barrier layer can line the first recess of a substrate. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174962

Interconnection structure and manufacturing method thereof

An interconnection structure includes a first dielectric layer, a first conductor, an etch stop layer, and a second dielectric layer. The first conductor is partially in the first dielectric layer and having a portion protruding from the first dielectric layer. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174961

Air gap structure and method

A device comprises a first protection layer over sidewalls and a bottom of a first trench in a first dielectric layer, a first barrier layer over the first protection layer, a first metal line in the first trench, a second protection layer over sidewalls and a bottom of a second trench in the first dielectric layer, a second barrier layer over the second protection layer, a second metal line in the first trench, an air gap between the first trench and the second trench and a third protection layer over sidewalls of a third trench in the first dielectric layer, wherein the first protection layer, the second protection layer and the third protection are formed of a same material.. . ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174957

Method of forming interconnection structure

A method includes depositing a dielectric structure on a first conductive structure, etching the dielectric structure to form a via opening, etching the dielectric structure to form a trench over the via opening, depositing a first protective layer on a bottom surface of the trench, filling the trench and the via opening with a second conductive structure, and removing the first protective layer to form an air gap between the second conductive structure and the dielectric structure.. . ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174956

Method for manufacturing interconnection

A method for manufacturing an interconnect structure is provided, and the method is as below. A dielectric layer is deposited over a substrate. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174937

Info structure with copper pillar having reversed profile

A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174930

Method for testing bridging in adjacent semiconductor devices and test structure

Bridging testing method between adjacent semiconductor devices includes forming patterned diffusion region on semiconductor substrate, and forming first conductive layer over diffusion region. First conductive layer is patterned in same pattern as patterned diffusion region. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174925

Structure and formation method of semiconductor device structure

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174922

Finfet structures and methods of forming the same

A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.. . ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174919

Dual epitaxial growth process for semiconductor device

A method of forming a semiconductor device includes forming first and second fin structures on a substrate and a patterned polysilicon structure on first portions of the first and second fin structures. The method further includes depositing an insulating layer on second portions of the first and second fin structures and on the patterned polysilicon structure, which may be followed by selectively removing the insulating layer from the second portions and patterning a first hard mask layer on the second portion of the second fin structure. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174918

Finfet devices and methods of forming

In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a first material of a first fin. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174917

Finfet structures and methods of forming the same

An embodiment is a method including forming a first fin in a first region of a substrate and a second fin in a second region of the substrate, forming a first isolation region on the substrate, the first isolation region surrounding the first fin and the second fin, forming a first dummy gate over the first fin and a second dummy gate over the second fin, the first dummy gate and the second dummy gate having a same longitudinal axis, replacing the first dummy gate with a first replacement gate and the second dummy gate with a second replacement gate, forming a first recess between the first replacement gate and the second replacement gate, and a filling an insulating material in the first recess to form a second isolation region.. . ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174916

Gate structures with various widths and method for forming the same

Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a first metal gate structure formed over the substrate. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174915

Method of manufacturing a semiconductor device with metal gate etch selectivity control

A method of manufacturing a semiconductor device includes forming a first layer of a conductive material in gate spaces created by removing portions of a dummy gate structure. The first layer further includes a top layer on an entire structure formed on a fin structure, and a gate space for a short channel gate and a gate space for a long channel gate. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174914

Multi-depth etching in semiconductor arrangement

Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174913

Semiconductor device and method

A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having ge impurities, the source/drain region free of the ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the ge impurities; and forming a metal contact electrically coupled to the silicide layer.. . ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174912

Semiconductor device having merged epitaxial features with arc-like bottom surface and method of making the same

A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate, two semiconductor fins over the substrate, and a semiconductor feature over the two semiconductor fins. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174904

Self-aligned spacers and method forming same

A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174898

Device and method for reducing contact resistance of a metal

A device comprises a semiconductor substrate; a dielectric layer deposited over the semiconductor substrate, the dielectric layer including a trench; and a structure in the trench. The structure includes a chemical vapor deposition (cvd) tan layer formed on a side wall of the trench; a physical vapor deposition (pvd) ta layer formed over the cvd tan layer; and a metal-containing layer formed over the pvd ta layer.. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174888

Method for forming trench liner passivation

In a method for fabricating a semiconductor device, a trench is etched in a semiconductor substrate having a top surface, and a lining oxide layer is formed conformal to the trench. A negatively-charged liner covering the lining oxide layer and conformal to the trench is formed. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174886

Interconnect structure and method of forming the same

An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (esl); an upper low-k (lk) dielectric layer over the lower esl; a first conductive feature in the upper lk dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower esl; a first gap along an interface of the first conductive feature and the upper lk dielectric layer; and an upper esl over the upper lk dielectric layer, the first conductive feature, and the first gap.. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174885

Semiconductor device, method, and tool of manufacture

An embodiment is an apparatus. The apparatus includes: a collective wafer platter including a plurality of individual wafer pockets, the individual wafer pockets having respective individual wafer platters, the individual wafer platters configured to rotate around respective first axes, the collective wafer platter configured to rotate around a second axis; a motor coupled to the collective wafer platter; and a control unit configured to control the motor such that the individual wafer platters rotate around the respective first axes, and the collective wafer platter rotates around the second axis.. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174883

Plasma distribution control

A system is configured to perform plasma related fabrication processes. The system includes a process chamber and a wafer stage positioned within the process chamber. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174865

Fan-out structure and method of fabricating the same

A semiconductor structure and a method of forming include a first semiconductor die and a first dummy die over a carrier, wherein a thickness of the first semiconductor die is greater than a thickness of the first dummy die, a first molding compound layer over the carrier, the first molding compound layer extending along sidewalls of the first semiconductor die and the first dummy die and a first interconnect structure over the first molding compound layer, wherein the first interconnect structure comprises a first metal feature electrically coupled to the first semiconductor die and the first molding compound layer is formed between the first dummy die and the first metal feature.. . ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174854

Fin-like field effect transistor patterning methods for increasing process margins

Methods are disclosed herein for patterning integrated circuit devices, such as fin-like field effect transistor devices. An exemplary method includes forming a material layer that includes an array of fin features, and performing a fin cut process to remove a subset of the fin features. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174853

Pattern fidelity enhancement with directional patterning technology

A method for semiconductor manufacturing includes providing a substrate and a patterning layer over the substrate; forming a hole in the patterning layer; applying a first directional etching along a first direction to inner sidewalls of the hole; and applying a second directional etching along a second direction to the inner sidewalls of the hole, wherein the second direction is different from the first direction.. . ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174846

Semiconductor structure having low-k spacer and method of manufacturing the same

The present disclosure provides a semiconductor structure, including a semiconductor fin, a metal gate over the semiconductor fin, and a sidewall spacer composed of low-k dielectric surrounding opposing sidewalls of the metal gate. A portion of the sidewall spacer comprises a tapered profile with a greater separation of the opposing sidewalls toward a top portion and a narrower separation of the opposing sidewalls toward a bottom portion of the sidewall spacer. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174839

Lithography patterning with sub-resolution assistant patterns and off-axis illumination

A photolithography system includes a substrate stage for holding a workpiece, and a mask having main patterns and sub-resolution assistant patterns. The system further includes a diffractive optical element (doe) for directing a radiation having an aerial image of the main patterns onto the workpiece. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174837

Material composition and process for substrate modification

Provided is a material composition and method for substrate modification. A substrate is patterned to include a plurality of features. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174831

Hardmask composition and methods thereof

Provided is a material composition and method for that includes forming a silicon-based resin over a substrate. In various embodiments, the silicon-based resin includes a nitrobenzyl functional group. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174830

Material composition and methods thereof

Provided is a material composition and method that includes forming a patterned resist layer on a substrate, where the patterned resist layer has a first line width roughness. In various embodiments, the patterned resist layer is coated with a treatment material, where a first portion of the treatment material bonds to surfaces of the patterned resist layer. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174829

Cmp cleaning system and method

A cleaning apparatus and a method of using the cleaning apparatus are provided. The method includes first moving a pencil pad into contact with a top surface of a wafer, wherein the pencil pad is connected to a pivot arm and second moving the pivot arm in a sweeping motion from a first zone to a second zone, the first zone being closer to a center of the top surface of the wafer than the second zone, wherein the sweeping motion is controlled by a controller, the pivot arm moves at a first speed in the first zone and the pivot arm moves at a second speed in the second zone, wherein the first speed is different from the second speed.. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174828

Patterning process with silicon mask layer

A lithography method is provided in accordance with some embodiments. The lithography method includes forming an under layer on a substrate; forming a silicon-containing middle layer on the under layer, wherein the silicon-containing middle layer has a thermal base generator (tbg) composite; forming a photosensitive layer on the silicon-containing middle layer; performing an exposing process to the photosensitive layer; and developing the photosensitive layer, thereby forming a patterned photosensitive layer.. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174821

Nanowire field effect transistor device having a replacement gate

A device includes a substrate, a buffer layer, a nanowire, a gate structure, and a remnant of a sacrificial layer. The buffer layer is above the substrate. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174820

Plasma enhanced atomic layer deposition

According to one example, a process includes performing a first plurality of layer deposition cycles of a deposition process on a substrate, and after performing the first plurality of layer deposition cycles, performing a plasma enhanced layer deposition cycle comprising a plasma treatment process. The first plurality of layer deposition cycles are performed without a plasma treatment process.. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174807

Plasma generation for ion implanter

An ion implanter comprises a dissociation chamber in the ion implanter. The dissociation chamber has an input port for receiving a gas and an output port for outputting ions. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174656

Adjustment circuit for partitioned memory block

The present disclosure describes an adjustment circuit that can be used, for example, in a memory system with partitioned memory blocks. The adjustment circuit can include a controller circuit, a timer circuit, and a temperature adaptive reference (tar) generator. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174649

Pre-charging bit lines through charge-sharing

In one embodiment, a static random access memory (sram) device is provided. The sram device comprises a plurality of memory cells, a bit line coupled to a first set of the plurality of memory cells at data nodes, and a first voltage supply line coupled to a second set of the plurality of memory cells. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180174643

Dual rail device with power detector for controlling power to first and second power domains

A dual rail device includes a first power domain circuit coupled to a first power supply through a first header control switch and a second power domain circuit coupled to a second power supply. The first and second power supplies have different steady-state voltage levels. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180173932

Fingerprint sensor device and method

A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180173832

Circuit testing and manufacture using multiple timing libraries

A method includes generating a first timing library for a first set of circuit elements for a first set of input parameters. Generating the first timing library includes determining device characteristics for each of the circuit elements in the first set of circuit elements and storing the determined device characteristics in a database. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180173117

Extreme ultraviolet lithography system with debris trapper on exhaust line

An extreme ultraviolet (euv) lithography system includes a collector designed to collect and reflect euv radiation, a cover integrated with the collector, a first exhaust line connected to the cover and configured to receive debris vapor from the collector, a debris trapper connected to the first exhaust line and configured to trap the debris vapor, and a second exhaust line connected to the debris trapper.. . ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180173110

Noise reduction for overlay control

The present disclosure provides a method. The method includes patterning a substrate by a patterning tool; collecting a plurality of overlay errors from a plurality of fields on the substrate; identifying noise from the plurality of overlay errors by applying a first filtering operation and a second filtering operation that is different from the first filtering operation. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180173101

Extreme ultraviolet photoresist with high-efficiency electron transfer

A method includes forming a photoresist layer over a substrate, wherein the photoresist layer includes a polymer, a sensitizer, and a photo-acid generator (pag), wherein the sensitizer includes a resonance ring that includes nitrogen and at least one double bond. The method further includes performing an exposing process to the photoresist layer. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180173096

Extreme ultraviolet photolithography method with developer composition

The present disclosure provides a method for lithography patterning in accordance with some embodiments. The method includes forming a photoresist layer over a substrate, wherein the photoresist layer includes a metal-containing chemical; performing an exposing process to the photoresist layer; and performing a first developing process to the photoresist layer using a first developer, thereby forming a patterned resist layer, wherein the first developer includes a first solvent and a chemical additive to remove metal residuals generated from the metal-containing chemical.. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180173093

Pellicle structures and methods of fabricating thereof

A structure including an euv mask and a pellicle attached to the euv mask. The pellicle includes a pellicle frame and a plurality of pellicle membrane layers attached to the pellicle frame. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180173092

Pellicle fabrication methods and structures thereof

A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180173090

Optical proximity correction methodology using pattern classification for target placement

Optical proximity correction (opc) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (ic) design layout having an ic pattern; generating target points for a contour corresponding with the ic pattern based on a target placement model, wherein the target placement model is selected based on a classification of the ic pattern; and performing an opc on the ic pattern using the target points, thereby generating a modified ic design layout. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180173089

Extreme ultraviolet lithography system, device, and method for printing low pattern density features

A lithography system includes a radiation source configured to generate an extreme ultraviolet (euv) light. The lithography system includes a mask that defines one or more features of an integrated circuit (ic). ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180172627

On-chip reference electrode for biologically sensitive field effect transistor

A semiconductor device including a biosensor with an on-chip reference electrode embedded within the semiconductor device, and associated manufacturing methods are provided. In some embodiments, a pair of source/drain regions is disposed within a device substrate and separated by a channel region. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180172514

Spectroscopic overlay metrology

A spectroscopic overlay metrology system and corresponding spectroscopic overlay metrology methods are disclosed herein for improving overly measurement accuracy, optimizing overlay recipes, and/or minimizing (or eliminating) asymmetry-induced overly error from overlay measurements. An exemplary method includes generating a diffraction spectrum by an overlay target from incident radiation having more than one wavelength. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180171226

Wet etch chemistry for selective silicon etch

For a metal gate replacement integration scheme, the present disclosure describes removing a polysilicon gate electrode with a highly selective wet etch chemistry without damaging surrounding layers. For example, the wet etch chemistry can include one or more alkaline solvents with a steric hindrance amine structure, a buffer system that includes tetramethylammonium hydroxide (tmah) and monoethanolamine (mea), one or more polar solvents, and water.. ... Taiwan Semiconductor Manufacturing Company

06/21/18 / #20180169825

Method and system for monitoring polishing pad before cmp process

A chemical mechanical polish (cmp) system is provided. The cmp system includes a platen rotatable about a rotation axis. ... Taiwan Semiconductor Manufacturing Company

06/14/18 / #20180167075

Hybrid analog-to-digital converter

An analog-to-digital converter (adc) circuit includes a first adc stage comprising a first successive approximation register (sar) circuit that is configured to convert a current analog input signal into a first digital signal corresponding to a most-significant-bits (msb) portion of a current digital output signal, and to generate a residual voltage corresponding to a voltage value difference between the current analog input signal and the first digital signal; a second adc stage, coupled to the first adc stage, comprising an amplifier circuit that is configured to amplify the residual voltage; and a third adc stage, coupled to the second adc stage, comprising a second sar circuit that is configured to convert the amplified residual voltage into a second digital signal corresponding to a least-significant-bits (lsb) portion of the current digital output signal when the first sar circuit receives a subsequent analog input signal.. . ... Taiwan Semiconductor Manufacturing Company

06/14/18 / #20180167073

Novel phase-locked-loop architecture

A phase-lock-loop (pll) circuit includes a reference pll circuit configured to generate a reference clock signal; a single clock tree circuit, coupled to the reference pll circuit, and configured to distribute the reference clock signal; and a plurality of designated pll circuits coupled to the clock tree circuit, wherein the designated pll circuits are each configured to receive the distributed reference clock signal through the single clock tree circuit and provide a respective clock signal based on the reference clock signal.. . ... Taiwan Semiconductor Manufacturing Company








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