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Tela Innovations Inc patents


Recent patent applications related to Tela Innovations Inc. Tela Innovations Inc is listed as an Agent/Assignee. Note: Tela Innovations Inc may have other listings under different names/spellings. We're not affiliated with Tela Innovations Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Tela Innovations Inc-related inventors


Coarse grid design methods and structures

A layer of a mask material is deposited on a substrate. A beam of energy is scanned across the mask material in a rasterized linear pattern and in accordance with a scan pitch that is based on a pitch of conductive structure segments to be formed on the substrate. ... Tela Innovations Inc

Methods for cell phasing and placement in dynamic array architecture and implementation of the same

A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. ... Tela Innovations Inc

Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same

A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. ... Tela Innovations Inc

Methods, structures, and designs for self-aligning local interconnects used in integrated circuits

An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. ... Tela Innovations Inc

Super-self-aligned contacts and method for making the same

A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. ... Tela Innovations Inc

Methods for multi-wire routing and apparatus implementing same

A rectangular interlevel connector array (rica) is defined in a semiconductor chip. To define the rica, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. ... Tela Innovations Inc

Semiconductor chip and method for manufacturing the same

Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other by a gate pitch of less than or equal to about 193 nanometers. Each gate structure has a substantially rectangular shape with a width of less than or equal to about 45 nanometers and is positioned to extend lengthwise along a corresponding gate gridline. ... Tela Innovations Inc

Semiconductor chip and method for manufacturing the same

Gate structures formed from substantially rectangular shaped gate structure layout shapes positioned on a gate horizontal grid having at least seven gate gridlines within a region. A first-metal layer including first-metal structures formed from substantially rectangular shaped first-metal structure layout shapes is formed above top surfaces of the gate structures within the region. ... Tela Innovations Inc

Optimizing layout of irregular structures in regular layout context

A plurality of regular wires are formed within a given chip level, each having a linear-shape with a length extending in a first direction and a width extending in a second direction perpendicular to the first direction. The plurality of regular wires are positioned according to a fixed pitch such that a distance as measured in the second direction between lengthwise centerlines of any two regular wires is an integer multiple of the fixed pitch. ... Tela Innovations Inc

Semiconductor chip and method for manufacturing the same

Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other by a gate pitch of less than or equal to about 193 nanometers. Each gate structure has a substantially rectangular shape with a width of less than or equal to about 45 nanometers and is positioned to extend lengthwise along a corresponding gate gridline. ... Tela Innovations Inc

Methods for linewidth modification and apparatus implementing the same

A linear-shaped core structure of a first material is formed on an underlying material. A layer of a second material is conformally deposited over the linear-shaped core structure and exposed portions of the underlying material. ... Tela Innovations Inc

Circuitry and layouts for xor and xnor logic

An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. ... Tela Innovations Inc

Integrated circuit cell library for multiple patterning

A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. ... Tela Innovations Inc

Semiconductor chip including integrated circuit defined within dynamic array section

A semiconductor chip includes four linear-shaped conductive structures that each form a gate electrode of corresponding transistor of a first transistor type and a gate electrode of a corresponding transistor of a second transistor type. First and second ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines separated by a gate electrode pitch. ... Tela Innovations Inc

06/29/17 / #20170186771

Semiconductor chip and method for manufacturing the same

A first transistor has a gate electrode formed by a substantially linear portion of a first conductive structure. A second transistor has a gate electrode formed by a substantially linear portion of a second conductive structure. ... Tela Innovations Inc

06/22/17 / #20170177779

Integrated circuit implementing scalable meta-data objects

A method is disclosed for defining an integrated circuit. The method includes generating a digital data file that includes both electrical connection information and physical topology information for a number of circuit components. ... Tela Innovations Inc

06/15/17 / #20170170194

Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same

A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. ... Tela Innovations Inc

04/13/17 / #20170104004

Methods for cell boundary encroachment and semiconductor devices implementing the same

A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. ... Tela Innovations Inc

04/06/17 / #20170098602

Enforcement of semiconductor structure regularity for localized transistors and interconnect

A global placement grating (gpg) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the gpg is positioned to intersect each contact that interfaces with the chip level. ... Tela Innovations Inc

02/23/17 / #20170053937

Semiconductor chip and method for manufacturing the same

A first conductive structure forms a gate electrode of a first transistor of a first transistor type. A second conductive structure forms gate electrodes of both a second transistor of the first transistor type and a first transistor of a second transistor type. ... Tela Innovations Inc








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