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Toshiba Memory Corporation patents


Recent patent applications related to Toshiba Memory Corporation. Toshiba Memory Corporation is listed as an Agent/Assignee. Note: Toshiba Memory Corporation may have other listings under different names/spellings. We're not affiliated with Toshiba Memory Corporation, we're just tracking patents.

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Wireless communication device, wireless communication method, computer device, and information processing method

. . According to one embodiment, a wireless communication device includes a wireless-communication interface and a wireless-network-information controller. The wireless-communication interface is configured to communicate with one or more terminal using a wireless network. ... Toshiba Memory Corporation

Communication control device, communication control method, and non-transitory computer readable medium

According to one embodiment, a communication control device includes processing circuitry. The processing circuitry acquires at least either; wired communication characteristic information or wireless communication characteristic information from relaying devices or, storage characteristic information indicating usage of a plurality of storage devices storing data units that are transferred via the relaying devices and sent or received by a terminal in the wireless network or, data characteristic information indicating states of a plurality of data units stored in each of the storage devices. ... Toshiba Memory Corporation

Decoding device and decoding method

According to one embodiment, a decoding device that decodes a multi-dimensional error correction code having two or more component codes includes a storage unit that stores therein the multi-dimensional error correction code, an additional-information storage unit that manages each syndrome of the at least two component codes or a reliability flag indicating whether the syndrome has a value of 0 or other than 0, a decoder that performs a first decoding process in a unit of component code with respect to the multi-dimensional error correction code stored in the storage unit to detect an error vector of each component code, and a detection unit that determines whether detection of the error vector by the decoder is false detection, based on the syndrome or the reliability flag stored in the additional-information storage unit.. . ... Toshiba Memory Corporation

Frequency divider circuit

According to one embodiment, a frequency divider circuit includes a 1st flip-flop including a 1st terminal to which a clock signal is input, and including a 2nd terminal to which a 1st signal is input; a 2nd flip-flop including a 1st terminal to which the clock signal is input, and including a 2nd terminal to which a 2nd signal is input, the 2nd signal being output from the 1st flip-flop; a 3rd flip-flop including a 1st terminal to which the clock signal is input, and including a 2nd terminal to which a 3rd signal is input, the 3rd signal being output from the 2nd flip-flop; and an exclusive or gate including a 1st terminal to which the 4th signal is input, and including a 2nd terminal to which a 5th signal is input, the 5th signal being output from the 2nd flip-flop.. . ... Toshiba Memory Corporation

Memory device

A memory device according to an embodiment includes a first conductive layer; a second conductive layer; a first metal oxide layer that is provided between the first conductive layer and the second conductive layer and includes at least one first metal element selected from the group consisting of aluminum (al), gallium (ga), zirconium (zr), and hafnium (hf); and a second metal oxide layer that is provided between the first metal oxide layer and the second conductive layer and includes at least one second metal element selected from the group consisting of zinc (zn), titanium (ti), tin (sn), vanadium (v), niobium (nb), tantalum (ta), and tungsten (w). The first metal oxide layer includes a third metal element. ... Toshiba Memory Corporation

Semiconductor memory device and manufacturing method for same

A semiconductor memory device includes a plurality of first interconnections extending in a first direction, and a second interconnection extending in a second direction different from the first direction. The device further includes a resistance change film provided between the plurality of first interconnections and the second interconnection, the resistance change film including(a) silicon and a semiconductor layer including one or more elements selected from among oxygen, carbon, nitrogen, phosphorus, boron, and germanium, or (b) a first layer containing the germanium and a second layer containing the silicon.. ... Toshiba Memory Corporation

Memory device

A memory device includes a first conductive layer, a second conductive layer, and a variable resistance layer provided between the first and second conductive layers. The variable resistance layer includes a first layer having a semiconductor or a first metal oxide containing a first metal, and a second layer provided between the first layer and the second conductive layer, having a second metal oxide containing a second metal, and having crystal grains that are not in contact with at least one of an end face of the second layer on a side of the first conductive layer or an end face of the second layer on a side of the second conductive layer.. ... Toshiba Memory Corporation

Magnetic memory device and method of manufacturing the same

According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, a first non-magnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the first magnetic layer and having a fixed magnetization direction and provided on the first magnetic layer. The second magnetic layer includes a non-magnetic metal including at least one of mo (molybdenum), ta (tantalum), w (tungsten), hf (hafnium), nb (niobium) and ti (titanium).. ... Toshiba Memory Corporation

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes the following configuration. A resistance change element has first, second and third magnetic layers and a non-magnetic layer disposed between the first and second magnetic layers, and a metal layer disposed between the second and third magnetic layers. ... Toshiba Memory Corporation

Semiconductor device and method of manufacturing the same

According to one embodiment, a semiconductor device includes a semiconductor element having a substrate with at least two bending portions formed on a first side surface thereof. The two bending portions are displaced from each other in a first direction that is perpendicular to the first side surface of the substrate and parallel to a front surface of the substrate and in a second direction parallel to the front surface of the substrate and perpendicular to a top surface of the substrate. ... Toshiba Memory Corporation

Semiconductor device and method for manufacturing same

According to one embodiment, the joint part has a diameter larger than a diameter of the first columnar part and a diameter of the second columnar part. The joint part includes an intermediate semiconductor body continuous with the first semiconductor body and the second semiconductor body. ... Toshiba Memory Corporation

Memory device and rectifier

A memory device according to an embodiment includes a first conductive layer, a second conductive layer, a variable resistance layer disposed between the first conductive layer and the second conductive layer, and an organic molecular layer disposed between the variable resistance layer and the second conductive layer and containing organic molecules. Each of the organic molecules includes a first fused polycyclic unit having a first homo level, a second fused polycyclic unit having a second homo level higher in energy than the first homo level, and a third fused polycyclic unit disposed between the first fused polycyclic unit and the second fused polycyclic unit. ... Toshiba Memory Corporation

Semiconductor device

A semiconductor device includes a semiconductor pillar and a control electrode. The semiconductor pillar extends in a first direction, and includes a first region, a second region and an intermediate region provided along the first direction. ... Toshiba Memory Corporation

Storage device

A storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer. The storage device further includes a first variable resistance layer provided between the first and fifth conductive layers, a second variable resistance layer provided between the second and fifth conductive layers, a third variable resistance layer provided between the third and fifth conductive layers, and a fourth variable resistance layer provided between the first and sixth conductive layers. ... Toshiba Memory Corporation

09/27/18 / #20180277595

Semiconductor storage device

A semiconductor storage device includes first and second wirings that are in a first layer above the substrate, extend along a first direction, and are adjacent to each other along a second direction, third and fourth wirings that are in a second layer above the first layer, extend along the second direction, and are adjacent to each other along the first direction, first and second memory cells on the first wiring, and a third memory cell on the second wiring. The first to third memory cells each include a variable resistance element and a switching element. ... Toshiba Memory Corporation

09/27/18 / #20180277565

Semiconductor memory device

A semiconductor memory device includes wirings arranged in parallel along a first direction, the wirings including first and second wirings that are adjacent and a third wiring adjacent to the second wiring, a first pillar between the first and second wirings and a second pillar between the second and third wirings, the first and second pillars each extending in a second direction crossing the first direction toward the semiconductor substrate, and first and second bit lines connected to the first and second pillars, respectively. A first voltage is applied to the second wiring during a program operation on a first memory cell at an intersection of the second wiring and the first pillar, and a second voltage higher than the first voltage is applied to the second wiring during a program operation on a second memory cell at an intersection of the second wiring and the second pillar.. ... Toshiba Memory Corporation

09/27/18 / #20180277564

Semiconductor memory device and method for manufacturing the same

According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a circuit section, a first insulating layer, and a first columnar part. The stacked body is provided on the substrate and includes a plurality of electrode layers stacked with spacing from each other. ... Toshiba Memory Corporation

09/27/18 / #20180277563

Semiconductor memory device and method for manufacturing the same

According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a first insulating film, and a first film. The stacked body is provided on the substrate. ... Toshiba Memory Corporation

09/27/18 / #20180277562

Semiconductor memory device

A semiconductor memory device includes a substrate, electrode films provided on a first direction side of the substrate and arranged with spacing from each other along the first direction, semiconductor members extending in the first direction, a charge storage member provided between each of the electrode films and each of the semiconductor members, and a control circuit. Memory cells are formed in crossing portions of the electrode films and the semiconductor members. ... Toshiba Memory Corporation

09/27/18 / #20180277561

Semiconductor device and method for manufacturing the same

According to an embodiment, a semiconductor device includes a substrate, a stacked body, a first insulating film, a second insulating film and a plurality of contacts. The stacked body is provided on the substrate and includes a plurality of electrode films stacked with spacing from each other. ... Toshiba Memory Corporation

09/27/18 / #20180277560

Semiconductor memory device and manufacturing method of semiconductor memory device

According to an embodiment, a semiconductor memory device includes a stacked body in which insulating layers and electrode films are alternately stacked, a pillar member arranged in a memory hole that is disposed in the stacked body in a thickness direction, and a semiconductor layer provided below the pillar member. The pillar member has a structure in which a memory film and a channel layer are stacked in order from a side of the stacked body. ... Toshiba Memory Corporation

09/27/18 / #20180277559

Semiconductor memory device and method for manufacturing same

A semiconductor memory device includes a stacked body in which electrode films and insulating films are stacked alternately along a first direction, a semiconductor member extending in the first direction, and a charge storage member provided between the semiconductor member and the electrode film. The electrode film includes a first conductive layer and a second conductive layer. ... Toshiba Memory Corporation

09/27/18 / #20180277555

Semiconductor device and method for manufaturing same

According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided above the foundation layer, a semiconductor body, and a charge storage portion. The stacked body includes a plurality of electrode layers stacked with an air gap interposed, a plurality of select gate layers stacked in a stacking direction of the electrode layers, and an insulating body provided between the select gate layers adjacent to each other in the stacking direction. ... Toshiba Memory Corporation

09/27/18 / #20180277554

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first electrode layer and a second electrode layer formed thereon to be spaced from the first electrode layer, a columnar portion penetrating the first and second electrode layers in a first direction and including a semiconductor layer, a first insulating film between the first and second electrode layers and the semiconductor layer and in contact with the first electrode layer, a charge storage layer between the second electrode layer and the first insulating film, and an insulating film between the second electrode layer and the charge storage layer. The semiconductor layer includes a first portion facing the second electrode layer in a second direction intersecting with the first direction and a second portion in contact with the first portion in the first direction. ... Toshiba Memory Corporation

09/27/18 / #20180277529

Semiconductor package

A semiconductor package includes a substrate having opposing first and second surfaces, first memory chips stacked on the first surface, second memory chips stacked on the first surface, a controller chip for the first and second memory chips, installed on the first surface between the stacked first memory chips and the stacked second memory chips, a sealing portion that seals the first and second memory chips, and the controller chip, and a plurality of solder balls installed on the second surface. The first memory chips are stacked such that a first memory chip located directly above another first memory chip is shifted further toward the controller chip relative to said another first memory chip. ... Toshiba Memory Corporation

09/27/18 / #20180277516

Semiconductor device

A semiconductor device includes a first and a second chips. A first inductor is above a first surface or a second surface located on an opposite side to the first surface. ... Toshiba Memory Corporation

09/27/18 / #20180277515

Semiconductor device and manufacturing method thereof

A device includes a wiring substrate. A first semiconductor-chip has a first face, a second face, and a first side face between an outer edge of the first face and an outer edge of the second face, where the first side face is a first condition plane. ... Toshiba Memory Corporation

09/27/18 / #20180277514

Semiconductor device

A semiconductor device includes a substrate having first and second principal surfaces, and a semiconductor chip disposed on the first principal surface. The substrate includes a first conductor layer disposed on the first principal surface, a second conductor layer disposed on the second principal surface, at least one third conductive layer between the first conductive layer and the second conductive layer, a detection interconnection disposed in either the first conductive layer or the third conductive layer, and first and second pads disposed on the second conductive layer and connected to the detection interconnection. ... Toshiba Memory Corporation

09/27/18 / #20180277499

Semiconductor memory device and method for manufacturing the same

According to an embodiment, a semiconductor memory device includes a substrate, an insulating film, a plurality of conductive films, an insulating member, a plurality of stacked bodies, and a first member. The insulating member is provided on the insulating film, is positioned between the conductive films in a first direction along the substrate, and extends in a second direction along the substrate, the second direction crossing the first direction. ... Toshiba Memory Corporation

09/27/18 / #20180277498

Semiconductor device

A semiconductor device includes a mounting substrate including an interface, which is connectable with a host, and a first ground layer, a surface-mounted component mounted on the mounting substrate, and a plurality of solder balls between the mounting substrate and the surface-mounted component. The surface-mounted component includes a semiconductor chip, a package substrate that is positioned between the semiconductor chip and the solder balls and includes a second ground layer, a sealing portion that covers the semiconductor chip, and has an opening, a first conductive portion on a top surface of the sealing portion, and a second conductive portion on a side surface of the opening and electrically connected to the first conductive portion and the second ground layer. ... Toshiba Memory Corporation

09/27/18 / #20180277497

Semiconductor device and method of manufacturing the same

According to one embodiment, a semiconductor device includes a first semiconductor circuit layer including a first conductive layer, a second semiconductor circuit layer including a second conductive layer, and a third semiconductor circuit layer between the first semiconductor circuit layer and the second semiconductor circuit layer, the third semiconductor circuit layer including a third conductive layer in contact with the first conductive layer, a fourth conductive layer in contact with the second conductive layer, and a fifth conductive layer in contact with the third conductive layer and electrically connected to the fourth conductive layer. The fifth conductive layer has a width that is narrower than a width of the third conductive layer.. ... Toshiba Memory Corporation

09/27/18 / #20180277494

Semiconductor memory device and method for manufacturing the same

According to an embodiment, a semiconductor memory device includes a substrate, a first stacked body, a columnar part, a second insulating film, and a second stacked body. The first stacked body is provided in a first region on the substrate. ... Toshiba Memory Corporation

09/27/18 / #20180277493

Method of manufacturing semiconductor device and semiconductor device

A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.. . ... Toshiba Memory Corporation

09/27/18 / #20180277488

Semiconductor package and semiconductor package manufacturing method

A semiconductor package includes a substrate, a semiconductor element disposed on the substrate, an encapsulating layer covering side surfaces and a top surface of the semiconductor element, an electromagnetic shield layer covering side surfaces of the substrate and side surfaces and a top surface of the encapsulating layer, and a titanium oxide layer formed above a top surface of the electromagnetic shield layer, and including a first portion containing divalent titanium oxide and a second portion containing tetravalent titanium oxide.. . ... Toshiba Memory Corporation

09/27/18 / #20180277484

Semiconductor device

A semiconductor device includes a first chip having a through via, a second chip having a first terminal that is electrically connected to the through via, and a substrate having a second terminal disposed on a first surface thereof and electrically connected to the first terminal. When viewed along a straight line that intersects a center axis that is perpendicular to the first surface and intersects a center point of the substrate, the first terminal is disposed further towards the center axis than the second terminal and the through via is disposed further towards the center axis than the first terminal.. ... Toshiba Memory Corporation

09/27/18 / #20180277477

Storage device

A storage device includes a first wiring layer, a second wiring layer spaced from the first wiring layer in a first direction, and a plurality of electrode layers stacked in the first direction between the first wiring layer and the second wiring layer. A semiconductor pillar penetrates the plurality of electrode layers in the first direction. ... Toshiba Memory Corporation

09/27/18 / #20180277476

Semiconductor memory device and method for manufacturing same

A semiconductor memory device includes a first electrode film, a second electrode film group composed of a plurality of electrode films provided on the first electrode film, a third electrode film group composed of a plurality of electrode films provided on the first electrode film and spaced from the second electrode film group, a semiconductor member extending in a first direction in which the first electrode film and the second electrode film group are arranged, a charge storage member provided between the first electrode film and the semiconductor member, a first conductive film connecting the plurality of electrode films of the second electrode film group to each other and a second conductive film connecting the plurality of electrode films of the third electrode film group to each other.. . ... Toshiba Memory Corporation

09/27/18 / #20180277451

Manufacturing system for semiconductor device, method of manufacturing semiconductor device, and control device

According to an embodiment, a manufacturing system for a semiconductor device includes a first processing device and a second processing device, a measurement section, and an analysis section. The first processing device and the second processing device are adapted to perform a film formation process on a substrate in a wafer. ... Toshiba Memory Corporation

09/27/18 / #20180277436

Method of manufacturing semiconductor device

According to an embodiment, a method of manufacturing a semiconductor device includes forming a first modified zone in a wafer by irradiating the wafer with a laser having transmissivity with respect to the wafer along a part of a dicing line on the wafer, and forming a second modified zone in the wafer by irradiating the wafer with the laser along the dicing line on the wafer. The first modified zone is partially formed between a surface of the wafer and the second modified zone, a semiconductor interconnect layer being formed on the surface of the wafer.. ... Toshiba Memory Corporation

09/27/18 / #20180277435

Dicing method and laser processing apparatus

According to one embodiment, a dicing method is provided. The dicing method includes detecting a first distance between a first portion of a substrate and a first substrate information detection unit. ... Toshiba Memory Corporation

09/27/18 / #20180277407

Substrate processing device and method of manufacturing semiconductor device

A substrate processing device capable of stabilizing an etching amount of a metal film provided on a substrate is provided. The substrate processing device includes a first container, a second container and a control unit. ... Toshiba Memory Corporation

09/27/18 / #20180277406

Substrate treatment apparatus and manufacturing method of semiconductor device

According to an embodiment, a substrate treatment apparatus includes a vacuum chamber, a cylindrical member, a gas feed member, a support member and a plurality of plate members. The cylindrical member is disposed in the vacuum chamber and includes a gas outlet. ... Toshiba Memory Corporation

09/27/18 / #20180277400

Semiconductor manufacturing apparatus

According to an embodiment, a semiconductor manufacturing apparatus includes a process chamber, a load lock chamber, a gas purge mechanism and a movement mechanism. The process chamber treats a substrate using process gas in a vacuum state. ... Toshiba Memory Corporation

09/27/18 / #20180277388

Manufacturing method of semiconductor device and semiconductor manufacturing apparatus

A manufacturing method of a semiconductor device according to an embodiment implants impurities into a central portion of a polishing target film or an outer peripheral portion of the central portion of the polishing target film to cause an impurity concentration in the outer peripheral portion of the polishing target film and an impurity concentration in the central portion thereof to be different from each other, thereby modifying a surface of the polishing target film. The modified surface of the polishing target film is polished by a cmp method.. ... Toshiba Memory Corporation

09/27/18 / #20180277231

Semiconductor storage device

A word-line controller applies a voltage to a selected word-line. A bit-line controller applies voltages to bit-lines. ... Toshiba Memory Corporation

09/27/18 / #20180277230

Memory device and memory system

According to one embodiment, a memory device comprises a first memory cell configured to store data, a first word line connected to the first memory cell, a first circuit configured to supply a voltage to the first word line, a second circuit configured to control the first circuit, and a sequencer configured to control the first circuit and the second circuit. The sequencer, when data is written to the first memory cell, determines whether a condition is satisfied or not. ... Toshiba Memory Corporation

09/27/18 / #20180277229

Memory system and method for controlling memory system

According to one embodiment, a memory system includes a memory device and a controller. The controller is configured to make the memory device apply a first verify voltage to a first word line for determining whether writing of a first data value into a first cell transistor has been completed. ... Toshiba Memory Corporation

09/27/18 / #20180277228

Memory system

According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory is configured to execute a first to third read operations. ... Toshiba Memory Corporation

09/27/18 / #20180277227

Semiconductor memory device and read control method thereof

A semiconductor memory device includes a nonvolatile memory and a controller. The nonvolatile memory has a plurality of memory cells that are connected to word lines to which a read voltage is applied at the time of reading data stored in the memory cells. ... Toshiba Memory Corporation

09/27/18 / #20180277226

Memory system

According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. ... Toshiba Memory Corporation

09/27/18 / #20180277224

Memory device and information processing system

According to one embodiment, a memory device is connected to one or more information processing devices. The memory device includes a shared memory and a memory controller. ... Toshiba Memory Corporation

09/27/18 / #20180277223

Semiconductor memory device

A semiconductor memory device includes a memory cell array, a temperature sensor that generates a first voltage which is based on a temperature of the semiconductor memory device, compares the first voltage with a second voltage that is based on a result of previous temperature measurement, and generates a voltage generation signal based on a result of comparing the first voltage with the second voltage, and a voltage generating circuit that generates a voltage applied to the memory cell array based on the voltage generation signal.. . ... Toshiba Memory Corporation

09/27/18 / #20180277221

Method for controlling memory device

A memory device includes stacked word lines stacked and a semiconductor channel passing through the word lines in a first direction. Memory cells are disposed along the semiconductor channel in the first direction. ... Toshiba Memory Corporation

09/27/18 / #20180277220

Semiconductor memory device

A semiconductor memory device includes memory cell transistors, a word line connected to the plurality of memory cell transistors, bit lines that are respectively connected to the memory cell transistors, and a control circuit. The control circuit carries out a write operation on the memory cell transistors connected to the word line by performing, in sequence, a first loop of operations, including a first program operation followed by at least one verification operation, that are carried out until all memory cell transistors targeted by the first program operation have passed the at least one verification operation, a second loop of operations, including a second program operation and no verification operation, that are carried out for a fixed number of loops and a third loop of operations, including a third program operation and no verification operation, that are carried out for a fixed number of loops.. ... Toshiba Memory Corporation

09/27/18 / #20180277219

Semiconductor memory device

The present embodiment discloses a semiconductor memory device which includes a memory cell array, a signal pad, a first voltage pad, a first regulation circuit and a first operation circuit. The signal pad supplies an output signal associated with the memory cell array. ... Toshiba Memory Corporation

09/27/18 / #20180277218

Semiconductor storage device

A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.. ... Toshiba Memory Corporation

09/27/18 / #20180277217

Semiconductor memory device

A semiconductor memory device includes a plurality of blocks of memory cells, including first, second, and third blocks of a first group of blocks and fourth fifth and sixth blocks of a second group of blocks, a plurality of word lines for each of the blocks, a first decode circuit for the first group, and a second decode circuit for the second group. When the first block is selected, the first decode circuit transfers a first voltage to the word lines of the first block, transfers a second voltage lower than the first voltage to the word lines of the second block, and causes the word lines of the third block to go into an electrically floating state, and the second decode circuit causes the words lines of the fourth block, the fifth block, and the sixth block into the electrically floating state.. ... Toshiba Memory Corporation

09/27/18 / #20180277216

Semiconductor device

According to one embodiment, a semiconductor device includes: a first memory cell provided in a first semiconductor chip; a first output buffer circuit configured to output data of the first memory cell outside, the first output buffer circuit provided in the first semiconductor chip; a first calibration control circuit configured to calibrate an impedance of the first output buffer circuit, a first terminal connected to the first calibration control circuit, the first calibration control circuit provided in the first semiconductor chip; and a first resistance element connected to the first terminal, the first resistance element provided in the first semiconductor chip.. . ... Toshiba Memory Corporation

09/27/18 / #20180277207

Variable resistance memory

A semiconductor device according to an embodiment includes a memory cell array and a drive circuit section. The memory cell array includes memory cells. ... Toshiba Memory Corporation

09/27/18 / #20180277205

Memory device and control method thereof

A memory device includes a control circuit configured to (i) start a first application of a first voltage between a first conductive layer and a third conductive layer, (ii) start a second application of the first voltage between a second conductive layer and the third conductive layer after a lapse of a first delay time since the start of the first application of the first voltage, and (iii) start an application of a second voltage, which is smaller than the first voltage, between the first conductive layer and the third conductive layer after a lapse of a second delay time since the start of the second application of the first voltage between the second conductive layer and the third conductive layer.. . ... Toshiba Memory Corporation

09/27/18 / #20180277204

Memory system

A memory system according to one embodiment includes a memory device including a memory cell with a variable resistance value and a first controller, and a second controller. The first controller is configured to compare first read data read from the memory cell when a first voltage is applied to the memory cell with second read data read from the memory cell when a second voltage is applied to the memory cell. ... Toshiba Memory Corporation

09/27/18 / #20180277203

Storage device and control method thereof

A storage device includes a first conductive layer, a second conductive layer, a first variable resistance layer, and a control circuit. The control circuit is configured to apply a first voltage between the first conductive layer and the second conductive layer for a first time and apply a second voltage less than the first voltage for a second time longer than the first time after the application of the first voltage when the first variable resistance layer is in a first high resistance state. ... Toshiba Memory Corporation

09/27/18 / #20180277202

Semiconductor memory device

A semiconductor memory device includes a first conductor extending in a first direction and a second conductor extending in a second direction and disposed above the first conductor in a third direction. Third and fourth conductors extend in the first direction and adjacent to each other in the second direction. ... Toshiba Memory Corporation

09/27/18 / #20180277201

Semiconductor memory device

A semiconductor memory device includes a first memory cell having a first end connected to a first wiring and a second end connected to a second wiring and a second memory cell having a first end connected to the first wiring and a second end connected to a third wiring. A sense amplifier is configured to: sense a first current flowing in the first wiring when a first voltage is applied to the second and third wirings and a second voltage, larger than the first voltage, is applied to the first wiring; and sense a second current flowing in the first wiring when a third voltage larger than the second voltage is applied to the first wiring, the first voltage to the second wiring, and the second voltage to the third wiring. ... Toshiba Memory Corporation

09/27/18 / #20180277192

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a memory cell including a transistor formed of an oxide semiconductor, an insulation film, and a control electrode, and a capacitance element configured to store a charge, the memory cell being configured to store a coupling weight of a neuron model by a charge amount accumulated in the capacitance element; and a control circuit configured to output a signal as a sum of a product between input data of the memory cell and the coupling weight.. . ... Toshiba Memory Corporation

09/27/18 / #20180277189

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a first memory cell having a first variable resistance element, a second memory cell having a second variable resistance element, and a first circuit which controls writing to the first memory cell and the second memory cell. The first circuit receives a fir command instructing writing to the first memory cell, after receiving the first command, receives a second command instructing writing to the second memory cell, and after receiving the second command, performs writing to the second memory cell when performing writing to the first memory cell.. ... Toshiba Memory Corporation

09/27/18 / #20180277188

Memory device

According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data written and generate a second voltage, generate a first current based on the first voltage, generate a second current based on the second voltage, and add a third current to one of the first current and the second current, thereby determining data stored in the memory cell at the time of the first read.. . ... Toshiba Memory Corporation

09/27/18 / #20180277187

Computer system and memory device

According to one embodiment, a system includes: a device including a memory cell array, the device configured to execute first read operation of a first read method and second read operation of a second read method on the memory cell array; a processor configured to receive a first data from the device, the first data from a selected region in the memory cell array by the first read operation, configured to execute first calculation processing using the first data during the second read operation to the selected region, and configured to acquire a result of the first calculation processing by a first signal based on a comparison result of the first data and a second data, the first signal indicating that the first data is valid, and the second data from the selected region by the second read operation.. . ... Toshiba Memory Corporation

09/27/18 / #20180277186

Memory device

According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data is written and generate a second voltage, and determine data stored in the memory cell at the time of the first read based on the first voltage and the second voltage, wherein when writing the first data, the first circuit electrically sets a generation unit configured to generate the second voltage in a floating state.. . ... Toshiba Memory Corporation

09/27/18 / #20180277183

Memory device

According to one embodiment, a memory includes a first mtj element having a first area along a first plane; and second mtj elements each having a second area along the first plane. The second area is larger than or equal to twice the first area and smaller than or equal to five times the first area. ... Toshiba Memory Corporation

09/27/18 / #20180277182

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a first memory cell including a first resistance change memory element and a first transistor, a first word line electrically coupled to a control terminal of the first transistor, and a first circuit configured to, in a reading, apply a first voltage to the first word line during a first period and apply a second voltage higher than the first voltage to the first word line during a second period after the first period.. . ... Toshiba Memory Corporation

09/27/18 / #20180277180

Memory system

A memory system includes a semiconductor memory and a controller. The controller is configured to perform a read operation on the semiconductor memory in response to a read instruction received from a host. ... Toshiba Memory Corporation

09/27/18 / #20180277177

Memory device and memory system

According to one embodiment, a memory device includes: a memory cell; a read driver configured to supply a read pulse to the memory cell at the time of a read operation for the memory cell; a filter circuit configured to output a second signal in a first frequency domain from a first signal, the first signal being outputted from the memory cell by the read pulse; a hold circuit configured to hold a peak value of the second signal; and a sense amplifier circuit configured to read data from the memory cell based on the peak value.. . ... Toshiba Memory Corporation

09/27/18 / #20180277173

Control system

According to one embodiment, a control system includes: a memory device; and a controller. The memory device includes a first cell transistor. ... Toshiba Memory Corporation

09/27/18 / #20180277171

Semiconductor memory device

A semiconductor memory device includes a power source pad, a first bank including a plurality of memory cells, a second bank including a plurality of memory cells, the first bank being sandwiched between the power source pad and the second bank, first power supply lines connected to the power source pad and supplying power to the first bank and not to the second bank, and second power supply lines connected to the power source pad, passing over the first bank, and supplying power to the second bank and not to the first bank.. . ... Toshiba Memory Corporation

09/27/18 / #20180277170

Semiconductor device and electronic equipment

According to one embodiment, a semiconductor device includes an input/output circuit to which a signal is input or from which a signal is output; a first terminal connected to a power line of the input/output circuit; a second terminal connected to the power line; a resistance element connected between the second terminal and the power line; and a first capacitance element connected between the second terminal and a ground terminal.. . ... Toshiba Memory Corporation

09/27/18 / #20180276806

Method for detecting coordinates, coordinate output device and defect inspection device

A method for detecting coordinates includes detecting a first position in an inspection target placed on a placement surface of an inspection stage and a second position in the inspection target separated from the first position. A coordinate shift from the first position to the second position includes a first shift component in a first direction taken along the placement surface, and a second shift component in a second direction taken along the placement surface and crossing the first direction. ... Toshiba Memory Corporation

09/27/18 / #20180276557

Information processing device, information processing system, and information processing method

According to one embodiment, a quantum annealing machine 1 includes a quantum bit array 21 which includes a plurality of cells (quantum bits) 211 respectively including a floating gate 105, and a controller 10 which executes writing of data in the plurality of cells 211, and temporally controls tunneling of an electric charge with respect to the floating gate 105.. . ... Toshiba Memory Corporation

09/27/18 / #20180276521

Usb device

According to one embodiment, a usb device includes a usb connector, a casing, and a holding member. The casing is provided with an opening. ... Toshiba Memory Corporation

09/27/18 / #20180276135

Memory system and method of controlling nonvolatile memory

According to one embodiment, for each area having a first size, a number of accesses to the area is recorded in first information. In units of sub areas each having a second size smaller than the first size, access information for the sub area is recorded in the second information. ... Toshiba Memory Corporation

09/27/18 / #20180276129

Pre-fetching in a memory system configured with synthesized logical blocks

A memory system includes a memory and a memory controller. The memory includes first and second parallel operation elements, each including a plurality of first and second storage regions, respectively, and first and second buffers, respectively. ... Toshiba Memory Corporation

09/27/18 / #20180276123

Memory system and control method

According to one embodiment, a memory system is connectable to a host. The memory system includes a non-volatile memory and a memory controller. ... Toshiba Memory Corporation

09/27/18 / #20180276118

Memory system and control method of nonvolatile memory

A memory system includes a nonvolatile memory that includes a plurality of blocks and a memory controller with a control circuit. The control circuit executes a first garbage collection for a first stream, which includes reading valid first data stored in a first block associated with the first stream and valid second data stored in a second block associated with the first stream and writing the read first data and the read second data into a third block associated with the first stream, and a second garbage collection for a second stream, which includes reading valid third data stored in a fourth block associated with the second stream and valid fourth data stored in a fifth block associated with the second stream and writing the read third data and the read fourth data into a sixth block associated with the second stream.. ... Toshiba Memory Corporation

09/27/18 / #20180276115

Memory system

A memory system includes a nonvolatile memory having a plurality of blocks, and a memory controller. The memory controller is configured to control the nonvolatile memory, record an association between a first stream id and a first block in which first data corresponding to the first stream id is written, collect information on the first data written into the first block, and invalidate the association between the first stream id and the first block based on the collected information.. ... Toshiba Memory Corporation

09/27/18 / #20180276114

Memory controller

A memory controller controls first and second memory, and includes a control unit. In response to a first write command from a host, which designates a logical address for first data to be written to the first memory, the control unit determines whether mapping of the logical address is presently being managed in a first mode with a first cluster size or a second mode with a second cluster size that is smaller than the first cluster size, changes first mapping data for the logical address stored in a first table in the second memory, from the first cluster size to the second cluster size, if the mapping of the logical address is being managed in the first mode and the first mapping data can be compressed at a ratio lower than a first compression ratio, and writes the first data to a physical address of the first memory.. ... Toshiba Memory Corporation

09/27/18 / #20180276073

Memory system

A memory system includes a nonvolatile memory, a memory controller included in a first package, and a memory interface circuit included in a second package that is different from the first package. The memory controller includes an encoder for performing encoding for error correction. ... Toshiba Memory Corporation

09/27/18 / #20180276072

Memory controller and data reading method

According to one embodiment, a memory controller includes one or more processors configured to function as a writing unit and a reading unit. The writing unit writes data as threshold voltages of individual memory cells. ... Toshiba Memory Corporation

09/27/18 / #20180276071

Memory system and resistance change type memory

According to one embodiment, a memory system includes a resistance change type memory including a memory cell configured to hold first data and an ecc circuit configured to detect and to correct an error in the first data; and a controller configured to control an operation of the resistance change type memory. In a read operation for the memory, when the first data from the memory cell includes an error, the memory transmits second data in which the error is corrected and a first signal to the controller. ... Toshiba Memory Corporation

09/27/18 / #20180276070

Semiconductor storage device

According to an embodiment, a semiconductor storage device includes a detection circuit configured to detect an error in data read from a first memory cell array. The read data of a size corresponding to a page unit is subjected to detection of an error for each of a plurality of first units into which the page unit is divided. ... Toshiba Memory Corporation

09/27/18 / #20180276069

Memory controller, memory system, and control method

A memory controller includes an encoder configured to generate parity from input data, a randomizer circuit configured to generate first and second data portions using a first random number and input data and parity, a program interface configured to write the first and second data portions to a nonvolatile memory, a reading interface configured to read data from the nonvolatile memory, a conversion circuit configured to convert read data into an llr sequence, each llr generated based on a value one bit of the read data and a value of a corresponding bit of a second random number, and a decoder configured to decode the llr sequence to generate output data. User data stored in the nonvolatile memory as part of a codeword is restored from the codeword by reading the codeword from the nonvolatile memory and setting the second random number to be equal to the first random number.. ... Toshiba Memory Corporation

09/27/18 / #20180275921

Storage device

A storage device includes a command storage area in which a command is written, a command issuance notification area in which a notification that a command has been issued is written, a nonvolatile storage device configured to store data, and a controller configured to control an access to the nonvolatile storage device in response to the command from a host. Upon detecting that a first command is written in the command storage area, the controller executes a first step required for execution of the first command before a notification that the first command has been issued is written in the command issuance notification area.. ... Toshiba Memory Corporation

09/27/18 / #20180275918

Semiconductor memory device

A semiconductor memory device includes a memory cell array including a plurality of planes that are independently operable, a plurality of first output terminals through which data read from the memory cell array are output, a second output terminal through which a ready/busy signal indicating a ready/busy state of the memory cell array is output, a control circuit configured to generate a first signal indicating a ready/busy state of each of the plurality of planes, and a signal converter configured to convert the first signal to a second signal indicating a ready/busy state of each of the plurality of planes, the second signal being output through the second output terminal.. . ... Toshiba Memory Corporation

09/27/18 / #20180275917

Memory controller, memory system, and control method

A memory controller includes a memory interface that is connected to a non-volatile memory that includes a plurality of memory cells, and a control unit. The control unit controls the memory interface to perform writing of data that has a first number of bits to a first memory cell in an n-bit write mode (where n is 2 or more), and when performing reading of the data written into the first memory cell, to control the memory interface to perform reading of data in an m-bit read mode (where m is less than n), as a result of which data that has a second number of bits which is smaller than the first number of bits, is returned from the first memory cell.. ... Toshiba Memory Corporation

09/27/18 / #20180275911

Memory system and data relocating method

A memory system includes a nonvolatile semiconductor memory and a memory controller circuit. The memory controller circuit selects first and second blocks of the nonvolatile semiconductor memory, the first block being a garbage collection target block, the second block being a wear leveling target block or a refresh target block, relocates first data which is valid data stored in the first block in a series of write operations to a third block including first and second write operations, the third block being a block of the nonvolatile semiconductor memory having a free region, and relocates second data which is valid data stored in the second block in a series of write operations to a fourth block including a third write operation, the fourth block having a free region and being different from the third block, wherein the third write operation is performed between the first and second write operations.. ... Toshiba Memory Corporation

09/27/18 / #20180275900

Storage apparatus including nonvolatile memory

A storage apparatus includes a first memory, which is nonvolatile, a first controller that controls the first memory, a wireless antenna, a second memory, which is operable based on power supplied from the wireless antenna, and a second controller that is operable based on the power supplied from the wireless antenna, and performs communication using the wireless antenna. When performing communication with an external apparatus using the wireless antenna, the second controller performs authentication of the external apparatus, and stores in the second memory an authentication result indicating whether the authentication succeeded or failed. ... Toshiba Memory Corporation

09/27/18 / #20180275875

Memory system

A memory system which is accessible to a host device includes a volatile memory, a nonvolatile memory, and a memory controller that controls the volatile memory and the nonvolatile memory. The memory controller stores first data, which is stored in the volatile memory, in the nonvolatile memory, each time the memory controller stores second data, which is stored in the volatile memory, in the nonvolatile memory. ... Toshiba Memory Corporation

09/27/18 / #20180275874

Storage system and processing method

A storage system includes a plurality of storage nodes, each including a local processor and one or more non-volatile memory devices, a first control node having a first processor and directly connected to a first storage node, a second control node having a second processor and directly connected to a second storage node. The local processor of a node controls access to the non-volatile memory devices of said node and processes read and write commands issued from the first and second processors that are targeted for said node. ... Toshiba Memory Corporation

09/27/18 / #20180275735

Memory system and control method of memory system

A memory system includes a host interface, a nonvolatile memory, a power supply circuit, a protection circuit, and a first voltage monitor circuit. The power supply circuit is between the host interface and the nonvolatile memory, and supplies primary power to the nonvolatile memory. ... Toshiba Memory Corporation

09/27/18 / #20180275710

Standard voltage circuit and semiconductor integrated circuit

A standard voltage circuit includes an operational amplifier, first and second diodes, a resistance element, and a dummy leak generation circuit. The first diode is electrically connected to a first node of a first line which is disposed on an output terminal side of the operation amplifier and is electrically connected to a first input terminal of the operation amplifier through the first node. ... Toshiba Memory Corporation

09/27/18 / #20180275519

Pattern formation method

A pattern formation method includes forming a first pattern in a first film in a first region and forming a second pattern in the first film in a second region by using an optical lithography technology. The pattern formation method also includes forming a third pattern corresponding to the first pattern in a second film below the first film in the first region by using a self-organization lithography technology. ... Toshiba Memory Corporation

09/27/18 / #20180275510

Imprinting apparatus and imprinting method

An imprinting apparatus includes a substrate holding unit having a first region configured to receive a substrate, and a second region positioned outside a periphery of a first region, the substrate holding unit including a resist removing mechanism including at least one of an exhaust mechanism and an air supply mechanism disposed in the second region. The apparatus further includes a template holding unit configured to hold a template defining recess patterns such that the recess patterns face the substrate holding unit, and such that the template can come into contact with a resist deposited onto the substrate, and one or more nozzles configured to discharge the resist onto the substrate.. ... Toshiba Memory Corporation

09/27/18 / #20180275506

Reflection-type exposure mask

A reflection-type exposure mask includes a light reflector provided in a pattern on a substrate. The light reflector has a multilayer structure including first-type layers and second-type layers that are alternately stacked. ... Toshiba Memory Corporation

09/27/18 / #20180274092

Semiconductor manufacturing apparatus and method of manufacturing semiconductor device

A semiconductor manufacturing apparatus includes a reaction chamber configured to perform a process on a semiconductor substrate using a gas mixture comprising a first gas, and a first path configured to exhaust resultant gas that comprises the first gas from the reaction chamber. The semiconductor manufacturing apparatus further includes a first trap provided in the first path and configured to extract at least a portion of the first gas from the resultant gas, and a second path in which the trap is not provided and configured to exhaust the resultant gas from the reaction chamber.. ... Toshiba Memory Corporation

09/27/18 / #20180272391

Freeze cleaning apparatus

A freeze cleaning apparatus includes a table for supporting a processing target substrate having a first surface and a second surface opposite to the first surface, a liquid supply unit positioned to supply a cleaning liquid onto the second surface of the processing target substrate that is placed such that the first surface faces the table, and a cooling gas discharge unit in the table to supply a cooling gas to the first surface side of the processing target substrate. A gap between the table and the processing target substrate is set such that the cooling gas flows as a laminar flow between the table and the processing target substrate.. ... Toshiba Memory Corporation

09/20/18 / #20180270991

Electronic device

An electronic device includes a top plate having a first surface and a second surface that is positioned at an elevation that is lower than an elevation of the first surface, the second surface extending from a first end part of the top plate to a second end part of the top plate, a bottom plate provided under the top plate, and a circuit board placed between the top plate and the bottom plate and mounted with an electronic component. The top plate has opposing first and second edges and opposing third and fourth edges that are perpendicular to the first and the second edges, the first end part being formed at the first edge and the second end part being formed at the second edge.. ... Toshiba Memory Corporation

09/20/18 / #20180270956

Semiconductor device

A semiconductor device includes a mounting substrate including an interface, which is connectable with a host, a surface-mounted component mounted on the mounting substrate and having first and second electrode groups, a first solder portion that is positioned between a first electrode in the first electrode group and the mounting substrate to electrically connect the first electrode and the mounting substrate, and a second solder portion that is positioned between a second electrode in the second electrode group and the mounting substrate to electrically connect the second electrode and the mounting substrate. The second solder portion has a larger contact area with the mounting substrate than the first solder portion. ... Toshiba Memory Corporation

09/20/18 / #20180270943

Electronic apparatus

An electronic apparatus includes a top plate, a bottom plate provided under the top plate, a circuit board provided between the top plate and the bottom plate, an electronic component disposed on the circuit board, and an intermediate plate provided between the top plate and the circuit board. The intermediate plate is configured to provide a clearance between the top plate and intermediate plate, or between the circuit board and the intermediate plate. ... Toshiba Memory Corporation

09/20/18 / #20180269394

Variable resistance element and memory device

According to one embodiment, a variable resistance element includes first and conductive layers and first and second layers. The first conductive layer includes a first element including at least one selected from the group consisting of silver, copper, aluminum, nickel, and titanium. ... Toshiba Memory Corporation

09/20/18 / #20180269392

Memory device

A memory device includes first interconnects extending in a first direction; a second interconnect extending in a second direction crossing the first interconnects; an insulating film provided between two first interconnects; and a resistance change film between the first interconnects and the second interconnect. The resistance change film includes a first layer and second layers, the first layer extending in the second direction along the second interconnect, and the second layers being provided selectively between the respective first interconnects and the first layer. ... Toshiba Memory Corporation

09/20/18 / #20180269391

Memory device with multiple interconnect lines

According to one embodiment, a memory device includes a first interconnect, a second interconnect, a first layer, a second layer. The first interconnect includes a first region and a second region. ... Toshiba Memory Corporation

09/20/18 / #20180269390

Memory device

A memory device according to an embodiment includes a first conductive layer, a second conductive layer; and a first metal oxide layer provided between the first conductive layer and the second conductive layer. The first metal oxide layer includes titanium oxide, the first metal oxide layer has a first region and a second region, a mole fraction of anatase titanium oxide in the titanium oxide of the first region is a first mole fraction, and a mole fraction of anatase titanium oxide in the titanium oxide of the second region is a second mole fraction lower than the first mole fraction.. ... Toshiba Memory Corporation

09/20/18 / #20180269386

Magnetic memory device

According to one embodiment, a magnetic memory device includes a stacked structure including a first magnetic layer having a variable magnetization direction, a nonmagnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the nonmagnetic layer and having a fixed magnetization direction, wherein as viewed in a direction parallel to a stacked direction of the stacked structure, a pattern of a lower surface of the first magnetic layer is located inside a pattern of an upper surface of the first magnetic layer, and a pattern of an upper surface of the second magnetic layer is located inside a pattern of a lower surface of the second magnetic layer or substantially conforms to the pattern of the lower surface of the second magnetic layer.. . ... Toshiba Memory Corporation

09/20/18 / #20180269382

Magnetoresistive element and magnetic memory

A magnetic memory according to an embodiment includes: a first magnetic layer; a second magnetic layer; a first nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; a third magnetic layer disposed between the first magnetic layer and the first nonmagnetic layer; and a first layer disposed between the first magnetic layer and the third magnetic layer, wherein the first layer contains at least one element selected from the group consisting of co, fe, ni, and mn, and at least one element selected from the group consisting of ta, mo, zr, nb, hf, v, ti, sc, and la.. . ... Toshiba Memory Corporation

09/20/18 / #20180269381

Magnetic memory device

According to one embodiment, a magnetic memory device includes first and second magnetic members, and a conductive member. The first magnetic member includes first, second, and third extending portions. ... Toshiba Memory Corporation

09/20/18 / #20180269277

Semiconductor memory device

A semiconductor memory device according to an embodiment comprises a plurality of control gate electrodes, a first semiconductor layer, and a gate insulating layer. The plurality of control gate electrodes are arranged in a first direction that intersects a surface of a substrate. ... Toshiba Memory Corporation

09/20/18 / #20180269257

Semiconductor memory device

This semiconductor memory device includes: global first wiring lines; global second wiring lines; and memory blocks connected to the global first wiring lines and the global second wiring lines. The memory block includes: local first wiring lines; local second wiring lines; and memory cells connected to the local first wiring lines and the local second wiring lines. ... Toshiba Memory Corporation

09/20/18 / #20180269256

Storage device and production method thereof

According to one embodiment, a storage device includes a first wiring extending in a first direction, a second wiring connected to the first wiring and extending in a second direction, which crosses the first direction, a third wiring extending in a third direction, which crosses the second direction, and a first variable resistance film connected to the second wiring and the third wiring. The third wiring includes a first portion that extends in the third direction and a second portion that protrudes from a side surface of the first portion toward the second wiring and that has an end surface connected to the first variable resistance film.. ... Toshiba Memory Corporation

09/20/18 / #20180269255

Magnetic memory device

According to one embodiment, a magnetic memory device includes a memory cell array unit including magnetoresistive elements provided in an array in first and second directions, each including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer between the first and second magnetic layers, first transistors provided in an array in the first and second directions, and electrically connected to the magnetoresistive elements, respectively, switching units each electrically connected to corresponding ones of the first transistors in series, and each including at least one second transistor, wherein the first magnetic layers are separated from each other in the first and second directions, and the second magnetic layers are continuously provided in the first and second directions.. . ... Toshiba Memory Corporation

09/20/18 / #20180269228

Semiconductor memory device

According to an embodiment, a semiconductor memory device comprises control gate electrodes and a semiconductor layer. The control gate electrodes are stacked above a substrate. ... Toshiba Memory Corporation

09/20/18 / #20180269226

Semiconductor memory device and method for manufacturing same

A semiconductor memory device includes a substrate, a first stacked body provided in a first region on the substrate, a transistor formed in a second region of the substrate, and a block member provided between the first stacked body and the transistor. The first stacked body includes a plurality of first silicon oxide films and a plurality of electrode films stacked alternately one by one. ... Toshiba Memory Corporation

09/20/18 / #20180269224

Memory device

According to one embodiment, a memory device includes a plurality of first electrode layers stacked over each other in a stacking direction, a pair of second electrode layers located over the plurality of first electrode layers in the stacking direction, a channel layer extending through the first and second electrode layers, and a charge storage layer between each first electrode layer and the channel layer. A thickness in the stacking direction of at least one of the second electrode layers being greater than a thickness in the stacking direction of any of the first electrode layers.. ... Toshiba Memory Corporation

09/20/18 / #20180269223

Manufacturing method of semiconductor memory device

A manufacturing method of a semiconductor memory device includes disposing a first stacked body on a substrate, forming a first through via hole in the first stacked body, and determining to remove an upper portion of the first stacked body based on a comparison of a determined value of a width of the first through via hole with a reference value. The method further includes forming a second film in the first through via hole responsive to the determination to remove the upper portion of the first stacked body, removing the upper portion of the first stacked body and a portion of the second film, and disposing a second stacked body on the first stacked body and the second film. ... Toshiba Memory Corporation

09/20/18 / #20180269221

Semiconductor device

According to an embodiment, a semiconductor device includes a substrate, a stacked body, and a second insulating film. A first insulating film and an electrode film are alternately stacked in the stacked body so as to extend in a first direction along an upper surface of the substrate. ... Toshiba Memory Corporation

09/20/18 / #20180269219

Semiconductor memory device

According to an embodiment, a semiconductor memory device includes a substrate, a circuit portion, a stacked body, at least one columnar member, a device isolation portion, and at least one first support member. The columnar member is in contact with an interconnect layer, and includes a contact extending in a stacking direction of a plurality of electrode films in the stacked body. ... Toshiba Memory Corporation

09/20/18 / #20180269218

Semiconductor memory device

A semiconductor memory device includes a semiconductor member extending in a first direction, a first interconnect extending in a second direction crossing the first direction, and a first electrode disposed between the semiconductor member and the first interconnect. A curvature radius of a corner portion facing the semiconductor member in the first electrode is larger than a curvature radius of a corner portion facing the first interconnect in the first electrode.. ... Toshiba Memory Corporation

09/20/18 / #20180269217

Transistor, memory, and manufacturing method of transistor

According to one embodiment, a transistor includes: a gate electrode; a gate insulating layer provided on the gate electrode; an oxide semiconductor layer provided on the gate insulating layer; an oxygen supply layer provided on the oxide semiconductor layer; a first oxygen barrier layer provided on the oxygen supply layer; a source electrode provided to penetrate the oxygen supply layer and the first oxygen barrier layer and connected to the oxide semiconductor layer; and a drain electrode spaced apart from the source electrode, provided to penetrate the oxygen supply layer and the first oxygen barrier layer, and connected to the oxide semiconductor layer.. . ... Toshiba Memory Corporation

09/20/18 / #20180269210

Semiconductor memory

According to one embodiment, a memory includes: a bit line; a source line; a pillar extending in a first direction and including an oxide semiconductor layer; first, second and third layers arranged along the first direction and opposed to a side of the pillar; a memory cell at an intersection between the first layer and the pillar, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor at an intersection between the second layer and the pillar; and a second transistor at an intersection between the third layer and the pillar. A first end of the oxide semiconductor layer in the first direction is in contact with the source line, and a second end of the oxide semiconductor layer in the first direction is electrically disconnected from the bit line.. ... Toshiba Memory Corporation

09/20/18 / #20180269203

Storage device and capacitor

A capacitor includes a plurality of first electrode layers stacked in a first direction, a first conductor extending in the first direction through the plurality of first electrode layers, and a first insulating layer extending in the first direction along the first conductor and located between the first conductor and the plurality of first electrode layers. The capacitor includes a first capacitance provided between the first conductor and the plurality of first electrode layers.. ... Toshiba Memory Corporation

09/20/18 / #20180269196

Semiconductor device and manufacturing method thereof

According to an embodiment, a semiconductor device includes: a stacked body in which insulator layers and conductor layers alternately stacked; a block insulator film on a surface of the insulator layer and a surface of the conductor layer; a charge storage capacitor film on a surface of the block insulator film; a tunnel insulator film including a first insulator film on a surface of the charge storage capacitor film, a second insulator film on a surface of the first insulator film, and a third insulator film on a surface of the second insulator film; and a channel film on a surface of the third insulator film. A defect termination element is included in at least the first or the third insulator film, and defect termination element content concentrations of the first, the second, and the third insulator film are different from one another.. ... Toshiba Memory Corporation

09/20/18 / #20180269133

Semiconductor device and manufacturing method thereof

A semiconductor device according to an embodiment includes a semiconductor substrate including a first face having semiconductor elements, and a second face on an opposite side to the first face. A first insulating film is located on the first face of the semiconductor substrate. ... Toshiba Memory Corporation

09/20/18 / #20180269116

Measurement method, measurement program, and measurement system

According to one embodiment, there is provided a measurement method. The method includes acquiring layer information related to a plurality of layers to be superimposed for each of a plurality of shot regions on a substrate. ... Toshiba Memory Corporation

09/20/18 / #20180269082

Substrate treatment apparatus and manufacturing method of semiconductor device

According to an embodiment, a substrate treatment apparatus includes a hair member including a noble metal, and a liquid chemical supply member to supply a liquid chemical. While a tip part of the hair member is contact with a predetermined surface of a metal, the liquid chemical is supplied onto the surface of the metal, and the metal is removed with etching.. ... Toshiba Memory Corporation

09/20/18 / #20180269043

Magnetron sputtering apparatus and film formation method using magnetron sputtering apparatus

According to one embodiment, a film formation method using a magnetron sputtering apparatus including first and second magnets provided on first and second target holders, includes forming an insulating film on a wafer placed on a main surface of a wafer stage by sputtering first and second insulating targets set on the first and second target holders, wherein the wafer includes an effective area to be used for a product and an ineffective area outside the effective area, and when viewed from a direction perpendicular to the main surface of the wafer stage, at least a part of the first magnet overlaps the effective area of the wafer placed on the main surface of the wafer stage, and the entire second magnet does not overlap the effective area of the wafer placed on the main surface of the wafer stage.. . ... Toshiba Memory Corporation

09/20/18 / #20180268920

Screening method for magnetic storage device, screening apparatus for magnetic storage device, and manufacturing method of magnetic storage device

According to one embodiment, a screening method includes performing a first screening operation on a memory device at a first temperature to detect a defect in magnetoresistive effect elements of the memory device, replacing a first magnetoresistive effect element that is determined as defective in the first screening operation by substituting a second magnetoresistive effect element disposed in a redundancy area of the memory device for the first magnetoresistive, and performing a second screening operation on the memory device at a second temperature higher than the first temperature if the first screening operation detects a defect. Each of the first screening operation and the second screening operation includes writing data into the magnetoresistive effect element, reading data from the magnetoresistive effect element after the writing, and determining a magnetoresistive effect element is defective when the data as written does not match the data as read.. ... Toshiba Memory Corporation

09/20/18 / #20180268910

Memory system

According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. ... Toshiba Memory Corporation

09/20/18 / #20180268908

Memory system

According to one embodiment, a memory system includes a storage medium including a first cell transistor, a first data latch, and a second data latch; and a first controller. The first controller is configured to instruct to the storage medium to, after instructing the storage medium to write data into the first cell transistor and before completion of the writing of the data into the first cell transistor, suspend a process being performed to the first cell transistor, read data from the first data latch, read data from the second data latch, and read data from the first cell transistor.. ... Toshiba Memory Corporation

09/20/18 / #20180268906

Memory device and memory controller

According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. ... Toshiba Memory Corporation

09/20/18 / #20180268904

Nonvolatile semiconductor memory device with a plurality of memory blocks and a shared block decoder

A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. ... Toshiba Memory Corporation

09/20/18 / #20180268902

Storage device

A storage device includes a circuit on a substrate, electrode layers stacked on the circuit, a channel layer penetrating the electrode layers in a stacking direction, a plate-shaped first wire between the electrode layers and the circuit and electrically connected to the channel layer, a second wire at a level between the circuit and the first wire, a third wire between the circuit and the second wire, a contact plug penetrating the electrode layers and the first wire in the stacking direction and electrically connected to the second wire, and a columnar support body penetrating the electrode layers and the first wire in the stacking direction. The columnar support body has a lower end in contact with the second wire or the third wire. ... Toshiba Memory Corporation

09/20/18 / #20180268898

Non-volatile semiconductor memory device

A non-volatile semiconductor memory device includes a current source providing a reference current to a first node and a clamp circuit. The clamp circuit includes a transistor having a current path between the first node and a second node, and an amplifier circuit having a first input port at which a cell reference voltage can be received, a second input port connected to the second node, and an output port connected to a control terminal of the transistor. ... Toshiba Memory Corporation

09/20/18 / #20180268897

Semiconductor memory device

A semiconductor memory device includes a resistive-type memory cell and a sense amplifier for reading data from the memory cell. First and second transistors connected in parallel between a first node connected to the memory cell and a second node connected to the sense amplifier. ... Toshiba Memory Corporation

09/20/18 / #20180268893

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a first memory cell including a first transistor and a first capacitor, a second memory cell including a second transistor and a second capacitor, a first word line electrically coupled to the first transistor, a second word line electrically coupled to the second transistor, and a first circuit which supplies a first voltage to the first word line, and a second voltage different from the first voltage to the second word line, during a sleep mode.. . ... Toshiba Memory Corporation

09/20/18 / #20180268891

Semiconductor memory device and memory system

A semiconductor memory device includes a memory cell transistor, a word line coupled to the memory cell transistor, a temperature detection element configured to detect a temperature, and a control unit. The control unit is configured to determine, responsive to receiving a first command from a controller, a compensation value for a read voltage designated by the controller according to the detected temperature, and to lock updating of the compensation value.. ... Toshiba Memory Corporation

09/20/18 / #20180268887

Magnetoresistive element and magnetic memory

A magnetoresistive element according to an embodiment includes: a first nonmagnetic layer; a first magnetic layer; a second magnetic layer disposed between the first nonmagnetic layer and the first magnetic layer; a second nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; a third nonmagnetic layer disposed between the second nonmagnetic layer and the second magnetic layer; and a third magnetic layer disposed between the second nonmagnetic layer and the third nonmagnetic layer, wherein elements constituting the second magnetic layer at least partially differ from elements constituting the third magnetic layer, a relative permittivity of the first nonmagnetic layer is at least 10, and the third nonmagnetic layer contains at least one element selected from the group consisting of nb, ta, mo, w, hf, zr, ti, sc, v, cr, mn, fe, co, ni, mg, al, ru, ir, rh, pd, pt, cu, ag, and au.. . ... Toshiba Memory Corporation

09/20/18 / #20180268881

Semiconductor storage device and method of controlling the same

In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.. ... Toshiba Memory Corporation

09/20/18 / #20180268878

Non-volatile semiconductor memory device

A variable resistance non-volatile semiconductor memory device comprises a memory cell having variable resistance element connected in series with a selection transistor. The selection transistor has a control terminal connected to a word line. ... Toshiba Memory Corporation

09/20/18 / #20180268877

Semiconductor storage device

According to one embodiment, a semiconductor storage device includes: a memory cell array including a plurality of bit lines; a sense amplifier; a first circuit including a plurality of transistors respectively connected to the plurality of bit lines and the sense amplifier; and a plurality of interconnects which are provided at a position higher than the bit lines in the first circuit and are not directly connected to the first circuit. The semiconductor storage device does not include, at a position higher than the plurality of interconnects, an interconnect which electrically connects two positions in the semiconductor storage device.. ... Toshiba Memory Corporation

09/20/18 / #20180268692

Moving object and driving support system for moving object

A driving support system includes a first monitoring device on a first object, the first monitoring device having a first controller, a first camera, and a first display, a second monitoring device on a second object, the second monitoring device having a second controller and a second camera, and a server in communication with the first and second monitoring devices. The first and second controllers are each detect a target in images acquired from the respective first or second camera, calculate target information for the target, and transmit the target information to the server. ... Toshiba Memory Corporation

09/20/18 / #20180267906

Shared memory controller, shared memory module, and memory sharing system

According to an embodiment, upon receiving a use request including an identifier of a program and authentication information, a use request processing unit makes a determination on validity of the use request based on an id management information and access authority management information, generates an access key when the use request is valid, registers the access key in access key management information in correlation with a usable address range, and returns the access key to a transmission source of the use request. Upon receiving a read/write request including an address where reading-out or writing of data is performed and an access key, a read/write request processing unit makes a determination on validity of the read/write request based on the access key management information, and executes reading-out or writing of data with respect to a shared memory in response to the read/write request when the read/write request is valid.. ... Toshiba Memory Corporation

09/20/18 / #20180267853

Memory system

A memory system has a non-volatile memory, an error corrector, an error information storage, and an access controller. The non-volatile memory comprising a plurality of memory cells. ... Toshiba Memory Corporation








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