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Toshiba Memory Corporation patents


Recent patent applications related to Toshiba Memory Corporation. Toshiba Memory Corporation is listed as an Agent/Assignee. Note: Toshiba Memory Corporation may have other listings under different names/spellings. We're not affiliated with Toshiba Memory Corporation, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Toshiba Memory Corporation-related inventors


Authenticator, authenticatee and authentication method

According to one embodiment, an authenticator which authenticates an authenticatee, which stores first key information (nkey) that is hidden, includes a memory configured to store second key information (hkey) which is hidden, a random number generation module configured to generate random number information, and a data generation module configured to generate a session key (skey) by using the second key information (hkey) and the random number information. The authenticator is configured such that the second key information (hkey) is generated from the first key information (nkey) but the first key information (nkey) is not generated from the second key information (hkey).. ... Toshiba Memory Corporation

Semiconductor memory device and method for manufacturing same

A semiconductor memory device according to an embodiment includes a stacked body in which an electrode film and an insulating film are alternately stacked along a first direction, a semiconductor member extending in the first direction and piercing the stacked body, and a charge storage member provided between the semiconductor member and the electrode film. The electrode film includes a first portion. ... Toshiba Memory Corporation

Semiconductor device and method for manufacturing the same

A semiconductor device includes a metal column that extends in a stretching direction; a polymer layer that surrounds the metal column from a direction crossing the stretching direction; and a guide that surrounds the polymer layer in the crossing direction so as to be spaced from the metal column with the polymer layer interposed therebetween. A method for manufacturing semiconductor devices includes a step of filling a mixture containing metal particles and polymers in a guide; and a step of subjecting the mixture to a heat treatment so that the polymers agglomerate to the guide to form a polymer layer that makes contact with the guide and the metal particles agglomerate away from the guide with the polymer layer interposed therebetween to form a metal column that stretches in a stretching direction of the guide from the metal particles.. ... Toshiba Memory Corporation

Semiconductor device and manufacturing method thereof

A semiconductor device according to the present embodiment includes a stacked body having an end which is step-shaped and a contact in each of the steps of the end. Each of the steps includes alternating a plurality of conductive layers and a plurality of insulating layers. ... Toshiba Memory Corporation

Semiconductor manufacturing apparatus and manufacturing method of semiconductor device

A semiconductor manufacturing apparatus according to the present embodiment has a mount unit capable of mounting a substrate. A first supplier supplies a chemical solution onto the substrate. ... Toshiba Memory Corporation

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. ... Toshiba Memory Corporation

Information processing device, non-transitory computer readable recording medium, and information processing system

According to one embodiment, an information processing device includes a nonvolatile memory, assignment unit, and transmission unit. The assignment unit assigns logical address spaces to spaces. ... Toshiba Memory Corporation

Nand raid controller

An array controller for connection between a solid state drive controller and multiple non-volatile storage units is provided. The array controller comprises a plurality of enable outputs, each of which is connected to an enable input of one of the non-volatile storage units, and a buffer in which data to be written into or read from the non-volatile storage units is stored. ... Toshiba Memory Corporation

Template, imprint device, and manufacturing method of semiconductor device

According to an embodiment, a template includes steps in first to nth (n is an integer of 2 or greater) stairs formed in a staircase pattern in a height direction. The steps include first steps in the first to kth (k is an integer of 1 or greater and n−1 or less) stairs and second steps in (k+1)th to mth (m is an integer of k+1 or greater and n or less) stairs. ... Toshiba Memory Corporation

Semiconductor device and manufacturing method thereof

A semiconductor device according to present embodiment has first wirings provided in a first area and made of a first metal. A first gap is provided between the first wirings adjacent to each other. ... Toshiba Memory Corporation

Pattern formation method, imprint device, and computer-readable non-volatile storage medium storing drop recipe adjustment program

According to one embodiment, a pattern formation method includes correcting, based on a relationship between a residual film thickness of an imprint pattern and a dimension of an etching pattern that is formed using an imprint pattern as a mask, the residual film thickness of the imprint pattern; and using the imprint pattern with the corrected residual film thickness as a mask to form an etching pattern with the corrected dimension.. . ... Toshiba Memory Corporation

Semiconductor memory device

A semiconductor memory device according to an embodiment includes a first memory cell transistor and a second memory cell transistor, a select transistor, a bit line, a first word line and a second word line, a select gate line, and a controller. During the program operation in the write operation with the first word line selected, the controller applies a first voltage to the select gate line and a second voltage lower than the first voltage to the first word line before applying the program pulse to the first word line, and applies a third voltage lower than the first voltage and higher than the second voltage to the select gate line while applying the program pulse to the first word line.. ... Toshiba Memory Corporation

Memory system

According to one embodiment, a memory system includes a memory, and a processor. The memory converts an amount of charge held by a memory cell into a value. ... Toshiba Memory Corporation

Performance based method and system for patrolling read disturb errors in a memory unit

Disclosed herein is a method and a system for handling read disturb errors in a memory unit. Status information related to each memory block in the memory unit is retrieved and plurality of target memory blocks with valid pages and having highest block erase count are identified for patrolling. ... Toshiba Memory Corporation

08/02/18 / #20180217753

Memory system and control method

According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile memory and a controller circuitry. ... Toshiba Memory Corporation

08/02/18 / #20180217493

Imprint apparatus and manufacturing method of semiconductor

A plurality of light sources are provided and are able to be independently turned on and turned off. The light sources have directionality in directions of shot regions. ... Toshiba Memory Corporation

07/26/18 / #20180211971

Non-volatile memory device

According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. ... Toshiba Memory Corporation

07/26/18 / #20180211967

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. ... Toshiba Memory Corporation

07/26/18 / #20180211712

Semiconductor memory device

A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. ... Toshiba Memory Corporation

07/26/18 / #20180211708

Memory system and control method

A memory system includes a non-volatile memory having a plurality of memory cells, and a controller configured to carry out write operations in a first mode in which n-bit data is written per target memory cell of the non-volatile memory until an allowable data amount of data items has been written, and then, in a second mode in which m-bit data is written per target memory cell of the non-volatile memory, where n is an integer of one or more and m is an integer greater than n. The controller is further configured to detect that an idle state, in which a command has not been received from the host, has continued for a threshold period of time or more, increase the allowable data amount in response thereto, and after the increase, carry out a write operation to write data items in the non-volatile memory in the first mode.. ... Toshiba Memory Corporation

07/26/18 / #20180211707

Semiconductor memory device and method of controlling semiconductor memory device

A semiconductor memory device includes a nonvolatile semiconductor memory including a plurality of memory cells and a plurality of word lines each connected to a page unit of memory cells, and a memory controller that controls reading of data from the memory cells. The nonvolatile semiconductor memory performs either a first read operation in which all data from the page unit of memory cells connected to a selected word line among the plurality of word lines is read, or a second read operation in which a portion of the data from the page unit of memory cells connected to a selected word line among the plurality of word lines is read, and the memory controller is configured to cause the nonvolatile semiconductor memory to perform the second read operation when data at a target physical address of a read request can be read in a single second read operation.. ... Toshiba Memory Corporation

07/26/18 / #20180211706

Discharge circuit and semiconductor memory device

A discharge circuit includes first and second transistors of a first polarity, third and fourth transistors of a second polarity, and first and second current sources having first ends electrically connected to first end of the third transistor and first end of the fourth transistor, respectively, and second ends supplied with a first voltage. First end of the first transistor is supplied with a second voltage higher than the first voltage. ... Toshiba Memory Corporation

07/26/18 / #20180211700

Semiconductor memory device

A semiconductor memory device includes a memory cell transistor, a bit line, a sense amplifier circuit, a voltage generation circuit, and a control unit. The bit line is electrically connected to a terminal of the memory cell transistor. ... Toshiba Memory Corporation

07/26/18 / #20180210970

Memory system including key-value store

According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes an interface, a memory block, an address acquisition circuit and a controller. The interface receives a data write/read request or a request based on the key-value store. ... Toshiba Memory Corporation

07/26/18 / #20180210831

Memory system and method of controlling cache memory

According to one embodiment, a memory system includes first and second memories, and a controller configured to switch between first and second modes, search whether data of a logical address associated with a read command is stored in the first memory in the first mode, and read the data from the second memory without searching whether the data of the logical address associated with the read command is stored in the first memory in the second mode.. . ... Toshiba Memory Corporation

07/26/18 / #20180210654

Semiconductor memory device that randomizes data and randomizer thereof

A semiconductor memory device includes a nand memory including a plurality of blocks, each of which is a unit of data erasing, and a controller. The controller is configured to select an initial value from a group of initial values, based on an address of the nand memory in which data are to be written, set a value corresponding to the selected initial value to a linear feedback shift register circuit, randomize the data using an output value of the linear feedback shift register circuit, and write the randomized data to the address of the nand memory. ... Toshiba Memory Corporation

07/19/18 / #20180205397

Memory system

According to one embodiment, a memory system includes a first volatile memory, a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of chips. ... Toshiba Memory Corporation

07/19/18 / #20180205016

Semiconductor memory device and method for manufacturing same

According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region. ... Toshiba Memory Corporation

07/19/18 / #20180205006

Magnetoresistive memory device

A magnetoresistive memory device includes a first magnetic layer having a variable magnetization direction; a second magnetic layer, a magnetization direction of the second magnetic layer being invariable; a first nonmagnetic layer provided between the first magnetic layer and the second magnetic layer; and a second nonmagnetic layer provided on the first magnetic layer, which is opposite the first nonmagnetic layer. The first magnetic layer having a stacked layer structure in which amorphous magnetic material layer is sandwiched between crystalline magnetic material layers.. ... Toshiba Memory Corporation

07/19/18 / #20180204625

Semiconductor memory device

A semiconductor memory device includes first and second memory cell transistors between first and second select transistors, third and fourth memory cell transistors between third and fourth select transistors, a first word line for first and third memory cell transistors, a second word line for second and fourth memory cell transistors, first to fourth selection gate lines respectively for first through fourth select transistors, a bit line, and a source line. During a read operation, while a voltage applied to the second word line is boosted, voltages applied to the first word line and the third and fourth selection gate line are also boosted, after which the voltage applied to the first word line is lowered, and the third and fourth selection gate lines are discharged. ... Toshiba Memory Corporation

07/19/18 / #20180204623

Non-volatile semiconductor storage device

According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. ... Toshiba Memory Corporation

07/19/18 / #20180204622

Non-volatile semiconductor memory device and memory system

A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. ... Toshiba Memory Corporation

07/19/18 / #20180204619

Semiconductor memory device

A semiconductor memory device according to an embodiment includes: first to 32nd memory cells; first to 16th bit lines connected to the first to 16th memory cells; 17th to 32nd bit lines connected to the 17th to 32nd memory cells; a first word line connected to gates of the first to 32nd memory cells; first to 16th sense amplifiers configured to determine data read from the first to 16th memory cells at a first timing; and 17th to 32nd sense amplifiers configured to determine data read from the 17th to 32nd memory cells at a second timing. The first timing is different from the second timing.. ... Toshiba Memory Corporation

07/19/18 / #20180204615

Memory device

A memory device includes a sense amplifier including a first input node and a second input node and configured to output a signal based on a difference between input values at the first input node and the second input node; a first path including a memory cell to be selectively connected to the first input node and provided between the first input node and a ground node; and a second path including a reference cell to be selectively connected to the second input node and provided between the second input node and the ground node. The input value at the second input node of the sense amplifier is changed such that a change amount of the input value between two different temperatures t2 and (t2+Δt) in a second temperature region, at a temperature higher than in a first temperature region, of the memory cell becomes larger than the change amount of the input value between two different temperatures t1 and (t1+Δt) in the first temperature region of the memory cell, where Δt is an increase amount of the temperature.. ... Toshiba Memory Corporation

07/19/18 / #20180203772

Electronic equipment including storage device

According to one embodiment, a storage device includes a nonvolatile memory, controller and interface. The nonvolatile memory stores data. ... Toshiba Memory Corporation

07/19/18 / #20180203615

Storage control device, storage control method, and computer readable recording medium

According to one embodiment, a storage control device has, as a unit of storage, a stripe including one or more chunks being storage areas included in any of a plurality of storages. The storage control device includes a first selector, a divider, and a determiner. ... Toshiba Memory Corporation

07/12/18 / #20180198060

Electronic device

An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer which is in contact with the free layer and includes a rare earth metal nitride.. . ... Toshiba Memory Corporation

07/12/18 / #20180197962

Semiconductor device

A semiconductor device includes at least one memory cell including a first conductivity type first semiconductor region, a second conductivity type second semiconductor region, which is a source region of the memory cell, over a portion of the first semiconductor region, and a second conductivity type third semiconductor region, which is a drain region of the memory cell, over a portion of the first semiconductor region spaced from the second semiconductor region in a first direction, a gate insulating layer extending over a channel region of the memory cell, which includes a portion of the first semiconductor region between the second and third semiconductor regions, and including a first portion of first thickness and a second portion of second thickness less than the first thickness, an electrically floating gate electrode on the gate insulating layer, and a control gate adjacent to, and spaced from, the electrically floating gate electrode.. . ... Toshiba Memory Corporation

07/12/18 / #20180197878

Nonvolatile semiconductor memory device and method for manufacturing same

A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.. . ... Toshiba Memory Corporation

07/12/18 / #20180197874

Semiconductor device and method for manufacturing same

The semiconductor device includes a base material, a plurality of electrode layers, and a first contact portion. The plurality of electrode layers are provided above the base material and arranged along a first direction. ... Toshiba Memory Corporation

07/12/18 / #20180197616

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. ... Toshiba Memory Corporation

07/12/18 / #20180197614

Nonvolatile semiconductor memory device

When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. ... Toshiba Memory Corporation

07/12/18 / #20180197612

Three dimensional stacked nonvolatile semiconductor memory

A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. ... Toshiba Memory Corporation

07/12/18 / #20180197611

Semiconductor memory device

A semiconductor memory device includes first and second memory cells, first and second select transistors having first ends connected to the first and second memory cells, respectively, first and second bit lines connected to second ends of the first and second select transistors, respectively, and a select gate line connected to the first and second select transistors. A write operation includes first and second program loops. ... Toshiba Memory Corporation

07/12/18 / #20180197592

Resistance change type memory

According to one embodiment, a memory includes a bit line connected to a memory cell; and a read circuit to execute reading of data from the memory cell. The read circuit includes a first circuit having a first input terminal and detecting an output signal from the memory cell; a first transistor to control a current supplied to the memory cell based on a first control signal; and a second transistor. ... Toshiba Memory Corporation

07/12/18 / #20180196768

Semiconductor memory device with data buffering

A semiconductor storage device includes at least two nonvolatile semiconductor memories, a buffer in which data received from a host and to be written to the nonvolatile semiconductor memories in response to a write command received from the host can be temporarily stored, and a controller connected to the nonvolatile semiconductor memories and configured to transfer data stored in the buffer to a number n of the nonvolatile semiconductor memories in parallel. The number n is set according to a reception of data from the host, and n is greater than or equal to 1 and less than or equal to m, which is the number of nonvolatile semiconductor memories connected to the controller.. ... Toshiba Memory Corporation

07/12/18 / #20180196744

Memory system and method for controlling nonvolatile memory

According to one embodiment, a memory system includes a nonvolatile memory including a plurality of blocks and a controller. The controller manages a garbage collection count for each of blocks containing data written by a host, the garbage collection count indicating the number of times the data in said each of the blocks has been copied by a garbage collection operation of the nonvolatile memory. ... Toshiba Memory Corporation

07/12/18 / #20180196711

Memory device

According to one embodiment, a semiconductor memory device includes: a memory configured to store data; an error correcting circuit configured to correct an error in data read from the memory, and to generate a first signal of a first state, which is transmitted to an external along with the data if the error in the data cannot be corrected; and a first pin configured to transmit the first signal to the external and receive a data mask signal from the external.. . ... Toshiba Memory Corporation

07/12/18 / #20180196617

Information processing apparatus, information processing method, and computer program product

According to an embodiment, an information processing apparatus includes a non-volatile memory manager. The non-volatile memory manager is configured to save, in a non-volatile memory section, information of a plurality of storage sections to be read after rebooting. ... Toshiba Memory Corporation

07/05/18 / #20180190669

Semiconductor device and method for manufacturing the same

A method for manufacturing a semiconductor device includes forming a first semiconductor layer, forming a stacked body including alternately formed first and second layers on the first semiconductor layer, forming a hole from an upper surface of the stacked body to the first semiconductor layer to expose the first semiconductor layer therein. A first insulating layer is formed on the inner wall of the hole, and a second semiconductor layer is formed on the first insulating layer within the hole, wherein the second semiconductor layer is electrically connected to the first semiconductor layer. ... Toshiba Memory Corporation

07/05/18 / #20180190359

Semiconductor memory device capable of reducing chip size

According to one embodiment, a first well of the first conductivity type which is formed in a substrate. A second well of a second conductivity type which is formed in the first well. ... Toshiba Memory Corporation

07/05/18 / #20180190348

Semiconductor storage device and memory system

According to an embodiment, a control circuitry performing: a first operation of reading data out of a memory cell with a first voltage applied to a word line while changing the first voltage by a first shift amount within a first range, and a second operation of reading data out of the memory cell with a second voltage applied to the word line while changing the second voltage by a second shift amount within a second range, wherein the second shift amount is smaller than the first shift amount, and wherein the control circuitry performs the second operation to apply the second voltage to the word line subsequently to application of the first voltage to the word line in the first operation.. . ... Toshiba Memory Corporation

07/05/18 / #20180188963

Memory system and method of controlling memory system

According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. ... Toshiba Memory Corporation

06/28/18 / #20180183395

Active inductor and amplifier circuit

According to an embodiment, an active inductor has a first conductivity type mos transistor with a source that is connected to an electrical power source supply line and a drain that is connected to an output terminal. It has a capacitance between a gate of the first conductivity type mos transistor and the electrical power source supply line. ... Toshiba Memory Corporation

06/28/18 / #20180182773

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. ... Toshiba Memory Corporation

06/28/18 / #20180182464

Memory device to execute read operation using read target voltage

A memory device includes first and second memory strings, first and second word lines and a controller. The first memory string includes first and second memory cells, a first select transistor, a second select transistor, and a third select transistor between the first and second memory cells. ... Toshiba Memory Corporation

06/28/18 / #20180182455

Method for controlling resistive memory device

A method for controlling a resistive memory device is described. The resistive memory device including a memory cell provided between a first interconnection and a second interconnection crossing the first interconnection, and the memory cell transitions reversibly between a first resistance state and a second resistance state. ... Toshiba Memory Corporation

06/28/18 / #20180181305

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.. . ... Toshiba Memory Corporation

06/21/18 / #20180175912

File transmission/reception device and control method of file transmission/reception device

According to one embodiment, a file transmission/reception device includes a communication direction managing unit and an application unit. The communication direction managing unit, in near field communication, cuts off a connection with an opposing device in a case where a conflict occurs with the opposing device, and, after being reconnected to the opposing device, switches the file transmission/reception device to any one mode of a master mode and a slave mode. ... Toshiba Memory Corporation

06/21/18 / #20180175885

Hybrid ldpc-sec/secded decoding

A solid state storage device, comprising a non-volatile memory configured to store data encoded into a plurality of encoded data groups, each encoded data group of the plurality being encoded using a bch or hamming parity scheme, the plurality of encoded data groups being collectively further encoded by a parity scheme using a low density parity check (ldpc) code, a non-volatile memory controller communicatively coupled to the non-volatile memory and configured to access the plurality of encoded data groups, a first decoder configured to first decode the plurality of encoded data groups by hard-decision decoding the parity in each encoded data group, and a second decoder commutatively coupled to the first decoder and configured to determine the data groups decoded by the first decoder that contain errors, and to decode the parity of the data groups that contain errors using likelihood-of-errors information that is input to the second decoder.. . ... Toshiba Memory Corporation

06/21/18 / #20180175111

Semiconductor memory device

According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. ... Toshiba Memory Corporation

06/21/18 / #20180175058

Method of controlling a semiconductor memory device

According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.. ... Toshiba Memory Corporation

06/21/18 / #20180175057

Non-volatile storage device and method of manufacturing the same

According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. ... Toshiba Memory Corporation

06/21/18 / #20180175056

Semiconductor device and method for manufacturing same

According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. ... Toshiba Memory Corporation

06/21/18 / #20180175055

Semiconductor memory device

A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.. ... Toshiba Memory Corporation

06/21/18 / #20180175048

Nonvolatile semiconductor storage device

A nonvolatile semiconductor storage device having a control gate formed on a semiconductor substrate and including a cylindrical through hole. A block insulating film, a charge storage film, a tunnel insulating film, and a semiconductor layer are formed on a side surface of the control gate inside the through hole. ... Toshiba Memory Corporation

06/21/18 / #20180173430

Memory system that constructs virtual storage regions for virtual machines

A memory system connectable to a host includes a nonvolatile memory and a controller. The controller is configured to generate one or more virtual storage regions each of which is associated with a virtual machine running in the host, using physical memory regions of the nonvolatile memory, maintain a threshold value for each of said one or more virtual storage regions, determine a cumulative amount of data that have been written in each of said one or more virtual storage regions, and restrict writing of data with respect to a virtual storage region for which the cumulative amount exceeds the threshold value.. ... Toshiba Memory Corporation

06/14/18 / #20180166460

Semiconductor device and method for manufacturing same

A semiconductor device includes a stacked body, a columnar portion and a barrier film. The stacked body includes a plurality of insulating layers and a plurality of electrode layers including aluminum stacked alternately along a first direction. ... Toshiba Memory Corporation

06/14/18 / #20180166276

Method for manufacturing semiconductor device

A method for manufacturing a semiconductor device includes forming a mask layer including a) one metal from tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium, and iridium, b) boron, and c) carbon on a layer to be etched. The mask layer is patterned. ... Toshiba Memory Corporation

06/14/18 / #20180165011

Memory system and control method thereof

A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.. . ... Toshiba Memory Corporation

06/14/18 / #20180164680

Template and method of manufacturing semiconductor device

A template for patterning processes has a first protrusion portion on a first surface with a first step portion in a first region and a second step portion in a second region. The first step portion includes a plurality of first steps, at least one of which has a first step height and a first step width. ... Toshiba Memory Corporation

06/07/18 / #20180158508

Memory device including volatile memory, nonvolatile memory and controller

According to one embodiment, a memory device is connectable to a host, and includes a nonvolatile memory, a volatile memory which is used as a cache of the nonvolatile memory and has a higher access speed than the nonvolatile memory, and a controller which controls access to the nonvolatile memory and the volatile memory. The controller increments, when the controller receives a refresh command for the volatile memory from the host, a value of a refresh counter, and executes, when the value of the refresh counter exceeds a threshold, no refresh operation corresponding to the refresh command.. ... Toshiba Memory Corporation

06/07/18 / #20180157597

Ddr storage adapter

A method of accessing a persistent memory over a memory interface is disclosed. In one embodiment, the method includes allocating a virtual address range comprising virtual memory pages to be associated with physical pages of a memory buffer and marking each page table entry associated with the virtual address range as not having a corresponding one of the physical pages of the memory buffer. ... Toshiba Memory Corporation

06/07/18 / #20180157414

Storage device and control method of the same

According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller includes a host interface control circuit and a memory interface control circuit. ... Toshiba Memory Corporation

06/07/18 / #20180157282

Voltage regulator

A voltage regulator includes an operational amplifier that compares a feedback voltage that is proportional to an output voltage and a predetermined reference voltage that corresponds to a desired output voltage. The operational amplifier controls the conduction state of an output transistor according to the comparison. ... Toshiba Memory Corporation

06/07/18 / #20180157167

Manufacturing method of photomask and recording medium

A manufacturing method of a photomask according to the embodiment sets an exposure condition applied when a resist is formed into a three-dimensional target shape by using a photomask including a plurality of light-shielding areas. Subsequently, the method sets a hypothetical target shape obtained by correcting a target shape based on a development characteristic of the resist for the exposure condition. ... Toshiba Memory Corporation

06/07/18 / #20180157159

Photomask and manufacturing method of semiconductor device

A photomask according to the embodiment includes a glass substrate which has a first face and a second face located on a side opposite from the first face. The second face includes a transmission area and a light shielding area corresponding to an exposure pattern of a resist film exposed via the glass substrate. ... Toshiba Memory Corporation

05/31/18 / #20180152207

Memory controller, memory system, and control method

A memory controller according to an embodiment includes a memory interface that reads out a received word from a non-volatile memory and a decoder that performs bounded distance decoding for the read received word. The decoder sets rm (rm is a natural number equal to or larger than 1) symbols of a plurality of symbols constituting the received word, as options of symbol positions at each of which an error is assumed, generates a test pattern in which m (m is a natural number equal to or larger than 1 and equal to or smaller than the rm) symbols of the rm symbols are objects of rewriting, generates test hard-decision values by rewriting each of hard-decision values of the m symbols that are objects of rewriting in the test pattern, among the symbols, and performs bounded distance decoding for the test hard-decision values.. ... Toshiba Memory Corporation

05/31/18 / #20180151457

Semiconductor manufacturing method and semiconductor manufacturing apparatus

A semiconductor manufacturing method according to an embodiment includes forming a first film on a semiconductor substrate. The semiconductor manufacturing method includes forming cavities in the first film. ... Toshiba Memory Corporation

05/31/18 / #20180151418

Pattern forming method and imprint apparatus

A pattern forming method includes forming a first resist pattern on a substrate using imprint lithography. And forming a resist onto the substrate at least at positions corresponding to a second resist pattern and then curing the resist to form the a second resist pattern on the substrate.. ... Toshiba Memory Corporation

05/31/18 / #20180151235

Semiconductor device and operating method of same

A semiconductor device according to an embodiment includes first and second memory cells, a first word line, and first and second bit lines. The first memory cell has a first gate electrode and a first channel. ... Toshiba Memory Corporation

05/31/18 / #20180151229

Semiconductor memory system including a plurality of semiconductor memory devices

A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. ... Toshiba Memory Corporation

05/31/18 / #20180151200

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes: a first insulating layer; a global bit line and a reference bit line provided on the first insulating layer; a second insulating layer provided on the global bit line and the reference bit line; a select gate line provided on the second insulating layer; a first transistor provided on the global bit line; a local bit line coupled to the first transistor; first and second memory cells; and a sense amplifier. The global bit line and the reference bit line three-dimensionally intersect the select gate line via the second insulating layer.. ... Toshiba Memory Corporation

05/31/18 / #20180150238

Allocation of memory regions of a nonvolatile semiconductor memory for stream-based data writing

A semiconductor storage device comprises a nonvolatile semiconductor memory with memory regions, threads, and a controller. Each thread includes a buffer region in which write data from a host are stored before the write data are written to one of the memory regions, and the buffer region of each thread is different from buffer regions of the other threads. ... Toshiba Memory Corporation

05/24/18 / #20180146542

Uniformization of parasitic capacitance around wiring of a circuit substrate

A circuit substrate includes an insulating body, a wiring enclosed by the insulating body, a conductive layer formed within the insulating body on a same plane as the wiring, and electrically insulated from the wiring by the insulating body, and one or more conductive vias extending through an edge portion of the conductive layer in a thickness direction intersecting the plane. A first width of the insulating body between the wiring and the conductive layer at a first position in the plane direction that does not correspond to any of said one or more conductive vias is smaller than a second width of the insulating body between the wiring and the conductive layer at a second position in the plane direction that corresponds to one of said one or more conductive vias.. ... Toshiba Memory Corporation

05/24/18 / #20180145251

Variable resistance element and memory device

According to one embodiment, a variable resistance element includes first and second conductive layers and a first layer. The first conductive layer includes at least one of silver, copper, zinc, titanium, vanadium, chrome, manganese, iron, cobalt, nickel, tellurium, or bismuth. ... Toshiba Memory Corporation

05/24/18 / #20180145086

Dry etching method and method for manufacturing semiconductor device

A dry etching method includes a process of, while continuously applying bias power using an ion species to a material to be processed including a first conductive member, a first insulating film provided on the first conductive member, a second conductive member provided on the first insulating film, and a second insulating film provided on the second conductive member, dry etching the second insulating film to expose the second conductive member. A time for which the bias power is continuously applied is set to 50 microseconds or less and a duty ratio of the bias power is set to 50% or less.. ... Toshiba Memory Corporation

05/24/18 / #20180144808

Memory device that executes an erase operation for a nonvolatile memory

According to one embodiment, a memory device includes a controller, and a nonvolatile memory in which an erase operation is controlled by the controller, the nonvolatile memory including blocks, the erase operation executing every block, the nonvolatile memory transferring a first reply showing a completion of the erase operation and a fail bit count showing a number of memory cells in which a data erase is uncompleted after the completion of the erase operation to the controller. The controller selects a target block as a target of the erase operation based on the fail bit count.. ... Toshiba Memory Corporation

05/24/18 / #20180144801

Semiconductor memory device and writing operation mathod thereof

A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.. ... Toshiba Memory Corporation

05/24/18 / #20180144782

Magnetic memory and memory system

According to one embodiment, a magnetic memory includes: a first magnetoresistive effect element having a first resistance state or a second resistance state; and a read circuit. A read circuit is configured to apply the first read voltage to the first magnetoresistive effect element, hold a first charging potential caused by the first read voltage, apply a second read voltage higher than the first read voltage to the first magnetoresistive effect element, hold a second charging potential caused by the second read voltage, and determine whether the first magnetoresistive effect element is in the first resistance state or the second resistance state based on a comparison result between the first charging potential and the second charging potential.. ... Toshiba Memory Corporation

05/24/18 / #20180143992

Storage system

A storage system includes non-volatile storage devices and a control device. Each of the storage devices is divided into blocks, and data is erased in units of the blocks. ... Toshiba Memory Corporation

05/24/18 / #20180143901

Reconstruct drive for dynamic resizing

A solid-state drive (ssd) is configured for dynamic resizing. When the ssd approaches the end of its useful life because the over-provisioning amount is nearing the minimum threshold as a result of an increasing number of bad blocks, the ssd is reformatted with a reduced logical capacity so that the over-provisioning amount may be maintained above the minimum threshold.. ... Toshiba Memory Corporation

05/17/18 / #20180138923

Memory controller

According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. ... Toshiba Memory Corporation

05/17/18 / #20180138907

Data transmission device

According to one embodiment, a buffer circuit sets a level of transmission data to high or low, a power supply line supplies a power supply voltage to the buffer circuit, a buffer control circuit controls a switching operation of the buffer circuit, a current circuit feeds a dummy current to the power supply line, and a current control circuit controls the dummy current based on the level set in the transmission data.. . ... Toshiba Memory Corporation

05/17/18 / #20180138237

Magnetoresistive effect element and magnetic memory

According to one embodiment, a magnetoresistive effect element includes: a first magnetic layer; a nonmagnetic layer provided on the first magnetic layer; a second magnetic layer provided on the nonmagnetic layer; a first insulating layer provided at least on a side surface of the second magnetic layer; a second insulating layer covering at least a part of the first insulating layer; a conductive layer provided between the first insulating layer and the second insulating layer; and a first electrode including a first portion on the second magnetic layer and a second portion on a side surface of the second insulating layer. A height of a lower surface of the second portion is equal to or less than a height of an upper surface of the conductive layer.. ... Toshiba Memory Corporation

05/17/18 / #20180138197

Semiconductor device having a memory cell array provided inside a stacked body

According to one embodiment, a semiconductor device includes a stacked body, a memory cell array, and a columnar portion. The stacked body is provided on a major surface of a substrate. ... Toshiba Memory Corporation

05/17/18 / #20180138190

Semiconductor memory device

A semiconductor memory device includes a plurality of electrode layers stacked in a first direction; a semiconductor layer of a columnar shape extending through the electrode layers in the first direction; and a plurality of floating gates provided between the electrode layers and the semiconductor layer respectively. The floating gates surround the semiconductor layer. ... Toshiba Memory Corporation

05/17/18 / #20180138048

Pattern formation method

According to one embodiment, a pattern formation method includes forming a structure body on a first surface of a patterning member, the structure body having protrusions and a recess. The protrusions are arranged at a first pitch along a first direction. ... Toshiba Memory Corporation

05/17/18 / #20180137926

Semiconductor storage device

According to one embodiment, a semiconductor storage device includes: a nand string with a first set of memory cells including a first memory cell; and a second set of memory cells including a second memory cell disposed above the first memory cell. The number of memory cells included in the first set is different from that of memory cells included in the second set. ... Toshiba Memory Corporation

05/17/18 / #20180137285

Information processing apparatus and computer program product

According to one embodiment, an information processing apparatus includes a first memory, a signal generation unit, an integrity check unit, and an access-right update unit. Firmware is stored in the first memory. ... Toshiba Memory Corporation

05/17/18 / #20180137020

Electronic circuit board

According to an embodiment, an electronic circuit board includes a nonvolatile memory, a reading circuit to read data stored in the nonvolatile memory, a switch, and a communication circuit. When power is supplied from a first power source, the switch performs switching to a first state in which the nonvolatile memory and a host device configured to read and write data from and in the nonvolatile memory are connected. ... Toshiba Memory Corporation

05/17/18 / #20180136849

Memory controller, information processing apparatus, and processor

According to one embodiment, a memory controller includes a nonvolatile cache memory and a controller. The nonvolatile cache memory is configured to store a piece of data stored in a nonvolatile main memory connected to the memory controller. ... Toshiba Memory Corporation

05/17/18 / #20180136272

Fault detection apparatus

A fault detection apparatus is provided, including a measurement unit that measures a first time period taken until a reflection signal reflected on a fault of a test apparatus is received after a first signal is transmitted to the test apparatus; a memory unit that includes a cad data unit having cad data of the test apparatus and a model data unit to store model data indicating a relation between the first time period and a predicted conduction distance of the first signal; a control unit that calculates a range of a test object selected in the test apparatus, calculates the predicted conduction distance from the first time period based on the model data, and specifies a position of the fault which is separated by the predicted conduction distance from the measurement unit in said range; and a display unit that displays the position of the fault.. . ... Toshiba Memory Corporation

05/10/18 / #20180130820

Semiconductor memory device

A semiconductor memory device includes a first electrode layer extending in a first direction, a second electrode layer above the first electrode layer and extending in the first direction, a third electrode layer above the first electrode layer and extending in the first direction, an insulating member between the second and third electrode layers and extending in the first direction, first semiconductor members extending in the second direction through the first and second electrodes, second semiconductor members extending in the second direction through the first and third electrode layers, and third semiconductor members extending in the second direction, each having a first portion between the second and third electrode layers and in contact with the insulating member, and a second portion extending through the first electrode layer. In the first direction, an arrangement density of the third semiconductor members is lower than that of the first or second semiconductor member.. ... Toshiba Memory Corporation

05/10/18 / #20180130810

Semiconductor memory device and method for manufacturing the same

A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. ... Toshiba Memory Corporation

05/10/18 / #20180130529

Semiconductor memory device

According to embodiments, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell is provided between the first electrode and the second electrode and includes a metal film and a resistance change film. ... Toshiba Memory Corporation

05/10/18 / #20180129600

Memory system and control method

A memory system includes a nonvolatile memory having memory dies controlled in parallel and each including a plurality of physical blocks, and a controller. The controller manages a plurality of logical areas for storing data portions received from the host and parities calculated from the data portions, the logical areas including first and second logical areas for storing first and second parity groups, respectively. ... Toshiba Memory Corporation

05/10/18 / #20180129420

Memory system with selective access to first and second memories

A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an mpu that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.. . ... Toshiba Memory Corporation

05/10/18 / #20180129415

Memory system and method

According to one embodiment, a memory system includes a nonvolatile first memory, a second memory which has a buffer, and a memory controller. The memory controller manages a plurality of pieces of translation information. ... Toshiba Memory Corporation

05/03/18 / #20180122488

Semiconductor memory device for storing multivalued data

Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. ... Toshiba Memory Corporation

05/03/18 / #20180121592

Non-transitory computer readable storage medium, mask evaluation method and inspection apparatus

A non-transitory computer readable storage medium according to an embodiment stores a mask evaluation program evaluating a mask used to manufacture an integrated circuit device. The program causes a computer to realize a convolutional neural network. ... Toshiba Memory Corporation

05/03/18 / #20180121354

Memory system

A memory system includes a non-volatile memory, a buffer memory, and a controller. The controller is configured to write data corresponding to a write command received from a host in the buffer memory, and based on an indication from the host, do not write the data stored in the buffer memory into the non-volatile memory unless a non-volatilization event occurs, the non-volatilization event being one of a flush request from the host and a detection of a power shutdown.. ... Toshiba Memory Corporation

05/03/18 / #20180121136

Memory system

A memory system capable of being connected to a host, includes a non-volatile memory that includes a plurality of non-volatile memory dies, and a controller that is electrically connected to the non-volatile memory. The controller is configured to manage the plurality of non-volatile memory dies as a plurality of die sets, each die set including two or more of the non-volatile memory dies to which priorities are assigned respectively, select one die set from the plurality of die sets based on an identifier received from the host, and select, based on the assigned priorities, a non-volatile memory die from the selected die set as a writing destination die of write data received from the host.. ... Toshiba Memory Corporation

05/03/18 / #20180119288

Template and method of manufacturing semiconductor device

According to one embodiment, a template forming method is provided. In the template forming method, a template pattern is formed on a first surface of a substrate. ... Toshiba Memory Corporation

05/03/18 / #20180117796

Imprint template manufacturing apparatus and imprint template manufacturing method

According to one embodiment, an imprint template manufacturing apparatus includes: a stage that support a template having a convex portion where a concavo-convex pattern is formed; a supply head that supplies a liquid-repellent material in liquid form to the template on the stage; a moving mechanism that moves the stage and the supply head relatively in a direction along the stage; and a controller that controls the supply head and the moving mechanism such that the supply head applies the liquid-repellent material to at least a side surface of the convex portion so as to avoid the concavo-convex pattern. The liquid-repellent material contains a liquid-repellent component and a non-liquid-repellent component that react with the surface of the template, a volatile solvent that dissolves the liquid-repellent component, and a fluorine-based volatile solvent that dissolves the non-liquid-repellent component.. ... Toshiba Memory Corporation

05/03/18 / #20180117795

Imprint template manufacturing apparatus and imprint template manufacturing method

According to one embodiment, an imprint template manufacturing apparatus includes: a supply head that supplies a liquid-repellent material in liquid form to a template having a convex portion where a concavo-convex pattern is formed on a stage; a moving mechanism that moves the stage and the supply head relatively in a direction along the stage; a controller that controls the supply head and the moving mechanism such that the supply head applies the liquid-repellent material to at least a side surface of the convex portion so as to avoid the concavo-convex pattern; and a cleaning unit that supplies a liquid to the template coated with the liquid-repellent material. The liquid-repellent material contains a liquid-repellent component and a non-liquid-repellent component that react with the surface of the template, and a volatile solvent that dissolves the liquid-repellent component. ... Toshiba Memory Corporation

04/19/18 / #20180108418

Semiconductor memory device

A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.. ... Toshiba Memory Corporation

04/19/18 / #20180107592

Reconstruction of address mapping in a host of a storage system

A storage device includes a nonvolatile memory including a plurality of physical blocks, a communication interface connectable to a host, and a controller. The controller is configured to generate metadata of host data, which include user data and metadata of the user data, and write, in a physical block of the nonvolatile memory, the metadata of the host data, the metadata of the user data, and the user data continuously in this order, when the host data are received through the communication interface in association with a write command.. ... Toshiba Memory Corporation

04/19/18 / #20180107536

Memory system

According to one embodiment, a memory system includes a non-volatile first memory, a second memory, a battery, a first processor, and a second processor. The first processor is configured to execute fault diagnosis on the battery by discharging energy stored in the battery. ... Toshiba Memory Corporation

04/19/18 / #20180107432

Storage device and control method

According to one embodiment, a storage device includes a processor which executes first processing, second processing and third processing. The second processing includes processing for relaying a command issued by a host device, and an execution result of the first processing corresponding to the command, between the host device and the first processing. ... Toshiba Memory Corporation

04/19/18 / #20180107413

Reading of start-up information from different memory regions of a memory system

A memory system includes a nonvolatile semiconductor memory including a first memory region for storing start-up information and a second memory region for storing a copy of the start-up information, a volatile semiconductor memory, and a controller. The controller is configured to determine whether or not an address of the second memory region is stored in the volatile semiconductor memory, issue a first start-up read command, which designates no read address, to the nonvolatile semiconductor memory to read the start-up information from the first memory region if the address of the second memory region is not stored in the volatile semiconductor memory, and issue a second start-up read command, which designates the address of the second memory region as a read address, to read the start-up information from the second memory region if the address of the second memory region is stored in the volatile semiconductor memory.. ... Toshiba Memory Corporation

04/19/18 / #20180107391

Storage system having a host that manages physical data locations of storage device

A storage device includes a nonvolatile memory, a communication interface connectable to a host, and a controller. The controller is configured to carry out writing of data that is received through the communication interface at a physical location of the nonvolatile memory when a write command associated with the data is received through the communication interface, control the communication interface to return a first notification upon determining that the writing of data at the physical location of the nonvolatile memory has completed, and control the communication interface to return a second notification a predetermined period of time after the first notification has been returned.. ... Toshiba Memory Corporation

04/19/18 / #20180107389

Memory system

According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. ... Toshiba Memory Corporation

04/19/18 / #20180105936

Semiconductor manufacturing apparatus and manufacturing method of semiconductor device

According to some embodiments, a semiconductor manufacturing apparatus includes a first boat and a second boat, each of the first boat and the second boat having two support rings respectively provided at a top end and a bottom end thereof and a plurality of pillars provided between the top support ring and bottom support ring and spaced apart from one another. The pillar is provided with support protrusions on which a semiconductor substrate can be placed, and vertical positions of upper surfaces of the support protrusions of the second boat are lower than positions of upper surfaces of the support protrusions of the first boat. ... Toshiba Memory Corporation

04/05/18 / #20180097623

Authenticator, authenticatee and authentication method

According to one embodiment, an authenticator which authenticates an authenticatee, which stores first key information (nkey) that is hidden, includes a memory configured to store second key information (hkey) which is hidden, a random number generation module configured to generate random number information, and a data generation module configured to generate a session key (skey) by using the second key information (hkey) and the random number information. The authenticator is configured such that the second key information (hkey) is generated from the first key information (nkey) but the first key information (nkey) is not generated from the second key information (hkey).. ... Toshiba Memory Corporation

04/05/18 / #20180097011

Semiconductor memory device and method for manufacturing same

A semiconductor memory device according to one embodiment, includes a first electrode film, a plurality of semiconductor members, and a charge storage member. The first electrode film includes three or more first portions and a second portion connecting the first portions to each other. ... Toshiba Memory Corporation

04/05/18 / #20180096729

Semiconductor integrated circuit adapted to output pass/fail results of internal operations

In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.. . ... Toshiba Memory Corporation

04/05/18 / #20180096725

Semiconductor storage device and control method of semiconductor storage device with detecting levels of a multi-ary signal

According to one embodiment, there is provided a semiconductor storage device including n word lines, m bit lines, multiple memory cells, and a read circuit. N is an integer of four or greater. ... Toshiba Memory Corporation

04/05/18 / #20180096723

Semiconductor memory device which stores plural data in a cell

A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. ... Toshiba Memory Corporation

04/05/18 / #20180095663

Information processing device including host device and semiconductor memory device having a block rearrangement to secure free blocks

A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. ... Toshiba Memory Corporation

04/05/18 / #20180095523

Card and host apparatus

A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.. ... Toshiba Memory Corporation

03/29/18 / #20180091170

Memory system including a memory device that can determine optimum read voltage applied to a word line

A memory system includes a nonvolatile memory including a word line and a plurality of memory cells connected to the word line, and a controller configured to transmit to the nonvolatile memory, a command that causes the nonvolatile memory to search for an optimum read voltage for the plurality of memory cells connected to the word line.. . ... Toshiba Memory Corporation

03/29/18 / #20180090511

Integrated circuit device and method for manufacturing same

An integrated circuit device includes an insulating film, a contact extending in a first direction and being provided inside the insulating film, and an insulating member. A composition of the insulating member is different from a composition of the insulating film. ... Toshiba Memory Corporation

03/29/18 / #20180090510

Semiconductor memory device and method for manufacturing the same

According to one embodiment, a semiconductor memory device includes first to third conductive layers extending along a first direction, and a memory portion. A portion of the second conductive layer is provided between the third conductive layer and a portion of the first conductive layer. ... Toshiba Memory Corporation

03/29/18 / #20180090507

Semiconductor device and method for manufacturing same

A semiconductor device includes a stacked body and an insulating portion. The stacked body includes first to fourth electrode layers. ... Toshiba Memory Corporation

03/29/18 / #20180090450

Semiconductor device and method for manufacturing same

According to one embodiment, the recess has a side surface and a bottom surface. The side surface is continuous with the major surface. ... Toshiba Memory Corporation

03/29/18 / #20180090438

Semiconductor device and manufacturing method thereof

According to some embodiments, a semiconductor device includes a substrate and an insulating film that is provided on the substrate. The device further includes a contact plug which includes a barrier metal layer provided in the insulating film, and a plug material layer provided in the insulating film, the barrier metal layer disposed between the plug material layer and the insulating film. ... Toshiba Memory Corporation

03/29/18 / #20180090369

Semiconductor device manufacturing method

A semiconductor device manufacturing method includes forming a first hole in a first processed layer. A first sacrificial film is formed in the first hole. ... Toshiba Memory Corporation

03/29/18 / #20180090220

Semiconductor memory device

A semiconductor memory device includes memory cells, a word line connected to gates of the memory cells, and a control circuit configured to execute a write operation on the memory cells. The write operation includes a first program operation during which a first program voltage is applied to the word line, a first verify operation during which a first verification voltage is applied to the word line to determine whether or not the first program operation passed, a second program operation during which a second program voltage is applied to the word line, and a second verify operation during which a second verification voltage is applied to the word line to determine whether or not the second program operation passed. ... Toshiba Memory Corporation

03/29/18 / #20180090218

Memory system that carries out temperature-based access to a memory chip

A memory system is connectable to a host and comprises a memory chip including a nonvolatile semiconductor memory cell array, a memory controller, a first temperature sensor positioned to measure a first temperature, which is representative of a temperature of the memory controller, and a second temperature sensor positioned to measure a second temperature, which is representative of a temperature of the memory chip. The memory controller is configured to compare the first temperature against a first threshold temperature and a second temperature against a second threshold temperature and carry out access to the memory chip when either the first temperature is greater than the first threshold temperature or the second temperature is greater than the second threshold temperature.. ... Toshiba Memory Corporation

03/29/18 / #20180090212

Semiconductor memory device and memory system

A semiconductor memory device includes first, second, and third memory cells, and first, second, and third word lines that are respectively connected to gates of the first, second, and third memory cells. A control circuit executes first, second, and third read operations in response to first, second, and third command sets, respectively. ... Toshiba Memory Corporation

03/29/18 / #20180090210

Semiconductor memory device and method for driving same

A semiconductor memory device includes first to fourth electrodes; first and second semiconductor members; a first charge storage member provided between the first semiconductor member and the first electrode; a first interconnect connected to the second electrode side of the first semiconductor member and to the fourth electrode side of the second semiconductor member; and a control circuit. The control circuit sets the first interconnect to a floating state, causes a potential of the third electrode side of the second semiconductor member to increase to a first potential, causes the potential of the third electrode to increase to a second potential lower than the first potential, causes the potential of the second electrode to increase to a third potential lower than the first potential, applies a fourth potential lower than the second and the third potentials to the first electrode, and sets the fourth electrode to a floating state.. ... Toshiba Memory Corporation

03/29/18 / #20180090182

Semiconductor device having a slit for aligning a connector and a hole for determining positional accuracy of the slit

A semiconductor device includes a substrate, a nonvolatile semiconductor memory disposed on a surface of the substrate, and a controller disposed on a surface of the controller. The substrate has a slit on an edge on which interface connection terminals are formed, a ground pattern, first and second wiring patterns that are electrically connected to the ground pattern and extend in a direction in which the slit extends, and a through hole that is formed between the first and second wiring patterns and is large enough along a dimension between the first and second wiring patterns to span substantially all of the spacing between the first and second wiring patterns.. ... Toshiba Memory Corporation

03/29/18 / #20180089078

Storage device that restores data lost during a subsequent data write

A storage device that can be connected to a host device includes a plurality of nonvolatile memories. Each nonvolatile memory includes first memory cells connected to a first word line and second memory cells connected to a second word line. ... Toshiba Memory Corporation

03/29/18 / #20180089021

Storage device that restores data lost during a subsequent data write

A storage device includes a plurality of nonvolatile memories each of which includes first memory cells connected to a first word line and second memory cells connected to a second word line that is adjacent to the first word line, and a controller. The controller is configured to maintain parity data for data written in the first memory cells of the nonvolatile memories, and when carrying out data writing in the second memory cells connected to the second word line in a targeted nonvolatile memory, which is one of the plurality of nonvolatile memories, upon detecting a failure in the data writing therein, carrying out restoration of data that were written in the first memory cells of the targeted nonvolatile memory using the parity data.. ... Toshiba Memory Corporation

03/29/18 / #20180088828

Memory system with garbage collection

According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from a host, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the host before the first request is issued.. ... Toshiba Memory Corporation

03/29/18 / #20180088811

Storage device that compresses data received from a host before writing therein

A storage device includes a nonvolatile storage and a controller. The controller is configured to compress data received from a host in association with a write command designating a first data length as a length of the data and a starting logical address of the data, into compressed data of a second data length shorter than the first data length, write the compressed data in the nonvolatile storage. ... Toshiba Memory Corporation

03/29/18 / #20180088805

Storage device that writes data from a host during garbage collection

A memory system includes a controller, a buffer, and a nonvolatile memory including a plurality of blocks, wherein each of the blocks includes a plurality of pages and each of the pages includes a plurality of unit data portions. The controller is configured to carry out garbage collection by reading data from one or more pages of a target block of the garbage collection and selectively copying valid unit data portions included in the read data to another block, count a number of invalid unit data portions included in the read data, and accept, in the buffer, unit data portions from a host as write data, up to a number determined based on the counted number, during the garbage collection.. ... Toshiba Memory Corporation

03/29/18 / #20180088100

Analysis device

An analysis device includes a vapor phase decomposition unit, a heating unit, an evacuation unit, a recovery unit and an analysis unit. The vapor phase decomposition unit performs vapor phase decomposition of a first film on a substrate. ... Toshiba Memory Corporation

03/29/18 / #20180085799

Exhaust system, semiconductor manufacturing equipment, and method for operating the exhaust system

According to one embodiment, an exhaust system includes a first pump unit, a second pump unit, a shaft, and a motor. The first pump unit includes a first exhaust chamber, a first intake port, a first exhaust port, and a first rotor. ... Toshiba Memory Corporation








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