Real Time Touch



new TOP 200 Companies filing patents this week

new Companies with the Most Patent Filings (2010+)




Real Time Touch

United Microelectronics Corp patents


Recent patent applications related to United Microelectronics Corp. United Microelectronics Corp is listed as an Agent/Assignee. Note: United Microelectronics Corp may have other listings under different names/spellings. We're not affiliated with United Microelectronics Corp, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "U" | United Microelectronics Corp-related inventors


Complementary metal oxide semiconductor device and method of forming the same

A method for forming a complementary metal oxide semiconductor device is disclosed. First, a substrate having a first device region and a second device region is provided. ... United Microelectronics Corp

Semiconductor device with metal gate

A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (bbm) layer on the high-k dielectric layer. Preferably, the bbm layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.. ... United Microelectronics Corp

Method for fabricating semiconductor device

A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a spacer adjacent to the gate structure; forming a recess adjacent to the spacer; forming a buffer layer in the recess, wherein the buffer layer comprises a crescent moon shape; and forming an epitaxial layer on the buffer layer.. . ... United Microelectronics Corp

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region and the substrate includes a semiconductor layer on top of an insulating layer; forming a first front gate on the first region of the substrate and a second front gate on the second region of the substrate; removing part of the insulating layer under the first front gate; forming a first back gate on the insulating layer under the first front gate; and forming a second back gate under the second front gate.. . ... United Microelectronics Corp

Intra-metal capacitor and method of forming the same

A method of forming a capacitor includes the following steps. First, a substrate is provided. ... United Microelectronics Corp

Electrostatic discharge protection semiconductor device

An electrostatic discharge (esd) protection device includes a substrate, a first gate group and a second gate group on the substrate, a drain region and a fourth doped region respectively at two sides of the first gate group, a source region and the fourth doped region respectively at two sides of the second gate group, a first doped region in the substrate and surrounded by the drain region, and a second doped region in the substrate and surrounded by the fourth doped region. The drain region and the source region have a first conductivity type. ... United Microelectronics Corp

Semiconductor package structure and method for forming the same

A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. ... United Microelectronics Corp

Method of forming a semiconductor device

A method of forming a semiconductor device includes following steps. First of all, plural mandrel patterns are formed on a target layer. ... United Microelectronics Corp

Electrostatic discharge protection device and manufacturing method thereof

An esd protection device includes a semiconductor substrate, a well, a gate structure, a first source/drain region, a second source/drain region, a first doped region, and a second doped region. The well is disposed in the semiconductor substrate. ... United Microelectronics Corp

Semiconductor device with dummy pattern in high-voltage region and method of forming the same

A semiconductor device includes a substrate having a high-voltage (hv) region; hv gate structures formed in the hv region of the substrate; a hv dummy pattern disposed in the hv region, and the hv dummy pattern comprising at least a semiconductor portion and a dummy hm stack disposed on the semiconductor portion, wherein a height (hs) of the semiconductor portion of the hv dummy pattern is smaller than a height (hhv-g) of a hv gate electrode of one of the hv gate structures.. . ... United Microelectronics Corp

Method for determining abnormal equipment in semiconductor manufacturing system and program product

A method for determining abnormal equipment in semiconductor manufacturing system includes processing wafers. A measurement data relating to wafers at respective processing steps and at each tool stack run count for respective tools is provided. ... United Microelectronics Corp

Extreme ultraviolet mask

An extreme ultraviolet (euv) mask includes: a substrate having a first region and a second region; a reflective layer on the substrate; an absorbing layer on the reflective layer; and a first recess in the absorbing layer and in part of the reflective layer on the first region. Preferably, a bottom surface of the first recess exposes a top surface of the reflective layer.. ... United Microelectronics Corp

Semiconductor device

A semiconductor device including a substrate and a shallow trench isolation (sti) structure is provided. The substrate has a first voltage area and a second voltage area. ... United Microelectronics Corp

Method for fabricating semiconductor device

A semiconductor device including a logic transistor, a non-volatile memory (nvm) cell and a contact etching stop layer (cesl) is shown. The cesl includes a first silicon nitride layer on the logic transistor but not on the nvm cell, a silicon oxide layer on the first silicon nitride layer and on the nvm cell, and a second silicon nitride layer disposed on the silicon oxide layer over the logic transistor and disposed on the silicon oxide layer on the nvm cell.. ... United Microelectronics Corp

08/16/18 / #20180233504

Manufacturing method of semiconductor device

A manufacturing method of a semiconductor device includes the following steps. A barrier layer is formed in a first region and a second region of a semiconductor substrate. ... United Microelectronics Corp

08/16/18 / #20180233449

Method for fabricating contact electrical fuse

A method for fabricating semiconductor device includes the steps of first forming a first dielectric layer on a substrate, in which a first conductor is embedded within the first dielectric layer. Next, a second dielectric layer is formed on the first dielectric layer, part of the second dielectric layer is removed to form a contact hole, and a lateral etching process is conducted to expand the contact hole to form a funnel-shaped opening. ... United Microelectronics Corp

08/16/18 / #20180233419

Overlay mark and method for evaluating stability of semiconductor manufacturing process

The present invention provides an overlay mark, including a substrate and plural sets of first pattern block and second pattern block. A first direction and a second direction are defined on the substrate, wherein the first direction and the second direction are perpendicular to each other. ... United Microelectronics Corp

08/16/18 / #20180233416

Method for preventing dishing during the manufacture of semiconductor devices

A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a method approach of the embodiment, a substrate having at least a first area with a plurality of polysilicon gates and a second area adjacent to the first area is provided. ... United Microelectronics Corp

08/09/18 / #20180226435

Method for forming semiconductor device

The present invention provides a method of forming a semiconductor device. First, a substrate having a first insulating layer formed thereon is provided. ... United Microelectronics Corp

08/09/18 / #20180226403

Insulating layer next to fin structure and method of removing fin structure

A method of removing a fin structure includes providing a substrate. A fin structure extends from the substrate. ... United Microelectronics Corp

08/09/18 / #20180224817

Method of monitoring processing system for processing substrate

A method of monitoring a processing system for processing a substrate is provided. The method includes the following steps: acquiring data from the processing system for a plurality of parameters, the data including a plurality of data values; grouping the parameters into a plurality of sub-groups, each of the sub-groups including a plurality of correlated parameters; constructing a principle components analysis (pca) model from the data values for the correlated parameters in a first one of the sub-groups, including normalizing the data values in the first one of the sub-groups with a first weighting factor and a second weighting factor, wherein the first weighting factor is different from the second weighting factor; and determining a statistical quantity using the pca model.. ... United Microelectronics Corp

08/02/18 / #20180219063

Semiconductor device and method of fabricating the same

A semiconductor device and a method of fabricating the same are provide. The fabricating method includes providing a silicon-on-insulator (soi) substrate that includes, from bottom to top, a substrate, a first insulating layer and a semiconductor layer. ... United Microelectronics Corp

08/02/18 / #20180218917

Method of patterning semiconductor device

A method of patterning a semiconductor device includes following steps. First of all, a substrate is provided, and a first target pattern is formed in the substrate. ... United Microelectronics Corp

07/26/18 / #20180211966

Method for fabricating semiconductor structure

A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. ... United Microelectronics Corp

07/26/18 / #20180211960

Semiconductor device having fin-shaped structure and bump

A semiconductor device includes a substrate having a first region and a second region, a fin-shaped structure and a bump on the first region of the substrate, and a shallow trench isolation (sti) around the fin-shaped structure and on the bump. Preferably, the fin-shaped structure and the bump comprise different material, the fin-shaped structure comprises a top portion and a bottom portion, the top portion and the bottom portion comprise different semiconductor material, and a top surface of the bottom portion is lower than a top surface of all of the sti on both the first region and the second region and higher than a top surface of the bump and the top surface of the bump contacts the sti directly.. ... United Microelectronics Corp

07/26/18 / #20180208460

Semiconductor structure and manufacturing method for the same

A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a mems region. ... United Microelectronics Corp

07/19/18 / #20180205013

Resistive random access memory (rram) and forming method thereof

A method of forming a resistive random access memory (rram) includes the following steps. A first dielectric layer is formed on a first electrode layer. ... United Microelectronics Corp

07/19/18 / #20180204939

Semiconductor device including quantum wires

A semiconductor device includes a substrate including a first semiconductor material, a gate structure formed on the substrate, and a source stressor and a drain stressor formed in the substrate respectively in a recess at two sides of the gate structure. The source stressor and the drain stressor respectively include at least a first quantum wire and at least a second quantum wire formed on the first quantum wire. ... United Microelectronics Corp

07/19/18 / #20180204848

Semiconductor memory cell structure

A semiconductor memory cell structure includes a substrate, a tunnel dielectric layer formed on the substrate, a blocking dielectric layer formed on the substrate, a control gate formed on the blocking dielectric layer, and a tri-layered charge-trapping layer sandwiched between the tunnel dielectric layer and the blocking dielectric layer. Furthermore, the tri-layered charge-trapping layer includes a bottom nitride layer formed on the substrate, a top nitride layer formed on the bottom nitride layer, and a middle nitride layer sandwiched between the bottom nitride layer and the top nitride layer. ... United Microelectronics Corp

07/19/18 / #20180204838

Integrated circuit structure with semiconductor devices and method of fabricating the same

An integrated circuit (ic) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (ud) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the ud trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. ... United Microelectronics Corp

07/19/18 / #20180203344

Photomask

A photomask includes a substrate, a patterned absorber layer disposed on the substrate, and a plurality of openings. Each of the openings penetrates the patterned absorber layer and exposes a part of the substrate. ... United Microelectronics Corp

07/19/18 / #20180201498

Micro-electro-mechanical system structure and method for forming the same

A micro-electro-mechanical (mems) structure and a method for forming the same are disclosed. The mems structure includes a sacrificial layer, a lower dielectric film, an upper dielectric film, a plurality of through holes and a protective film. ... United Microelectronics Corp

07/12/18 / #20180197981

Method for fabricating semiconductor device

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first fin-shaped structure thereon; forming a spacer adjacent to the first fin-shaped structure; using the spacer as mask to remove part of the substrate for forming a second fin-shaped structure, wherein the second fin-shaped structure comprises a top portion and a bottom portion; and forming a doped portion in the bottom portion of the second fin-shaped structure.. . ... United Microelectronics Corp

07/12/18 / #20180197819

Interconnect structure and fabricating method thereof

An interconnect structure including a substrate, at least one ultra-thick metal (utm) layer, a first dielectric layer and at least one pad metal layer is provided. The at least one utm layer is disposed on the substrate. ... United Microelectronics Corp

07/12/18 / #20180197742

Doping method for semiconductor device

A doping method for a semiconductor device including the following steps is provided. A substrate is provided. ... United Microelectronics Corp

07/05/18 / #20180190785

Semiconductor device having asymmetric spacer structures

A semiconductor device including a semiconductor substrate, agate on the semiconductor substrate, a drain doping region in the semiconductor substrate on a first side of the gate, a source doping region in the semiconductor substrate on a second side of the gate, a first spacer structure on a first sidewall of the gate between the gate and the drain doping region, and a second spacer structure on a second sidewall of the gate between the gate and the source doping region. The first spacer structure is composed of a low-k dielectric layer on the first sidewall of the gate and a first spacer material layer on the low-k dielectric layer. ... United Microelectronics Corp

07/05/18 / #20180190714

Method for fabricating a semiconductor device

A method for fabricating a semiconductor device includes the steps of: forming a channel layer on a substrate; forming a gate dielectric layer on the channel layer; forming a source layer and a drain layer adjacent two sides of the gate dielectric layer; forming a bottom gate on the gate dielectric layer; forming a phase change layer on the bottom gate; and forming a top gate on the phase change layer.. . ... United Microelectronics Corp

07/05/18 / #20180190623

Package structure and method of manufacturing the same

The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided. ... United Microelectronics Corp

07/05/18 / #20180190499

Method for fabricating metal gate structure

A method for fabricating a metal gate structure includes following steps. A substrate is provided and followed by forming a high-k dielectric layer on the substrate. ... United Microelectronics Corp

07/05/18 / #20180190344

Six-transistor static random access memory cell and operation method thereof

The present invention provides a six transistor static random-access memory (6t-sram) cell, the 6t-sram cell includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, and a first storage node, a second inverter comprising a second pull-up transistor, a second pull-down transistor, and a second storage node, wherein the first storage node is coupled to gates of the second pull-up transistor and the second pull-down transistor, a switch transistor configured to couple the second storage node to gates of the first pull-up transistor and the first pull-down transistor, and an access transistor coupled to gates of the first pull-up transistor and the first pull-down transistor.. . ... United Microelectronics Corp

07/05/18 / #20180188185

Semiconductor structure and method for reviewing defects

A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.. . ... United Microelectronics Corp

06/28/18 / #20180182900

Semiconductor device and manufacturing method thereof

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate having a tunneling well, a tunneling oxide layer, a charge storage layer and a control gate. ... United Microelectronics Corp

06/28/18 / #20180182862

Method for forming a semiconductor structure

A method for forming a semiconductor structure includes the following steps. First, a preliminary structure is provided. ... United Microelectronics Corp

06/28/18 / #20180182860

Multi-threshold voltage semiconductor device

A semiconductor device preferably includes: a first metal-oxide semiconductor (mos) transistor on a substrate; a first ferroelectric (fe) layer connected to the first mos transistor; a second mos transistor on the substrate; and a second fe layer connected to the second mos transistor. Preferably, the first fe layer and the second fe layer include different capacitance.. ... United Microelectronics Corp

06/28/18 / #20180182766

Static random-access memory device

The present invention proposes a static random-access memory device (sram). The static random-access memory device is composed of two p-channel gates of loading transistor, two n-channel gates of driving transistor and two n-channel gates of accessing transistor in a memory cell. ... United Microelectronics Corp

06/21/18 / #20180175110

Resistive memory and method for manufacturing the same

A semiconductor structure includes a memory unit structure. The memory unit structure includes a transistor, a first electrode, two second electrode, and two resistive random access memory (rram) elements. ... United Microelectronics Corp

06/21/18 / #20180174970

Method for fabricating semiconductor device

A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a first gate structure on the substrate, a first spacer around the first gate structure, and an interlayer dielectric (ild) layer around the first spacer; performing a first etching process to remove part of the ild layer for forming a recess; performing a second etching process to remove part of the first spacer for expanding the recess; and forming a contact plug in the recess.. . ... United Microelectronics Corp

06/21/18 / #20180174966

Semiconductor device

A semiconductor device includes: a substrate having a first semiconductor layer, an insulating layer, and a second semiconductor layer; an active device on the substrate; an interlayer dielectric (ild) layer on the active device; a first contact plug adjacent to the active device; and a second contact plug in the ild layer and electrically connected to the active device. Preferably, the first contact plug includes a first portion in the insulating layer and the second semiconductor layer and a second portion in the ild layer, in which a width of the second portion is greater than a width of the first portion.. ... United Microelectronics Corp

06/14/18 / #20180166574

Finfet with epitaxial layer having octagonal cross-section

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first epitaxial layer adjacent to two sides of the gate structure; forming a patterned mask on the epitaxial layer; and using the patterned mask to remove part of the first epitaxial layer for forming a second epitaxial layer.. . ... United Microelectronics Corp

06/14/18 / #20180166571

Method for forming recess within epitaxial layer

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first recess adjacent to two sides of the gate structure; forming an epitaxial layer in the first recess; removing part of the epitaxial layer to forma second recess; and forming an interlayer dielectric (ild) layer on the gate structure and into the second recess.. . ... United Microelectronics Corp

06/14/18 / #20180166532

Method for fabricating cap layer on an epitaxial layer

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. ... United Microelectronics Corp

06/14/18 / #20180166455

Integrated circuit and method for manufacturing thereof

A method for manufacturing an integrated circuit includes following steps. A substrate including a memory region and a core region is provided. ... United Microelectronics Corp

06/14/18 / #20180166444

Method of forming fin shape structure

A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. ... United Microelectronics Corp

06/14/18 / #20180166441

Semiconductor device and fabrication method thereof

A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. ... United Microelectronics Corp

06/14/18 / #20180166434

Method for filling patterns

A method for filling patterns includes the steps of: providing a substrate having a cell region defined thereon; forming main patterns on the substrate and within the cell region; and filling first dummy patterns adjacent to the main patterns. Preferably, each of the first dummy patterns comprises a first length along x-direction between 2 μm to 5 μm and a second length along y-direction between 3 μm to 5 μm.. ... United Microelectronics Corp

06/14/18 / #20180162725

Semiconductor device and fabrication method thereof

A semiconductor device includes a semiconductor substrate comprising a mos transistor. A mems device is integrally constructed above the mos transistor. ... United Microelectronics Corp

06/07/18 / #20180158943

Field-effect transistor

A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. ... United Microelectronics Corp

06/07/18 / #20180158903

Method of fabricating sti trench and sti structure

A method of fabricating an sti trench has a sidewall with two different slopes. The fabricating steps include providing a substrate with a patterned mask thereon. ... United Microelectronics Corp

06/07/18 / #20180158902

Semiconductor device

A semiconductor device comprises a fin shaped structure, a shallow trench isolation, a diffusion break structure and a gate electrode. The fin shaped structure is disposed on a substrate. ... United Microelectronics Corp

06/07/18 / #20180158738

Semiconductor device structure

A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. ... United Microelectronics Corp

06/07/18 / #20180156862

Test key structure and method of measuring resistance of vias

The present invention provides a test key structure for measuring or simulating a target via array. The structure includes a substrate with a test region, a plurality of first conductive lines in the test region; a plurality of second conductive lines in the test region and on the first conductive lines, wherein the first conductive lines and the second conductive lines overlaps vertically in a plurality of target regions, and a plurality of vias disposed between the first conductive lines and the second conductive lines, wherein at least two vias vertically contact one of the first conductive lines and one of the second conductive lines. ... United Microelectronics Corp

05/31/18 / #20180151685

Method of forming semiconductor device

A method of forming a semiconductor device includes the following steps. A substrate is provided, and the substrate has a first region. ... United Microelectronics Corp

05/31/18 / #20180151666

Method of fabricating metal-insulator-metal capacitor

A method of fabricating a metal-insulator-metal capacitor includes providing a dielectric layer. The dielectric layer is etched to form a first hole including a first convex profile bulging into the dielectric layer. ... United Microelectronics Corp

05/31/18 / #20180151571

Layout of semiconductor transistor device

The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. ... United Microelectronics Corp

05/31/18 / #20180151555

Intra-metal capacitor and method of forming the same

An intra-metal capacitor is provided. The intra-metal capacitor is formed in a dielectric layer and comprising a first electrode and a second electrode, wherein the first electrode penetrate through the whole thickness of the dielectric layer, and the second electrode does not penetrate through the whole thickness of the dielectric layer.. ... United Microelectronics Corp

05/31/18 / #20180151428

Conductive structure and method for manufacturing conductive structure

A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. ... United Microelectronics Corp

05/31/18 / #20180151371

Semiconductor device and fabrication method thereof

A semiconductor device includes first fin-shaped structures and second fin-shaped structures, which are separately disposed on a semiconductor substrate. Each of the first and second fin-shaped structures includes a base portion and a top portion protruding from the top portion. ... United Microelectronics Corp

05/31/18 / #20180149978

Method for forming patterned structure

A method for forming a patterned structure includes following steps. First lines elongated in a first direction and second lines elongated in a second direction in a layout pattern are decomposed into two masks. ... United Microelectronics Corp

05/24/18 / #20180145081

Static random access memory unit cell

The present invention provides a sram unit cell which includes a semiconductor substrate, six transistors, a first well, two first doped regions and two second doped regions. The transistors are disposed on the semiconductor substrate, and include a first gate line and a second gate line. ... United Microelectronics Corp

05/24/18 / #20180144988

Semiconductor device and manufacturing method thereof

A semiconductor device includes a semiconductor substrate, a shallow trench isolation structure, gate electrodes, and a gate isolation structure. The semiconductor substrate includes fin structures, and each of the fin structures is elongated in a first direction. ... United Microelectronics Corp

05/24/18 / #20180143529

Method of forming photomask

A method of forming a photomask is provided. A first layout pattern is first provided to a computer system and followed by generating an assist feature pattern by the computer system based on the first layout pattern and adding the assist feature pattern into the first layout pattern to form a second layout pattern. ... United Microelectronics Corp

05/17/18 / #20180138316

Semiconductor device

A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a first dielectric layer covering on the oxide-semiconductor layer and the source/drain regions, a second gate between the two source/drain regions and partially covering the oxide-semiconductor layer, and a charge storage structure between the first gate electrode and the oxide-semiconductor layer.. . ... United Microelectronics Corp

05/17/18 / #20180138263

Semiconductor structure and method for forming the same

A semiconductor structure includes a capacitor. The capacitor includes a bottom electrode, a first high-k dielectric layer, a second high-k dielectric layer and a top electrode. ... United Microelectronics Corp

05/17/18 / #20180138180

Semiconductor device and method for fabricating the same

A semiconductor device includes a semiconductor substrate having a first region and a second region, a plurality of first semiconductor fins in the first region, a plurality of second semiconductor fins in the second region, a first solid-state dopant source layer within the first region on the semiconductor substrate, a first insulating buffer layer on the first solid-state dopant source layer, a second solid-state dopant source layer within the second region on the semiconductor substrate, a second insulating buffer layer on the second solid-state dopant source layer and on the first insulating buffer layer, a first fin bump in the first region, and a second fin bump in the second region. The first fin bump includes a first sidewall spacer and the second fin bump comprises a second sidewall spacer. ... United Microelectronics Corp

05/17/18 / #20180138178

Semiconductor device including barrier layer and manufacturing method thereof

A manufacturing method of a semiconductor device includes the following steps. A barrier layer is formed in a first region and a second region of a semiconductor substrate. ... United Microelectronics Corp

05/17/18 / #20180138167

Electrostatic discharge (esd) protection device and method fabricating the esd protection device

An electrostatic discharge (esd) device includes a gate structure, disposed on a substrate. A drain doped region of a first conductive type is in the substrate, adjacent to a first side of the gate structure, wherein the drain doped region has a first impurity concentration. ... United Microelectronics Corp

05/17/18 / #20180138166

Semiconductor device for electrostatic discharge protection

A semiconductor device for esd protection, includes a drain region, a first doped region, a second doped region and a source region. The drain region is disposed in a substrate at a first side of a gate and the drain region has a first conductivity type. ... United Microelectronics Corp

05/17/18 / #20180138125

Conductive structure, layout structure including conductive structure, and method for manufacturing conductive structure

A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. ... United Microelectronics Corp

05/17/18 / #20180138088

Method of forming semiconductor device

A semiconductor device and method of forming the same, the semiconductor device includes a first and second fin shaped structures, a first and second gate structures and a first and second plugs. The first and second fin shaped structures are disposed on a first region and a second region of a substrate and the first and second gate structure are disposed across the first and second fin shaped structures, respectively. ... United Microelectronics Corp

05/10/18 / #20180130871

Capacitor structure and manufacturing method thereof

The present invention provides a capacitor structure, including a bottom plate and a top plate, wherein the top plate has a first sidewall, and wherein an area of the top plate is less than an area of the bottom plate. The capacitor structure further includes a dielectric layer in between the bottom plate and the top plate, the dielectric layer having a second sidewall, wherein the first sidewall is aligned with the second sidewall, and at least one sidewall spacer placed against the first sidewall of the top plate and the second sidewall of the dielectric layer, and overlaying a portion of the bottom plate.. ... United Microelectronics Corp

05/10/18 / #20180130753

Semiconductor device

A semiconductor device includes a substrate including a plurality of chip areas and a scribe line defined thereon, and a mark pattern disposed in the scribe line. The mark pattern includes a plurality of unit cells immediately adjacent to each other, and each unit cell includes a first active region, a second active region isolated from the first active region, a plurality of first gate structures extending along a first direction and arranged along a second direction perpendicular to the first direction, and a plurality of first conductive structures. ... United Microelectronics Corp

05/10/18 / #20180130742

Method for fabricating semiconductor device having a patterned metal layer embedded in an interlayer dielectric layer

A method for fabricating semiconductor device first includes providing a substrate and a shallow trench isolation (sti) in the substrate, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ild) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask as mask are utilized to remove part of the first ild layer for forming a recess, and a patterned metal layer is formed in the recess and on the sti.. ... United Microelectronics Corp

05/03/18 / #20180122897

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes the steps of first providing a substrate, forming a gate structure on the substrate, forming a hard mask on the substrate and the gate structure, patterning the hard mask to form trenches exposing part of the substrate, and forming raised epitaxial layers in the trenches. Preferably, the gate structure is extended along a first direction on the substrate and the raised epitaxial layers are elongated along a second direction adjacent to two sides of the gate structure.. ... United Microelectronics Corp

05/03/18 / #20180122707

Method for forming semiconductor device

The present invention provides a method for forming a semiconductor device, comprising the following steps: firstly, a substrate is provided, having a nmos region and a pmos region defined thereon, next, a gate structure is formed on the substrate within the nmos region, and a disposal spacer is formed on two sides of the gate structure, afterwards, a mask layer is formed on the pmos region to expose the nmos region, next, a recess is formed on two sides of the gate structure spaced from the gate structure by the disposal spacer within the nmos region, the disposal spacer is then removed after the recess is formed, and an epitaxial layer is formed into the recess.. . ... United Microelectronics Corp

05/03/18 / #20180122705

Method for fabricating semiconductor device

First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ild) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different. ... United Microelectronics Corp

05/03/18 / #20180122693

Method for forming semiconductor structure

A method for forming a semiconductor structure is provided, including the following steps. A first dielectric layer is formed on a substrate. ... United Microelectronics Corp

05/03/18 / #20180120693

Method for correcting layout pattern

A method of correcting a layout pattern is provided in the present invention. The method includes the following steps. ... United Microelectronics Corp

04/19/18 / #20180108837

Semiconductor device having memory cell structure and method of manufacturing the same

A semiconductor device is provided, including a lower conducting layer formed above a substrate, an upper conducting layer, and a memory cell structure formed on the lower conducting layer (such as formed between the lower and upper conducting layers). The memory cell structure includes a bottom electrode formed on the lower conducting layer and electrically connected to the lower conducting layer, a transitional metal oxide (tmo) layer formed on the bottom electrode, a tmo sidewall oxides formed at sidewalls of the tmo layer, a top electrode formed on the tmo layer, and spacers formed on the bottom electrode. ... United Microelectronics Corp

04/19/18 / #20180108744

Method of manufacturing semiconductor memory device

A method of manufacturing a semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device formed from the manufacturing method includes a plurality of semiconductor memory cells and an electric isolating structure. ... United Microelectronics Corp

04/19/18 / #20180108656

Asymmetrical fin structure and method of fabricating the same

An asymmetrical fin structure includes a substrate. The substrate includes a top surface. ... United Microelectronics Corp

04/19/18 / #20180108570

Method for manufacturing fins

A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. ... United Microelectronics Corp

04/19/18 / #20180108528

Gate oxide structure and method for fabricating the same

A method for forming a gate oxide layer on a substrate is provided, in which a region of the substrate is defined out by a shallow trench isolation (sti) structure. An oxide layer covers over the substrate and a mask layer with an opening to expose oxide layer corresponding to the region with an interface edge of the sti structure. ... United Microelectronics Corp

04/12/18 / #20180102434

Vertical channel oxide semiconductor field effect transistor and method for fabricating the same

A semiconductor device includes: a channel layer surrounded by a source layer; a first dielectric layer around the source layer; a gate layer around the channel layer and on the source layer; a first oxide semiconductor layer between the gate layer and the channel layer; a second oxide semiconductor layer between the gate layer and the drain layer; a second gate dielectric layer between the second oxide semiconductor layer and the drain layer; a drain layer on the gate layer and around the channel layer; and a second dielectric layer around the drain layer.. . ... United Microelectronics Corp

04/12/18 / #20180102411

Semiconductor device with single-crystal nanowire finfet

A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. ... United Microelectronics Corp

04/12/18 / #20180102408

Semiconductor device and method of forming the same

A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. ... United Microelectronics Corp

04/05/18 / #20180097110

Method for manufacturing a semiconductor structure

A method for manufacturing a semiconductor structure comprises the following steps. First, a recess is formed in a substrate. ... United Microelectronics Corp

04/05/18 / #20180097109

Semiconductor device

The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.. . ... United Microelectronics Corp

04/05/18 / #20180097104

High-voltage metal-oxide-semiconductor transistor and fabrication method thereof

A high-voltage mos transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. ... United Microelectronics Corp

04/05/18 / #20180097098

Method for fabricating finfet

The present invention provides a method of fabricating a finfet, comprising the following steps: first, a substrate having a plurality of fin structures disposed thereon is provided, an sti disposed between adjacent fin structures and a gate structure crossing the fin structures. Next, the fin structures not covered by the gate structure and the sti not covered by the gate structure are etched, until the sti is removed entirely and a first recessed and protruding profile is formed on the substrate, wherein the first recessed and protruding profile includes a first recess and a plurality of second recesses, and the position of the second recesses corresponds to the position of the fin structures, and an epitaxial layer is formed on the first recessed and protruding profile.. ... United Microelectronics Corp

04/05/18 / #20180096995

Finfet structure and fabricating method of gate structure

A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. ... United Microelectronics Corp

03/22/18 / #20180083141

Semiconductor device

A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate, and an anti-ferroelectric layer. ... United Microelectronics Corp

03/15/18 / #20180076500

Microstrip line structure and method for fabricating the same

A method for fabricating microstrip line structure is disclosed. First, a substrate is provided, ground patterns are formed on the substrate, an interlayer dielectric (ild) layer is formed on the ground patterns, contact plugs are formed in the ild layer, a ground plate is formed on the ild layer, and a signal line is formed on the ground plate. ... United Microelectronics Corp

03/15/18 / #20180076327

Semiconductor device and method for fabricating the same

A semiconductor device includes: a gate structure extending along a first direction on a substrate, in which the gate structure includes a first edge and a second edge extending along the first direction; a first doped region adjacent to one side of the gate structure, in which the first doped region includes a third edge and a fourth edge extending along the first direction; a second doped region adjacent to another side of the gate structure, in which the second doped region comprises a fifth edge and a sixth edge extending along the first direction; a first fin-shaped structure extending from the second edge of the gate structure toward the third edge of the first doped region; and a second fin-shaped structure extending from the first edge of the gate structure toward the sixth edge of the second doped region.. . ... United Microelectronics Corp

03/15/18 / #20180076207

Mask rom and process for fabricating the same

A mask rom is shown, including first resistors as a first part of memory cells, second resistors as a second part of memory cells, and contact plugs. Each first resistor includes: an undoped first poly-si layer including a convex portion and a step structure with a step height adjacent to the convex portion, a spacer on the sidewall of the step structure, and a first silicide layer on the first poly-si layer and being divided apart by the spacer. ... United Microelectronics Corp

03/08/18 / #20180069089

Method of forming semiconductor structure

A method of forming a semiconductor structure is disclosed. A substrate having a first area and a second area is provided, wherein a first surface of the first area is lower than a second surface of the second area. ... United Microelectronics Corp

03/08/18 / #20180068998

Bipolar junction transistor

A bipolar junction transistor (bjt) includes a semiconductor substrate and a first isolation structure. The semiconductor substrate includes a first fin structure disposed in an emitter region, a second fin structure disposed in a base region, and a third fin structure disposed in a collector region. ... United Microelectronics Corp

03/08/18 / #20180068951

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate structure is formed on the substrate, a first spacer is formed around the first gate structure, and an interlayer dielectric (ild) layer is formed around the first spacer. ... United Microelectronics Corp

03/08/18 / #20180067241

Color filter device and forming method thereof

A color filter device includes a dielectric layer, a passivation layer, a plurality of color filters and an inorganic film. The dielectric layer is disposed on a substrate, wherein the substrate has a light sensing area and a periphery area, and the periphery area is beside the light sensing area. ... United Microelectronics Corp

03/01/18 / #20180061963

Fabricating method of semiconductor structure

A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. ... United Microelectronics Corp

03/01/18 / #20180061950

Transistor device with threshold voltage adjusted by body effect

A transistor device including a substrate, a gate structure, a first doped region, a second doped region and a body region is provided. The gate structure is disposed on the substrate. ... United Microelectronics Corp

03/01/18 / #20180061752

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a capacitor is formed on the substrate and a hard mask on the capacitor, in which the capacitor includes a bottom electrode, a capacitor dielectric layer, and a top electrode. ... United Microelectronics Corp

03/01/18 / #20180061656

Method for forming semiconductor structure

A method for forming a semiconductor structure includes following steps. A substrate is provided, and a semiconductor layer is formed on the substrate. ... United Microelectronics Corp

03/01/18 / #20180057354

Semiconductor sensor and method of manufacturing the same

A semiconductor sensor, comprising a gas-sensing device and an integrated circuit electrically connected to the gas-sensing device, is provided. The gas-sensing device includes a substrate having a sensing area and an interconnection area in the vicinity of the sensing area, an inter-metal dielectric (imd) layer formed above the substrate in the sensing area and in the interconnection area, and an interconnect structure formed in the interconnection area. ... United Microelectronics Corp

02/22/18 / #20180053826

Semiconductor device and method for fabricating the same

A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. ... United Microelectronics Corp

02/22/18 / #20180053771

Semiconductor structure and method for fabricating the same

A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. ... United Microelectronics Corp

02/22/18 / #20180053761

Semiconductor device and manufacturing method thereof

A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. ... United Microelectronics Corp

02/22/18 / #20180053729

Alignment mark structure with dummy pattern

An alignment mark structure including a substrate, an alignment mark and at least one dummy pattern is provided. The alignment mark is disposed on the substrate. ... United Microelectronics Corp

02/15/18 / #20180047848

Method of fabricating semiconductor device

A semiconductor device and a method of fabricating the same, the semiconductor device includes a plurality of fin shaped structures, a trench, a spacing layer and a dummy gate structure. The fin shaped structures are disposed on a substrate. ... United Microelectronics Corp

02/15/18 / #20180047842

Semiconductor structure and method for forming the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, at least a first cell, and at least a second cell. ... United Microelectronics Corp

02/15/18 / #20180047810

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a gate structure is formed on the substrate, a recess is formed adjacent to the gate structure, a buffer layer is formed in the recess, and an epitaxial layer is formed on the buffer layer. ... United Microelectronics Corp

02/15/18 / #20180047809

Bipolar junction transistor device and method for fabricating the same

A bipolar junction transistor (bjt) device includes a semiconductor substrate, a first doping region with a first conductivity, a second doping region with a second conductivity, a third doping region with the first conductivity, at least one stacked block and a conductive contact. The first doping region is formed in the semiconductor substrate. ... United Microelectronics Corp

02/15/18 / #20180047635

Semiconductor device and manufacturing method thereof

A semiconductor device includes a semiconductor substrate, an isolation structure, and a spacer. The semiconductor substrate includes at least one fin structure. ... United Microelectronics Corp

02/08/18 / #20180040694

Semiconductor structure and method of forming the same

A semiconductor structure and method of forming the same. The semiconductor structure includes a fin structure formed on a substrate and an isolation structure formed therein. ... United Microelectronics Corp

02/08/18 / #20180040693

Method for fabricating shallow trench isolation between fin-shaped structures

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (sti) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first sti from the first region; forming a second sti on the first region; removing the patterned hard mask; and forming a gate structure on the second sti.. . ... United Microelectronics Corp

02/08/18 / #20180040558

Semiconductor device and method of fabricating the same

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, a plurality of gates and a plurality of plugs. ... United Microelectronics Corp

02/01/18 / #20180033961

Semiconductor device and manufacturing method thereof

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a bottom metal layer, a resistive random access memory (reram) cell structure, and an upper metal layer. ... United Microelectronics Corp

02/01/18 / #20180033891

Oxide semiconductor device

An oxide semiconductor device includes an oxide semiconductor transistor and a protection wall. The protection wall extends in a vertical direction and surrounds the oxide semiconductor transistor. ... United Microelectronics Corp

02/01/18 / #20180033874

Method of fabricating a semiconductor device

A method of fabricating a semiconductor device is disclosed. A substrate is provided. ... United Microelectronics Corp

02/01/18 / #20180033636

Method of fabricating a semiconductor structure

A method of fabricating a semiconductor structure is provided. A substrate surface is provided and a first layer is disposed on the substrate surface. ... United Microelectronics Corp

02/01/18 / #20180033633

Method for planarizing material layer

A method for planarizing a silicon layer includes providing a silicon layer having at least one recess therein. Next, a photoresist layer is formed to cover the silicon layer and fill up the recess. ... United Microelectronics Corp

01/25/18 / #20180027337

Piezoresistive microphone and method of fabricating the same

A piezoresistive microphone includes a substrate, an insulating layer, and a polysilicon layer. A first pattern is disposed within the polysilicon layer. ... United Microelectronics Corp

01/18/18 / #20180019341

Tunneling transistor and method of fabricating the same

A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. ... United Microelectronics Corp

01/18/18 / #20180019324

Semiconductor device having silicon-germanium layer on fin and method for manufacturing the same

A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (sige) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The sige layer formed on the top surface has a first thickness, the sige layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.. ... United Microelectronics Corp

01/18/18 / #20180019205

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first dielectric layer is formed on the substrate, in which a first conductor is embedded within the first dielectric layer. ... United Microelectronics Corp

01/11/18 / #20180012992

Semiconductor device and method of forming the same

A semiconductor device and a forming method thereof, the semiconductor device includes a first and a second wells, a source region, a drain region, two gate structures and at least one doping region. The first well with a first conductive type is disposed in a substrate, and the source region is disposed in the first well. ... United Microelectronics Corp

01/11/18 / #20180012976

Semiconductor structure

A method for making a semiconductor device. A substrate having a fin structure is provided. ... United Microelectronics Corp

01/11/18 / #20180012975

Method of fabricating semiconductor device

A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, agate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. ... United Microelectronics Corp

01/11/18 / #20180012971

Planar field effect transistor

A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. ... United Microelectronics Corp

01/11/18 / #20180012899

Integrated circuit and method for manufacturing thereof

A method for manufacturing an integrated circuit includes following steps. A substrate including a memory region and a core region is provided. ... United Microelectronics Corp

01/11/18 / #20180012882

Semiconductor structure for electrostatic discharge protection

A semiconductor structure for electrostatic discharge (esd) protection is provided. The semiconductor structure includes a substrate, a first doped well, a source doped region, a drain doped region, and a gate structure. ... United Microelectronics Corp

01/11/18 / #20180012808

Semiconductor device and fabrication method thereof

A method for fabricating a semiconductor device is provided. A substrate having a dummy gate thereon is prepared. ... United Microelectronics Corp

01/11/18 / #20180012793

Method for fabricating a semiconductor device

A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a stop layer between the dielectric layer and the substrate, wherein the stop layer contacts the substrate directly and the dielectric layer covers the top surface of the stop layer; forming an opening in the dielectric layer, wherein the dielectric layer comprises a damaged layer adjacent to the opening; forming a dielectric protective layer in the opening; forming a metal layer in the opening; removing the damaged layer and the dielectric protective layer to form a void, wherein the void exposes a top surface of the substrate; and forming a cap layer on and covering the dielectric layer, the void, and the metal layer.. . ... United Microelectronics Corp

01/11/18 / #20180012772

Method of planarizing substrate surface

A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. ... United Microelectronics Corp

01/11/18 / #20180012771

Method of planarizing substrate surface

A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. ... United Microelectronics Corp

01/04/18 / #20180006133

Device with reinforced metal gate spacer and method of fabricating

A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. ... United Microelectronics Corp

01/04/18 / #20180006129

Transistor and manufacturing method thereof

A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. ... United Microelectronics Corp

01/04/18 / #20180006040

Static random-access memory (sram) cell array and forming method thereof

A static random-access memory (sram) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each pg (pass-gate) finfet shares at least one of the active fins with a pd (pull-down) finfet, and at least one dummy fin is disposed between the two active fins having two adjacent pu (pull-up) finfets thereover in a static random-access memory cell. ... United Microelectronics Corp

01/04/18 / #20180006038

Layout pattern for static random access memory

A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device, a second pass gate device, a third pass gate device and a fourth pass gate device disposed on a substrate. A plurality of fin structures is disposed on the substrate, the fin structures including at least one first fin structure and at least one second fin structure. ... United Microelectronics Corp

01/04/18 / #20180005835

Memory device

Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. ... United Microelectronics Corp

12/28/17 / #20170373191

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device is disclosed. First, a fin-shaped structure is formed on a substrate, a first liner is formed on the substrate and the fin-shaped structure, a second liner is formed on the first liner, part of the second liner and part of the first liner are removed to expose a top surface of the fin-shaped structure, part of the first liner between the fin-shaped structure and the second liner is removed to form a recess, and an epitaxial layer is formed in the recess.. ... United Microelectronics Corp








ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009



###

This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with United Microelectronics Corp in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for United Microelectronics Corp with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

###