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Zing Semiconductor Corporation patents


Recent patent applications related to Zing Semiconductor Corporation. Zing Semiconductor Corporation is listed as an Agent/Assignee. Note: Zing Semiconductor Corporation may have other listings under different names/spellings. We're not affiliated with Zing Semiconductor Corporation, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "Z" | Zing Semiconductor Corporation-related inventors


Metal-ono-vacuum tube charge trap flash (vtctf) nonvolatile memory and the method for making the same

The present invention relates to a method for preparing vacuum tube flash memory structure, to form a vacuum channel in the flash memory, and using oxide-nitride-oxide (ono) composite materials as gate dielectric layer, wherein the nitride layer serves as a charge-trap layer to provide a blocking insulating between the gate electrode and the vacuum channel. The present structure exhibits superior program and erase speed as well as the retention time. ... Zing Semiconductor Corporation

Method for growing monocrystalline silicon by using czochralski method

The present application provides a method for growing monocrystalline silicon by using czochralski method, comprising: step (1) melting a deuterium-, nitrogen- and barium-doped silicon sheet and a polycrystalline silicon in a crucible; step (2) forming a deuterium- and nitrogen-doped monocrystalline silicon ingot by using magnetic field-applied czochralski method. The impurity level of the melt and the grown crystal can be reduced according to the present application. ... Zing Semiconductor Corporation

Semiconductor structure and method for forming the same

The present invention relates to a semiconductor structure and a method for forming the same. The method comprises steps of providing a substrate having a dummy gate, forming an elevated semiconductor source/drains epitaxy growing with lower in-situ doping concentration; forming a second elevated semiconductor source/drains epitaxy growing with higher in-situ doping concentration.. ... Zing Semiconductor Corporation

Hybrid integration fabrication of nanowire gate-all-around ge pfet and polygonal iii-v pfet cmos device

The present invention provides a method of manufacturing nanowire semiconductor device. In the active region of the pmos the first nanowire is formed with high hole mobility and in the active region of the nmos the second nanowire is formed with high electron mobility to achieve the objective of improving the performance of nanowire semiconductor device.. ... Zing Semiconductor Corporation

Finfet and fabrication method thereof

Present embodiments provide for a finfet and fabrication method thereof. The fabrication method includes two selective etching processes to form the channel. ... Zing Semiconductor Corporation

Soi substrate and manufacturing method thereof

The present invention application provides a method for manufacturing a soi substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; implanting a deuterium and hydrogen co-doping layer at a certain pre-determined depth of the first wafer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer; separating a part of the first wafer from the second wafer; and forming a deuterium and hydrogen co-doping semiconductor layer on the second wafer.. . ... Zing Semiconductor Corporation

Metal-ono-vacuum tube charge trap flash (vtctf) nonvolatile memory and the method for making the same

The present invention relates to a method for preparing vacuum tube flash memory structure, to form a vacuum channel in the flash memory, and using oxide-nitride-oxide (ono) composite materials as gate dielectric layer, wherein the nitride layer serves as a charge-trap layer to provide a blocking insulating between the gate electrode and the vacuum channel. The present structure exhibits superior program and erase speed as well as the retention time. ... Zing Semiconductor Corporation

Complementary nanowire semiconductor device and fabrication method thereof

Present embodiments provide for a complementary nanowire semiconductor device and fabrication method thereof. The fabrication method comprises providing a substrate, wherein the substrate has a nmos active region, a pmos active region and a shallow trench isolation (sti) region; forming a plurality of first hexagonal epitaxial wires on the nmos active region and the pmos active region by selective epitaxially growing a germanium (ge) crystal material; selectively etching the substrate to suspend the pluralities of first hexagonal epitaxial wires on the substrate; forming a plurality of second hexagonal epitaxial wires on the nmos active region by selective epitaxially growing a iii-v semiconductor crystal material surrounding the pluralities of first hexagonal epitaxial wires on the nmos active region; depositing a dielectric material on the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires, wherein the dielectric material covers the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires; and depositing a conducting material on the dielectric material for forming a gate electrode surrounding the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires, wherein the pluralities of first hexagonal epitaxial wires are a plurality of first nanowires and the pluralities of second hexagonal epitaxial wires are a plurality of second nanowires.. ... Zing Semiconductor Corporation

Complementary nanowire semiconductor device and fabrication method thereof

Present embodiments provide for a complementary nanowire semiconductor device and fabrication method thereof. The fabrication method comprises providing a substrate, wherein the substrate has a nmos active region, a pmos active region and a shallow trench isolation (sti) region; forming a plurality of first hexagonal epitaxial wires on the nmos active region and the pmos active region by selective epitaxially growing a germanium (ge) crystal material; selectively etching the substrate to suspend the pluralities of first hexagonal epitaxial wires on the substrate; forming a plurality of second hexagonal epitaxial wires on the nmos active region by selective epitaxially growing a iii-v semiconductor crystal material surrounding the pluralities of first hexagonal epitaxial wires on the nmos active region; depositing a dielectric material on the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires, wherein the dielectric material covers the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires; and depositing a conducting material on the dielectric material for forming a gate electrode surrounding the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires, wherein the pluralities of first hexagonal epitaxial wires are a plurality of first nanowires and the pluralities of second hexagonal epitaxial wires are a plurality of second nanowires.. ... Zing Semiconductor Corporation

Soi substrate and manufacturing method thereof

This invention application provides a method for manufacturing a soi substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; irradiating the first semiconductor substrate via a ion beam for forming a deuterium and helium co-doping layer to a pre-determined depth from a top surface of the first insulating layer; growing a second insulating layer on a top surface of the second semiconductor substrate for form a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer; separating a part of the first wafer from the second wafer; and forming a deuterium and helium co-doping semiconductor layer on the second wafer.. . ... Zing Semiconductor Corporation

Soi substrate and manufacturing method thereof

The present invention application provides a method for manufacturing a soi substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; implanting a deuterium and hydrogen co-doping layer at a certain pre-determined depth of the first wafer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer; separating a part of the first wafer from the second wafer; and forming a deuterium and hydrogen co-doping semiconductor layer on the second wafer.. . ... Zing Semiconductor Corporation

Soi substrate and manufacturing method thereof

This invention application provides a method for manufacturing a soi substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; irradiating the first semiconductor substrate via a ion beam for forming a doping layer to a pre-determined depth from a top surface of the first insulating layer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer at a deuterium atmosphere; separating a part of the first wafer from the second wafer; and forming a deuterium doped layer on the second wafer.. . ... Zing Semiconductor Corporation

Thermal processing method for wafer

The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a non-oxygenated gas mixture comprising deuterium gas and at least one kind of low active gas, and a rapid heating processing process is performed on a surface of the wafer to heat the wafer to a predetermined high temperature. ... Zing Semiconductor Corporation

Thermal processing method for wafer

The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a gas mixture comprising oxygen gas and deuterium gas, and a rapid thermal processing process is performed on a surface of the wafer. ... Zing Semiconductor Corporation

09/07/17 / #20170253993

Method for growing monocrystalline silicon and monocrystalline silicon ingot prepared thereof

This invention provides a method for growing monocrystalline silicon by applying czochralski method comprising forming a melt of silicon-containing materials in a crucible and pulling the melt for monocrystalline silicon growth, which is characterized by, the silicon-containing materials comprising a deuterium-implanted nitride-deposited silicon and a monocrystalline silicon, introducing a gas containing argon during formation of the melt, and, applying a magnetic field during the pulling step. This invention also provides a method for producing a wafer based on the above monocrystalline silicon.. ... Zing Semiconductor Corporation

09/07/17 / #20170253991

Method for growing monocrystalline silicon and monocrystalline silicon ingot prepared thereof

This invention provides a method for growing monocrystalline silicon by applying czochralski method comprising forming a melt of silicon-containing materials in a crucible and pulling the melt for monocrystalline silicon growth, which is characterized by, introducing a gas containing argon during formation of the melt, and, applying a magnetic field during the pulling step. This invention also provides a method for producing a wafer based on the above monocrystalline silicon.. ... Zing Semiconductor Corporation

08/03/17 / #20170222049

Vertical transistor and the fabrication method

A vertical transistor and the fabrication method. The transistor comprises a first surface and a second surface that is opposite to the first surface. ... Zing Semiconductor Corporation

08/03/17 / #20170222034

Method for formation of vertical cylindrical gan quantum well transistor

The present invention provides a method for forming a quantum well device having high mobility and high breakdown voltage with enhanced performance and reliability. A method for fabrication of a vertical cylindrical gan quantum well power transistor for high power application is disclosed. ... Zing Semiconductor Corporation

06/22/17 / #20170179269

Method for making iii-v nanowire quantum well transistor

The present invention provides a field effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first iii-v compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first iii-v compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first iii-v compound layer. ... Zing Semiconductor Corporation

05/11/17 / #20170133510

High voltage junctionless field effect device and its method of fabrication

A structure and a method of fabrication are disclosed of a high voltage junctionless field effect device. A channel layer and a barrier layer are formed sequentially underneath the gate structure. ... Zing Semiconductor Corporation

05/11/17 / #20170133488

High-voltage junctionless device with drift region and the method for making the same

The present invention discloses a method of forming a high voltage junctionless device with drift region. The drift region formed between the semiconductor channel and the dielectric layer enables the high voltage junctionless device to exhibit higher punch-through voltages and high mobility with better performance and reliability.. ... Zing Semiconductor Corporation

04/27/17 / #20170117407

Vertical transistor and the fabrication method

A vertical transistor and the fabrication method. The transistor comprises a first surface and a second surface that is opposite to the first surface. ... Zing Semiconductor Corporation

04/27/17 / #20170117400

Method of forming fin structure on patterned substrate that includes depositing quantum well layer over fin structure

Embodiments provide a quantum well device and the method for forming this device with high mobility and higher punch through voltages. For forming the quantum well device, a buffer layer can be formed on a patterned substrate of a quantum well device. ... Zing Semiconductor Corporation

04/27/17 / #20170117398

Method for formation of vertical cylindrical gan quantum well transistor

The present invention provides a method for forming a quantum well device having high mobility and high breakdown voltage with enhanced performance and reliability. A method for fabrication of a vertical cylindrical gan quantum well power transistor for high power application is disclosed. ... Zing Semiconductor Corporation

04/27/17 / #20170117138

Method of preparation of iii-v compound layer on large area si insulating substrate

A method for making iii-v-on-insulator on large-area si substrate wafer by confined epitaxial lateral overgrowth (celo) has been disclosed. This method, based on selective epitaxy, starting from defining an epitaxy seed window to the si substrate in a thermal oxide, from which the iii-v material will grow.. ... Zing Semiconductor Corporation

04/20/17 / #20170110580

Coms structure and fabrication method thereof

Present embodiments provide for a cmos structure and a fabrication method thereof. While the source-drain epitaxial material formed in each of the pmos device region and the nmos device region, deuterium gas is used as the carrier gas to store the deuterium atoms in the interstice of the source-drain epitaxial material as an impurity. ... Zing Semiconductor Corporation

04/20/17 / #20170110540

Method for making iii-v nanowire quantum well transistor

The present invention provides a filed effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first iii-v compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first iii-v compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first iii-v compound layer. ... Zing Semiconductor Corporation

04/20/17 / #20170110373

Complementary metal-oxide-semiconductor field-effect transistor and method thereof

This invention application provides a complementary metal-oxide-semiconductor field-effect transistor and method thereof. The transistor comprises a semiconductor substrate, a n-type field-effect transistor positioned in the semiconductor substrate, and a p-type field-effect transistor positioned in the semiconductor substrate and spaced apart the n-type field-effect transistor. ... Zing Semiconductor Corporation

04/20/17 / #20170110362

Soi structure and fabrication method

Present embodiments provide for a soi substrate and fabricating method thereof are provided. The fabricating method of soi substrate comprises: providing a first substrate, wherein a first dielectric layer is formed on the first substrate; implanting deuterium ions into the first substrate, wherein a deuterium-impurity layer is formed in the first substrate at predetermined depth; providing a second substrate, wherein a second dielectric layer is formed on the second substrate and bounded with the first dielectric layer; performing an annealing process, wherein microbubbles are formed in the deuterium-impurity layer; and cutting the first substrate from the deuterium-impurity layer to obtain the soi substrate.. ... Zing Semiconductor Corporation

04/20/17 / #20170107640

Method for forming monocrystalline silicon ingot and wafers

The present invention relates to a method for forming monocrystalline silicon ingot and wafers. At first, silica is doped with deuterium atoms which is retained in interstices therein. ... Zing Semiconductor Corporation

04/20/17 / #20170107638

Method for forming monocrystalline silicon ingot and wafer

The present invention relates to a method for forming monocrystalline silicon ingot and wafer. When forming a monocrystalline silicon ingot, melted silicon is introduced with a gas comprising deuterium atoms to receive the deuterium atoms at interstice sites, and thus the oxygen, carbon and other impurity contained therein are decreased. ... Zing Semiconductor Corporation

04/13/17 / #20170104085

Semiconductor structure and forming method thereof

This invention provides a semiconductor structure and a forming method thereof. The method for forming the semiconductor structure comprises providing a substrate having a dummy gate; forming source-drain regions in the substrate located in the two sides of the dummy gate, wherein the source-drain region is doped with deuterium; removing the dummy gate; and forming a gate structure having a gate oxide layer in the location of the dummy gate, wherein the deuterium enters the gate oxide layer. ... Zing Semiconductor Corporation

04/13/17 / #20170104079

Vacuum tube nonvolatile memory and the method for making the same

The present invention provides a vacuum tube nonvolatile memory and the method of manufacturing it. The vacuum tube nonvolatile memory comprises oxide-nitride-oxide composite structure as gate dielectric layer, wherein the nitride layer can trap charges and provide better insulating block capability between the gate and vacuum channel. ... Zing Semiconductor Corporation

04/13/17 / #20170103900

Method for forming wafer

This invention provides a method for forming a wafer comprising forming a silicon substrate, and then performing rapid thermal annealing to the substrate to form a passivation layer. The passivation layer reduces the surface roughness of the silicon substrate. ... Zing Semiconductor Corporation

04/13/17 / #20170103899

Semiconductor structure and method for forming the same

The present invention relates to a semiconductor structure and a method for forming the same. The method comprises steps of providing a substrate having a dummy gate, forming a source/drain epitaxy layer doped with deuterium at two sides of the dummy gate on the substrate through a process of chemical vapor deposition for epitaxy; removing the dummy gate and forming a gate structure having a gate oxide layer introducing the deuterium. ... Zing Semiconductor Corporation

04/13/17 / #20170103887

Method for forming epitaxial layer

This invention provides a method for forming an epitaxial layer comprising, during formation of the epitaxial layer by vapor phase deposition, introducing a carrier gas containing deuterium. Because of the deuterium atmosphere, the deuterium atoms are introduced in the silicon epitaxial film. ... Zing Semiconductor Corporation








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